Heteroepitaxial wafer and method for manufacturing the same

Abstract

The objective is to provide a heteroepitaxial wafer having a gate insulating film that is as reliable as silicon and does not experience basal plane dislocation problems, as well as a method for manufacturing the same. [Solution] The method for manufacturing a heteroepitaxial wafer includes the steps of: S1 removing the native oxide film on the surface of a single-crystal silicon substrate 2 by hydrogen baking; S2 forming a 3C-SiC epitaxial layer 3 on the single-crystal silicon substrate; S3 forming a silicon layer 4 on the 3C-SiC epitaxial layer; and S4 forming a silicon oxide film 5 by thermal oxidation of the silicon layer.

Description

Technical Field

[0001] The present invention relates to a heteroepitaxial wafer and a method for manufacturing the same.

Background Art

[0002] The need for power devices has been increasing in a very wide range, including the fields of automotive electrification and FA (Factory Automation). Also, the energy loss in power semiconductors has become non-negligible, and research on structures with good energy efficiency has been conducted and significant results have been achieved. This energy loss occurs when electrical energy is converted into heat, and while many efforts have been made to deal with this waste heat, there are also constraints. For example, in the case of in-vehicle IGBTs, as HV and EV become more highly functional, the number of electronic devices mounted has increased, and the cooling system has become larger for cooling, which has a significant impact on the design of automobiles.

[0003] Therefore, the use of materials other than silicon has been studied. Among them, SiC has a high breakdown strength due to its wide bandgap of 2.2 to 3.3 eV, and also has a high thermal conductivity, so it is expected as a semiconductor material for various semiconductor devices such as power devices and high-frequency devices.

[0004] Patent Document 1 discloses a method for manufacturing a semiconductor wafer in which a 3C-SiC layer is formed on a silicon substrate and a silicon layer is formed on the 3C-SiC layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Non-Patent Documents

[0006]

Non-Patent Document 1

[0007] Unlike silicon, which is grown by melting, SiC is grown using methods such as sublimation and gas growth. However, it has more crystal defects than silicon and its productivity is inferior. Furthermore, when used in actual devices, substrates with epitaxial growth on top of the bulk crystal are used. In this case, especially when forward current flows in power devices, the basal plane dislocations of the bulk crystal expand as stacking faults, leading to a problem of current degradation. In addition to the high number of crystal defects, the composition of silicon and carbon makes it difficult to form highly reliable gate insulating films like those made of silicon in devices such as IGBTs.

[0008] The present invention has been made to solve the above problems and aims to provide a heteroepitaxial wafer having a gate insulating film that does not cause basal plane dislocation problems and has the same level of reliability as silicon, and a method for manufacturing the same. [Means for solving the problem]

[0009] The present invention has been made to achieve the above objective and provides a heteroepitaxial wafer having a 3C-SiC epitaxial layer on a single-crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer.

[0010] Such heteroepitaxial wafers, by having a 3C-SiC epitaxial layer on a silicon substrate, enable large-diameter substrates and eliminate the problem of basal plane dislocation expansion due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in IGBT applications, it can have a voltage-holding layer with equivalent voltage resistance characteristics even when thinner than silicon. Moreover, since silicon on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film is equivalent to that of silicon.

[0011] The present invention has also been made to achieve the above objectives and provides a method for manufacturing a heteroepitaxial wafer, comprising the steps of: removing a native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking; epitaxially growing a 3C-SiC epitaxial layer on the surface of the single-crystal silicon substrate using a gas containing carbon and silicon as a source gas; forming a silicon layer on the 3C-SiC epitaxial layer; and thermally oxidizing the silicon layer.

[0012] This heteroepitaxial wafer manufacturing method allows for the creation of large-diameter substrates by epitaxially growing a 3C-SiC epitaxial layer on a silicon substrate, and prevents the problem of bulk crystal basal plane dislocations expanding as stacking faults due to forward current. Furthermore, because 3C-SiC has a wide bandgap, it is possible to form a voltage-bearing layer with equivalent voltage resistance characteristics to silicon even when thinner than silicon, for IGBT applications. In addition, since silicon grown on 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film can be manufactured to be equivalent to that of silicon.

[0013] In this case, the silicon layer can be single-crystal silicon, polysilicon, or amorphous silicon.

[0014] These silicon materials can be used to oxidize the aforementioned silicon layer into an amorphous silicon oxide film.

[0015] In this case, the thickness of the silicon layer can be set to 0.45 times the thickness of the silicon oxide film.

[0016] This makes it possible to form a silicon oxide film of the desired thickness. [Effects of the Invention]

[0017] As described above, the heteroepitaxial wafer of the present invention, by having a 3C-SiC epitaxial layer on a silicon substrate, results in a large-diameter substrate and eliminates the problem of basal plane dislocation expansion due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in the case of IGBT applications, it can have a voltage-holding layer with equivalent voltage resistance characteristics even when thinner than silicon. Moreover, since silicon on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film is also equivalent to that of silicon.

[0018] Furthermore, according to the heteroepitaxial wafer manufacturing method of the present invention, a large-diameter substrate can be realized by epitaxially growing a 3C-SiC epitaxial layer on a silicon substrate, and a wafer can be manufactured without the problem of basal plane dislocations of the bulk crystal expanding as stacking faults due to forward current. In addition, since 3C-SiC has a wide bandgap, in the case of IGBT applications, a voltage-holding layer with equivalent voltage resistance characteristics can be formed even if it is thinner than silicon. Moreover, since silicon grown on 3C-SiC is used as an oxide film in the gate area where reliability is required, a gate insulating film with the same reliability as silicon can be manufactured. [Brief explanation of the drawing]

[0019] [Figure 1] A schematic cross-sectional view of an example of a heteroepitaxial wafer according to the present invention is shown. [Figure 2] An example of a wafer growth sequence by the heteroepitaxial wafer manufacturing method according to the present invention is shown. [Modes for carrying out the invention]

[0020] Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.

[0021] As described above, there has been a demand for a heteroepitaxial wafer having a gate insulating film with high reliability equivalent to silicon without causing the problem of basal plane dislocation, and a method for manufacturing the same.

[0022] The inventors of the present invention have intensively studied the above problems, and by combining SiC, which has basic characteristics suitable for power devices (high insulation characteristics due to a wide bandgap, high thermal conductivity), with conventionally used silicon, they have conceived that an efficient substrate for power semiconductors, particularly for IGBTs, can be manufactured.

[0023] As a result of further studies by the inventors of the present invention, a heteroepitaxial wafer having a 3C-SiC epitaxial layer on a single-crystalline silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer has a 3C-SiC epitaxial layer on the silicon substrate, resulting in a large-diameter substrate and no problem of basal plane dislocation expansion due to forward conduction. Also, since 3C-SiC has a wide bandgap, in the case of IGBT applications, it has a breakdown voltage holding layer with equivalent breakdown voltage characteristics even if it is thinner than silicon. Furthermore, since silicon on 3C-SiC is used as an oxide film for the gate portion where reliability is required, the reliability of the gate insulating film is also equivalent to that of silicon, and the present invention has been completed.

[0024] The inventors have also conducted extensive research on the above problem and have now developed a method for manufacturing a heteroepitaxial wafer that includes the steps of: removing the native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking; epitaxially growing a 3C-SiC epitaxial layer on the surface of the single-crystal silicon substrate using a gas containing carbon and silicon as a source gas; forming a silicon layer on the 3C-SiC epitaxial layer; and thermally oxidizing the silicon layer. By using shal growth, large-diameter substrates can be realized, and products can be manufactured that do not suffer from the problem of bulk crystal basal plane dislocations expanding as stacking faults due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in the case of IGBT applications, a voltage-bearing layer with equivalent voltage resistance characteristics can be formed even if it is thinner than silicon. Moreover, since silicon grown on 3C-SiC is used as an oxide film for the gate portion where reliability is required, it has been found that a gate insulating film with the same reliability as silicon can be manufactured, thus completing the present invention.

[0025] [Hetero-epitaxial wafers] Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows a schematic cross-sectional view of an example of a heteroepitaxial wafer according to the present invention. The heteroepitaxial wafer 1 shown in Figure 1 has a 3C-SiC epitaxial layer 3 on a single-crystal silicon substrate 2 and a silicon oxide film 5 on the 3C-SiC epitaxial layer 3.

[0026] The single-crystal silicon substrate 2 can be a substrate with a diameter of 300 mm or more. This makes it possible to manufacture devices with larger diameters than when using single-crystal bulk SiC manufactured by sublimation or other methods. Other characteristics are not particularly limited, but for example, the plane orientation of the main surface may be (111), the conductivity type may be p-type or n-type, and the resistivity may be low resistivity of 0.1 Ω·cm or less or high resistivity of 1000 Ω·cm or more. The single-crystal silicon substrate can be manufactured using the same single-crystal manufacturing equipment and procedures as conventional single crystals.

[0027] By having a 3C-SiC epitaxial layer 3 on a single-crystal silicon substrate 2, the current conductivity degradation that occurs when bulk crystals are used, as described above, is avoided.

[0028] In IBGT applications, the 3C-SiC epitaxial layer 3 serves as the dielectric strength retention layer. While the dielectric breakdown field strength of silicon is 0.3 MV / cm, the dielectric breakdown field strength of 3C-SiC is 3 MV / cm, which is 10 times greater for 3C-SiC than for silicon. In other words, equivalent performance can be obtained with a dielectric strength retention layer that is 1 / 10th the thickness of that of conventional silicon IGBTs. It is not necessary to form the dielectric strength retention layer with only 3C-SiC; a combination of SiC and silicon may also be used.

[0029] As described later, the silicon oxide film 5 becomes a gate insulating film with the same reliability as silicon.

[0030] [Method for manufacturing heteroepitaxial wafers] Next, the method for manufacturing heteroepitaxial wafers according to the present invention will be described with reference to Figure 2. Figure 2 shows an example of a wafer growth sequence by the heteroepitaxial wafer manufacturing method according to the present invention. Note that the matters described above regarding heteroepitaxial wafers may be omitted.

[0031] (Step to remove the native oxide film by hydrogen baking: S1) First, a single-crystal silicon substrate 2 is placed in a reduced-pressure (RP-)CVD apparatus, and the native oxide film on the surface is removed by hydrogen baking (H2 annealing). If an amorphous oxide film remains, SiC nucleation on the single-crystal silicon substrate 2 will not be possible. The H2 annealing at this stage is not particularly limited, but it is preferable to use a temperature of 1000°C to 1200°C. Within this temperature range, it is not necessary to take a long time to prevent the native oxide film from remaining, and the occurrence of slip can be effectively reduced. The pressure and time of the H2 annealing are not particularly restricted, as long as the native oxide film is removed.

[0032] (Step for epitaxial growth of 3C-SiC epitaxial layer: S2) Next, the single-crystal silicon substrate 2 is preferably set to a temperature of 300°C to 1100°C, and a gas containing carbon and silicon, such as monomethylsilane or trimethylsilane, is introduced as a source gas to perform SiC nucleation. Compared to Si, C atoms are smaller and more easily vaporized, so trimethylsilane is preferable in terms of raw material efficiency as it allows for easier adjustment of growth conditions.

[0033] SiC nucleation can be performed, for example, on the surface of a single-crystal silicon substrate 2 at a pressure of 100 Torr (13332 Pa) or less and a temperature of 300°C or higher. However, since epitaxial growth of SiC is promoted at temperatures of 800°C or higher, it is more preferable to set the SiC nucleation temperature to 800°C or higher so that SiC nucleation and the formation of the 3C-SiC epitaxial layer 3 can be performed under the same conditions. Furthermore, at temperatures of 1100°C or lower, polycrystallization and the adhesion of by-products to the inner wall of the CVD apparatus can be effectively suppressed. This is presumed to be because at high temperatures, molecules adsorbed on the substrate surface desorb before epitaxial growth, causing a gas-phase reaction.

[0034] Furthermore, the growth pressure for epitaxial growth of the 3C-SiC epitaxial layer 3 is preferably 100 Torr (13332 Pa) or less. If the growth pressure is 100 Torr or less, polycrystallization of the 3C-SiC can be effectively prevented. If the pressure is 10 Torr or less, and more preferably 1 Torr or less, vacancies will be formed directly beneath the 3C-SiC epitaxial layer 3, and the effect of relaxing the stress on the entire epitaxial layer can be obtained.

[0035] Since the film thickness at this time depends on the pressure and temperature, the film deposition time can be appropriately set based on the pressure and temperature conditions set to achieve the desired thickness of the 3C-SiC epitaxial layer 3.

[0036] (Step to form the silicon layer: S3) A silicon layer 4 is grown on the 3C-SiC epitaxial layer 3, which has been grown to a predetermined thickness as described above, using a CVD apparatus.

[0037] The silicon layer 4 does not need to be single-crystal silicon; it can also be polysilicon or amorphous silicon. This is because the silicon layer 4 is oxidized to form an amorphous silicon oxide film.

[0038] (Process of thermal oxidation of the silicon layer: S4) The silicon layer 4 is thermally oxidized to form a silicon oxide film 5. The thermal oxidation conditions are not particularly limited and can be adjusted and optimized according to the equipment and process.

[0039] To completely oxidize silicon layer 4 to form silicon oxide film 5, the thickness of silicon layer 4 is calculated by working backward from the desired thickness of silicon oxide film 5. While it is preferable to determine the thickness by prior testing, the thickness of silicon layer 4 can be set to 45% of the desired thickness of silicon oxide film 5. This is because it is known that when silicon is oxidized to form a silicon oxide film, volume expansion causes the ratio of the thickness of the silicon oxide film to the thickness of the original silicon to become 1:0.45 (Non-Patent Literature 1).

[0040] By using a silicon oxide film 5 instead of silicon layer 4, the gate oxide film quality in semiconductor devices can be improved. In other words, in conventional SiC devices, the gate insulating film is formed using SiC, which has reliability issues. However, in this invention, silicon is grown on a 3C-SiC epitaxial layer 3, and this silicon is used to form the gate insulating film, making it possible to ensure the same gate reliability as conventional silicon IGBTs. Furthermore, the thickness of the silicon layer in this case only needs to be thicker than the required gate structure and can be set arbitrarily. [Examples]

[0041] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0042] A 3C-SiC epitaxial layer was formed on a 300 mm diameter single-crystal silicon substrate, and then a single-crystal Si epitaxial layer was formed on its surface. By oxidizing this silicon epitaxial layer, a silicon oxide film with a thickness of 100 nm was formed on the surface of the substrate.

[0043] Specifically, first, a single-crystal silicon substrate 2 was prepared, with a diameter of 300 mm, a surface orientation of (111), boron doping, and high resistivity. The single-crystal silicon substrate was placed on a susceptor in the reactor of a reduced-pressure CVD apparatus, and the substrate surface was annealed with H2 at 1080°C for 1 minute to remove the native oxide film.

[0044] Next, trimethylsilane gas was introduced at a growth temperature of 900°C and a growth pressure of 5 Torr (666.6 Pa) to perform SiC nucleation and growth of the 3C-SiC epitaxial layer 3. Growth was carried out for 15 minutes until the film thickness reached 45 nm. Subsequently, the XRD spectrum was examined in a plane configuration, and a 3C-SiC(220) peak parallel to Si(220) was observed, confirming that a single-crystal 3C-SiC epitaxial layer 3 had grown.

[0045] Next, a 45 nm single-crystal silicon layer 4 was formed on the 3C-SiC epitaxial layer 3 by introducing trichlorosilane gas at a growth temperature of 1100°C and atmospheric pressure. The substrate was then placed in a pyrogenic oxidation furnace and the silicon layer 4 was completely oxidized for 30 minutes at 1000°C to form a silicon oxide film 5, thereby obtaining the desired heteroepitaxial wafer.

[0046] The obtained heteroepitaxial wafers were subjected to oxide film breakdown pressure evaluation. A 300 nm layer of phosphorus-doped polysilicon was grown as the electrode. Subsequently, 1 mm was etched using photolithography and dry etching (CF4 / O2 mixed gas). 2 300 electrodes of this size were formed on a wafer. These elements were subjected to a current of 0.01 A / cm² at room temperature. 2We applied electrical stress for 10 seconds to check for initial defective elements, but the percentage was 0%, indicating good performance.

[0047] Next, ten of these elements were randomly selected, and the current was monitored while applying a voltage in 0.25V steps. Dielectric breakdown was defined as a current value of 0.01A, and the breakdown voltage was measured. As a result, the breakdown voltages of all these elements were greater than 70V, indicating good characteristics.

[0048] As described above, according to the embodiments of the present invention, it was possible to manufacture heteroepitaxial wafers with large diameter substrates that do not experience current degradation and, when used for IGBT applications, have voltage resistance characteristics and gate insulating film reliability equivalent to those of silicon.

[0049] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0050] 1... Heteroepitaxial wafer, 2... Single crystal silicon substrate, 3...3C-SiC epitaxial layer, 4...Silicon layer, 5...Silicon oxide film.

Claims

1. A heteroepitaxial wafer characterized by having a 3C-SiC epitaxial layer on a single-crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer.

2. A process to remove the native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking, A step of epitaxially growing a 3C-SiC epitaxial layer on the surface of a single-crystal silicon substrate using a gas containing carbon and silicon as a source gas, The process of forming a silicon layer on the 3C-SiC epitaxial layer, A method for manufacturing a heteroepitaxial wafer, characterized by comprising the step of thermally oxidizing the silicon layer.

3. The method for manufacturing a heteroepitaxial wafer according to claim 2, characterized in that the silicon layer is single-crystal silicon, polysilicon, or amorphous silicon.

4. The method for manufacturing a heteroepitaxial wafer according to claim 2 or 3, characterized in that the thickness of the silicon layer is 0.45 times the thickness of the silicon oxide film.

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