Integrated circuit device

Abstract

To provide an integrated circuit device that can reduce the decrease in charging voltage to a capacitor caused by wiring resistance. [Solution] An integrated circuit device comprising a first pad and a second pad connected to a capacitor, and a transistor section that controls the charging and discharging of the capacitor via the first pad and the second pad, wherein, in a plan view, the transistor section includes a first part and a second part arranged on either side of the first pad and the second pad.

Description

Technical Field

[0001] The present invention relates to an integrated circuit device.

Background Art

[0002] Patent Document 1 discloses a DC-DC converter that operates intermittently and is provided with switching means capable of electrically isolating each of a plurality of capacitors in order to suppress the outflow of charge from the capacitors during non-operation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the charge pump operation for charging and discharging a capacitor, if the wiring resistance is large, the charging voltage to the capacitor may decrease due to voltage drop, but the DC-DC converter described in Patent Document 1 does not consider this problem.

Means for Solving the Problems

[0005] One aspect of the integrated circuit device according to the present invention is a first pad and a second pad connected to a capacitor, and a transistor unit that controls charging and discharging of the capacitor via the first pad and the second pad. In a plan view, the transistor unit includes a first portion and a second portion disposed with the first pad and the second pad interposed therebetween.

Brief Description of the Drawings

[0006] [Figure 1] External perspective view showing a multifunction printer. [Figure 2] A perspective view showing the internal structure of the scanner unit. [Figure 3] A schematic exploded perspective view showing the configuration of the image sensor module. [Figure 4] A schematic plan view showing the arrangement of the image reading chips. [Figure 5] A diagram showing the functional configuration of the scanner unit. [Figure 6] A functional block diagram showing the configuration of the integrated circuit device of this embodiment. [Figure 7] A diagram showing an example of a switching circuit configuration. [Figure 8] A diagram showing the equivalent circuit of a switching circuit in the charged state of a capacitor. [Figure 9] A diagram showing the equivalent circuit of a switching circuit in the discharge state of a capacitor. [Figure 10] A diagram showing the layout configuration of an integrated circuit device. [Figure 11] A diagram showing the layout configuration of the switching circuit and the electrostatic protection circuit in this embodiment. [Figure 12] A diagram showing the circuit configuration of a PMOS transistor. [Figure 13] A diagram showing the layout configuration of PMOS transistors. [Figure 14] A diagram showing the layout configuration of the switching circuit and electrostatic protection circuit in the comparative example. [Modes for carrying out the invention]

[0007] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The drawings used are for illustrative purposes only. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

[0008] The integrated circuit device of the present invention can be used in various electronic devices. Below, we will describe an integrated circuit device used as an analog front end in a scanner unit, using a multifunction device having a printer unit and a scanner unit as an example.

[0009] 1. Structure of a multifunction printer Figure 1 is an external perspective view of the multifunction device 1. As shown in Figure 1, the multifunction device 1 includes a printer unit 2, which is an image recording device, and a scanner unit 3, which is an image reading device. Specifically, the multifunction device 1 integrates the printer unit 2, which is the main body of the device, and the scanner unit 3, which is an upper unit located on top of the printer unit 2. In the following description, the front-to-back direction in Figure 1 will be referred to as the X-axis direction, and the left-to-right direction as the Y-axis direction.

[0010] As shown in Figure 1, the printer unit 2 comprises a transport unit (not shown) that feeds recording media such as printing paper or single sheets along a feed path, a printing unit (not shown) positioned above the feed path and performing inkjet printing on the recording media, a panel-type operation unit 63 positioned on the front, a device frame (not shown) that mounts the transport unit, the printing unit, and the operation unit 63, and a device housing 65 that covers them. The device housing 65 is provided with an outlet 66 through which the printed recording media is discharged. Although not shown, a USB port and a power port are located on the lower rear of the printer unit 2. In other words, the multifunction device 1 is configured to be connectable to a computer or the like via the USB port.

[0011] The scanner unit 3 is rotatably supported by the printer unit 2 via a hinge portion 4 at the rear end, and covers the upper part of the printer unit 2 so as to be openable and closable. That is, by pulling up the scanner unit 3 in the rotational direction, the upper surface opening of the printer unit 2 is exposed, and the inside of the printer unit 2 is exposed through the upper surface opening. On the other hand, by lowering the scanner unit 3 in the rotational direction and placing it on the printer unit 2, the upper surface opening is closed by the scanner unit 3. Thus, by opening the scanner unit 3, it is possible to replace the ink cartridge, eliminate paper jams, etc.

[0012] FIG. 2 is a perspective view showing the internal structure of the scanner unit 3. As shown in FIGS. 1 and 2, the scanner unit 3 includes an upper frame 11 which is a housing, an image reading unit 12 housed in the upper frame 11, and an upper lid 13 rotatably supported on the upper part of the upper frame 11. As shown in FIG. 2, the upper frame 11 includes a box-shaped lower case 16 that houses the image reading unit 12, and an upper case 17 that covers the top surface of the lower case 16. A glass document placement plate (not shown) is widely arranged on the upper case 17, and a document medium with the reading surface facing down is placed thereon. On the other hand, the lower case 16 is formed in a shallow box shape with an open upper surface.

[0013] As shown in Figure 2, the image reading unit 12 includes a line sensor type sensor unit 31, a sensor carriage 32 on which the sensor unit 31 is mounted, a guide shaft 33 extending in the Y-axis direction and supporting the sensor carriage 32 so that it can slide freely, and a self-propelled sensor movement mechanism 34 that moves the sensor carriage 32 along the guide shaft 33. The sensor unit 31 has an image sensor module 41 which is a CMOS line sensor extending in the X-axis direction, and reciprocates in the Y-axis direction along the guide shaft 33 by the motor-driven sensor movement mechanism 34. CMOS is an abbreviation for Complementary Metal-Oxide-Semiconductor. This allows the image of the medium to be read on the document placement plate to be read. The sensor unit 31 may also be a CCD line sensor. CCD is an abbreviation for Charge Coupled Device.

[0014] FIG. 3 is an exploded perspective view schematically showing the configuration of the image sensor module 41. In the example shown in FIG. 3, the image sensor module 41 includes a case 411, a light source 412, a lens 413, a module substrate 414, and an image reading chip 415 which is a semiconductor device for reading an image. The light source 412, the lens 413, and the image reading chip 415 are housed between the case 411 and the module substrate 414. The case 411 is provided with a slit. The light source 412 has, for example, R, G, and B light-emitting diodes, and according to the usage situation of the user, the R, G, and B light-emitting diodes, that is, the red LED, the green LED, and the blue LED, emit light in sequence or simultaneously. That is, in the case of color scanning, the light source 412 causes the red LED, the green LED, and the blue LED to emit light in sequence, and in the case of monochrome scanning, the light source 412 causes the red LED, the green LED, and the blue LED to emit light simultaneously. LED is an abbreviation for Light emitting diode. The light emitted by the light source 412 is irradiated onto the read medium through the slit, and the light from the read medium enters the lens 413 through the slit. The lens 413 guides the input light to the image reading chip 415. Then, the image reading chip 415 reads the image formed on the read medium based on the light reflected by the read medium from the light irradiated by the light source 412.

[0015] FIG. 4 is a plan view schematically showing the arrangement of the image reading chips 415. As shown in FIG. 4, a plurality of image reading chips 415 are arranged side by side in a one-dimensional direction, specifically, in the X-axis direction, on the module substrate 414. Each image reading chip 415 has a large number of light receiving elements arranged in a row. The higher the density of the light receiving elements of each image reading chip 415, the higher the resolution of the scanner unit 3 capable of reading an image. Also, the larger the number of image reading chips 415, the larger the scanner unit 3 capable of reading a large image can be realized.

[0016] 2. Functional Configuration of Scanner Unit Figure 5 is a functional block diagram showing the functional configuration of a scanner unit 3, which is an image reading device. In the example shown in Figure 5, the scanner unit 3 is composed of an integrated circuit device 100 that functions as an analog front end, a control unit 300, a red LED 412R, a green LED 412G, a blue LED 412B, and a plurality of image reading chips 415. As mentioned above, the red LED 412R, green LED 412G, and blue LED 412B are provided on the light source 412, and the plurality of image reading chips 415 are arranged in a row on the module board 414. There may be multiple instances of each of the red LED 412R, green LED 412G, and blue LED 412B. In addition, the integrated circuit device 100 and the control unit 300 are provided on the module board 414 or on a different board (not shown) from the module board 414. The control unit 300 may be implemented as an integrated circuit.

[0017] The integrated circuit device 100 supplies a drive signal DrvR to the red LED 412R for a predetermined exposure time Δt at a predetermined timing, causing the red LED 412R to light up. Similarly, the integrated circuit device 100 supplies a drive signal DrvG to the green LED 412G for a predetermined exposure time Δt at a predetermined timing, causing the green LED 412G to light up, and supplies a drive signal DrvB to the blue LED 412B for a predetermined exposure time Δt at a predetermined timing, causing the blue LED 412B to light up. The integrated circuit device 100 causes the red LED 412R, green LED 412G, and blue LED 412B to light up one by one.

[0018] The control unit 300 supplies a clock signal CLK and a command signal CMD to a plurality of image reading chips 415. The clock signal CLK is the operating clock signal of the image reading chip 415, and the command signal CMD is a signal that includes various commands such as commands for setting the resolution of image reading by the scanner unit 3, and commands for instructing the start and end of image reading.

[0019] Each image reading chip 415 operates in synchronization with the clock signal CLK and generates and outputs an image signal OS having image information of a set resolution based on the light received by each light-receiving element from the image formed on the reading medium, through the emission of a red LED 412R, a green LED 412G, or a blue LED 412B.

[0020] The integrated circuit device 100 receives the image signal OS output by each image reading chip 415 as either of the two-channel image signals OS1 or OS2, performs amplification processing and A / D conversion processing on each image signal OS to convert it into a digital signal that includes a digital value corresponding to the amount of light received by each photodetector, and transmits each digital signal sequentially to the control unit 300.

[0021] The control unit 300 receives each digital signal transmitted sequentially from the integrated circuit device 100 and generates image information read by the image sensor module 41.

[0022] 3. Functional Configuration of Integrated Circuit Devices Figure 6 is a functional block diagram showing the configuration of the integrated circuit device 100 of this embodiment. As shown in Figure 6, the integrated circuit device 100 includes CDS circuits 101a, 101b, adders 102a, 102b, D / A converters 103a, 103b, programmable gain amplifiers 104a, 104b, A / D conversion circuit 105, interface circuit 106, register 107, power supply circuit 108, LED driver 109, and switching circuit 110. CDS is an abbreviation for Correlated Double Sampling.

[0023] The power supply circuit 108 is a circuit that generates the power supply voltage for each part of the integrated circuit device 100.

[0024] The CDS circuit 101a receives the first channel image signal OS1 as input. The CDS circuit 101a removes noise contained in the image signal OS1 by correlated double sampling and outputs a voltage signal corresponding to the light received by each photodetector in the image reading chip 45.

[0025] The adder 102a outputs a signal obtained by adding the signal output from the CDS circuit 101a and the signal output from the D / A converter 103a. The D / A converter 103a receives an offset correction value stored in register 107 as input and outputs an analog signal having an offset correction voltage. Therefore, the adder 102a outputs a signal from which the offset voltage included in the signal output from the CDS circuit 101a has been removed.

[0026] The programmable gain amplifier 104a outputs a signal that has been amplified by a preset gain from the signal output from the adder 102a.

[0027] In this way, the CDS circuit 101a, adder 102a, D / A converter 103a, and programmable gain amplifier 104a perform signal processing on the first channel image signal OS1.

[0028] The CDS circuit 101b receives the second channel image signal OS2. The CDS circuit 101b removes noise contained in the image signal OS1 by correlated double sampling and outputs a voltage signal corresponding to the light received by each photodetector in the image reading chip 45.

[0029] The adder 102b outputs a signal obtained by adding the signal output from the CDS circuit 101b and the signal output from the D / A converter 103b. The D / A converter 103b receives an offset correction value stored in register 107 as input and outputs an analog signal having an offset correction voltage. Therefore, the adder 102b outputs a signal from which the offset voltage included in the signal output from the CDS circuit 101b has been removed.

[0030] The programmable gain amplifier 104b outputs a signal that has been amplified by a preset gain from the signal output from the adder 102b.

[0031] In this way, the CDS circuit 101b, adder 102b, D / A converter 103b, and programmable gain amplifier 104b perform signal processing on the second channel image signal OS2.

[0032] The A / D conversion circuit 105 converts the analog signals output from the programmable gain amplifier 104a and the analog signals output from the programmable gain amplifier 104b into digital signals in a time-division manner. The A / D conversion circuit 105 outputs the converted digital signals to the control unit 300.

[0033] The interface circuit 106 is a circuit that communicates data with the control unit 300, and writes and reads various data to and from the register 107 in response to requests from the control unit 300. Various data, such as the offset correction value mentioned above, are stored in the register 107.

[0034] The LED driver 109 generates drive signals DrvR, DrvG, and DrvB based on the drive voltage output from the switching circuit 110, and outputs them to the red LED 412R, green LED 412G, and blue LED 412B, respectively.

[0035] The switching circuit 110 is connected to the VDD terminal, CPH terminal, CPL terminal, VCP terminal, and VSS terminal of the integrated circuit device 100. The VDD terminal and VCP terminal are connected to both ends of an external capacitor 151 of the integrated circuit device 100, and the CPH terminal and CPL terminal are connected to both ends of an external capacitor 152 of the integrated circuit device 100.

[0036] The switching circuit 110 and capacitors 151 and 152 constitute a charge pump circuit 150, which generates a voltage at the VCP terminal by boosting the voltage at the VDD terminal. The voltage at the VCP terminal is supplied to the LED driver 109 as the drive voltage.

[0037] 4. Configuration of the switching circuit Figure 7 shows an example configuration of the switching circuit 110. Figure 7 also shows the electrostatic protection circuits 121-126 and capacitors 151 and 152 connected to the switching circuit 110.

[0038] As shown in Figure 7, the switching circuit 110 includes a control circuit 115 and a transistor section 116. The transistor section 116 includes a PMOS transistor 111, an NMOS transistor 112, a PMOS transistor 113, and an NMOS transistor 114.

[0039] PMOS transistor 111 has its source connected to the CPH terminal and its drain connected to the VCP terminal. NMOS transistor 112 has its source connected to the CPH terminal and its drain connected to the VDD terminal. PMOS transistor 113 has its source connected to the VDD terminal and its drain connected to the CPL terminal. NMOS transistor 114 has its source connected to the VSS terminal and its drain connected to the CPL terminal.

[0040] The control circuit 115 outputs control signals to the gates of the PMOS transistors 111, 112, 113, and 114, controlling the capacitor 151 to either a charged state or a discharged state.

[0041] The transistor section 116, configured in this way, controls the charging and discharging of the capacitor 151 via the VDD terminal, CPH terminal, CPL terminal, VCP terminal, and VSS terminal.

[0042] Figure 8 shows the equivalent circuit of the switching circuit 110 when capacitor 151 is controlled to a charged state. As shown in Figure 8, when capacitor 151 is charged, PMOS transistors 111, 113 and NMOS transistor 114 each function as switching elements, and NMOS transistor 112 functions as a current source. The control circuit 115 outputs a high-level control signal to the gates of PMOS transistors 111, 113 and NMOS transistor 114, and also outputs a voltage control signal to the gate of NMOS transistor 112 corresponding to the voltage at the VCP terminal. As a result, PMOS transistors 111 and 113 become non-conductive, NMOS transistor 114 becomes conductive, and the desired current flows between the drain and source of NMOS transistor 112. Consequently, as shown by the dashed line in Figure 8, the desired current flows from the power supply to ground, and charge is accumulated in capacitor 151.

[0043] Figure 9 shows the equivalent circuit of the switching circuit 110 when capacitor 151 is controlled to a discharge state. As shown in Figure 9, when capacitor 151 is discharged, PMOS transistor 111 and NMOS transistors 112 and 114 each function as switching elements, and PMOS transistor 113 functions as a current source. The control circuit 115 outputs an L-level control signal to the gates of PMOS transistor 111 and NMOS transistors 112 and 114, and also outputs a voltage control signal to the gate of PMOS transistor 113 corresponding to the voltage at the VCP terminal. As a result, NMOS transistors 112 and 114 become non-conductive, PMOS transistor 111 becomes conductive, and the desired current flows between the source and drain of PMOS transistor 113. As a result, as shown by the dashed line in Figure 9, the desired current flows from the power supply through capacitor 151 to capacitor 152, and the charge stored in capacitor 151 is released and stored in capacitor 152.

[0044] In this way, as capacitor 151 repeatedly cycles between charging and discharging, the desired charge is accumulated in capacitor 152, and the voltage at the VCP terminal rises to the desired voltage.

[0045] Returning to the explanation of Figure 7, the electrostatic protection circuits 121 to 126 are located inside the integrated circuit device 100. Electrostatic protection circuit 121 is connected between the CPL terminal and the VSS terminal. Electrostatic protection circuit 122 is connected between the VDD terminal and the VSS terminal. Electrostatic protection circuit 123 is connected between the VDD terminal and the CPH terminal. Electrostatic protection circuit 124 is connected between the CPH terminal and the VSS terminal. Electrostatic protection circuit 125 is connected between the VDD terminal and the VCP terminal. Electrostatic protection circuit 126 is connected between the VCP terminal and the VSS terminal.

[0046] 5. Layout configuration of integrated circuit device Figure 10 shows the layout configuration of the integrated circuit device 100. As shown in Figure 10, the integrated circuit device 100 includes a semiconductor substrate 200. In plan view, the semiconductor substrate 200 is rectangular and has side 200a, side 200b intersecting side 200a, side 200c opposite side 200a, and side 200d opposite side 200b. In plan view, the contours of the integrated circuit device 100 and the semiconductor substrate 200 are almost identical. Therefore, in plan view, the integrated circuit device 100 is rectangular and has sides 200a, 200b, 200c, and 200d.

[0047] Numerous pads 201 are arranged on the semiconductor substrate 200 along sides 200a, 200b, 200c, and 200d.

[0048] The power supply circuit 108 is located at a corner near the point where sides 200b and 200c intersect. The LED driver 109 is located between the switching circuit 110 and the electrostatic protection circuits 121-126 and the power supply circuit 108.

[0049] The CDS circuits 101a, 101b, adders 102a, 102b, D / A converters 103a, 103b, and programmable gain amplifiers 104a, 104b are located at the corners near the intersection of sides 200c and 200d. Logic circuits such as the interface circuit 106 and register 107 are located at the corners near the intersection of sides 200a and 200d. The A / D conversion circuit 105 is located between the logic circuits and the CDS circuits 101a, 101b, adders 102a, 102b, D / A converters 103a, 103b, and programmable gain amplifiers 104a, 104b.

[0050] The switching circuit 110 and the electrostatic protection circuits 121-126 are located at the corners near the intersection of sides 200a and 200b. Within region A1 where the switching circuit 110 and the electrostatic protection circuits 121-126 are located, multiple pads 201 are positioned in areas away from sides 200a and 200b.

[0051] Figure 11 shows the layout configuration of the switching circuit 110 and the electrostatic protection circuits 121-126. Note that the control circuit 115 and wiring diagrams are omitted in Figure 11. As shown in Figure 11, in region A1, 11 pads 201a-201k are arranged in a line along the X direction. Pads 201a-201k correspond to the 11 pads 201 arranged in region A1 in Figure 10.

[0052] Pads 201a, 201b, and 201c correspond to the VSS terminals shown in Figure 6 and are connected to each other by wiring not shown. Pads 201d and 201e correspond to the CPL terminals shown in Figure 6 and are connected to each other by wiring not shown. Pads 201f and 201g correspond to the VDD terminals shown in Figure 6 and are connected to each other by wiring not shown. Pads 201h and 201i correspond to the CPH terminals shown in Figure 6 and are connected to each other by wiring not shown. Pads 201j and 201k correspond to the VCP terminals shown in Figure 6 and are connected to each other by wiring not shown.

[0053] NMOS transistor 114 is divided into four parts, with pads 201c and 201d each positioned on either side in the Y direction. PMOS transistor 113 is divided into four parts, with pads 201e and 201f each positioned on either side in the Y direction. NMOS transistor 112 is divided into four parts, with pads 201g and 201h each positioned on either side in the Y direction. PMOS transistor 111 is also divided into four parts, with pads 201i and 201j each positioned on either side in the Y direction.

[0054] Specifically, as shown in Figure 12, the PMOS transistor 111 is configured by connecting multiple PMOS transistors 111a in parallel, and as shown in Figure 13, these multiple PMOS transistors 111a are divided into four sections and arranged so as to sandwich the pads 201i and 201j in the Y direction. Although not shown in the figures, the configuration and layout of the NMOS transistors 112, 113, and 114 are the same as those of the PMOS transistor 111.

[0055] As shown in Figure 11, in a plan view of the semiconductor substrate 200, the transistor portion 116 includes a first portion 116a and a second portion 116b arranged on either side of the pads 201c to 201j. For example, the first portion 116a includes half of a plurality of PMOS transistors 111a connected in parallel to each other that constitute a PMOS transistor 111. Similarly, the first portion 116a includes half of a plurality of NMOS transistors connected in parallel to each other that constitute an NMOS transistor 112. Similarly, the first portion 116a includes half of a plurality of PMOS transistors connected in parallel to each other that constitute a PMOS transistor 113. Similarly, the first portion 116a includes half of a plurality of NMOS transistors connected in parallel to each other that constitute an NMOS transistor 114.

[0056] The first portion 116a and the second portion 116b of the transistor section 116 are arranged along the Y direction, and the pads 201c to 201j are arranged along the X direction which intersects the Y direction. For example, the X direction and the Y direction are orthogonal.

[0057] As shown in Figure 11, electrostatic protection circuit 121 is located between pads 201c and 201d and is connected to pads 201a, 201b, 201c and pad 201d by wiring (not shown). Electrostatic protection circuit 123 is located between 201g and pad 201h and is connected to pads 201f, 201g and pads 201h, 201i by wiring (not shown). Electrostatic protection circuit 125 is located near pad 201k and is connected to pads 201f, 201g and pads 201j, 201k by wiring (not shown).

[0058] Furthermore, electrostatic protection circuit 122 is positioned so as to sandwich pad 201g and a portion of NMOS transistor 112, and is connected to pads 201f, 201g and pads 201a, 201b, 201c by wiring (not shown). Electrostatic protection circuit 124 is positioned so as to sandwich pad 201h and a portion of NMOS transistor 112, and also sandwich pad 201i and a portion of PMOS transistor 111, and is connected to pads 201h, 201i and pads 201a, 201b, 201c by wiring (not shown). Electrostatic protection circuit 126 is positioned so as to sandwich pad 201j and a portion of PMOS transistor 111, and is connected to pads 201j, 201k and pads 201a, 201b, 201c by wiring (not shown).

[0059] In other words, as shown in Figure 11, in a plan view of the semiconductor substrate 200, the first portion 116a of the transistor section 116 is positioned between the pads 201g to 201j and the electrostatic protection circuits 122, 124, and 126. In this way, because the electrostatic protection circuits 122, 124, and 126 are positioned with a gap between them and the pads 201g to 201j, the first portion 116a and the second portion 116b of the transistor section 116 are positioned adjacent to the pads 201c to 201j. Therefore, the shortest distance between the first portion 116a and the pads 201c to 201j is almost zero, and the shortest distance between the second portion 116b and the pads 201c to 201j is also almost zero.

[0060] The transistor section 116, configured in this way, controls the charging and discharging of the capacitor 151 via pads 201a to 201k.

[0061] In a typical layout configuration, pads 201a to 201k are located in an area close to edge 200a of the semiconductor substrate 200, and electrostatic protection circuits 121 to 126 are located near pads 201a to 201k. Therefore, as a comparative example to this embodiment, Figure 14 shows the layout configuration of the switching circuit 110 and electrostatic protection circuits 121 to 126 when pads 201a to 201k are provided in an area close to edge 200a. Note that the control circuit 115 and wiring diagrams are omitted in Figure 14.

[0062] In the comparative example layout shown in Figure 14, each of the multiple PMOS transistors 111a included in the PMOS transistor 111 is connected to pads 201i and 201j by wiring (not shown). The distance in the Y direction between pads 201i and 201j and the PMOS transistor 111a closest to pads 201i and 201j, i.e., the shortest distance, is defined as d1. In the Y direction, the distance between pads 201i and 201j and the PMOS transistor 111a furthest from pads 201i and 201j, i.e., the longest distance, is defined as d2.

[0063] In this case, the PMOS transistor 111 is composed of multiple PMOS transistors 111a, so the resistance R of the wiring connecting each of the pads 201i and 201j to the PMOS transistor 111 is roughly calculated using equation (1) with the shortest distance d1 and the longest distance d2. In equation (1), Rp is the sheet resistance of the wiring and W is the wiring width.

[0064]

number

[0065] The resistance R of each wire for NMOS transistor 112, PMOS transistor 113, and NMOS transistor 114 is also calculated using equation (1). When current flows through these wires, a voltage drop occurs, and the voltage drop is larger when the resistance R is large. For example, if the resistance R is 1Ω, a voltage drop of 0.2V will occur when a current of 200mA flows. The larger this voltage drop, the smaller the decrease in the charging voltage to capacitors 151 and 152, and therefore the lower the charging efficiency.

[0066] In contrast, in the layout configuration of this embodiment shown in Figure 11, as described above, the shortest distance between the first part 116a of the transistor section 116 and pads 201c to 201j is almost zero, and the shortest distance between the second part 116b of the transistor section 116 and pads 201c to 201j is also almost zero. Therefore, for example, with respect to the PMOS transistor 111, the shortest distance is almost zero, and if the longest distance is d3, the resistance value R of the wiring connecting each of the pads 201i and 201j to the PMOS transistor 111 can be calculated roughly by equation (2) using the longest distance d3. In equation (2), Rp is the sheet resistance value of the wiring, and W is the wiring width.

[0067]

number

[0068] Here, from Figures 11 and 14, if we assume that the longest distance d3 in this embodiment is approximately half the longest distance d2 in the comparative example, then equation (2) is transformed into equation (3).

[0069]

number

[0070] Comparing equations (1) and (3), in the layout configuration of this embodiment, the resistance value R is reduced to 1 / 2 or less compared to the example configuration of the comparative example, and the voltage drop due to wiring resistance is reduced to 1 / 2 or less.

[0071] As described above, in this configuration, the PMOS transistors 111 are arranged adjacent to each other, sandwiching pads 201i and 201j. This shortens the wiring connecting the PMOS transistors 111 to pads 201i and 201j, thus reducing the wiring resistance. As a result, the voltage drop between the PMOS transistor 111 and the CPH terminal corresponding to pad 201i is reduced, as is the voltage drop between the PMOS transistor 111 and the VCP terminal corresponding to pad 201j.

[0072] Similarly, by arranging the NMOS transistors 112 adjacent to pads 201g and 201h, the wiring connecting the NMOS transistors 112 to pads 201g and 201h is shortened, thus reducing the wiring resistance. As a result, the voltage drop between the NMOS transistor 112 and the VDD terminal corresponding to pad 201g is reduced, as is the voltage drop between the NMOS transistor 112 and the CPH terminal corresponding to pad 201h.

[0073] Similarly, by arranging the PMOS transistors 113 adjacent to pads 201e and 201f, the wiring connecting the PMOS transistors 113 to pads 201e and 201f is shortened, thus reducing the wiring resistance. As a result, the voltage drop between the PMOS transistor 113 and the CPL terminal corresponding to pad 201e is reduced, as is the voltage drop between the PMOS transistor 113 and the VDD terminal corresponding to pad 201f.

[0074] Similarly, by arranging the NMOS transistors 114 adjacent to pads 201c and 201d, the wiring connecting the NMOS transistors 114 to pads 201c and 201d is shortened, thus reducing the wiring resistance. As a result, the voltage drop between the NMOS transistor 114 and the VSS terminal corresponding to pad 201c is reduced, as is the voltage drop between the NMOS transistor 114 and the CPL terminal corresponding to pad 201d.

[0075] Therefore, with the arrangement of the transistor section 116 and pads 201c to 201j shown in Figure 11, the drop in the charging voltage to capacitors 151 and 152 is reduced, improving charging efficiency and efficiently generating the desired drive voltage.

[0076] As shown in Figures 10 and 11, in a plan view of the semiconductor substrate 200 (plan view of the integrated circuit device 100), the transistor section 116, electrostatic protection circuits 121-126, and pads 201a-201k are located in region A1 at the corners of the semiconductor substrate 200 (corners of the integrated circuit device 100). Therefore, the distance between the edge 200a and the pads 201a-201k is relatively short, and it is possible to connect the pads 201a-201k to the electrodes provided on a substrate (not shown) on which the integrated circuit device 100 is mounted using bonding wires, thus reducing the constraints on the mounting method of the integrated circuit device 100.

[0077] Note that pads 201h and 201i are examples of "first pads," and pads 201d and 201e are examples of "second pads." Furthermore, pad 201j is another example of "first pads," and pads 201f and 201g are other examples of "second pads." Also, the Y direction is an example of "first direction," and the X direction is an example of "second direction."

[0078] 6. Effects As described above, in the integrated circuit device 100 of this embodiment, the first part 116a and the second part 116b of the transistor section 116 that controls the charging and discharging of capacitors 151 and 152 are arranged with pads 201c to 201j in between. Furthermore, pads 201a to 201k are arranged along the X direction, and the first part 116a and the second part 116b are arranged along the Y direction. As a result, the maximum distance between the transistor section 116 and 201c to 201j is shortened. Furthermore, none of the electrostatic protection circuits 121-126 are located between the first part 116a and the pads 201c-201j, nor between the second part 116b and the pads 201c-201j. Since the first part 116a and the second part 116b are located adjacent to the pads 201c-201j, the maximum distance between the transistor section 116 and the pads 201c-201j becomes shorter. As a result, the length of each wire connecting the transistor section 116 and the pads 201c-201j decreases, and the resistance of each wire decreases, thus reducing the voltage drop between the transistor section 116 and the pads 201c-201j. Consequently, according to the integrated circuit device 100 of this embodiment, the decrease in charging voltage to capacitors 151 and 152 due to wiring resistance is reduced, and the charging efficiency of capacitors 151 and 152 is improved.

[0079] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments or modified examples, and can be implemented in various forms without departing from its essence. For example, the above embodiments and their respective modifications can be combined as appropriate.

[0080] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0081] The following can be derived from the embodiments and modifications described above.

[0082] One embodiment of an integrated circuit device is: First pad and second pad connected to the capacitor, The device comprises a transistor section that controls the charging and discharging of the capacitor via the first pad and the second pad, In a plan view, the transistor portion includes a first portion and a second portion arranged between the first pad and the second pad.

[0083] In this integrated circuit device, the first and second parts of the transistor section that control the charging and discharging of the capacitor are arranged with the first and second pads in between, thus shortening the maximum distance between the transistor section and the first and second pads. As a result, the wiring connecting the transistor section to the first and second pads becomes shorter, and the resistance value of each wiring decreases, thus reducing the voltage drop between the transistor section and the first and second pads. Therefore, this integrated circuit device can reduce the decrease in the charging voltage to the capacitor caused by wiring resistance.

[0084] In one embodiment of the integrated circuit device, The first and second portions may be arranged adjacent to the first and second pads.

[0085] In this integrated circuit device, the maximum distance between the transistor section and the first and second pads is reduced, resulting in shorter wiring connections between the transistor section and the first and second pads. This reduces the resistance of each wiring, thus decreasing the voltage drop between the transistor section and the first and second pads. Consequently, this integrated circuit device can reduce the decrease in the charging voltage to the capacitor caused by wiring resistance.

[0086] In one embodiment of the integrated circuit device, The first and second portions are arranged along a first direction, and the first pad and the second pad may be arranged along a second direction intersecting the first direction.

[0087] In this integrated circuit device, the distance between the first part of the transistor section and the first and second pads is shortened, and the distance between the second part of the transistor section and the first and second pads is also shortened, so the voltage drop between the transistor section and the first and second pads is reduced. Therefore, with this integrated circuit device, the decrease in the charging voltage to the capacitor caused by wiring resistance can be reduced.

[0088] In one embodiment of the integrated circuit device, In a plan view, the first portion may be positioned between the first pad or the second pad and an electrostatic protection circuit connected to the first pad or the second pad.

[0089] In this integrated circuit device, the distance between the first portion of the transistor section and the first and second pads is shortened, thus reducing the voltage drop between the transistor section and the first and second pads. Therefore, this integrated circuit device can reduce the decrease in the charging voltage to the capacitor caused by wiring resistance.

[0090] In one embodiment of the integrated circuit device, In a plan view, the transistor portion may be positioned at the corner of the integrated circuit device.

[0091] In this integrated circuit device, the first or second portion is positioned between the first and second pads and the edges of the integrated circuit device. However, since the transistor portion is positioned at the corner of the integrated circuit device, the distance between that edge and the first and second pads becomes relatively small. Therefore, with this integrated circuit device, it is also possible to connect the first and second pads to external electrodes of the integrated circuit device with bonding wires, thus reducing constraints on the mounting method. [Explanation of Symbols]

[0092] 1…Multifunction device, 2…Printer unit, 3…Scanner unit, 4…Hinge section, 11…Upper frame, 12…Image reading section, 13…Top cover, 16…Bottom case, 17…Top case, 31…Sensor unit, 32…Sensor carriage, 33…Guide axis, 34…Sensor movement mechanism, 41…Image sensor module, 63…Operation section, 65…Device housing, 66…Outlet, 100…Integrated circuit device, 101a,101b…CDS circuit, 102a,102b…Adder, 103a,103b…D / A converter, 104a,104b…Programmable gain amplifier, 105…A / D conversion circuit, 106…Interface circuit, 107…Register, 108…Power supply circuit, 109…LED driver, 110…Switching circuit, 111…PMOS transistor, 111a …PMOS transistor, 112…NMOS transistor, 113…PMOS transistor, 114…NMOS transistor, 115…Control circuit, 116…Transistor section, 116a…First part, 116b…Second part, 121…Electrostatic protection circuit, 122…Electrostatic protection circuit, 123…Electrostatic protection circuit, 124…Electrostatic protection circuit, 125…Electrostatic protection circuit, 126…Electrostatic protection circuit, 150…Charge pump circuit, 151…Capacitor, 152…Capacitor, 200…Semiconductor substrate, 200a, 200b, 200c, 200d…Edges, 201, 201a~201k…Pads, 300…Control unit, 411…Case, 412…Light source, 412R…Red LED, 412G…Green LED, 412B…Blue LED, 413…Lens, 414…Module substrate, 415…Image reading chip

Claims

1. First pad and second pad connected to the capacitor, The device comprises a transistor section that controls the charging and discharging of the capacitor via the first pad and the second pad, In a plan view, the transistor portion includes a first portion and a second portion arranged on either side of the first pad and the second pad, respectively, in an integrated circuit device.

2. In claim 1, The first and second parts are arranged adjacent to the first and second pads in an integrated circuit device.

3. In claim 1, An integrated circuit device in which the first and second parts are arranged along a first direction, and the first pad and the second pad are arranged along a second direction intersecting the first direction.

4. In claim 1, An integrated circuit device in which, in a plan view, the first portion is positioned between the first pad or the second pad and an electrostatic protection circuit connected to the first pad or the second pad.

5. In any one of claims 1 to 4, In a plan view, the transistor portion is located at the corner of the integrated circuit device.

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