Manufacturing method of wiring boards

Abstract

To provide a method for manufacturing a wiring board that can form via conductors with high positional accuracy. [Solution] The method for manufacturing a wiring board according to the embodiment includes: preparing a support 10 having a metal film layer 12 formed on the upper surface of a support substrate 11; forming a resist layer 20 having openings corresponding to an alignment pattern on the upper surface of the metal film layer 12; forming a metal plating layer 31 on the upper surface of the metal film layer 12 within the openings to form an alignment pattern with the resist layer 20 and the metal plating layer 31; forming an insulating layer 41 so as to cover the upper surface of the metal plating layer 31 and the upper surface of the resist layer 20; forming through holes in the insulating layer 41 with reference to the position of the alignment pattern; filling the through holes with a conductive material to form via conductors; and removing the support 10.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board. A support having a metal layer on its upper surface is prepared, a resist layer having openings is formed on the metal layer, a plating layer is formed in the openings, and then the resist layer is removed to form a conductor layer having a pattern corresponding to the openings. After an insulating layer is formed so as to cover the conductor layer and the metal layer, through-holes for via conductors are formed in the insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, when the substrate material is viewed from above in a plan view, the difference in reflectance between the upper surface of the conductor layer formed by plating and the upper surface of the metal layer of the support is small, and the recognition of the pattern constituted by the conductor layer may be low. Therefore, when positioning the through-holes for via conductors using the pattern of the conductor layer, the positional accuracy may deteriorate.

Means for Solving the Problems

[0005] The present invention provides a method for manufacturing a wiring board, comprising: preparing a support having a metal film layer formed on the upper surface of a support substrate; forming a resist layer having openings corresponding to an alignment pattern on the upper surface of the metal film layer; forming a metal plating layer on the upper surface of the metal film layer within the openings to form an alignment pattern using the resist layer and the metal plating layer; forming an insulating layer so as to cover the upper surface of the metal plating layer and the upper surface of the resist layer; forming through holes in the insulating layer with reference to the positions of the alignment pattern; filling the through holes with a conductive material to form via conductors; and removing the support.

[0006] According to embodiments of the present invention, it is believed that the recognizability of the pattern formed by the conductive layer can be improved, and the positional accuracy of the through-holes for via conductors can be enhanced. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 2] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 3] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 4A] A plan view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 4B] A cross-sectional view of the wiring board shown in Figure 5A. [Figure 5] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 6] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 7] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 8] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 9] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 10]A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 11] A cross-sectional view illustrating one step in the manufacturing method of the wiring board according to the embodiment. [Figure 12] A cross-sectional view illustrating one step of a modified example of the manufacturing method of the wiring board according to the embodiment. [Figure 13] A cross-sectional view illustrating one step of a modified example of the manufacturing method of the wiring board according to the embodiment. [Figure 14] A cross-sectional view illustrating one step of a modified example of the manufacturing method of the wiring board according to the embodiment. [Figure 15] A cross-sectional view illustrating one step of a modified example of the manufacturing method of the wiring board according to the embodiment. [Modes for carrying out the invention]

[0008] A method for manufacturing a wiring board according to an embodiment will be described with reference to the drawings. The drawings illustrate the manufacturing process of a wiring board according to an embodiment. The configuration and shape of the wiring board illustrated in the drawings are merely examples of wiring boards manufactured by the manufacturing method according to the embodiment. The manufacturing process of the wiring board illustrated in the drawings shows a process of manufacturing a wiring board by alternately laminating three conductor layers and two insulating layers, but the laminated structure of the wiring board manufactured by the manufacturing method of the embodiment, as well as the number of conductor layers and insulating layers, are not limited to the laminated structure of the wiring board and the number of conductor layers and insulating layers, respectively, illustrated in the drawings. Furthermore, the referenced drawings are drawn to facilitate understanding of the features of the present invention, and the size and proportions of each component may not be accurate.

[0009] In the following explanation, the direction in which the conductor layer and insulating layer are laminated during the manufacturing process of a circuit board will be referred to as "upward" or "upward direction," and the surface facing upward will be referred to as the "top surface." The direction opposite to the lamination direction will be referred to as "downward" or "downward direction," and the surface facing downward will be referred to as the "bottom surface."

[0010] The manufacturing process for the wiring board manufacturing method of the embodiment will be explained with reference to Figures 1 to 11.

[0011] First, in the process shown in FIG. 1, a support 10 is prepared. As the support 10, one in which a metal film layer 12 is formed on the upper surface of a support substrate 11 is used. As the support substrate, any material such as a glass plate, a silicon plate, a metal foil, etc. can be used, but in this embodiment, preferably, a glass plate is used. The thickness of the support substrate 11 can be, for example, about 0.5 to 2.0 mm. The support 10 preferably includes a release layer 13 between the support substrate 11 and the metal film layer 12. Thereby, in the process shown in FIG. 8 described later, the wiring substrate can be easily removed from the support substrate 11.

[0012] The metal film layer 12 is formed of an arbitrary metal material, and can be formed of, for example, a metal material including copper, a copper alloy, nickel, a nickel alloy, titanium, or a titanium alloy. The metal film layer 12 can preferably be formed of a metal material including copper or a copper alloy. Thereby, in the process shown in FIG. 9 described later, the metal film layer 12 can be easily removed by an etching process. The metal film layer 12 is not limited to a single layer, and may have a multilayer structure using different metal materials. When the metal film layer 12 has a multilayer structure, the upper surface can preferably be formed of a metal material including copper or a copper alloy. For example, the metal film layer 12 may have a two-layer structure in which titanium is laminated on the lower layer and copper is laminated on the upper layer. The metal film layer 12 can be used as a power supply layer when forming the first conductor layer 31 using an electrolytic plating method in the process shown in FIG. 2 described later.

[0013] Furthermore, as shown in FIG. 1, a resist layer 20 is formed on the upper surface 12a of the metal film layer 12 of the support 10. The resist layer 20 has an opening 20x corresponding to an alignment pattern formed in the process shown in FIG. 2 described later in a region PA on the metal film layer 12. Also, the resist layer 20 has an opening 20y corresponding to a circuit wiring pattern in a region PB on the metal film layer 12. The thickness of the resist layer 20 is preferably 8 μm or more and 20 μm or less. The arrangement pitch of the circuit wiring pattern is, for example, about 2 to 10 μm. The arrangement pitch of the alignment pattern is not particularly restricted. Any shape can be used for the shape of the alignment pattern, and for example, it may be circular or annular in plan view.

[0014] The resist layer 20 is formed by applying a liquid or paste-like resist material made of a photosensitive resin composition containing, for example, an epoxy resin, a polyhydroxy ether resin, a phenol resin, or a polyimide resin onto the upper surface 12a of the metal film layer 12. The resist layer 20 may be formed by thermocompression bonding a film (for example, a dry film resist, etc.) made of a photosensitive resin composition containing, for example, an epoxy resin onto the upper surface 12a of the metal film layer 12. The applied or thermocompression-bonded resist material is exposed and developed using a mask having an appropriate opening pattern, whereby a resist layer 20 having openings 20x and 20y is formed. Note that the resist layer 20 may be formed by laminating a film-like resist material in which the openings 20x and 20y are formed in advance onto the upper surface 12a of the metal film layer 12.

[0015] Next, in the process shown in FIG. 2, a metal plating layer is formed in the opening 20x in the region PA and the opening 20y in the region PB. Specifically, a first conductor layer 31 made of a metal plating layer is formed on the upper surface 12a of the metal film layer 12 within the openings 20x and 20y. The first conductor layer 31 is formed by any metal plating layer formation method, and is formed, for example, by an electrolytic plating method or a electroless plating method. Further, the first conductor layer 31 may have a multilayer structure formed by different metal plating layer formation methods. When the first conductor layer 31 has a multilayer structure, it is desirable that the upper surface portion be formed by an electrolytic plating method or a electroless plating method. When the first conductor layer 31 is formed by an electrolytic plating method, the metal film layer 12 can be used as a power supply layer.

[0016] The first conductor layer 31 can be formed from any conductive material, but preferably from a conductive material containing copper, copper alloy, nickel, nickel alloy, titanium, or titanium alloy. When the first conductor layer 31 is formed by electroplating, from the viewpoint of formation efficiency, the same type of conductive material as that used for the metal film layer 12 may be used as the plating material. For example, if the upper surface of the metal film layer 12 is formed from a conductive material containing copper or a copper alloy, the first conductor layer 31 may also be formed from a conductive material containing copper or a copper alloy. Furthermore, if the first conductor layer 31 has a multilayer structure, each layer may be formed from a different conductive material.

[0017] As shown in Figure 2, an alignment pattern is formed by the resist layer 20 and the first conductor layer 31, which is a metal plating layer, within the region PA. As shown in the process in Figure 4A, which will be described later, the alignment pattern is formed to have an arbitrary shape when the wiring board is viewed from above, and is recognized by the difference between the reflectance R31 of the upper surface 31a of the first conductor layer 31 and the reflectance R20 of the upper surface 20a of the resist layer 20. Preferably, the reflectance R31 of the upper surface 31a of the first conductor layer 31 is three times or more than the reflectance R20 of the upper surface 20a of the resist layer 20. Specifically, it is desirable that the reflectance R31 is about 55% or more, and the reflectance R20 is about 10% or less.

[0018] In prior art documents, the resist layer is removed after the first wiring layer (corresponding to the first conductor layer 31) is formed. Removal of the resist layer exposes the upper surface of the support (copper foil) (corresponding to the upper surface of the metal film layer 12) in the region where the first wiring layer is not formed. In this case, the alignment pattern is formed by the first wiring layer and the copper foil, and is recognized by the difference between the reflectance of the upper surface of the first wiring layer and the reflectance of the upper surface of the copper foil. Both the first wiring layer and the copper foil are made of metallic materials, and if the first wiring layer is formed using copper foil as a power supply layer in an electroplating method, it may be formed from the same type of metallic material. In this case, the difference between the reflectance of the upper surface of the first wiring layer and the reflectance of the upper surface of the copper foil is small, and the contrast of the alignment pattern may be low, resulting in poor recognition.

[0019] As shown in Figure 2, if the resist layer 20 is not peeled off after the first conductor layer 31 is formed, and the resist layer 20 remains in the non-formed portion 31x of the first conductor layer 31, the alignment pattern is formed by the first conductor layer 31 and the resist layer 20. Since the first conductor layer 31 is made of a metallic material and the resist layer 20 is made of a resin material, the difference between the reflectance R31 of the upper surface 31a of the first conductor layer 31 and the reflectance R20 of the upper surface 20a of the resist layer 20 is greater than the difference between the reflectance R31 of the upper surface 31a of the first conductor layer 31 and the reflectance R12 of the upper surface 12a of the metal film layer 12. As a result, the contrast of the alignment pattern is increased, improving recognition, and the via openings 41x can be formed with high positional accuracy in the process shown in Figures 4A and 4B, which will be described later.

[0020] Next, in the process shown in Figure 3, a first insulating layer 41 is formed so as to cover the upper surface 31a of the first conductive layer 31, which is a metal plating layer, and the upper surface 20a of the resist layer 20. The first insulating layer 41 is formed using any insulating resin material. For example, the first insulating layer 41 can be formed using insulating resins such as epoxy resin, polyimide resin, BT resin (bismaleimide-triazine resin), polyphenylene ether resin, and phenolic resin. The first insulating layer 41 may also contain any of the following: fluororesin, liquid crystal polymer (LCP), fluoroethylene fluoride resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). The first insulating layer 41 may also contain inorganic fillers such as fine particles made of silica (SiO2), alumina, or mullite. The first insulating layer 41 may also be formed by heat-pressing an insulating resin molded into a film. The thickness of the first insulating layer 41 is, for example, 7 μm to 15 μm. Furthermore, if the first insulating layer 41 contains fillers, etc., the recognition of the alignment pattern may be reduced in the process shown in Figures 4A and 4B described later due to scattering and refraction caused by the fillers, etc. Therefore, the content of fillers, etc. may be adjusted to an extent that does not excessively reduce the recognition of the alignment pattern.

[0021] Next, in the process shown in Figures 4A and 4B, via openings 41x are formed in the first insulating layer 41 with reference to the position of the alignment pattern. Specifically, via openings 41x are formed in the first insulating layer 41 with reference to the via conductor formation position within the region PB where the circuit wiring pattern is formed. Figure 4A is a plan view of the wiring board during the process. Figure 4B is a cross-sectional view of the wiring board shown in Figure 4A along line II. As shown in Figure 4B, the via openings 41x penetrate the first insulating layer 41 in the thickness direction, exposing a portion of the upper surface 31a of the first conductor layer 31 at the bottom. The via openings 41 are formed by a laser processing method, for example, using a CO2 laser or a UV laser. When the via openings 41x are formed by a laser processing method, a cleaning (desmear) process is performed to remove the processing-modified material (smear) adhering to the upper surface 31a of the first conductor layer 31 exposed at the bottom of the via openings 41x. Plasma etching is preferably used for cleaning.

[0022] The via opening 41x formed by the laser processing method is, for example, a frustoconical recess in which the area of ​​the bottom surface is smaller than the area of ​​the top surface of the opening. With the increasing density and thinning of circuit wiring patterns on the wiring board, high precision is required for positioning when forming the via opening 41x. For positioning the via opening 41x, an alignment pattern formed in region PA is used. The alignment pattern can be formed in any shape, but for example, it may be annular as shown in Figure 4A. A data acquisition device such as a camera is installed so that the first alignment pattern can be viewed from above the first insulating layer 41, and the alignment pattern is acquired as image data. In the alignment pattern shown in Figure 4A, the peripheral and central parts are formed of the first conductor layer 31, and the annular part in between is formed of the resist layer 20. As described above, the reflectance R31 of the upper surface 31a of the first conductor layer 31 and the reflectance R20 of the upper surface 20a of the resist layer 20 have a difference of more than three times, so image data of the alignment pattern can be acquired with high contrast using a camera or the like. By recognizing the position of the wiring board using this image data of the alignment pattern, via openings 41x can be formed with high positional accuracy.

[0023] Next, the via conductor 32V and the second conductor layer 32 are formed in the process shown in Figure 5. The via conductor 32V is formed by filling the via opening 41x with a conductive material. The second conductor layer 32 is formed on the first insulating layer 41 and includes a circuit wiring pattern. The via conductor 32V is formed integrally with the second conductor layer 32. The second conductor layer 32 is electrically connected to the first conductor layer 31, which is exposed at the bottom of the via opening 41x, via the via conductor 32V. The second conductor layer 32 can be formed from any conductive material, but, like the first conductor layer 31, it is preferably formed from a conductive material containing copper, copper alloy, nickel, nickel alloy, titanium, or titanium alloy. The second conductor layer 32 may be formed from the same conductive material as the first conductor layer 31, or from a different conductive material.

[0024] The second conductor layer 32 is formed by any metal film formation method and may have a single-layer structure or a multilayer structure combining different metal film formation methods. If the second conductor layer 32 has a multilayer structure, each layer may be formed of a different conductor material. The second conductor layer 32 can be formed, for example, using a semi-additive method. In the semi-additive method, first, a seed layer (not shown) is formed on the upper surface 31a of the first conductor layer 31 exposed at the bottom of the via opening 41x, the side wall of the via opening 41x, and the first insulating layer 41 by sputtering or electroless plating. Furthermore, a resist layer (not shown) with an opening corresponding to the second conductor layer 32 is formed on the seed layer. Then, a plating layer (not shown) is formed in the opening of the resist layer by electroplating using the seed layer as a power supply layer. This forms a via conductor 32V within the via opening 41x. Subsequently, after the resist layer is removed, the seed layer in the portion not covered by the plating layer is removed by etching, using the plating layer as a mask. As a result, a second conductor layer 32, including a circuit wiring pattern, is formed on the first insulating layer 41.

[0025] Next, in the process shown in Figure 6, the same process as described using Figures 3 to 5 is repeated to laminate the second insulating layer 42 and the third conductor layer 33 on top of the first insulating layer 41 and the second conductor layer 32. In order to form via openings 42x in the second insulating layer 42, alignment patterns (not shown) are appropriately formed in appropriate areas of the second conductor layer 32 in the process shown in Figure 5, and these are used to position the via openings 42x. In the manufacturing method of the wiring board of this embodiment, as an example, a process for manufacturing a wiring board having three conductor layers and two insulating layers is shown, but it is not limited to this, and the number of laminated conductor layers and insulating layers may be greater. In this way, a build-up wiring layer is formed on the upper surface of the support 10.

[0026] The multiple conductor layers constituting the wiring board may be formed from the same conductor material or from different conductor materials. Furthermore, the multiple conductor layers may be formed using the same metal film formation method or from different metal film formation methods. The thickness of the conductor layers is, for example, about 3 μm to 6 μm. The multiple insulating layers constituting the wiring board may be formed using different insulating resins, but it is preferable that they be formed using the same insulating resin. Furthermore, it is preferable that the multiple insulating layers contain approximately the same amount of filler of the same composition. This can reduce warping in the wiring board. The thickness of the insulating layers is, for example, about 7 μm to 15 μm.

[0027] Next, in the process shown in Figure 7, the first solder resist layer 50 is formed so as to cover the upper surfaces of the third conductor layer 33 and the second insulating layer 42. The first solder resist layer 50 is formed using, for example, a photosensitive polyimide resin or epoxy resin, and an opening 50x is formed by photolithography technology. A portion of the upper surface 33a of the third conductor layer 33 is exposed in the opening 50x. The upper surface 33a of the third conductor layer 33 exposed in the opening 50x is used for electrical connection with electronic components mounted on the wiring board by soldering or the like.

[0028] Next, in the process shown in Figure 8, the support substrate 11 of the support 10 is removed. As described above, since the support 10 has a release layer 13 between the support substrate 11 and the metal thin film 12, the support substrate 11 can be easily removed. After the support substrate 11 is removed, the release layer 13 is removed. The release layer 13 is removed, for example, by a cleaning process using oxygen plasma.

[0029] Next, the metal film layer 12 is removed in the process shown in Figure 9. The metal film layer 12 is removed, for example, by wet etching. With the removal of the metal film layer 12, the lower surface 31b of the first conductor layer 31 and the lower surface 20b of the resist layer 20 are exposed.

[0030] Next, the resist layer 20 is removed in the process shown in Figure 10. The resist layer 20 is removed, for example, using a stripping solution. With the removal of the resist layer 20, the lower surface 41b of the first insulating layer 41, which was covered by the resist layer 20, is exposed.

[0031] Next, in the process shown in Figure 11, a second solder resist layer 60 is formed so as to cover the lower surface 31b of the first conductor layer 31 and the lower surface 41b of the first insulating layer 41. The second solder resist layer 60 is formed using, for example, a photosensitive polyimide resin or epoxy resin, similar to the first solder resist layer 50 shown in the process of Figure 7, and an opening 60x is formed by photolithography. A portion of the lower surface 31b of the first conductor layer 31 is exposed in the opening 60x. External connection terminals such as solder balls or lead pins may be formed on the lower surface 31b of the first conductor layer 31 that is exposed in the opening 60x. The external connection terminals are used as terminals for electrically or mechanically connecting to a mounting substrate (not shown), such as a motherboard. Alternatively, the first conductor layer 31 itself that is exposed in the opening 60x may serve as an external connection terminal.

[0032] Next, the manufacturing process for a modified example of the manufacturing method of the wiring board of the embodiment will be explained using Figures 1 to 8 and Figures 12 to 15. In the following, explanations of the same content as described above using Figures 1 to 8 will be omitted as appropriate, and only the differences from the above will be explained.

[0033] First, a support 10 is prepared using the same process as shown in Figure 1, and a resist layer 20 is formed on the upper surface 12a of the metal film layer 12 of the support 10. The resist layer 20 has openings 20x corresponding to alignment patterns in region PA on the metal film layer 12. The resist layer 20 also has openings 20y corresponding to circuit wiring patterns in region PB on the metal film layer 12.

[0034] Next, a first conductive layer 31 made of a metal plating layer is formed in the opening 20x in region PA and the opening 20y in region PB using a process similar to that shown in Figure 2.

[0035] Next, in the process shown in Figure 12, the resist layer 20 is partially removed. Specifically, as shown in Figure 12, the upper side of the resist layer 20 is partially removed by the stripping solution such that a portion of the resist layer 20 remains as residue 21 on the lower surface of the non-formed portion 31x of the first conductor layer 31. Since a portion of the resist layer 20 remains within the non-formed portion 31x of the first conductor layer 31, the upper surface 12a of the metal film layer 12 is not exposed. As a result, the alignment pattern is formed by the first conductor layer 31 and the residue 21. The thickness of the residue 21 is preferably 1 μm or more and 4 μm or less.

[0036] Next, in the process shown in Figure 13, the first insulating layer 41 is formed in the same manner as in the process shown in Figure 3, so as to cover the upper surface 31a of the first conductor layer 31 and the upper surface 21a of the residue 21.

[0037] Next, via openings 41x are formed in the first insulating layer 41 in the same manner as shown in Figures 4A and 4B, with reference to the positions of the alignment patterns. Specifically, via openings 41x are formed in the first insulating layer 41 at the positions where via conductors are formed within the region PB where the circuit wiring pattern is formed.

[0038] Next, the via conductor 32V and the second conductor layer 32 are formed in a process similar to that shown in Figure 5. The via conductor 32V is formed by filling the via opening 41x with conductor material. The second conductor layer 32 is formed on the first insulating layer 41 and includes a circuit wiring pattern. The via conductor 32V is formed integrally with the second conductor layer 32. The second conductor layer 32 is electrically connected to the first conductor layer 31, which is exposed at the bottom of the via opening 41x, via the via conductor 32V.

[0039] Next, by repeating the same process as shown in Figures 3 to 5, in the same manner as the process shown in Figure 6, the second insulating layer 42 and the third conductor layer 33 are laminated on top of the first insulating layer 41 and the second conductor layer 32. In the manufacturing method of the wiring board of this embodiment, as an example, a process for manufacturing a wiring board having three conductor layers and two insulating layers is shown, but it is not limited to this, and the number of laminated conductor layers and insulating layers may be greater.

[0040] Next, in a process similar to that shown in Figure 7, the first solder resist layer 50 is formed so as to cover the upper surfaces of the third conductor layer 33 and the second insulating layer 42.

[0041] Next, the support base material 11 of the support 10 is removed in a process similar to that shown in Figure 8.

[0042] Next, the metal film layer 12 is removed in the process shown in Figure 13. Removal of the metal film layer 12 exposes the lower surface 31b of the first conductor layer 31 and the lower surface 21b of the residue 21.

[0043] Next, the residue 21 is removed in the process shown in Figure 14. Removal of the residue 21 exposes the lower surface 41c of the first insulating layer 41, which was covered by the residue 21. Since the thickness of the residue 21 is less than the thickness of the resist layer 20, the residue 21 can be easily removed. Furthermore, after the residue 21 is removed, the step difference between the lower surface 31b of the first conductor layer 31 and the lower surface 41c of the first insulating layer 41 is smaller than the step difference between the lower surface 31b of the first conductor layer 31 and the lower surface 41b of the first insulating layer 41 shown in Figure 10, thus facilitating the formation of the second solder resist layer 60 in the process shown in Figure 15, which will be described later.

[0044] Next, in the process shown in Figure 15, a second solder resist layer 60 is formed so as to cover the lower surface 31b of the first conductor layer 31 and the lower surface 41c of the first insulating layer 41. The second solder resist layer 60 is formed using, for example, a photosensitive polyimide resin or epoxy resin, similar to the process shown in Figure 11, and an opening 60x is formed by photolithography. A portion of the lower surface 31b of the first conductor layer 31 is exposed in the opening 60x. External connection terminals such as solder balls or lead pins may be formed on the lower surface 31b of the first conductor layer 31 that is exposed in the opening 60x.

[0045] The method for manufacturing a wiring board in the embodiment is not limited to the method described with reference to Figures 1 to 15, and its conditions and sequence may be changed as appropriate. Depending on the structure of the wiring board to be manufactured, some steps in the method for manufacturing a wiring board may be omitted, or other steps may be added. In other words, the wiring board manufactured by the method for manufacturing a wiring board in the embodiment is not limited to the structure shown in Figures 1 to 15, and the number, size, and material of its constituent members may be changed as appropriate. Furthermore, depending on the required characteristics and functions of the wiring board, some members may be omitted, or other members may be added.

[0046] In the manufacturing method of the wiring board of this embodiment, a build-up wiring layer is formed only on one side (top surface) of the support 10, but wiring layers may also be formed on both sides (top and bottom surfaces) of the support 10. Alternatively, in the manufacturing process of the wiring board, a build-up wiring layer may be formed on one side of each of the two supports, and the supports may be bonded together on the sides where no wiring layer is formed. This may make processes such as multi-layering of wiring layers and cutting of the wiring board more efficient.

[0047] As described above, according to the manufacturing method of the wiring board of the embodiment, in the process of forming through holes for via conductors, the contrast when observing the alignment pattern is increased, improving the recognition of the alignment pattern and potentially improving the positional accuracy of the through holes. [Explanation of Symbols]

[0048] 1 Wiring board 10 Support 11 Supporting base material 12 Metal film layer 13. Exfoliation layer 20 resistance layers 21 Residue 31. First Conductor Layer 32 Second Conductor Layer 33 Third Conductor Layer 32V, 33V via conductors 41. First insulating layer 42 Second insulating layer 50 First Solder Resist Layer 60 Second Solder Resist Layer

Claims

1. A support is prepared in which a metal film layer is formed on the upper surface of the support substrate, A resist layer having openings corresponding to the alignment pattern is formed on the upper surface of the metal film layer. A metal plating layer is formed on the upper surface of the metal film layer within the opening, and an alignment pattern is formed by the resist layer and the metal plating layer. An insulating layer is formed so as to cover the upper surface of the metal plating layer and the upper surface of the resist layer. Referencing the position of the alignment pattern, through holes are formed in the insulating layer, The through-hole is filled with a conductive material to form a via conductor, A method for manufacturing a wiring board, comprising removing the support mentioned above.

2. A method for manufacturing a wiring board according to claim 1, After removing the support, The metal film layer is removed, exposing the lower surface of the resist layer and the lower surface of the metal plating layer. This further includes removing the resist layer and exposing the lower surface of the insulating layer.

3. A method for manufacturing a wiring board according to claim 1, Forming the alignment pattern is The method further includes partially removing the resist layer such that a portion of it, including the lower surface of the resist layer, remains.

4. A method for manufacturing a wiring board according to claim 2, The method further includes forming a solder resist layer so as to cover the lower surface of the insulating layer and the lower surface of the metal plating layer.

5. A method for manufacturing a wiring board according to claim 1, The position of the alignment pattern is referenced by identifying the difference between the reflectance of the upper surface of the metal plating layer and the reflectance of the upper surface of the resist layer.

6. A method for manufacturing a wiring board according to claim 5, The reflectance of the upper surface of the metal plating layer is three times or more the reflectance of the upper surface of the resist layer.

7. A method for manufacturing a wiring board according to claim 1, The support substrate is a glass substrate, a ceramic substrate, or a silicon substrate.

8. A method for manufacturing a wiring board according to claim 1, The metal film layer and the metal plating layer are formed from the same material.

9. A method for manufacturing a wiring board according to claim 1, The support has a release layer on the lower surface of the metal film layer.

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