Backend capacitor for memory cell and peripheral circuit, and method for forming the same

Abstract

The present invention provides a method and a device structure for forming a device structure that eliminates the need for additional masks, thereby reducing production costs and process complexity, while ensuring improved performance and scalability of the memory array and peripheral circuits. [Solution] An efficient method for simultaneously forming a memory node capacitor 60 and a voltage stabilization capacitor 160 in a semiconductor structure including a memory array region 100 and a peripheral device region 200, wherein these capacitors are integrated within a lower-level dielectric material layer 760 and a lower-level metal wiring structure 780, and high capacitance is achieved with a minimal device footprint by utilizing a dielectric capping layer 10 having memory region openings and peripheral region openings.

Description

Background Art

[0001] Capacitors are essential for devices such as gain cell memory cells. Manufacturing high-capacity capacitors with a minimum device footprint is a difficult task. Furthermore, integrating capacitors into both the memory array and the peripheral circuits increases production costs and process complexity, while simultaneously imposing potential limitations on the performance and scalability of the resulting memory devices.

Summary of the Invention

Problems to be Solved by the Invention

[0002] The present invention relates to a back-end capacitor for memory cells and peripheral circuits and a method of forming the same. The back-end capacitor includes an array of memory node capacitors and a voltage stabilization capacitor. Each of the memory node capacitors is a charge storage capacitor for each memory cell of the memory array, and the voltage stabilization capacitor is configured to stabilize the voltage of the peripheral circuits. [[ID=E16]]

Means for Solving the Problems

[0003] Various embodiments of the present invention provide an efficient method for simultaneously forming memory node capacitors and voltage stabilization capacitors within a semiconductor structure. By integrating these capacitors within a lower-level dielectric material layer and a lower-level metal wiring structure and utilizing a dielectric capping layer having memory region openings and peripheral region openings, this method addresses the problem of achieving high capacity with a minimum device footprint.

Advantages of the Invention

[0004] This approach eliminates the need for additional masks, thereby reducing production costs and process complexity while ensuring improved performance and scalability of the memory array and peripheral circuits.

Brief Description of the Drawings

[0005] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion. It should be noted that in a pseudo-vertical section view, elements may be arbitrarily placed within or outside the vertical plane of the view, and there may not be a specific physical vertical plane that displays all the elements shown in the pseudo-vertical section view.

[0006] [Figure 1] This is a vertical cross-sectional view of the structure of the first embodiment after the formation of the memory transistors, peripheral circuits, lower-level dielectric material layer and lower-level metal wiring structure for the memory array, according to the first embodiment of the present invention. [Figure 2A] This is a schematic circuit diagram of a two-transistor gain cell memory cell that can be used in the structure of the first embodiment. [Figure 2B] This is a schematic circuit diagram of a 3-transistor gain cell memory cell that can be used in the structure of the first embodiment. [Figure 3] This is a vertical cross-sectional view of the structure of the first embodiment after the formation of the dielectric capping layer, according to the first embodiment of the present invention. [Figure 4] This is a vertical cross-sectional view of the structure of the first embodiment after the formation of individual openings through the dielectric capping layer, according to the first embodiment of the present invention. [Figure 5] This is a vertical cross-sectional view of the structure of the first embodiment after deposition of a capacitor material layer stack, including a first electrode material layer, a node dielectric material layer, and a second electrode material layer, onto a dielectric capping layer, according to the first embodiment of the present invention. [Figure 6] This is a vertical cross-sectional view of the structure of the first embodiment after deposition of the hard mask material layer, according to the first embodiment of the present invention. [Figure 7] This is a vertical cross-sectional view of the structure of the first embodiment after the formation of the array of memory node capacitors and voltage stabilization capacitors according to the first embodiment of the present invention. [Figure 8A] This is a vertical cross-sectional view of the structure of the first embodiment after the formation of the upper-level dielectric material layer and the upper-level metal wiring structure according to the first embodiment of the present invention. [Figure 8B] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8C] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8D] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8E] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8F] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8G] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 8H] This is a vertical cross-sectional view of one of the alternative configurations of the first embodiment structure according to the first embodiment of the present invention. [Figure 9] This is a vertical cross-sectional view of the structure of the second embodiment after a capacitor material layer stack, including a first electrode material layer, a node dielectric material layer, and a second electrode material layer, has been deposited on a dielectric capping layer according to the second embodiment of the present invention. [Figure 10] This is a vertical cross-sectional view of the second embodiment structure after various second electrodes have been formed by performing a planarization process according to the second embodiment of the present invention. [Figure 11] This is a vertical cross-sectional view of the second embodiment structure after the array hard mask plate and peripheral hard mask plate have been formed according to the second embodiment of the present invention. [Figure 12] This is a vertical cross-sectional view of the second embodiment structure after forming the array of memory node capacitors and the voltage stabilization capacitor according to the second embodiment of the present invention. [Figure 13A]A vertical cross-sectional view of the structure of the second embodiment after forming the upper-level dielectric material layer and the upper-level metal wiring structure according to the second embodiment of the present invention. [Figure 13B] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13C] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13D] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13E] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13F] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13G] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 13H] A vertical cross-sectional view of one of the alternative configurations of the structure of the second embodiment according to the second embodiment of the present invention. [Figure 14] A vertical cross-sectional view of the structure of the third embodiment after forming various second electrodes by performing a planarization process according to the third embodiment of the present invention. [Figure 15] A vertical cross-sectional view of the structure of the third embodiment after forming an array of memory node capacitors and voltage stabilization capacitors according to the first embodiment of the present invention. [Figure 16A] A vertical cross-sectional view of the structure of the third embodiment after forming the upper-level dielectric material layer and the upper-level metal wiring structure according to the third embodiment of the present invention. [Figure 16B] A vertical cross-sectional view of one of the alternative configurations of the structure of the third embodiment according to the third embodiment of the present invention. <( [Figure 16C] A vertical cross-sectional view of one of the alternative configurations of the structure of the third embodiment according to the third embodiment of the present invention. [Figure 16D]This is a vertical cross-sectional view of one of the alternative configurations of the third embodiment structure according to the third embodiment of the present invention. [Figure 16E] This is a vertical cross-sectional view of one of the alternative configurations of the third embodiment structure according to the third embodiment of the present invention. [Figure 16F] This is a vertical cross-sectional view of one of the alternative configurations of the third embodiment structure according to the third embodiment of the present invention. [Figure 17] This is a vertical cross-sectional view of the fourth embodiment structure after a metal-filled material layer has been formed according to the fourth embodiment of the present invention. [Figure 18] This is a vertical cross-sectional view of the fourth embodiment structure after an array of memory damascene pads and at least one peripheral damascene pad have been formed according to the fourth embodiment of the present invention. [Figure 19] This is a vertical cross-sectional view of the fourth embodiment structure after depositing a capacitor material layer stack including a first electrode material layer, a node dielectric material layer, and a second electrode material layer, and a hard mask material layer on a dielectric capping layer according to the fourth embodiment of the present invention. [Figure 20] This is a vertical cross-sectional view of the fourth embodiment structure after forming the array of memory node capacitors and voltage stabilization capacitors according to the fourth embodiment of the present invention. [Figure 21A] This is a vertical cross-sectional view of the fourth embodiment structure after forming the upper-level dielectric material layer and the upper-level metal wiring structure according to the fourth embodiment of the present invention. [Figure 21B] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21C] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21D] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21E] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21F]This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21G] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21H] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21I] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21J] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 21K] This is a vertical cross-sectional view of one of the alternative configurations of the fourth embodiment structure according to the fourth embodiment of the present invention. [Figure 22] This is a first flowchart showing the sequence of processing steps for forming the semiconductor structure of the present invention. [Figure 23] This is a second flowchart showing the sequence of processing steps for forming the semiconductor structure of the present invention. [Modes for carrying out the invention]

[0007] The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to facilitate understanding of the invention. These are merely examples and not limiting. The drawings are not drawn to scale. Elements having the same reference number refer to the same element and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise. Embodiments in which multiple instances of a described element are repeated are expressly contemplated unless expressly indicated otherwise. Embodiments in which non-essential elements are omitted are expressly contemplated even if such embodiments are known in the art but are not expressly disclosed.

[0008] Furthermore, spatial relative terms such as “down,” “below,” “lower,” “up,” and “above” may be used herein for ease of description to describe the relationship between one element or feature and another, as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented in a different way (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0009] The present invention relates generally to semiconductor device structures and methods for manufacturing the same. Specifically, the present invention relates to a device structure and method for manufacturing the same, including memory node capacitors for memory arrays and voltage stabilization capacitors used in peripheral circuits. Peripheral circuits and memory array transistors may be formed on a semiconductor substrate. Lower-level metal wiring structures may be formed within dielectric material layers. Dielectric capping layers having memory region openings and peripheral region openings may be formed. Capacitor material layer stacks may be deposited and patterned to form memory node capacitors and voltage stabilization capacitors. This process addresses the challenge of manufacturing high-capacitance capacitors with a minimal device footprint and integrates capacitors into both memory arrays and peripheral circuits without requiring additional masks, thereby reducing production costs and process complexity. Embodiments of the present invention may be used to improve the performance and scalability of memory devices by efficiently integrating high-capacitance capacitors into both memory arrays and peripheral circuits. Various aspects of the present invention are described with reference to the accompanying drawings.

[0010] Referring to Figure 1, a structure of a first embodiment for forming a memory array and a voltage stabilization capacitor is shown. As used herein, a voltage stabilization capacitor refers to any capacitor configured to maintain a stable voltage supply by mitigating fluctuations in a power supply circuit, thereby ensuring consistent performance and reliability of the power supply circuit in operation. Voltage stabilization capacitors help stabilize voltage levels in a power supply circuit, protecting sensitive components from voltage spikes and voltage drops that could potentially affect data integrity, processing speed, or any other performance metric of the power supply circuit. Non-limiting examples of voltage stabilization capacitors include charge pump capacitors, bypass capacitors, and decoupling capacitors, which are known in the art.

[0011] The structure of the first embodiment includes a semiconductor substrate 9, which may be any type of semiconductor substrate known in the art. For example, the semiconductor substrate 9 may include a single-crystal silicon substrate, a compound semiconductor substrate, a semiconductor on an insulator (SOI) substrate, etc. An isolation structure 702, such as a shallow trench isolation structure, may be formed on top of the semiconductor substrate 9. Various semiconductor devices may be formed on the semiconductor substrate 9. The structure of the first embodiment may include a memory array region 100 on which a memory array is later formed, and a peripheral device region 200 on which peripheral devices and at least one voltage stabilizing capacitor are later formed. Various semiconductor devices may include transistors, such as field-effect transistors, which include their respective pairs of source / drain regions 2 and their respective gate electrodes 5. A source / drain metal-semiconductor alloy region 8 (such as a metal silicide region) may be formed on the source / drain regions 2. As used herein, the source / drain regions may refer to the source region and / or drain region individually or collectively, depending on the context. Furthermore, it should be noted that the source / drain regions may, depending on the operating mode, operate as either a source region or a drain region. Generally, any type of field-effect transistor known in the art may be formed on the semiconductor substrate 9.

[0012] A subset of transistors formed in the memory array region 100 and used as components of the memory array is referred to herein as memory transistors 710. The circuits formed by the interconnections of the memory transistors 710 are referred herein as memory transistor circuits 720. Electrical connections to and from the memory transistors 710 may be provided by metal wiring structures formed within a dielectric material layer. The metal wiring structures are referred herein as lower-level metal wiring structures 780, and the dielectric material layer is referred herein as lower-level dielectric material layer 760. In one embodiment, the type of memory cell in the memory array formed within the first embodiment structure may be of a type that uses at least one field-effect transistor and a memory node capacitor per memory cell. For example, the type of memory cell in the memory array may be a gain cell (GC) memory cell that uses two or three transistors and memory node capacitors per memory cell. In this embodiment, all components of the memory array may be formed and interconnected in this processing step, except for the array of memory node capacitors.

[0013] The doped semiconductor wells 102 may be formed within the semiconductor substrate 9. The metal-semiconductor alloy regions 108 may be formed on a subset of the doped semiconductor wells 102. At least one doped semiconductor well 102 and optionally at least one metal-semiconductor alloy region 108 may function as an electrical ground for a subset of the nodes of a later-formed capacitor. A subset of the lower-level metal wiring structure 780 may be electrically connected to at least one doped semiconductor well 102 and optionally at least one metal-semiconductor alloy region 108.

[0014] Additional semiconductor devices, such as additional transistors, may be formed in the peripheral device region 200 to provide peripheral circuits 740, which may be any type of circuit known in the art. For example, peripheral circuits 740 may include logic circuits for operating a memory array that is formed later. In this embodiment, peripheral circuits 740 may include word line driver circuits, bit line driver circuits, sense amplifier circuits, address decoder circuits, data latch and buffer circuits, input / output controller circuits, etc. Additionally or alternatively, peripheral circuits 740 may include power supply circuits that are later electrically connected to voltage stabilization capacitors. Electrical connections to and from the peripheral circuits 740 to various nodes may be provided by additional lower-level metal wiring structures 780 formed within the lower-level dielectric material layer 760. Generally, lower-level metal wiring structures 780 may include, but are not limited to, metal wiring structures, metal via structures, metal pad structures, integrated metal wiring and via structures, etc., any type of metal wiring structure known in the art.

[0015] While Figure 1 illustrates two metal wiring interconnection levels, it should be understood that the number of metal wiring levels used to provide electrical connections within the memory transistor circuit 720 and peripheral circuit 740 may be selected depending on the complexity of the electrical connections within the memory transistor circuit 720 and peripheral circuit 740. The number of metal wiring levels may generally range from 1 to 10, but a larger number may also be used.

[0016] Generally, peripheral circuits 740 may be formed on the semiconductor substrate 9 in the peripheral device region 200, and the transistors of the memory array may be formed on the semiconductor substrate 9 in the memory array region 100. The combination of the lower-level metal wiring structure 780 and the lower-level dielectric material layer 760 may be formed on the semiconductor substrate 9 so as to provide appropriate electrical connections to the memory transistor circuit 720 and the peripheral circuits 740.

[0017] Referring to Figure 2A, a schematic circuit diagram of a two-transistor gain cell memory cell is shown, which may be used in the structure of the first embodiment in Figure 1. The two-transistor gain cell memory cell includes a combination of a write transistor WT, a read transistor RT, and a memory node capacitor. The source node of the write transistor WT may be connected to the write bit line WBL, the gate electrode of the write transistor WT may be connected to the write word line WWL, and the drain node of the write transistor WT may be connected to the gate electrode of the read transistor RT. The drain node of the write transistor WT is also connected to the first electrode of the memory node capacitor and functions as a storage node SN where charge is stored. The second electrode of the memory node capacitor may be electrically grounded. The source node of the read transistor RT may be connected to the source bit line SBL, and the drain node of the read transistor RT may be connected to the read bit line RBL. The read transistor RT and the write transistor WT may include a pair of memory transistors 710 as shown in Figure 1.

[0018] Referring to Figure 2B, a schematic circuit diagram of a 3-transistor gain cell memory cell is shown, which may be used in the structure of the first embodiment in Figure 1. The 3-transistor gain cell memory cell shown in Figure 2B may be derived from the 2-transistor gain cell memory cell shown in Figure 2A by replacing the read transistor RT with a series connection of a first read transistor RT1 and a second read transistor RT2. The drain node of the write transistor WT is connected to the gate electrode of the first read transistor RT1. The source node of the first read transistor RT1 is connected to the source bit line SBL. The drain node of the first read transistor RT1 is connected to the source node of the second read transistor RT2. The drain node of the second read transistor RT2 is connected to the read bit line RBL. The gate electrode of the second read transistor RT2 is connected to the read word line RWL.

[0019] It should be understood that the exemplary configurations of the gain cell memory cell shown in Figures 2A and 2B are merely illustrative, and any alternative configuration of the gain cell memory cell may be used. Furthermore, embodiments of the present invention are not limited to gain cell memory cells and may be used in any type of memory device using at least one memory transistor 710 and a memory node capacitor. For example, a charge storage memory cell using an access transistor and a memory node capacitor may be used in the same way as a dynamic random access memory device. Generally, an array of memory transistors 710 used in a memory array may be formed and electrically wired in the first embodiment structure shown in Figure 1, and an array of memory node capacitors may be formed subsequently and electrically connected to the array of memory transistors 710.

[0020] Referring to Figure 3, the metal pad may be formed within the dielectric material layer, or it may be formed as a subset of the lower-level metal wiring structure 780. In one embodiment, an additional lower-level dielectric material layer 760 may be formed on top of the lower-level dielectric material layer 760 provided in the first embodiment structure shown in Figure 1, and the metal pad may be formed within the additional lower-level dielectric material layer 760. Alternatively, the metal pad may be formed at the top level of the lower-level dielectric material layer 760 provided in the first embodiment structure shown in Figure 1.

[0021] The metal pads may include an array of connecting metal pads 781 formed in the memory array region 100. Each of the connecting metal pads 781 may be electrically connected to one of the memory transistors 710. For example, each of the connecting metal pads 781 may include components of the storage node SN shown in Figures 2A and 2B, and may be electrically connected to the gate electrode of the read transistor and the drain node of the write transistor. The metal pads may further include peripheral region metal pads 782 formed together with the peripheral device region 200. Generally, the array of connecting metal pads 781 and the peripheral region metal pads 782 may be formed at the top level of the lower-level dielectric material layer 760. The upper surfaces of the array of connecting metal pads 781 and the peripheral region metal pads 782 may be formed in a horizontal plane including the upper surface of the top layer selected from the lower-level dielectric material layer 760. Generally, each of the lower-level dielectric material layers 760 may contain any interlayer dielectric (ILD) material known in the art, such as undoped silicate glass, doped silicate glass, organosilicate glass, or silicon nitride.

[0022] According to one aspect of the present invention, the dielectric capping layer 10 may be formed as a continuous dielectric material layer on a lower-level dielectric material layer 760. In one embodiment, the dielectric capping layer 10 may be formed directly on the upper surface of the connecting metal pad 781 and directly on the upper surface of the peripheral region metal pad 782. The dielectric capping layer 10 includes a dielectric material which may subsequently be used as an etching stop material layer during a subsequent anisotropic etching process that patterns the memory node capacitor and voltage stabilization capacitor. For example, the dielectric capping layer 10 may include silicon carbide, silicon carbide nitride, silicon carbide oxide, silicon nitride, or dielectric metal oxide (aluminum oxide, hafnium oxide, etc.). The thickness of the dielectric capping layer 10 may be in the range of 5 nm to 60 nm, for example, in the range of 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0023] Referring to Figure 4, discrete openings (19, 29) may be formed through the dielectric capping layer 10. Specifically, a photoresist layer 17 may be coated on the dielectric capping layer 10 and lithographically patterned to form openings therein. The pattern of openings within the photoresist layer 17 may be selected such that the area range of each opening within the photoresist layer 17 is entirely located within the periphery of the underlying metal pads (781, 782). An etching process may be performed to transfer the pattern of openings within the photoresist layer 17 through the dielectric capping layer 10. The etching process may include an anisotropic etching process such as a reactive ion etching process, or an isotropic etching process such as a wet etching process. Generally, the chemical properties of the etching process for etching the material of the dielectric capping layer 10 may be selective to the metallic material of the underlying metal pads (781, 782). An array of memory region openings 19 may be formed in the memory array region 100, and at least one peripheral region opening 29 may be formed in the peripheral device region 200. The array of connecting metal pads 781 may be physically exposed beneath the array of memory area openings 19. The peripheral area metal pads 782 may be physically exposed beneath at least one of the peripheral area openings 29. The photoresist layer 17 may be subsequently removed, for example, by ashing.

[0024] Referring to Figure 5, a capacitor material layer stack (20L, 30L, 40L) including a first electrode material layer 20L, a node dielectric material layer 30L, and a second electrode material layer 40L may be deposited on the dielectric capping layer 10. The first electrode material layer 20L includes and / or is essentially composed of a first metallic material. In one embodiment, the first metallic material may be, for example, a conductive metal nitride material (such as TiN, TaN, WN, or MoN) or a refractory metal (such as W, Mo, Ta, Nb, or Re) having a melting point higher than 2,000 degrees Celsius and providing sufficient resistance to metal diffusion and / or contamination to the surrounding dielectric material. The first electrode material layer 20L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the first electrode material layer 20L may be in the range of 5 nm to 60 nm, for example, in the range of 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0025] The first electrode material layer 20L may be deposited within the array of memory region openings 19 and within at least one peripheral region opening 29. In one embodiment, the first electrode material layer 20L may be deposited directly on the physically exposed upper segments of the array of connecting metal pads 781, the side walls of the memory region openings 19, the physically exposed upper segments of the peripheral region metal pads 782, the side walls of each peripheral region opening 29, and the upper surface of the dielectric capping layer 10. In one embodiment, the first electrode material layer 20L may be formed with vertical undulations in its vertical cross-sectional profile, and the first electrode material layer 20L includes a first horizontally extending portion 20H1 having areaal overlap with the dielectric capping layer 10 in a plan view, a second horizontally extending portion 20H2 located within the region of the array of memory region openings 19 and at least one peripheral region opening 29, and tubular connecting portions 20C connecting each periphery of the second horizontally extending portion 20H2 to the periphery of each opening within the first horizontally extending portion 20H1. As used herein, plan views are views aligned vertically. In one embodiment, the tubular connectors 20C may have a taper in a vertical cross-sectional view, and the outer walls of each tubular connector 20C may have a taper angle ranging from 5 to 60 degrees with respect to the vertical. Generally, the topographic features of the openings (19, 29) penetrating the dielectric capping layer 10 may be replicated on the upper surface of the first electrode material layer 20L with respect to the size of the openings (19, 29) penetrating the dielectric capping layer 10, accompanied by a lateral shift (e.g., reduction) of the lateral range of each recessed surface segment on the upper surface of the first electrode material layer 20L.

[0026] The node dielectric material layer 30L comprises and / or essentially consists of a dielectric material suitable as the node dielectric of the capacitor. In one embodiment, the node dielectric material layer 30L comprises a dielectric material having a dielectric constant of at least 7.9. In one embodiment, the node dielectric material layer 30L comprises and / or essentially consists of a dielectric metal oxide such as silicon nitride, aluminum oxide, or transition metal oxide. The node dielectric material layer 30L may be deposited by chemical vapor deposition or atomic layer deposition. The thickness of the node dielectric material layer 30L may be in the range of 4 nm to 12 nm, for example, in the range of 5 nm to 8 nm, but smaller and larger thicknesses may also be used.

[0027] The node dielectric material layer 30L may be deposited as a continuous material layer having a uniform thickness throughout. In one embodiment, the node dielectric material layer 30L may be formed with vertical undulations in the vertical cross-sectional profile, and as a result, the node dielectric material layer 30L includes a first horizontal extension 30H1 that overlaps in area with the dielectric capping layer 10 in the plan view, a second horizontal extension 30H2 located within the area of ​​the array of memory region openings 19 and at least one peripheral region opening 29, and tubular connecting portions 30C that connect each periphery of the second horizontal extension 30H2 to the periphery of each opening in the first horizontal extension 30H1. In one embodiment, the tubular connecting portions 30C may have a taper in the vertical cross-sectional view, and as a result, the outer wall of each tubular connecting portion 30C may have a taper angle in the range of 5 to 60 degrees with respect to the vertical. Generally, the topographic features of the openings (19, 29) penetrating the dielectric capping layer 10 may be replicated on the upper surface of the nodal dielectric material layer 30L with respect to the size of the openings (19, 29) penetrating the dielectric capping layer 10, such as a lateral shift, including a reduction in the lateral range of each recessed surface segment on the upper surface of the nodal dielectric material layer 30L.

[0028] The second electrode material layer 40L contains and / or essentially consists of a second metallic material. The second metallic material may be the same as the first metallic material or may be different from the first metallic material. The second metallic material may contain any material that may be used as the first electrode material. The second electrode material layer 40L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the second electrode material layer 40L may be in the range of 5 nm to 60 nm, for example, in the range of 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0029] In one embodiment, the second electrode material layer 40L is formed with vertical undulations in its vertical cross-sectional profile, and as a result, the second electrode material layer 40L includes a first horizontal extension 40H1 having areaal overlap with the dielectric capping layer 10 in a plan view, a second horizontal extension 40H2 located within the region of the array of memory region openings 19 and at least one peripheral region opening 29, and tubular connectors 40C connecting each periphery of the second horizontal extension 40H2 to the periphery of each opening in the first horizontal extension 40H1. As used herein, a plan view is a view along the vertical direction. In one embodiment, the tubular connectors 40C may have a taper in a vertical cross-sectional view, and as a result, the outer wall of each tubular connector 40C may have a taper angle ranging from 5 to 60 degrees with respect to the vertical direction. Generally, the topographic features of the openings (19, 29) penetrating the dielectric capping layer 10 may be replicated on the upper surface of the second electrode material layer 40L with respect to the size of the openings (19, 29) penetrating the dielectric capping layer 10, such as a lateral shift, including a reduction in the lateral range of each recessed surface segment on the upper surface of the second electrode material layer 40L. Thus, the upper surface of the second electrode material layer 40L may be formed having vertically recessed surface segments that overlap the array of memory region openings 19 and at least one peripheral region opening 29.

[0030] Referring to Figure 6, the hard mask material layer 50L may be deposited as desired. The hard mask material layer 50L includes hard mask materials such as silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or dielectric metal oxides (such as aluminum oxide or transition metal oxides). The thickness of the hard mask material layer 50L may be in the range of 5 nm to 100 nm, for example, in the range of 10 nm to 50 nm, but smaller and larger thicknesses may also be used. The hard mask material layer 50L may be deposited, for example, by chemical vapor deposition or atomic layer deposition.

[0031] Referring to Figure 7, a photoresist layer (not shown) may be applied on top of the hard mask material layer 50L and lithographically patterned into a two-dimensional array of discrete photoresist material portions overlapping the array of connecting metal pads 781 and a photoresist material portion overlapping the peripheral region metal pads 782. A first anisotropic etching process may be performed to transfer the pattern within the patterned photoresist material portions through the hard mask material layer 50L. The patterned portion of the hard mask material layer 50L includes an array hard mask plate 50 formed in the memory array region 100 and at least one peripheral hard mask plate 150 formed in the peripheral device region 200. The photoresist layer may then be removed by ashing.

[0032] A second anisotropic etching process may be performed to transfer patterns in the array hard mask plate 50 and at least one peripheral hard mask plate 150 through the capacitor material layer stack (20L, 30L, 40L). In this embodiment, the combination of the array hard mask plate 50 and at least one peripheral hard mask plate 150 may be used as an etching mask for etching the material of the capacitor material layer stack (20L, 30L, 40L). The second anisotropic etching process may have a selective etching chemistry for the material of the dielectric capping layer 10. In an alternative embodiment, the removal of the photoresist layer used as an etching mask for patterning the hard mask material layer 50L may be performed after the second anisotropic etching process.

[0033] Each sidewall of the patterned portion of the second electrode material layer 40L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150. Each sidewall of the patterned portion of the node dielectric material layer 30L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150. Each sidewall of the patterned portion of the first electrode material layer 20L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150.

[0034] Generally, the capacitor material layer stack (20L, 30L, 40L) may be patterned by transferring the pattern in the array of array hard mask plates 50 and at least one peripheral hard mask plate 150 through at least the node dielectric material layer 30L and the first electrode material layer 20L using an anisotropic etching process that selectively etches the material of the capacitor material layer stack (20L, 30L, 40L) against the material of the dielectric capping layer 10. The patterned portion of the capacitor material layer stack (20L, 30L, 40L) remaining in the memory array region 100 includes an array of memory node capacitors 60. The patterned portion of the capacitor material layer stack (20L, 30L, 40L) remaining in the peripheral device region 200 includes voltage stabilization capacitors 160. Thus, the capacitor material layer stack (20L, 30L, 40L) may be patterned to include an array of memory node capacitors 60 and voltage stabilization capacitors 160.

[0035] Each memory node capacitor 60 includes a vertical stack of a first memory capacitor electrode 20, a memory capacitor node dielectric 30, and a second memory capacitor electrode 40. Each first memory capacitor electrode 20 is a patterned portion of the first electrode material layer 20L. Each memory capacitor node dielectric 30 is a patterned portion of the node dielectric material layer 30L. Each second memory capacitor electrode 40 is a patterned portion of the second electrode material layer 40L. The voltage stabilizing capacitor 160 includes a vertical stack of a first stabilizing capacitor electrode 120, a stabilizing capacitor node dielectric 130, and a second stabilizing capacitor electrode 140. The first stabilizing capacitor electrode is a patterned portion of the first electrode material layer 20L. The stabilizing capacitor node dielectric 130 is a patterned portion of the node dielectric material layer 30L. The second stabilizing capacitor electrode 140 is a patterned portion of the second electrode material layer 40L.

[0036] According to one aspect of the present invention, each of the memory node capacitors 60 is a charge storage capacitor for each memory cell of the memory array. The sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may coincide perpendicularly with each other, that is, they may be located in the same vertical plane. Furthermore, the sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may coincide perpendicularly with the sidewalls of the array hard mask plate 50 that overlaps them. In one embodiment, the sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may be located completely outside the area defined by the sidewalls of the connecting metal pad 781 located below them in a plan view, i.e., in a view along the vertical direction. In other words, the area range of each connecting metal pad 781 may be entirely contained within the area range of the memory node capacitor 60 that overlaps it in the plan view, thereby offsetting the periphery of each metal pad 781 laterally inward with respect to the periphery of the memory node capacitor 60 that overlaps it.

[0037] Generally, each of the memory node capacitors 60 includes a first memory capacitor electrode 20 electrically connected to one of the respective connecting metal pads 781. In one embodiment, each second memory capacitor electrode 40 may be formed on a contoured upper surface having a vertically recessed surface segment that overlaps the respective memory region opening 19.

[0038] The peripheral region metal pad 782 is electrically short-circuited (i.e., electrically coupled) with the first stabilizing capacitor electrode 120 when the first stabilizing capacitor electrode 120 is formed. In one embodiment, each of the first stabilizing capacitor electrode 120, the stabilizing capacitor node dielectric 130, and the second stabilizing capacitor electrode 140 may be formed on their respective contoured upper surfaces, each including a set of at least one vertically recessed surface segments that overlap over at least one peripheral region opening 29 in the dielectric capping layer 10.

[0039] The structure of the first embodiment includes an array of memory node capacitors 60 that overlaps a lower-level dielectric material layer 760 that overlaps the transistors. A lower-level metal wiring structure 780 may be formed within the lower-level dielectric material layer 760 and includes an array of connecting metal pads 781 that are electrically connected to one of each of the transistors and to one of the first electrodes (i.e., first memory capacitor electrodes 20) of each of the memory node capacitors 60. A voltage stabilizing capacitor 160 may be located on the lower-level dielectric material layer 760 and may be configured to stabilize the voltage of the peripheral circuit 740. A dielectric capping layer 10 overlaps the array of connecting metal pads 781 and includes an array of memory region openings 19 that provide electrical connections between the first electrodes (i.e., first memory capacitor electrodes 20) and the array of connecting metal pads 781, and further includes at least one peripheral region opening 29 that is located below or laterally surrounds the first stabilizing capacitor electrode 120.

[0040] In one embodiment, each first memory capacitor electrode 20 of the memory node capacitor 60 includes a first horizontal extension 20H1 that overlaps the dielectric capping layer 10, and a downward projection adjacent to the inner circumference of the first horizontal extension 20H1, projecting downward relative to the first horizontal extension 20H1 and filling one of each of the memory region openings 19. Each memory capacitor node dielectric 30 may have vertical undulations in its vertical cross-sectional profile and may include a first horizontal extension 30H1 that overlaps in area with the dielectric capping layer 10 in its plan view, a second horizontal extension 30H2 within one region of the memory region opening 19, and a tubular connecting portion 30C that connects the periphery of the second horizontal extension 30H2 to the periphery of the opening in the first horizontal extension 30H1.

[0041] Referring to Figure 8A, an upper-level dielectric material layer 770 and an upper-level metal wiring structure 790 may be formed to provide electrical connections to and from the second memory capacitor electrode 40, the second stabilizing capacitor electrode 140, and the lower-level metal wiring structure 780. The upper-level metal wiring structure 790 may include an array electrode contact via structure 791 in contact with one of each of the second memory capacitor electrodes 40, at least one peripheral upper electrode contact via structure 793 in contact with the second stabilizing capacitor electrode 140, a peripheral lower electrode contact via structure 795 extending vertically through the dielectric capping layer 10 and in contact with the peripheral region metal pad 782, and connection via structures 797 in contact with each metal wiring or each metal pad which may be formed within the lower-level dielectric material layer 760. Furthermore, the upper-level metal wiring structure 790 may include a memory area upper metal wiring 792 that contacts a plurality of array electrode contact via structures 791, and at least one peripheral area metal wiring 794 that contacts each subset of the peripheral upper electrode contact via structures 793.

[0042] In one embodiment, the upper metal wiring 792 of the memory area may contact a connection via structure 797 electrically connected to an electrical ground node, which may include a doped semiconductor well 102 and a semiconductor substrate 9. In some embodiments, one of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be electrically grounded, and the other of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be connected to a power node of a circuit such as a peripheral circuit 740. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically grounded through a peripheral lower electrode contact via structure 795. In this embodiment, the upper metal wiring 792 of the memory area may contact the peripheral lower electrode contact via structure 795. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes an electrical node (which may or may not be a power node) that is not electrically short-circuited (i.e., not unintentionally electrically coupled) to any of the connection metal pads 781.

[0043] Figures 8B to 8F are vertical cross-sectional views of an alternative configuration to the structure of the first embodiment according to the first embodiment of the present invention.

[0044] Referring to Figure 8B, a first alternative configuration of the first embodiment structure may be derived from the first embodiment structure of Figure 8A by directly connecting the peripheral region metal pad 782 to a lower-level metal wiring structure 780, such as a metal via structure. In this embodiment, the connecting via structure 797 may be formed directly on the upper surface of the peripheral region metal pad 782.

[0045] Referring to Figure 8C, a second alternative configuration of the first embodiment structure may be derived from the first alternative configuration of the first embodiment structure in Figure 8B by connecting each peripheral upper electrode contact via structure 793 to a single peripheral region metal wiring 794.

[0046] Referring to Figure 8D, a third alternative configuration of the first embodiment structure may be derived from a second alternative configuration of the first embodiment structure in Figure 8B by using a single peripheral upper electrode contact via structure 793.

[0047] Referring to Figure 8E, a fourth configuration of the first embodiment structure may be derived from the first embodiment structure of Figure 8A by electrically grounding the second stabilizing capacitor electrode 140 through the peripheral upper electrode contact via structure 793. In this embodiment, the upper metal wiring 792 of the memory area may be in contact with the peripheral upper electrode contact via structure 793. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes a power node that is not directly connected to the connecting metal pad 781. For example, the first stabilizing capacitor electrode 120 may be electrically connected to the power node through the peripheral lower electrode contact via structure 795, the peripheral area metal wiring 794, and the connecting via structure 797.

[0048] Referring to Figure 8F, a fifth alternative configuration of the first embodiment structure may be derived from the fourth alternative configuration of the first embodiment structure in Figure 8E by directly connecting the peripheral region metal pad 782 to a lower-level metal wiring structure 780, such as a metal via structure. In this embodiment, the peripheral lower electrode contact via structure 795 may be omitted.

[0049] Referring to Figure 8G, a sixth alternative configuration of the first embodiment structure may be derived from any of the above configurations of the first embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically coupled to either of the connecting metal pads 781. In one embodiment, the second stabilizing capacitor electrode 140 may be electrically short-circuited to a power node through the peripheral lower electrode contact via structure 795, peripheral region metal wiring 794, and connecting via structure 797.

[0050] Referring to Figure 8H, the seventh alternative configuration of the first embodiment structure may be derived from any of the above configurations of the first embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically coupled to either of the connecting metal pads 781. In one embodiment, the first stabilizing capacitor electrode 120 and the peripheral region metal pad 782 may be electrically short-circuited to the power node through the peripheral region metal pad 782.

[0051] Referring to Figures 8A to 8H together, the memory array may include an array of gain cell transistors, and the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure 780.

[0052] Referring to Figure 9, the structure of the second embodiment is shown after depositing a capacitor material layer stack (20L, 30L, 40L) including a first electrode material layer 20L, a node dielectric material layer 30L, and a second electrode material layer 40L on the dielectric capping layer 10. The structure of the second embodiment may be formed by performing the processing steps described with reference to Figures 1, 3, 4, and 5.

[0053] Referring to Figure 10, a planarization process may be performed to remove the portion of the second electrode material layer 40L that overlaps with the horizontal plane including the top surface of the node dielectric material layer 30L. For example, a chemical mechanical polishing (CMP) process may be performed to remove the portion of the second electrode material layer 40L that overlaps with the horizontal plane including the top surface of the node dielectric material layer 30L. Each discrete remaining portion of the second electrode material layer 40L formed on each memory region opening 19 constitutes a second memory capacitor electrode 40. Each second memory capacitor electrode 40 may have a lateral range that is smaller than the lateral range of the memory region opening 19 located beneath each of them in the dielectric capping layer 10, and that is entirely located within that lateral range.

[0054] At least one remaining portion of the second electrode material layer 40L may be formed in the peripheral device region 200. Each remaining portion of the second electrode material layer 40L is referred to herein as a second stabilizing capacitor electrode 140. Each second stabilizing capacitor electrode 140 may have a lateral range that is smaller than the lateral range of the peripheral region opening 29 located beneath each of them in the dielectric capping layer 10, and that is entirely located within that lateral range. The second memory capacitor electrode 40 is the upper electrode of an array of memory node capacitors that are formed later, and each second stabilizing capacitor electrode 140 is the upper electrode of a voltage stabilizing capacitor that is formed later. In one embodiment, all upper surfaces of the second memory capacitor electrode 40 and at least one second stabilizing capacitor electrode 140 may be formed in a horizontal plane including the uppermost planar surface of the node dielectric material layer 30L.

[0055] Referring to Figure 11, a hard mask material layer may be formed on the node dielectric material layer 30L and various second electrodes (40, 140) by performing the processing steps described with reference to Figure 6. A photoresist layer (not shown) may be coated on the hard mask material layer and lithographically patterned with a two-dimensional array of discrete photoresist material portions overlapping on the array of connecting metal pads 781 and photoresist material portions overlapping on peripheral region metal pads 782. A first anisotropic etching process may be performed to transfer the pattern within the patterned photoresist material portions through the hard mask material layer. The patterned portions of the hard mask material layer 50L include an array hard mask plate 50 formed in the memory array region 100 and at least one peripheral hard mask plate 150 formed in the peripheral device region 200. The photoresist layer may then be removed by ashing.

[0056] Referring to Figure 12, a second anisotropic etching process may be performed to transfer the patterns in the array hard mask plate 50 and at least one peripheral hard mask plate 150 through a capacitor material layer stack (20L, 30L, 40) including a first electrode material layer 20L, a node dielectric material layer 30L, and various second electrodes (40, 140). In this embodiment, the combination of the array hard mask plate 50 and at least one peripheral hard mask plate 150 may be used as an etching mask for etching the material of the capacitor material layer stack (20L, 30L, 40). The second anisotropic etching process may have an etching chemistry that selectively etches the material of the node dielectric material layer 30L and the first electrode material layer 20L relative to the material of the dielectric capping layer 10. The entirety of the second electrodes (40, 140) may be covered by the array hard mask plate 50 and at least one peripheral hard mask plate 150 during the second anisotropic etching process. Therefore, the second electrode (40, 140) is not etched during the second anisotropic etching process.

[0057] Each sidewall of the second electrode (40, 140) is laterally recessed inward from the periphery of the portion that overlaps the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively. Each sidewall of the patterned portion of the node dielectric material layer 30L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively. Each sidewall of the patterned portion of the first electrode material layer 20L may coincide perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively.

[0058] Generally, the capacitor material layer stack (20L, 30L, 40) may be patterned by transferring the pattern in the array of array hard mask plates 50 and at least one peripheral hard mask plate 150 through at least the node dielectric material layer 30L and the first electrode material layer 20L using an anisotropic etching process that selectively etches the material of the capacitor material layer stack (20L, 30L, 40) relative to the material of the dielectric capping layer 10. The patterned portion of the capacitor material layer stack (20L, 30L, 40) remaining in the memory array region 100 includes an array of memory node capacitors 60. The patterned portion of the capacitor material layer stack (20L, 30L, 40) remaining in the peripheral device region 200 includes a voltage stabilization capacitor 160. Thus, the capacitor material layer stack (20L, 30L, 40) may be patterned to include an array of memory node capacitors 60 and a voltage stabilization capacitor 160.

[0059] Each memory node capacitor 60 includes a vertical stack of a first memory capacitor electrode 20, a memory capacitor node dielectric 30, and a second memory capacitor electrode 40. Each first memory capacitor electrode 20 is a patterned portion of the first electrode material layer 20L. Each memory capacitor node dielectric 30 is a patterned portion of the node dielectric material layer 30L. Each second memory capacitor electrode 40 is a patterned portion of the second electrode material layer 40L. The voltage stabilizing capacitor 160 includes a vertical stack of a first stabilizing capacitor electrode 120, a stabilizing capacitor node dielectric 130, and a second stabilizing capacitor electrode 140. The first stabilizing capacitor electrode is a patterned portion of the first electrode material layer 20L. The stabilizing capacitor node dielectric 130 is a patterned portion of the node dielectric material layer 30L. The second stabilizing capacitor electrode 140 is a patterned portion of the second electrode material layer 40L.

[0060] According to one aspect of the present invention, each of the memory node capacitors 60 is a charge storage capacitor for each memory cell of the memory array. The sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may coincide perpendicularly with each other, that is, they may be located in the same vertical plane. Furthermore, the sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may coincide perpendicularly with the sidewalls of the array hard mask plate 50 that overlaps them. In one embodiment, the sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may be located completely outside the area defined by the sidewalls of the connecting metal pad 781 located below them, in a plan view, i.e., in a view along the vertical direction. In other words, the area range of each connecting metal pad 781 may be entirely contained within the area range of the first memory capacitor electrode 20 that overlaps it in the plan view, thereby offsetting the periphery of each metal pad 781 laterally inward with respect to the periphery of the first memory capacitor electrode 20 that overlaps it.

[0061] In one embodiment, the sidewalls of the second memory capacitor electrodes 40 within each memory node capacitor 60 may be located entirely within the area defined by the sidewalls of the connecting metal pads 781 located beneath them in a plan view. In other words, the area range of each second memory capacitor electrode 40 may be entirely contained within the area range of the connecting metal pads 781 located beneath them in a plan view, thereby offsetting the periphery of each metal pad 781 laterally outward with respect to the periphery of the second memory capacitor electrode 40 overlapping it. Generally, each of the memory node capacitors 60 includes a first memory capacitor electrode 20 electrically connected to one of the connecting metal pads 781.

[0062] The peripheral region metal pad 782 may be electrically coupled to the first stabilizing capacitor electrode 120 during its formation. In one embodiment, each of the first stabilizing capacitor electrode 120 and the stabilizing capacitor node dielectric 130 may be formed on an upper surface having respective contours including each set of at least one vertically recessed surface segments that overlap over at least one peripheral region opening 29 in the dielectric capping layer 10.

[0063] The structure of the second embodiment includes an array of memory node capacitors 60 that overlaps a lower-level dielectric material layer 760 that overlaps the transistors. The lower-level metal wiring structure 780 may be formed within the lower-level dielectric material layer 760 and includes an array of connecting metal pads 781 that are electrically connected to one of each of the transistors and to one of the first electrodes (i.e., first memory capacitor electrodes 20) of each of the memory node capacitors 60. A voltage stabilizing capacitor 160 may be located on the lower-level dielectric material layer 760 and may be configured to stabilize the voltage of the peripheral circuit 740. The dielectric capping layer 10 overlaps the array of connecting metal pads 781 and includes an array of memory region openings 19 that provide electrical connections between the first electrodes (i.e., first memory capacitor electrodes 20) and the array of connecting metal pads 781, and further includes at least one peripheral region opening 29 that is located below or laterally surrounds the first stabilizing capacitor electrode 120.

[0064] In one embodiment, each first memory capacitor electrode 20 of the memory node capacitor 60 includes a first horizontal extension 20H1 that overlaps the dielectric capping layer 10, and a downward projection adjacent to the inner circumference of the first horizontal extension 20H1, projecting downward relative to the first horizontal extension 20H1 and filling one of each of the memory region openings 19. Each memory capacitor node dielectric 30 may have vertical undulations in its vertical cross-sectional profile and may include a first horizontal extension 30H1 that overlaps in area with the dielectric capping layer 10 in its plan view, a second horizontal extension 30H2 within one region of the memory region opening 19, and a tubular connecting portion 30C that connects the periphery of the second horizontal extension 30H2 to the periphery of the opening in the first horizontal extension 30H1.

[0065] In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as a memory capacitor node dielectric 30) that contacts the upper surface of a first electrode (i.e., a first memory capacitor electrode 20), and a second electrode (i.e., a second stabilized capacitor electrode 140) having an upper surface located in a horizontal plane including the upper surface of the node dielectric (such as the memory capacitor node dielectric 30). In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as the memory capacitor node dielectric 30) having side walls, and is contacted by the lower surface of an array hard mask plate 50 having side walls that coincide perpendicularly with the side walls of the node dielectric (such as the memory capacitor node dielectric 30).

[0066] Referring to Figure 13A, an upper-level dielectric material layer 770 and an upper-level metal wiring structure 790 may be formed to provide electrical connections to and from the second memory capacitor electrode 40, the second stabilizing capacitor electrode 140, and the lower-level metal wiring structure 780. The upper-level metal wiring structure 790 may include an array electrode contact via structure 791 in contact with one of each of the second memory capacitor electrodes 40, at least one peripheral upper electrode contact via structure 793 in contact with the second stabilizing capacitor electrode 140, a peripheral lower electrode contact via structure 795 in contact with the first stabilizing capacitor electrode 120, and connection via structures 797 in contact with each metal wiring or each metal pad which may be formed in the lower-level dielectric material layer 760. Furthermore, the upper-level metal wiring structure 790 may include a memory region upper metal wiring 792 in contact with a plurality of array electrode contact via structures 791, and at least one peripheral region metal wiring 794 in contact with each subset of the peripheral upper electrode contact via structures 793. The peripheral lower electrode contact via structure 795 extends vertically over portions of the stabilizing capacitor node dielectric 130 that are not located beneath any of the second stabilizing capacitor electrodes 140.

[0067] In one embodiment, the upper metal wiring 792 of the memory area may contact a connection via structure 797 electrically connected to an electrical ground node, the electrical ground node may include a doped semiconductor well 102 and a semiconductor substrate 9. In some embodiments, one of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be electrically grounded, and the other of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be connected to a power node of a circuit such as a peripheral circuit 740. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically grounded through a peripheral lower electrode contact via structure 795. In this embodiment, the upper metal wiring 792 of the memory area may contact the peripheral lower electrode contact via structure 795. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes an electrical node (which may or may not be a power node) that is not electrically coupled to any of the connection metal pads 781.

[0068] Figures 13B to 13H are vertical cross-sectional views of an alternative configuration of the second embodiment structure according to the second embodiment of the present invention.

[0069] Referring to Figure 13B, the first alternative configuration of the second embodiment structure may be derived from the second embodiment structure of Figure 13A by forming at least one hole (such as an array of holes) through the peripheral region metal pad 782, or by forming multiple peripheral region metal pads 782 (such as a two-dimensional array of peripheral region metal pads 782) instead of a single peripheral region metal pad 782.

[0070] Referring to Figure 13C, a second alternative configuration of the second embodiment structure may be derived from the second embodiment structure of Figure 13A by directly connecting the peripheral region metal pad 782 to a lower-level metal wiring structure 780, such as a metal via structure. In this embodiment, the connecting via structure 797 may be formed directly on the upper surface of the peripheral region metal pad 782.

[0071] Referring to Figure 13D, a third alternative configuration of the second embodiment structure may be derived from the second embodiment structure of Figure 13B by electrically grounding the second stabilizing capacitor electrode 140 through the peripheral upper electrode contact via structure 793. In this embodiment, the memory area upper metal wiring 792 may be in contact with the peripheral upper electrode contact via structure 793. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes a power node that is not directly connected to the connecting metal pad 781. For example, the first stabilizing capacitor electrode 120 may be electrically connected to the power node through the peripheral lower electrode contact via structure 795, the peripheral area metal wiring 794, and the connecting via structure 797.

[0072] Referring to Figure 13E, a fourth configuration of the second embodiment structure may be derived from the second embodiment structure of Figure 13A by forming at least one hole (such as an array of holes) through the peripheral region metal pad 782, or by forming multiple peripheral region metal pads 782 (such as a two-dimensional array of peripheral region metal pads 782) instead of a single peripheral region metal pad 782.

[0073] Referring to Figure 13F, a fifth alternative configuration of the second embodiment structure may be derived from the fourth alternative configuration of the second embodiment structure in Figure 13E by directly connecting the peripheral region metal pad 782 to a lower-level metal wiring structure 780, such as a metal via structure. In this embodiment, the peripheral lower electrode contact via structure 795 may be omitted.

[0074] Referring to Figure 13G, a sixth alternative configuration of the second embodiment structure may be derived from any of the above configurations of the second embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically coupled to either of the connecting metal pads 781. In one embodiment, the second stabilizing capacitor electrode 140 may be electrically short-circuited to the power node through the peripheral lower electrode contact via structure 795, peripheral region metal wiring 794, and connecting via structure 797.

[0075] Referring to Figure 13H, the seventh alternative configuration of the second embodiment structure may also be derived from any of the above configurations of the second embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically coupled to either of the connecting metal pads 781. In one embodiment, the first stabilizing capacitor electrode 120 and the peripheral region metal pad 782 may be electrically short-circuited to the power node through the peripheral region metal pad 782.

[0076] Referring to Figures 13A to 13H comprehensively, the memory array may include an array of gain cell transistors, and the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure 780.

[0077] Referring to Figure 14, a third embodiment structure according to a third embodiment of the present invention is shown, which may be derived from the second embodiment structure shown in Figure 10 by omitting the formation of the peripheral region metal pad 782. In this embodiment, each portion of the first electrode material layer 20L located within at least one peripheral region opening 29 may be in contact with the dielectric surface of the lower level dielectric material layer 760. The total number of at least one second stabilizing capacitor electrode 140 and the area range of each second stabilizing capacitor electrode 140 may be selected to minimize dishing of the at least one second stabilizing capacitor electrode 140 during a chemical mechanical polishing process that patterns the at least one second stabilizing capacitor electrode 140.

[0078] Referring to Figure 15, the processing steps described with reference to Figure 11 may be performed to form the array hard mask plate 50 and at least one peripheral hard mask plate 150. Subsequently, a second anisotropic etching process may be performed to transfer the patterns in the array hard mask plate 50 and at least one peripheral hard mask plate 150 through a capacitor material layer stack (20L, 30L, 40) including a first electrode material layer 20L, a node dielectric material layer 30L, and various second electrodes (40, 140). In this embodiment, the combination of the array hard mask plate 50 and at least one peripheral hard mask plate 150 may be used as an etching mask for etching the material of the capacitor material layer stack (20L, 30L, 40). The second anisotropic etching process may have an etching chemistry that selectively etches the material of the node dielectric material layer 30L and the material of the first electrode material layer 20L with respect to the material of the dielectric capping layer 10. The entire second electrode (40, 140) may be covered by the array hard mask plate 50 and at least one peripheral hard mask plate 150 during the second anisotropic etching process. Therefore, the second electrode (40, 140) is not etched during the second anisotropic etching process.

[0079] Each sidewall of the second electrode (40, 140) is laterally recessed inward from one peripheral portion that overlaps the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively. Each sidewall of the patterned portion of the node dielectric material layer 30L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively. Each sidewall of the patterned portion of the first electrode material layer 20L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively.

[0080] Generally, the capacitor material layer stack (20L, 30L, 40) may be patterned by transferring the pattern in the array of array hard mask plates 50 and at least one peripheral hard mask plate 150 through at least the node dielectric material layer 30L and the first electrode material layer 20L, using an anisotropic etching process that selectively etches the material of the capacitor material layer stack (20L, 30L, 40) relative to the material of the dielectric capping layer 10. The patterned portion of the capacitor material layer stack (20L, 30L, 40) remaining in the memory array region 100 includes an array of memory node capacitors 60. The patterned portion of the capacitor material layer stack (20L, 30L, 40) remaining in the peripheral device region 200 includes a voltage stabilization capacitor 160. Thus, the capacitor material layer stack (20L, 30L, 40) may be patterned to include an array of memory node capacitors 60 and a voltage stabilization capacitor 160.

[0081] Each memory node capacitor 60 includes a vertical stack of a first memory capacitor electrode 20, a memory capacitor node dielectric 30, and a second memory capacitor electrode 40. Each first memory capacitor electrode 20 is a patterned portion of the first electrode material layer 20L. Each memory capacitor node dielectric 30 is a patterned portion of the node dielectric material layer 30L. Each second memory capacitor electrode 40 is a patterned portion of the second electrode material layer 40L. The voltage stabilizing capacitor 160 includes a vertical stack of a first stabilizing capacitor electrode 120, a stabilizing capacitor node dielectric 130, and a second stabilizing capacitor electrode 140. The first stabilizing capacitor electrode is a patterned portion of the first electrode material layer 20L. The stabilizing capacitor node dielectric 130 is a patterned portion of the node dielectric material layer 30L. The second stabilizing capacitor electrode 140 is a patterned portion of the second electrode material layer 40L.

[0082] According to one aspect of the present invention, each of the memory node capacitors 60 is a charge storage capacitor for each memory cell of the memory array. The sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may coincide perpendicularly with each other, that is, they may be located in the same vertical plane. Furthermore, the sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may coincide perpendicularly with the sidewalls of the array hard mask plate 50 that overlaps them. In one embodiment, the sidewalls of the first memory capacitor electrode 20 and the memory capacitor node dielectric 30 within each memory node capacitor 60 may be located completely outside the area defined by the sidewalls of the connecting metal pad 781 located below them, in a plan view, i.e., in a view along the vertical direction. In other words, the area range of each connecting metal pad 781 may be entirely contained within the area range of the first memory capacitor electrode 20 that overlaps it in the plan view, thereby offsetting the periphery of each metal pad 781 laterally inward with respect to the periphery of the first memory capacitor electrode 20 that overlaps it.

[0083] In one embodiment, the sidewalls of the second memory capacitor electrodes 40 within each memory node capacitor 60 may be located entirely within the area defined by the sidewalls of the connecting metal pads 781 located beneath them in a plan view. In other words, the area range of each second memory capacitor electrode 40 may be entirely contained within the area range of the connecting metal pads 781 located beneath them in a plan view, thereby offsetting the periphery of each metal pad 781 laterally outward with respect to the periphery of the second memory capacitor electrode 40 overlapping it. Generally, each memory node capacitor 60 includes a first memory capacitor electrode 20 electrically connected to one of the connecting metal pads 781.

[0084] The peripheral region metal pad 782 is electrically short-circuited with the first stabilizing capacitor electrode 120 during its formation. In one embodiment, each of the first stabilizing capacitor electrode 120 and the stabilizing capacitor node dielectric 130 may be formed on an upper surface having respective contours including each set of at least one vertically recessed surface segments that overlap over at least one peripheral region opening 29 in the dielectric capping layer 10.

[0085] The structure of the third embodiment includes an array of memory node capacitors 60 that overlaps a lower-level dielectric material layer 760 that overlaps the transistors. The lower-level metal wiring structure 780 may be formed within the lower-level dielectric material layer 760 and includes an array of connecting metal pads 781 that are electrically connected to one of each of the transistors and to one of the first electrodes (i.e., first memory capacitor electrodes 20) of each of the memory node capacitors 60. A voltage stabilizing capacitor 160 may be located on the lower-level dielectric material layer 760 and may be configured to stabilize the voltage of the peripheral circuit 740. The dielectric capping layer 10 overlaps the array of connecting metal pads 781 and includes an array of memory region openings 19 that provide electrical connections between the first electrodes (i.e., first memory capacitor electrodes 20) and the array of connecting metal pads 781, and further includes at least one peripheral region opening 29 that is located below or laterally surrounds the first stabilizing capacitor electrode 120.

[0086] In one embodiment, each first memory capacitor electrode 20 of the memory node capacitor 60 includes a first horizontal extension 20H1 that overlaps the dielectric capping layer 10, and a downward projection adjacent to the inner circumference of the first horizontal extension 20H1, projecting downward relative to the first horizontal extension 20H1 and filling one of each of the memory region openings 19. Each memory capacitor node dielectric 30 may have vertical undulations in its vertical cross-sectional profile and may include a first horizontal extension 30H1 that overlaps in area with the dielectric capping layer 10 in its plan view, a second horizontal extension 30H2 within one region of the memory region opening 19, and a tubular connecting portion 30C that connects the periphery of the second horizontal extension 30H2 to the periphery of the opening in the first horizontal extension 30H1.

[0087] In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as a memory capacitor node dielectric 30) that contacts the upper surface of a first electrode (i.e., a first memory capacitor electrode 20), and a second electrode (i.e., a second stabilized capacitor electrode 140) having an upper surface located in a horizontal plane including the upper surface of the node dielectric (such as the memory capacitor node dielectric 30). In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as the memory capacitor node dielectric 30) having side walls, and is contacted by the lower surface of an array hard mask plate 50 having side walls that coincide perpendicularly with the side walls of the node dielectric (such as the memory capacitor node dielectric 30).

[0088] Referring to Figure 16A, an upper-level dielectric material layer 770 and an upper-level metal wiring structure 790 may be formed to provide electrical connections to and from the second memory capacitor electrode 40, the second stabilizing capacitor electrode 140, and the lower-level metal wiring structure 780. The upper-level metal wiring structure 790 may include an array electrode contact via structure 791 in contact with one of each of the second memory capacitor electrodes 40, at least one peripheral upper electrode contact via structure 793 in contact with the second stabilizing capacitor electrode 140, a peripheral lower electrode contact via structure 795 in contact with the first stabilizing capacitor electrode 120, and connection via structures 797 in contact with each metal wiring or each metal pad which may be formed in the lower-level dielectric material layer 760. Furthermore, the upper-level metal wiring structure 790 may include a memory region upper metal wiring 792 in contact with a plurality of array electrode contact via structures 791, and at least one peripheral region metal wiring 794 in contact with each subset of the peripheral upper electrode contact via structures 793. The peripheral lower electrode contact via structure 795 extends vertically over portions of the stabilizing capacitor node dielectric 130 that are not located beneath any of the second stabilizing capacitor electrodes 140.

[0089] In one embodiment, the upper metal wiring 792 of the memory area may contact a connecting via structure 797 electrically connected to an electrical ground node, which may include a doped semiconductor well 102 and a semiconductor substrate 9. In some embodiments, one of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be electrically grounded, and the other of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be connected to a power node of a circuit such as a peripheral circuit 740. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically grounded through a peripheral lower electrode contact via structure 795. In this embodiment, the upper metal wiring 792 of the memory area may contact the peripheral lower electrode contact via structure 795. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes an electrical node (which may or may not be a power node) that is not electrically short-circuited to any of the connecting metal pads 781.

[0090] Figures 16B to 16F are vertical cross-sectional views of an alternative configuration of the third embodiment structure according to the third embodiment of the present invention.

[0091] Referring to Figure 16B, the first alternative configuration of the third embodiment structure is achieved by forming a single peripheral upper electrode contact via structure 793 instead of multiple peripheral upper electrode contact via structures 793, as shown in Figure 16 This may be derived from the structure of the third embodiment of A.

[0092] Referring to Figure 16C, a second alternative configuration of the third embodiment structure may be derived from the third embodiment structure of Figure 16A by electrically grounding the second stabilizing capacitor electrode 140 through the peripheral upper electrode contact via structure 793. In this embodiment, the memory area upper metal wiring 792 may be in contact with the peripheral upper electrode contact via structure 793. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes a power node that is not directly connected to the connecting metal pad 781. For example, the first stabilizing capacitor electrode 120 may be electrically connected to the power node through the peripheral lower electrode contact via structure 795, the peripheral area metal wiring 794, and the connecting via structure 797.

[0093] Referring to Figure 16D, a third alternative configuration of the third embodiment structure may be derived from the second configuration of the third embodiment structure in Figure 16C by forming a single peripheral region opening 29 instead of multiple peripheral region openings 29. In this embodiment, the first stabilizing capacitor electrode 120 may include a single recessed region formed within the single peripheral region opening 29.

[0094] Referring to Figure 16E, a fourth alternative configuration of the third embodiment structure may be derived from any of the above configurations of the third embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically short-circuited to either of the connecting metal pads 781. In one embodiment, the second stabilizing capacitor electrode 140 may be electrically short-circuited to the power node.

[0095] Referring to Figure 16F, a fifth alternative configuration of the third embodiment structure may be derived from any of the above configurations of the third embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically short-circuited to either of the connecting metal pads 781. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically short-circuited to the power node through the peripheral lower electrode contact via structure 795, the peripheral region metal wiring 794, and the connecting via structure 797.

[0096] Referring to Figures 16A to 16F comprehensively, the memory array may include an array of gain cell transistors, and the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure 780.

[0097] Referring to Figure 17, the fourth embodiment structure according to the fourth embodiment of the present invention may be derived from the first embodiment structure shown in Figure 4 by removing the photoresist layer 17 and depositing a metal-filled material layer 22L. The metal-filled material layer 22L may be deposited within the array of memory region openings 19, within at least one peripheral region opening 29, and on the dielectric capping layer 10. The metal-filled material layer 22L may include, and / or consist essentially of, a conductive metal nitride material (such as TiN, TaN, WN, or MoN) or a refractory metal (such as W, Mo, Ta, Nb, or Re) with a melting point higher than 2,000 degrees Celsius and providing sufficient resistance to metal diffusion and / or contamination to the surrounding dielectric material. The metal-filled material layer 22L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the first electrode material layer 20L may be in the range of 10 nm to 100 nm, for example, in the range of 20 nm to 40 nm, but smaller and larger thicknesses may also be used.

[0098] Referring to Figure 18, a planarization process may be performed to remove the portion of the metal-filled material layer 22L from above the horizontal plane including the upper surface of the dielectric capping layer 10. For example, a chemical mechanical polishing process may be performed to remove the metallic material from the metal-filled material layer 22L from above the horizontal plane including the upper surface of the dielectric capping layer 10. The dielectric capping layer 10 may be used as a planarization stopper layer during the chemical mechanical polishing process. The remaining portion of the metal-filled material layer 22L includes an array of memory damascene pads 22 that fill an array of memory area openings 19 and at least one peripheral damascene pad 122 that fills at least one peripheral area opening 29. The array of memory damascene pads 22 is formed within the array of memory area openings 19, and the at least one peripheral damascene pad 122 is formed within at least one peripheral area opening 29. The upper surfaces of the memory damascene pads 22 and at least one peripheral damascene pad 122 may be formed in a horizontal plane that includes the upper surface of a dielectric capping layer on which the first electrode material layer 20L is formed on the array of memory damascene pads 22 and at least one peripheral damascene pad 122.

[0099] Referring to Figure 19, the processing steps described with reference to Figure 5 may be performed to form a capacitor material layer stack (20L, 30L, 40L) on the dielectric capping layer 10, including a first electrode material layer 20L, a node dielectric material layer 30L, and a second electrode material layer 40L. The first electrode material layer 20L may be deposited directly on the upper surface of the memory damascene pad 22 and at least one peripheral damascene pad 122. Subsequently, the processing steps described with reference to Figure 6 may be performed to form a hard mask material layer 50L.

[0100] Referring to Figure 20, a photoresist layer (not shown) may be applied to the hard mask material layer 50L and lithographically patterned into a two-dimensional array of discrete photoresist material portions overlapping the array of memory damascene pads 22 and a photoresist material portion overlapping at least one peripheral damascene pad 122. A first anisotropic etching process may be performed to transfer the pattern within the patterned photoresist material portions through the hard mask material layer 50L. The patterned portion of the hard mask material layer 50L includes an array hard mask plate 50 formed in the memory array region 100 and at least one peripheral hard mask plate 150 formed in the peripheral device region 200. The photoresist layer may then be removed by ashing.

[0101] A second anisotropic etching process may be performed to transfer the patterns in the array hard mask plate 50 and at least one peripheral hard mask plate 150 through the capacitor material layer stack (20L, 30L, 40L). In this embodiment, the combination of the array hard mask plate 50 and at least one peripheral hard mask plate 150 may be used as an etching mask for etching the material of the capacitor material layer stack (20L, 30L, 40L). The second anisotropic etching process may have a selective etching chemistry for the material of the dielectric capping layer 10. In an alternative embodiment, the removal of the photoresist layer used as an etching mask for patterning the hard mask material layer 50L may be performed after the second anisotropic etching process.

[0102] Each sidewall of the patterned portion of the second electrode material layer 40L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150. Each sidewall of the patterned portion of the node dielectric material layer 30L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150. Each sidewall of the patterned portion of the first electrode material layer 20L coincides perpendicularly with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150.

[0103] Generally, the capacitor material layer stack (20L, 30L, 40L) may be patterned by transferring the pattern in the array of array hard mask plates 50 and at least one peripheral hard mask plate 150 through at least the node dielectric material layer 30L and the first electrode material layer 20L using an anisotropic etching process that selectively etches the material of the capacitor material layer stack (20L, 30L, 40L) against the material of the dielectric capping layer 10. The patterned portion of the capacitor material layer stack (20L, 30L, 40L) remaining in the memory array region 100 includes an array of memory node capacitors 60. The patterned portion of the capacitor material layer stack (20L, 30L, 40L) remaining in the peripheral device region 200 includes voltage stabilization capacitors 160. Thus, the capacitor material layer stack (20L, 30L, 40L) may be patterned to include an array of memory node capacitors 60 and voltage stabilization capacitors 160.

[0104] Each memory node capacitor 60 includes a vertical stack of a first memory capacitor electrode 20, a memory capacitor node dielectric 30, and a second memory capacitor electrode 40. Each first memory capacitor electrode 20 is a patterned portion of the first electrode material layer 20L. Each memory capacitor node dielectric 30 is a patterned portion of the node dielectric material layer 30L. Each second memory capacitor electrode 40 is a patterned portion of the second electrode material layer 40L. The voltage stabilizing capacitor 160 includes a vertical stack of a first stabilizing capacitor electrode 120, a stabilizing capacitor node dielectric 130, and a second stabilizing capacitor electrode 140. The first stabilizing capacitor electrode is a patterned portion of the first electrode material layer 20L. The stabilizing capacitor node dielectric 130 is a patterned portion of the node dielectric material layer 30L. The second stabilizing capacitor electrode 140 is a patterned portion of the second electrode material layer 40L.

[0105] According to one aspect of the present invention, each of the memory node capacitors 60 is a charge storage capacitor for each memory cell of the memory array. The sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may coincide perpendicularly with each other, that is, they may be located in the same vertical plane. Furthermore, the sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may coincide perpendicularly with the sidewalls of the array hard mask plate 50 that overlaps them. In one embodiment, the sidewalls of the first memory capacitor electrode 20, the memory capacitor node dielectric 30, and the second memory capacitor electrode 40 within each memory node capacitor 60 may be located completely outside the area defined by the sidewalls of the memory damascene pad 22 located below them in a plan view, i.e., in a view along the vertical direction. In other words, the area range of each memory damascene pad 22 may be entirely contained within the area range of the memory node capacitor 60 that overlaps it in the plan view, thereby offsetting the periphery of each metal pad 781 laterally inward with respect to the periphery of the memory node capacitor 60 that overlaps it.

[0106] Generally, each of the memory node capacitors 60 includes a first memory capacitor electrode 20 electrically connected to one of the memory damascene pads 22. In one embodiment, each second memory capacitor electrode 40 may be formed on a contoured upper surface having a vertically recessed surface segment that overlaps the respective memory region opening 19.

[0107] At least one peripheral damascene pad 122 is electrically short-circuited with the first stabilizing capacitor electrode 120 during its formation. In one embodiment, each of the first stabilizing capacitor electrode 120, the stabilizing capacitor node dielectric 130, and the second stabilizing capacitor electrode 140 may be formed on their respective contoured upper surfaces, each including at least one set of vertically recessed surface segments that overlap over at least one peripheral region opening 29 in the dielectric capping layer 10.

[0108] The structure of the first embodiment includes an array of memory node capacitors 60 that overlaps a lower-level dielectric material layer 760 that overlaps the transistors. A lower-level metal wiring structure 780 may be formed within the lower-level dielectric material layer 760 and includes an array of memory damascene pads 22 that are electrically connected to one of each of the transistors and electrically connected to one of the first electrodes of each of the memory node capacitors 60 (i.e., the first memory capacitor electrode 20). A voltage stabilizing capacitor 160 may be located on top of the lower-level dielectric material layer 760 and may be configured to stabilize the voltage of the peripheral circuit 740. The dielectric capping layer 10 has an array of memory damascene pads 22 formed therein that fill an array of memory region openings 19, and further has at least one peripheral damascene pad 122 formed therein that fills at least one peripheral region opening 29. Each memory damascene pad 22 is located beneath the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) and is electrically short-circuited with it. Each peripheral damascene pad 122 is located beneath the first electrode of the voltage stabilizing capacitor 160 (i.e., the first stabilizing capacitor electrode 120) and is electrically short-circuited with it.

[0109] In one embodiment, each first memory capacitor electrode 20 of the memory node capacitor 60 may have a uniform thickness throughout its entirety between its upper and lower surfaces. Each memory capacitor node dielectric 30 of the memory node capacitor 60 may have a uniform thickness throughout its entirety between its upper and lower surfaces. Each second memory capacitor electrode 40 of the memory node capacitor 60 may have a uniform thickness throughout its entirety between its upper and lower surfaces.

[0110] Referring to Figure 21A, an upper-level dielectric material layer 770 and an upper-level metal wiring structure 790 may be formed to provide electrical connections to and from the second memory capacitor electrode 40, the second stabilizing capacitor electrode 140, and the lower-level metal wiring structure 780. The upper-level metal wiring structure 790 may include an array electrode contact via structure 791 that contacts one of each of the second memory capacitor electrodes 40, at least one peripheral upper electrode contact via structure 793 that contacts the second stabilizing capacitor electrode 140, a peripheral lower electrode contact via structure 795 that contacts at least one peripheral damascene pad 122, and connection via structures 797 that contact each metal wiring or each metal pad that may be formed in the lower-level dielectric material layer 760. Furthermore, the upper-level metal wiring structure 790 may include a memory region upper metal wiring 792 that contacts a plurality of array electrode contact via structures 791, and at least one peripheral region metal wiring 794 that contacts each subset of the peripheral upper electrode contact via structures 793.

[0111] In one embodiment, the upper metal wiring 792 of the memory area may contact a connection via structure 797 electrically connected to an electrical ground node, which may include a doped semiconductor well 102 and a semiconductor substrate 9. In some embodiments, one of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be electrically grounded, and the other of the first stabilizing capacitor electrode 120 and the second stabilizing capacitor electrode 140 may be connected to a power node of a circuit such as a peripheral circuit 740. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically grounded through a peripheral lower electrode contact via structure 795. In this embodiment, the upper metal wiring 792 of the memory area may contact the peripheral lower electrode contact via structure 795. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes an electrical node (which may or may not be a power node) that is not electrically short-circuited to any of the memory damascene pads 22.

[0112] Figures 21B to 21K are vertical cross-sectional views of an alternative configuration of the fourth embodiment structure according to the fourth embodiment of the present invention.

[0113] Referring to Figure 21B, the first alternative configuration of the fourth embodiment structure may be derived from the fourth embodiment structure of Figure 21A by forming a plurality of voltage stabilizing capacitors 160 having a first stabilizing capacitor electrode 120 that contacts the same peripheral damascene pad 122.

[0114] Referring to Figure 21C, a second alternative configuration of the fourth embodiment structure may be derived from the fourth embodiment structure in Figure 21A or from the first alternative embodiment of the fourth embodiment structure in Figure 21B by directly connecting at least one peripheral damascene pad 122 to a lower-level metal wiring structure 780, such as a metal via structure. In this embodiment, the connecting via structure 797 may be formed directly on the upper surface of at least one peripheral damascene pad 122.

[0115] Referring to Figure 21D, a third alternative configuration of the fourth embodiment structure may be derived from the fourth embodiment structure of Figure 21A by electrically grounding the second stabilizing capacitor electrode 140 through the peripheral upper electrode contact via structure 793. In this embodiment, the memory area upper metal wiring 792 may be in contact with the peripheral upper electrode contact via structure 793. In one embodiment, the voltage stabilizing capacitor 160 may be configured to stabilize the voltage of the peripheral circuit 740. In one embodiment, the voltage stabilizing capacitor 160 includes a power node that is not directly connected to the memory damascene pad 22. For example, the first stabilizing capacitor electrode 120 may be electrically connected to the power node through the peripheral lower electrode contact via structure 795, the peripheral area metal wiring 794, and the connecting via structure 797.

[0116] Referring to Figure 21E, a fourth alternative configuration of the fourth embodiment structure may be derived from a third alternative configuration of the fourth embodiment structure in Figure 21D by extending one of the metal wirings formed in the lower-level dielectric material layer 760 so that the one of the metal wirings contacts the bottom surface of at least one peripheral damascene pad 122. In this embodiment, the peripheral lower electrode contact via structure 795 may be omitted.

[0117] Referring to Figure 21F, the fifth alternative configuration of the fourth embodiment structure may be derived from the fourth alternative configuration of the fourth embodiment structure by forming multiple peripheral damascene pads 122 instead of a single peripheral damascene pad 122.

[0118] Referring to Figure 21G, the sixth alternative configuration of the fourth embodiment structure may be derived from any of the above configurations of the fourth embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically short-circuited to either of the memory damascene pads 22. In one embodiment, the second stabilizing capacitor electrode 140 may be electrically short-circuited to a power node.

[0119] Referring to Figure 21H, the seventh alternative configuration of the fourth embodiment structure may also be derived from any of the above configurations of the fourth embodiment structure (such as the second alternative configuration shown in Figure 21C) by forming multiple peripheral damascene pads 122 instead of a single peripheral damascene pad 122.

[0120] Referring to Figure 21I, the eighth alternative configuration of the fourth embodiment structure may be derived from any of the above configurations of the fourth embodiment structure by not electrically grounding either the first stabilizing capacitor electrode 120 or the second stabilizing capacitor electrode 140. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically short-circuited to any of the memory damascene pads 22. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically short-circuited to a power node through a peripheral lower electrode contact via structure 795, peripheral region metal wiring 794, and connecting via structure 797. The second stabilizing capacitor electrode 140 may be electrically connected to a single peripheral region metal wiring 794 or multiple peripheral region metal wirings 794.

[0121] Referring to Figure 21J, the ninth alternative configuration of the fourth embodiment structure may be derived from any of the above configurations of the fourth embodiment structure by not electrically connecting the first stabilizing capacitor electrode 120 to the electrical node of the peripheral circuit 740 through the peripheral area metal pad 782. In this embodiment, neither the first stabilizing capacitor electrode 120 nor the second stabilizing capacitor electrode 140 is electrically short-circuited to any of the memory damascene pads 22. In one embodiment, the first stabilizing capacitor electrode 120 may be electrically short-circuited to the power node through the peripheral area metal pad 782. The second stabilizing capacitor electrode 140 may be electrically connected to a single peripheral area metal wiring 794 or multiple peripheral area metal wirings 794.

[0122] Referring to Figure 21K, the tenth alternative configuration of the fourth embodiment structure may be derived from the ninth configuration of the fourth embodiment structure by forming multiple peripheral damascene pads 122 instead of a single peripheral damascene pad 122. The second stabilizing capacitor electrode 140 may be electrically connected to a single peripheral region metal wiring 794 or multiple peripheral region metal wirings 794.

[0123] Referring to Figures 21A to 21K comprehensively, the memory array may include an array of gain cell transistors, and the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure 780.

[0124] Referring comprehensively to Figures 1 to 21K, a device structure is provided according to various embodiments of the present invention, and the device structure is, In the peripheral device region 200, peripheral circuits 740 located on the semiconductor substrate 9, and transistors located in the memory array region 100 on the semiconductor substrate 9, A memory array comprising an array of memory node capacitors 60 superimposed on a lower-level dielectric material layer 760 superimposed on transistors, wherein a lower-level metal wiring structure 780 may be formed within the lower-level dielectric material layer 760, and the memory array comprising an array of connecting metal pads 781 electrically connected to one of each transistor and electrically connected to one of each first electrodes (i.e., first memory capacitor electrode 20) of the memory node capacitors 60, A voltage stabilizing capacitor 160 is located on the lower-level dielectric material layer 760 and configured to stabilize the voltage of the peripheral circuit 740, A dielectric capping layer 10 includes an array of memory region openings 19 that overlap the array of connecting metal pads 781 and provide an electrical connection between the first electrode (i.e., the first memory capacitor electrode 20) and the array of connecting metal pads 781, and further includes at least one peripheral region opening 29 located beneath or laterally surrounding the first stabilizing capacitor electrode 120, Includes.

[0125] In one embodiment, each of the memory node capacitors 60, one first electrode (i.e., the first memory capacitor electrode 20), includes a first horizontal extension 20H1 that overlaps the dielectric capping layer 10, and a downward projection adjacent to the inner circumference of the first horizontal extension 20H1, projecting downward relative to the first horizontal extension 20H1, and filling one of the memory region openings 19. In one embodiment, each of the memory node capacitors 60 includes a respective node dielectric (such as the memory capacitor node dielectric 30) having a vertical wavy shape in its vertical cross-sectional profile, a first horizontal extension 30H1 that overlaps in area with the dielectric capping layer 10 in a plan view, a second horizontal extension 30H2 within one region of the memory region opening 19, and a tubular connection 30C that connects the periphery of the second horizontal extension 30H2 to the periphery of the opening within the first horizontal extension 30H1. In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as a memory capacitor node dielectric 30) that contacts the upper surface of a first electrode (i.e., a first memory capacitor electrode 20), and a second electrode (i.e., a second stabilized capacitor electrode 140) having an upper surface located in a horizontal plane including the upper surface of the node dielectric (such as the memory capacitor node dielectric 30). In one embodiment, each of the memory node capacitors 60 includes a node dielectric (such as the memory capacitor node dielectric 30) having sidewalls, which are in contact with the lower surface of an array hard mask plate 50 having sidewalls perpendicular to the sidewalls of the node dielectric (such as the memory capacitor node dielectric 30). In one embodiment, the device structure further includes an array of memory damascene pads 22 located within an array of memory region openings 19, and each first electrode of the memory node capacitors 60 (i.e., a first memory capacitor electrode 20) contacts one upper surface of each of the memory damascene pads 22. In one embodiment, the memory array includes an array of gain cell transistors, and the first electrode of the memory node capacitor 60 (i.e., the first memory capacitor electrode 20) is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure 780.

[0126] Figure 22 is a first flowchart showing the sequence of processing steps for forming the semiconductor structure of the present invention.

[0127] Referring to step 2210 and Figures 1, 2A, and 2B, peripheral circuits 740 are formed on the semiconductor substrate 9 in the peripheral device region 200, and transistors for the memory array are formed on the semiconductor substrate 9 in the memory array region 100.

[0128] Referring to step 2220 and Figures 1 and 3, a combination of a lower-level metal wiring structure 780 and a lower-level dielectric material layer 760 is formed on the transistor. A subset of the lower-level metal wiring structure 780 includes an array of connecting metal pads 781 electrically connected to one of the respective transistors.

[0129] Referring to step 2230 and Figures 3 and 4, the dielectric capping layer 10 is formed on the lower-level dielectric material layer 760. The dielectric capping layer 10 includes an array of memory region openings 19 beneath which an array of connecting metal pads 781 is exposed, and at least one peripheral region opening 29 formed in the peripheral device region 200.

[0130] Referring to step 2240 and Figures 5, 9, and 17-19, a capacitor material layer stack (20L, 30L, 40L) including a first electrode material layer 20L, a node dielectric material layer 30L, and a second electrode material layer 40L is deposited on the dielectric capping layer 10.

[0131] Referring to step 2250 and Figures 6, 7, 8A-8H, 10, 11, 12, 13A-13H, 14, 15, 16A-16F, 20, and 21A-21K, the capacitor material layer stacks (20L, 30L, 40L) are patterned into an array of memory node capacitors 60 and a voltage stabilization capacitor 160. Each of the memory node capacitors 60 is a charge storage capacitor for each memory cell in the memory array, and the voltage stabilization capacitor 160 is configured to stabilize the voltage of the peripheral circuitry 740.

[0132] In one embodiment, the first electrode material layer 20L is deposited directly on the physically exposed surface of the array of connecting metal pads 781, the sidewalls of the memory region openings 19, and the upper surface of the dielectric capping layer 10. In one embodiment, the node dielectric material layer 30L is formed with vertical undulations in the vertical cross-sectional profile, and the node dielectric material layer 30L includes a first horizontally extending portion 30H1 having areaal overlap with the dielectric capping layer 10 in the plan view, a second horizontally extending portion 30H2 in the region of the array of memory region openings 19 and at least one peripheral region opening 29, and a tubular connecting portion 30C connecting each peripheral portion of the second horizontally extending portion 30H2 to the peripheral portion of each opening in the first horizontally extending portion 30H1. In one embodiment, the method further includes forming at least a hard mask material layer 50L on the node dielectric material layer 30L of a capacitor material layer stack (20L, 30L, 40L), patterning the hard mask material layer 50L onto an array hard mask plate 50 and at least one peripheral hard mask plate 150, and transferring the pattern in the array of array hard mask plates 50 and at least one peripheral hard mask plate 150 through at least the node dielectric material layer 30L and the first electrode material layer 20L using an anisotropic etching process that selectively etches the material of the capacitor material layer stack (20L, 30L, 40L) against the material of the dielectric capping layer 10, thereby patterning the capacitor material layer stack (20L, 30L, 40L). In one embodiment, the upper surface of the second electrode material layer 40L is formed having a vertically recessed surface segment that overlaps the array of memory region openings 19 and at least one peripheral region opening 29, and each sidewall of the patterned portion of the second electrode material layer 40L perpendicularly coincides with one sidewall of the array hard mask plate 50 and at least one peripheral hard mask plate 150, respectively. In one embodiment, the method further includes the step of removing the portion of the second electrode material layer 40L above a horizontal plane including the upper surface of the node dielectric material layer 30L, the remaining portion of the second electrode material layer 40L including the second electrode 40 of the array of memory node capacitors 60 and the second electrode 140 of the voltage stabilization capacitor 160.In one embodiment, the method further comprises depositing a metal-filling material layer within an array of memory region openings 19, within at least one peripheral region opening 29, and on a dielectric capping layer 10, and removing a portion of the metal-filling material layer from above a horizontal plane including the upper surface of the dielectric capping layer 10, the remaining portion of the metal-filling material layer comprising an array of memory damascene pads filling the array of memory region openings 19 and at least one peripheral damascene pad filling at least one peripheral region opening 29. In one embodiment, the portion of the metal-filling material layer is removed by performing a chemical mechanical polishing process to remove the material of the metal-filling material layer using the dielectric capping layer 10 as a planarization stopper layer.

[0133] Figure 23 is a second flowchart showing the sequence of processing steps for forming the semiconductor structure of the present invention.

[0134] Referring to step 2310 and Figures 1, 2A, 2B, and 3, a combination of a lower-level metal wiring structure 780 and a lower-level dielectric material layer 760 may be formed on the semiconductor substrate 9. A subset of the lower-level metal wiring structure 780 includes an array of connecting metal pads 781 formed in the memory array region 100.

[0135] Referring to step 2320 and Figures 3 and 4, the dielectric capping layer 10 may be formed on the lower-level dielectric material layer 760. The dielectric capping layer 10 includes an array of memory region openings 19 beneath which an array of connecting metal pads 781 is exposed, and at least one peripheral region opening 29 formed in the peripheral device region 200.

[0136] Referring to step 2330 and Figures 5, 6, 7, 8A-8H, 9, 10, 11, 12, 13A-13H, 14, 15, 16A-16F, 17, 18, 19, 20, and 21A-21K, an array of memory node capacitors 60 and a voltage stabilization capacitor 160 may be formed. Each of the memory node capacitors 60 includes a first memory capacitor electrode 20 electrically connected to one of the connecting metal pads 781, and the voltage stabilization capacitor 160 includes a power node that is not directly connected to the connecting metal pads 781.

[0137] In one embodiment, the method may further include depositing a capacitor material layer stack (20L, 30L, 40L) comprising a first electrode material layer 20L, a node dielectric material layer 30L, and a second electrode material layer 40L onto a dielectric capping layer 10, and patterning the capacitor material layer stack (20L, 30L, 40L) onto an array of memory node capacitors 60 and a voltage stabilization capacitor 160, where each first memory capacitor electrode 30 is a patterned portion of the first electrode material layer 30L, and the first stabilization capacitor electrode 130 of the voltage stabilization capacitor 160 is an additional patterned portion of the first electrode material layer 30L. In one embodiment, the first electrode material layer 30L is deposited within an array of memory region openings 19 and within at least one peripheral region opening 29. In one embodiment, the method may further include forming a peripheral region metal pad 782 within a lower-level dielectric material layer 760, where the dielectric capping layer 10 may be formed directly on the upper surface of the peripheral region metal pad 782, and the peripheral region metal pad 782 may be electrically short-circuited to the first stabilizing capacitor electrode 160 when the first stabilizing capacitor electrode 160 is formed. In one embodiment, the method may further include forming an array of memory damascene pads 781 within an array of memory region openings 19, and forming at least one peripheral damascene pad within at least one peripheral region opening 29, where the first electrode material layer 30L is formed on the array of memory damascene pads and on the at least one peripheral damascene pad.

[0138] Various embodiments of the present invention provide an efficient method for simultaneously forming memory node capacitors and voltage stabilization capacitors in a semiconductor structure. By integrating these capacitors within a lower-level dielectric material layer and a lower-level metal wiring structure, and utilizing a dielectric capping layer having memory region openings and peripheral region openings, this method addresses the challenge of achieving high capacitance with a minimal device footprint. This approach eliminates the need for additional masks, thereby reducing production costs and process complexity while ensuring improved performance and scalability of memory arrays and peripheral circuits.

[0139] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Each embodiment described using the term “includes” also implicitly discloses that, unless expressly disclosed otherwise herein, the term “includes” may be replaced with the terms “essentially constituted” or “constituted” in some embodiments. Whenever two or more elements are enumerated as alternatives in the same paragraph or in different paragraphs, a group of Markushes containing lists of two or more elements may also be implicitly disclosed. Whenever the auxiliary verb “can” is used in this disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such an element or processing step is not performed are also expressly contemplated, insofar as the resulting apparatus or device can provide an equivalent result. Thus, whenever the auxiliary verb “can” applied to the formation of an element or the execution of a processing step can provide the same or equivalent result, it should also be interpreted as “maybe” or “maybe, or not,” wherever the omission of such element formation or processing step can provide the same or equivalent result, and equivalent results include somewhat better and somewhat inferior results. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same objectives and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention. [Industrial applicability]

[0140] The present invention relates to a back-end capacitor for memory cells and peripheral circuits, the back-end capacitor comprising an array of memory node capacitors and a voltage stabilization capacitor, each of which is a charge storage capacitor for each memory cell in the memory array, and the voltage stabilization capacitor is configured to stabilize the voltage of the peripheral circuit. [Explanation of symbols]

[0141] 2 Source / Drain Areas 5 gates 8. Source / Drain Metal-Semiconductor Alloy Region 9 Semiconductor substrates 10 Dielectric capping layer 17 Photoresist layer 19, 29 openings 20 First memory capacitor electrode 20C, 30C, 40C tubular connector 20H1, 30H1, 40H1 1st horizontal extension part 20H2, 30H2, 40H2 2nd horizontal extension part 20L, 30L, 40L Capacitor Material Layer Stack 781, 782, 22 Memory Machine Pad 22L metal filling material layer 30 Memory capacitor node dielectric 40, 140 2nd electrode 50 Array Hard Mask Plates 50L Hard Mask Material Layer 60 Memory node capacitors 100 memory array area 102 doped semiconductor wells 120, 130, 160 First stabilizing capacitor electrode 122 Peripheral Damascus Pad 150 Peripheral hard mask plate 200 Peripheral Device Area 710 memory transistors 720 Memory Transistor Circuit 740 Peripheral Circuits 760 Lower-level dielectric material layer 770 Upper-level dielectric material layer 780 Lower-level metal wiring structure 781 Memory Machine Pad 781, 782 Metal pads 790 High-level metal wiring structure 791 Array electrode contact via structure 792 Upper metal wiring of the memory area 793 Peripheral upper electrode contact via structure 794 Peripheral area metal wiring 795 Peripheral lower electrode contact via structure 797 Connection via structure RT, RT1, RT2 Readout Transistors SN Storage Node WT writing transistor

Claims

1. In the peripheral device region, peripheral circuits are formed on the semiconductor substrate, and in the memory array region, transistors of the memory array are formed on the semiconductor substrate. On the transistor, a combination is formed of a lower-level metal wiring structure including an array of connecting metal pads, each of which is electrically connected to one of the transistors, and a lower-level dielectric material layer. A dielectric capping layer is formed on the lower-level dielectric material layer, including an array of memory region openings in which the array of connecting metal pads is exposed below, and at least one peripheral region opening formed in the peripheral device region. A capacitor material layer stack including a first electrode material layer, a node dielectric material layer, and a second electrode material layer is deposited on the dielectric capping layer. The capacitor material layer stack is patterned into an array of memory node capacitors and a voltage stabilization capacitor, wherein each of the memory node capacitors is a charge storage capacitor for each memory cell of the memory array, and the voltage stabilization capacitor is configured to stabilize the voltage of the peripheral circuit. A method for forming a device structure, including [a specific element].

2. The method according to claim 1, wherein the first electrode material layer is deposited directly on the exposed upper surface segment of the array of connecting metal pads, the sidewall of the memory region opening, and the upper surface of the dielectric capping layer.

3. The method according to claim 1, wherein the node dielectric material layer is formed to have vertical undulations in a vertical cross-sectional profile, such that the node dielectric material layer includes a first horizontally extending portion having areaal overlap with the dielectric capping layer in a plan view, a second horizontally extending portion within the region of the array of memory region openings and the region of at least one peripheral region opening, and a tubular connecting portion connecting one peripheral portion of each of the second horizontally extending portions to the peripheral portion of each opening in the first horizontally extending portion.

4. Forming at least a hard mask material layer on the node dielectric material layer of the capacitor material layer stack, The hard mask material layer is patterned onto an array hard mask plate and at least one peripheral hard mask plate. A method for transferring patterns in the array of array hard mask plates and the at least one peripheral hard mask plate through at least the node dielectric material layer and the first electrode material layer using an anisotropic etching process, wherein the anisotropic etching process selectively etches the material of the capacitor material layer stack relative to the material of the dielectric capping layer, thereby patterning the capacitor material layer stack. The method according to claim 1, further comprising:

5. The upper surface of the second electrode material layer is formed having a vertically recessed surface segment that overlaps the array of memory region openings and the at least one peripheral region opening. Each sidewall of the patterned portion of the second electrode material layer coincides perpendicularly with one sidewall of the array hard mask plate and the at least one peripheral hard mask plate. The method according to claim 4.

6. The further step includes removing the portion of the second electrode material layer above a horizontal plane including the upper surface of the node dielectric material layer, The method according to claim 4, wherein the remaining portion of the second electrode material layer includes the second electrode of the memory node capacitor array and the second electrode of the voltage stabilization capacitor.

7. A metal-filling material layer is deposited within the array of memory region openings, within the at least one peripheral region opening, and on the dielectric capping layer. Removing a portion of the metal-filling material layer from above a horizontal plane including the upper surface of the dielectric capping layer, wherein the remaining portion of the metal-filling material layer includes an array of memory pads filling the array of memory region openings and at least one peripheral pad filling the at least one peripheral region opening. The method according to claim 1, further comprising:

8. The method according to claim 7, wherein the portion of the metal-filled material layer is removed by performing a chemical mechanical polishing process to remove the material of the metal-filled material layer using the dielectric capping layer as a planar stopper layer.

9. Forming a combination on a semiconductor substrate of a lower-level metal wiring structure including an array of connecting metal pads, a subset of which is formed in the memory array region, and a lower-level dielectric material layer, On the lower-level dielectric material layer, a dielectric capping layer is formed which includes an array of memory region openings into which the array of connecting metal pads is exposed below, and at least one peripheral region opening formed in the peripheral device region. To form an array of memory node capacitors and a voltage stabilization capacitor, wherein each of the memory node capacitors includes a first memory capacitor electrode electrically connected to one of the connecting metal pads, and the voltage stabilization capacitor includes an electrical node that is not electrically short-circuited to any of the connecting metal pads. A method for forming a device structure, including [a specific element].

10. A capacitor material layer stack including a first electrode material layer, a node dielectric material layer, and a second electrode material layer is deposited on the dielectric capping layer. The capacitor material layer stack is patterned onto the array of memory node capacitors and the voltage stabilization capacitor, wherein each of the first memory capacitor electrodes is a patterned portion of the first electrode material layer, and the first stabilization capacitor electrode of the voltage stabilization capacitor is an additional patterned portion of the first electrode material layer. The method according to claim 9, further comprising:

11. The method according to claim 10, wherein the first electrode material layer is deposited within the array of memory region openings and within the at least one peripheral region opening.

12. The further includes forming a peripheral region metal pad within the lower-level dielectric material layer, The dielectric capping layer is formed directly on the upper surface of the peripheral region metal pad. The peripheral region metal pad is electrically short-circuited with the first stabilizing capacitor electrode when the first stabilizing capacitor electrode is formed. The method according to claim 10.

13. Forming an array of memory damascene pads within the array of memory area openings, The method involves forming at least one peripheral damascene pad within the at least one peripheral region opening, wherein the first electrode material layer is formed on the array of memory damascene pads and on the at least one peripheral damascene pad. The method according to claim 12.

14. Peripheral circuits located on a semiconductor substrate within the peripheral device area, A memory array comprising transistors located in a memory array region on a semiconductor substrate, and an array of memory node capacitors overlapping a lower-level dielectric material layer overlapping the transistors, wherein the lower-level metal wiring structure is formed within the lower-level dielectric material layer and includes an array of connecting metal pads electrically connected to one of the transistors and electrically connected to one of the first electrodes of the memory node capacitors, A voltage stabilizing capacitor located on the lower-level dielectric material layer and configured to stabilize the voltage of the peripheral circuit, A dielectric capping layer comprising an array of memory region openings that overlap the array of connecting metal pads and provide an electrical connection between the first electrode and the array of connecting metal pads, further comprising at least one peripheral region opening located beneath or laterally surrounding the first stabilizing capacitor electrode, A device structure that includes this.

15. The device structure according to claim 14, wherein each of the first electrodes of the memory node capacitor includes a horizontally extending portion that overlaps the dielectric capping layer and a downwardly protruding portion adjacent to the inner circumference of the horizontally extending portion and protruding downward relative to the horizontally extending portion to fill each of the memory region openings.

16. The device structure according to claim 14, wherein each of the memory node capacitors includes a node dielectric having vertical relief in a vertical cross-sectional profile, and includes a first horizontally extending portion having areaal overlap with the dielectric capping layer in a plan view, a second horizontally extending portion within one region of the memory region opening, and a tubular connecting portion connecting the periphery of the second horizontally extending portion to the periphery of the opening within the first horizontally extending portion.

17. Each of the memory node capacitors is A node dielectric in contact with the upper surface of the first electrode, A second electrode having an upper surface located in a horizontal plane including the upper surface of the node dielectric, The device structure according to claim 14.

18. The device structure according to claim 14, wherein each of the memory node capacitors includes a node dielectric having a side wall, and is in contact with the lower surface of an array hard mask plate having a side wall perpendicular to the side wall of the node dielectric.

19. The device structure according to claim 14, further comprising an array of memory damascene pads located within the array of memory region openings, wherein each of the first electrodes of the memory node capacitors is in contact with one upper surface of each of the memory damascene pads.

20. The memory array includes an array of gain cell transistors, The device structure according to claim 14, wherein the first electrode of the memory node capacitor is electrically connected to one gate electrode of each of the gain cell transistors through each subset of the lower-level metal wiring structure.

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