Display drivers and display devices

Abstract

To provide a display driver or similar device that can prevent situations where the potential of the monitor signal becomes unstable, making it impossible to correctly detect abnormalities. [Solution] The display driver 20 includes a driver circuit 30 that outputs a drive signal SD, an output terminal TQ that outputs the drive signal SD to the display electrode EL of the electro-optic panel 200, an input terminal TI to which a monitor signal SM is input from the display electrode EL, and a test circuit 40. The test circuit 40 includes a comparison circuit 50 that compares the voltage of the monitor signal SM with a reference voltage VR, a determination circuit 56 that determines an abnormality based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50, and a potential setting circuit 60 that pulls down or pulls up the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD.

Description

Technical Field

[0006] , ,

[0001] The present invention relates to a display driver, a display device, etc.

Background Art

[0002] Patent Document 1 discloses a liquid crystal driver having a first segment terminal that outputs a drive signal to a segment electrode and a second segment terminal that inputs a monitor signal from the segment electrode. In Patent Document 1, a detection circuit detects an abnormality in a signal line of a liquid crystal panel by detecting a drive abnormality of the segment electrode based on the monitor signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, for example, if a signal line connecting the detection circuit and the display electrode is disconnected, the potential of the monitor signal becomes unstable, and there is a high possibility that an abnormality cannot be correctly detected.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a display driver including a driver circuit that outputs a drive signal, an output terminal that outputs the drive signal to a display electrode of an electro-optical panel, an input terminal to which a monitor signal is input from the display electrode, and an inspection circuit. The inspection circuit includes a comparison circuit that compares the voltage of the monitor signal with a reference voltage, a determination circuit that determines an abnormality based on an expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit, and a potential setting circuit that performs pull-down or pull-up of a signal line of the monitor signal according to the voltage level of the drive signal.

[0006] Other aspects of this disclosure relate to a display device including the display driver described above and the electro-optical panel. [Brief explanation of the drawing]

[0007] [Figure 1] An example configuration of the display device according to this embodiment. [Figure 2] Detailed configuration example of a display device. [Figure 3] Examples of segment electrode placement and segment signal line wiring. [Figure 4] Examples of common electrode placement and common signal line wiring. [Figure 5] Detailed configuration examples of test circuits and driver circuits. [Figure 6] Detailed configuration examples of test circuits and driver circuits. [Figure 7] Diagram illustrating the configuration and operation of the potential setting circuit. [Figure 8] Diagram illustrating the configuration and operation of the potential setting circuit. [Figure 9] Diagram illustrating the configuration and operation of the potential setting circuit. [Figure 10] Other configuration examples of potential setting circuits. [Figure 11] A signal waveform diagram illustrating the operation of the display device of this embodiment. [Modes for carrying out the invention]

[0008] The following describes this embodiment. Note that the embodiment described below does not unduly limit the scope of the claims. Furthermore, not all of the configurations described in this embodiment are necessarily essential components.

[0009] 1. Display driver, display device Figure 1 shows an example configuration of the display device 10 of this embodiment. The display device 10 includes a display driver 20 and an electro-optic panel 200. The display driver 20 includes a driver circuit 30, a test circuit 40, an output terminal TQ, and an input terminal TI. The electro-optic panel 200 is provided with multiple display electrodes EL. Note that the display driver 20 and the display device 10 are not limited to the configuration shown in Figure 1, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components.

[0010] The display driver 20 is a circuit that drives the electro-optic panel 200 to display an image, and is implemented by a circuit device called an IC (Integrated Circuit). The circuit device is a semiconductor chip manufactured by a semiconductor process, in which circuit elements are formed on a semiconductor substrate. The display driver 20 is mounted on the glass substrate of the electro-optic panel 200, for example. For example, the display driver 20 is mounted on the glass substrate on which the display electrodes EL are provided. Alternatively, the display driver 20 may be mounted on a circuit board, and the circuit board and the electro-optic panel 200 may be connected by a flexible substrate.

[0011] The electro-optic panel 200 is a display panel, such as a liquid crystal panel. The electro-optic panel 200 has a plurality of display electrodes EL and a plurality of electro-optic elements. The electro-optic elements are, for example, liquid crystal elements. Each pixel of the electro-optic panel 200 is composed of the display electrodes EL and the electro-optic elements, and an image is displayed on the electro-optic panel 200.

[0012] The display device 10 is a device that displays an image based on, for example, image data. The display device 10 is also called a display module or an electro-optical device. The display device 10 is, for example, a cluster display that is a display of a meter panel, a center information display, a head-up display that displays a virtual image in the user's field of view, or an in-vehicle display device such as an electronic mirror. The in-vehicle display device is a display device mounted on an automobile such as a four-wheeled or two-wheeled vehicle. Alternatively, the display device 10 may be a display device mounted on a moving body other than a vehicle such as a ship, a head-mounted display called an HMD, a television device, or a display of an information processing device.

[0013] The display driver 20 includes a driver circuit 30, an output terminal TQ, an input terminal TI, and an inspection circuit 40.

[0014] The driver circuit 30 outputs a drive signal SD for driving the electro-optical panel 200. When the electro-optical panel 200 is a segment liquid crystal panel, the driver circuit 30 outputs a segment drive signal for driving the segment electrodes or a common drive signal for driving the common electrodes as the drive signal SD.

[0015] The output terminal TQ is a terminal that outputs the drive signal SD to the display electrode EL of the electro-optical panel 200. The input terminal TI is a terminal to which a monitor signal SM is input from the display electrode EL. The input terminal TI can also be called a monitor terminal. These output terminal TQ and input terminal TI are, for example, pads of the display driver 20 which is a circuit device. For example, in a pad region, a metal layer is exposed from a passivation film which is an insulating layer, and the exposed metal layer constitutes a pad which is a terminal of the display driver 20. The terminal may be an external connection terminal of a package in which the display driver 20 is housed.

[0016] The inspection circuit 40 is a circuit for inspecting abnormal states such as disconnection or short circuit of signal lines of the electro-optical panel 200, and includes a comparison circuit 50, a determination circuit 56, and a potential setting circuit 60.

[0017] The comparison circuit 50 compares the voltage of the monitor signal SM with the reference voltage VR. Specifically, the electro-optic panel 200 is wired with signal lines L1 and L2, one end of which is connected to the display electrode EL. The drive signal SD from the driver circuit 30 is output to the display electrode EL via signal line L1, and the monitor signal SM from the display electrode EL is input to the inspection circuit 40 via signal line L2. The inspection circuit 40 checks whether an abnormality has been detected in the signal line based on the monitor signal SM fed back from the display electrode EL driven by the drive signal SD. Specifically, the comparison circuit 50 of the inspection circuit 40 compares the voltage of the input monitor signal SM with the reference voltage VR and outputs a signal CQ indicating the comparison result, and the judgment circuit 56 detects an abnormality based on the comparison result. The reference voltage VR is a threshold voltage for judgment, and can be, for example, a voltage that is approximately midway between the high-level and low-level potentials of the monitor signal SM. In this case, the comparison circuit 50 may compare two or more reference voltages VR with the voltage of the monitor signal SM. For example, the comparison circuit 50 may compare the voltage of the monitor signal SM with the reference voltage on the high-potential side, and compare the voltage of the monitor signal SM with the reference voltage on the low-potential side, and output the comparison result. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information by electrical signals. The electrical connection may be a connection via a passive element or the like.

[0018] The determination circuit 56 makes an abnormality determination based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50. For example, the determination circuit 56 makes a determination of a drive abnormality in which the drive of the display electrode EL becomes abnormal. For example, the determination circuit 56 determines an abnormality in the signal line. Then, the determination circuit 56 outputs a signal JQ indicating the abnormality determination result. For example, the determination circuit 56 determines whether an abnormal state such as a disconnection or a short circuit has occurred in the signal lines L1 and L2 based on the signal of the expected value EV and the comparison result signal CQ from the comparison circuit 50, and outputs a signal JQ indicating that such an abnormality has occurred. The expected value EV is a value expected as the voltage level of the signal output as the drive signal SD by the driver circuit 30. For example, when the driver circuit 30 outputs a high-level drive signal SD, the expected value EV becomes the first logic level, and when the driver circuit 30 outputs a low-level drive signal SD, the expected value EV becomes the second logic level. Hereinafter, the first logic level is a high level and the second logic level is a low level for explanation. However, the first logic level may be a low level and the second logic level may be a high level. Also, the high level of the drive signal SD of the driver circuit 30 corresponds to, for example, the high level of the drive power supply voltage used for driving the electro-optical panel 200, and the high level of the expected value EV corresponds to, for example, the high level of the logic power supply voltage.

[0019] The potential setting circuit 60 sets the potential of the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD. For example, the potential setting circuit 60 pulls down or pulls up the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD. For example, the potential setting circuit 60 pulls down or pulls up the signal line L2 of the monitor signal SM according to whether the drive signal SD is high level or low level. The signal line L2 is a signal line to which one end is connected to the display electrode EL to which the drive signal SD of the driver circuit 30 is input, and is a signal line to which a monitor signal SM with a voltage level corresponding to the drive signal SD is expected to be transmitted. In this case, for example, if an abnormality such as a break in the signal line L1 of the drive signal SD occurs, the monitor signal SM with a voltage level corresponding to the drive signal SD will not be transmitted to the signal line L2, the potential of the signal line L2 will become unstable, and there is a risk that the judgment circuit 56 will not be able to correctly detect the abnormality. In this embodiment, the potential setting circuit 60 sets the potential of the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD, and performs, for example, pull-down or pull-up of the signal line L2. This prevents a situation in which the potential of the signal line L2 becomes unstable and the judgment circuit 56 is unable to correctly detect an abnormality.

[0020] As described above, the display driver 20 of this embodiment includes a driver circuit 30, an output terminal TQ that outputs a drive signal SD from the driver circuit 30 to the display electrode EL, an input terminal TI that receives a monitor signal SM from the display electrode EL, and a test circuit 40. The comparison circuit 50 of the test circuit 40 compares the voltage of the monitor signal SM with a reference voltage VR, and the determination circuit 56 determines whether there is an abnormality such as a broken wire based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50. The potential setting circuit 60 pulls down or pulls up the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD. Therefore, even if an abnormality such as a broken wire in the signal line L1 occurs and there is a risk that the potential of the signal line L2 will become unstable, the potential setting circuit 60 pulls down or pulls up the signal line L2 of the monitor signal SM according to the voltage level of the drive signal SD, so that the potential of the signal line L2 is set to a low level or a high level. This prevents the determination circuit 56 from being unable to correctly detect the abnormality.

[0021] Specifically, the potential setting circuit 60 pulls down the signal line L2 of the monitor signal SM when the drive signal SD output by the driver circuit 30 is at a high level, and pulls up the signal line L2 of the monitor signal SM when the drive signal SD is at a low level. For example, if an abnormality occurs, such as a break in the signal line L1 of the drive signal SD, the signal line L2 of the monitor signal SM will not be driven by the driver circuit 30, causing the signal line L2 to become high impedance and the potential of the monitor signal SM to become unstable. Consequently, the potential of the monitor signal SM will be adversely affected by the potential of the surrounding wiring, such as due to the coupling of parasitic inter-wiring capacitances.

[0022] For example, suppose a display electrode ELB near a display electrode EL is driven by a drive signal SDB via a signal line LB. In this case, the signal waveform of the drive signal SDB for the display electrode ELB may be the same as the signal waveform of the drive signal SD for the display electrode EL. For example, when both the display electrode EL and the display electrode ELB are lit, or when both the display electrode EL and the display electrode ELB are off, the drive signal SD and the drive signal SDB will have the same signal waveform. Now suppose the signal line LB for the drive signal SDB is wired near the signal line L2 for the monitor signal SM of the drive signal SD. Then, the monitor signal SM, whose potential is unstable due to a break in the wire or the like, will be affected by the drive signal SDB on the nearby signal line LB, and its potential will change in the same way as the potential change of the drive signal SDB. For example, due to the coupling of capacitance between the signal line L2 and the signal line LB, when the drive signal SDB is at a high level, the monitor signal SM will also be at a high level, and when the drive signal SDB is at a low level, the monitor signal SM will also be at a low level. As a result, even if an abnormality such as a break in the signal line L1 of the drive signal SD occurs, the inspection circuit 40 may not be able to correctly detect this abnormality.

[0023] In other words, if no abnormality such as a broken wire occurs, the inspection circuit 40 determines that no abnormality has occurred when the monitor signal SM becomes high level when the drive signal SD is high level, and when the monitor signal SM becomes low level when the drive signal SD is low level, and the comparison result of the comparison circuit 50 matches the expected value. However, the monitor signal SM, whose potential is unstable due to a broken wire or the like, is affected by the drive signal SDB of the signal line LB, which is near the signal line L2. For example, if the drive signal SDB becomes high level when the drive signal SD becomes high level, the monitor signal SM, which is in a high impedance state, will also become high level due to the coupling of parasitic interwiring capacitance between signal line LB and signal line L2. Also, if the drive signal SDB becomes low level when the drive signal SD becomes low level, the monitor signal SM, which is in a high impedance state, will also become low level due to the coupling of parasitic interwiring capacitance between signal line LB and signal line L2. Therefore, even though an abnormality such as a broken wire has occurred, the inspection circuit 40 may determine that the monitor signal SM is changing in the same way as the expected value, resulting in a situation where the inspection circuit 40 cannot correctly detect the abnormality.

[0024] In this embodiment, the potential setting circuit 60 pulls down the signal line L2 of the monitor signal SM when the drive signal SD is at a high level, and pulls up the signal line L2 of the monitor signal SM when the drive signal SD is at a low level. Therefore, when both the drive signal SD and the nearby drive signal SDB are at a high level, the potential setting circuit 60 pulls down the signal line L2, preventing the potential of the monitor signal SM from being pulled to the high level side due to coupling of inter-wiring capacitances. Also, when both the drive signal SD and the nearby drive signal SDB are at a low level, the potential setting circuit 60 pulls up the signal line L2, preventing the potential of the monitor signal SM from being pulled to the low level side due to coupling of inter-wiring capacitances. Therefore, it is possible to prevent the inspection circuit 40 from being unable to correctly detect abnormalities such as open circuits.

[0025] Figure 2 shows a detailed configuration example of the display driver 20 and display device 10 of this embodiment. In Figure 2, the display device 10 includes the display driver 20, the electro-optic panel 200, and the processing unit 300. Note that the display driver 20 and display device 10 are not limited to the configuration in Figure 2, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components.

[0026] The electro-optic panel 200 is a panel driven, for example, by a static drive method. Specifically, the electro-optic panel 200 includes a first glass substrate, a second glass substrate, and liquid crystal. The liquid crystal, which is an electro-optic element, is sealed between the first and second glass substrates. Segment electrodes are provided on the first glass substrate, and a common electrode is provided on the second glass substrate. The display driver 20 outputs a segment drive signal to the segment electrodes. The display driver 20 also outputs a common drive signal to the common electrode. As a result, a drive signal, which is the potential difference between the segment drive signal and the common drive signal, is applied to the liquid crystal between the segment electrodes and the common electrode. The segment electrodes and the common electrode are transparent electrodes, for example, ITO (Indium Tin Oxide). In the following description, the electro-optic panel 200 will mainly be described as a segment liquid crystal panel having segment electrodes and a common electrode as display electrodes EL, but this embodiment is not limited to this.

[0027] The processing unit 300 is, for example, a host device for the display driver 20, and is implemented by, for example, a processor or a display controller. The processor is a CPU or a microcomputer, etc. The processing unit 300 may also be a circuit device composed of multiple circuit components. For example, in automotive electronic equipment, the processing unit 300 may be an ECU (Electronic Control Unit).

[0028] The display driver 20 includes a segment driver circuit 31, a common driver circuit 32, a segment inspection circuit 41, a common inspection circuit 42, a line latch 70, a data storage circuit 80, a control circuit 100, an interface circuit 110, and an oscillator circuit 120. Each of the segment driver circuit 31 and the common driver circuit 32 corresponds to the driver circuit 30 in Figure 1, and each of the segment inspection circuit 41 and the common inspection circuit 42 corresponds to the inspection circuit 40 in Figure 1. In other words, in this case, the display driver 20 has multiple inspection circuits 40.

[0029] The segment driver circuit 31 outputs a segment drive signal to drive the segment electrodes of the electro-optic panel 200. For example, the segment driver circuit 31 drives the electro-optic panel 200 using a static drive method or a duty cycle drive method. For example, the display driver 20 has an output terminal to which a segment drive signal is output, and the segment drive signal is output to the segment electrodes of the electro-optic panel 200 via this output terminal. In this case, the drive signal SD, display electrode EL, and output terminal TQ in Figure 1 correspond to the segment drive signal, segment electrode, and output terminal of the segment drive signal, respectively.

[0030] The common driver circuit 32 outputs a common drive signal to drive the common electrode of the electro-optic panel 200. For example, the display driver 20 has an output terminal to which the common drive signal is output, and the common drive signal is output to the common electrode of the electro-optic panel 200 via this output terminal. In this case, the drive signal SD, the display electrode EL, and the output terminal TQ in Figure 1 correspond to the common drive signal, the common electrode, and the output terminal of the common drive signal, respectively. That is, in this case, the display driver 20 has multiple output terminals TQ.

[0031] The segment inspection circuit 41 is a circuit that inspects for abnormalities in the signal lines of the segment electrodes. For example, the segment inspection circuit 41 checks whether an abnormality such as a break or short circuit has occurred in the signal lines of the segment electrodes. The common inspection circuit 42 is a circuit that inspects for abnormalities in the signal lines of the common electrode. For example, the common inspection circuit 42 checks whether an abnormality such as a break or short circuit has occurred in the signal lines of the common electrode. Each of these segment inspection circuits 41 and common inspection circuits 42 corresponds to the inspection circuit 40 in Figure 1. In other words, in this case, the display driver 20 has multiple inspection circuits 40.

[0032] The data storage circuit 80 is a circuit that stores data for display purposes, and can be implemented using memory such as RAM. The data storage circuit 80 stores data for display purposes of the electro-optical panel 200. The display data includes, for example, on / off data or grayscale data for the display of a display corresponding to a segment electrode. This display data is received from, for example, the processing unit 300 via the interface circuit 110 and stored in the data storage circuit 80.

[0033] The line latch 70 latches display data from the data storage circuit 80. The line latch 70, being a data latch, latches display data from the data storage circuit 80 based on a latch signal from, for example, the control circuit 100. The segment driver circuit 31 then generates and outputs a segment drive signal based on the data latched to the line latch 70. The line latch 70 is implemented using a flip-flop circuit or the like.

[0034] The control circuit 100 is a logic circuit that operates based on a clock signal from, for example, the oscillator circuit 120. The control circuit 100 can be implemented using, for example, an ASIC (Application Specific Integrated Circuit) with automatic placement and routing such as a gate array, or a processor such as a CPU. The control circuit 100 controls the display timing, sets the operation of the display driver 20, and so on.

[0035] The interface circuit 110 is a circuit that acts as an interface with the external processing unit 300 and performs communication processing between the processing unit 300 and the display driver 20. For example, the interface circuit 110 receives various types of data from the processing unit 300, such as command data and display data. The interface circuit 110 can be implemented using a serial interface circuit such as I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface).

[0036] The oscillation circuit 120 generates an oscillation signal and outputs a clock signal based on the oscillation signal. Each circuit of the display driver 20, such as the control circuit 100, operates based on this clock signal.

[0037] Figure 3 shows an example of the arrangement of segment electrodes and wiring of segment signal lines in the electro-optic panel 200, and Figure 4 shows an example of the arrangement of common electrodes and wiring of common signal lines.

[0038] In Figure 3, the electro-optic panel 200 is provided with segment electrodes ES1 to ES7 and segment signal lines LS1 to LS14. The segment terminals TS1 and TS2 of the display driver 20 are connected to segment electrode ES1 by segment signal lines LS1 and LS2, respectively. Similarly, the segment terminals TS3 and TS4 of the display driver 20 are connected to segment electrode ES2 by segment signal lines LS3 and LS4, respectively. The connection between segment terminals TS5 to TS14 and segment electrodes ES3 to ES7 by segment signal lines LS5 to LS14 is similar. Each of the segment terminals TS1, TS3, TS5, TS7, TS9, TS11, and TS13 in Figure 3 corresponds to the output terminal TQ from which the drive signal SD in Figure 1 is output. Each of the segment terminals TS2, TS4, TS6, TS8, TS10, TS12, and TS14 corresponds to the input terminal TI from which the monitor signal SM is input. Although Figure 3 shows an example where the segment electrode is a 7-segment display electrode, there are various types of segment electrodes, such as icon electrodes for warning lights.

[0039] In Figure 4, the electro-optical panel 200 is provided with common electrodes EC1 to EC7 and common signal lines LC1 and LC2. The common terminals TC1 and TC2 of the display driver 20 are connected to the common electrodes EC1 to EC7 by common signal lines LC1 and LC2, respectively. Common terminal TC1 in Figure 4 corresponds to the output terminal TQ from which the drive signal SD in Figure 1 is output. Common terminal TC2 corresponds to the input terminal TI from which the monitor signal SM is input.

[0040] 2. Test circuit, driver circuit Figures 5 and 6 show detailed configuration examples of the test circuit 40 and driver circuit 30. Figure 5 shows a configuration example where the test circuit 40 and driver circuit 30 are the segment test circuit 41 and segment driver circuit 31 of Figure 2, respectively. Figure 6 shows a configuration example where the test circuit 40 and driver circuit 30 are the common test circuit 42 and common driver circuit 32 of Figure 2, respectively. In Figure 5, the driver circuit 30 outputs a drive signal SD for the segment based on display data from the data storage circuit 80. In contrast, in Figure 6, no such display data is input, and the driver circuit 30 outputs a drive signal SD for the common based on the control of the control circuit 100. In the following explanation, for the sake of simplicity, the configuration of Figure 5 will be used as the main example.

[0041] The polarity inversion circuit 74 performs polarity inversion processing on the data for display of the segment read from the data storage circuit 80 based on the polarity signal input from the control circuit 100. For example, the polarity inversion circuit 74 outputs data DI at the same logic level as the display data for positive polarity frames, and outputs data DI with the logic level of the display data inverted for negative polarity frames. The latch 72 latches the data DI from the polarity inversion circuit 74 based on the latch signal LT from the control circuit 100. The latch 72 is a latch that constitutes the line latch 70 in Figure 2, and is implemented by, for example, a flip-flop circuit.

[0042] The driver circuit 30 includes a level shifter 36 and an output driver 34. The level shifter 36 receives the latched data DQ from the latch 72 and performs a level shift of the data DQ signal. For example, the level shifter 36 performs a level shift from the logic power supply voltage level to the drive power supply voltage level of the electro-optic panel 200. The output driver 34 then outputs a drive signal SD based on the display signal after the level shift by the level shifter 36.

[0043] The test circuit 40 includes a comparison circuit 50, a judgment circuit 56, a reference voltage generation circuit 58, a potential setting circuit 60, and a switch SW. The comparison circuit 50 includes a comparator 52 and a level shifter 54.

[0044] The switch SW is turned on when the inspection circuit 40 is in judgment mode, which determines whether there is a drive abnormality. As a result, the monitor signal SM from the display electrode EL is input to the comparator 52 of the comparison circuit 50 via the turned-on switch SW.

[0045] The reference voltage generation circuit 58 generates reference voltages VRH and VRL based on the power supply voltages VCC and VSS. VCC is the drive power supply voltage for the high-potential side of the electro-optic panel 200, and VSS is the power supply voltage for the low-potential side. For example, the reference voltage generation circuit 58 is composed of a ladder resistor circuit having multiple resistors connected in series to the VCC node and the VSS node, and generates reference voltages VRH and VRL by voltage division by these multiple resistors. Reference voltage VRH is the reference voltage on the high-potential side, which is the VCC side, and reference voltage VRL is the reference voltage on the low-potential side, which is the VSS side. Reference voltage VRH is, for example, about 60-90% of VCC, and reference voltage VRL is, for example, about 10-40% of VCC. As an example, reference voltage VRH is, for example, about 70% of VCC, and reference voltage VRL is, for example, about 30% of VCC.

[0046] The comparator 52 of the comparison circuit 50 compares the voltage of the monitor signal SM from the display electrode EL with the reference voltages VRH and VRL, and the comparison result is output from the comparison circuit 50 as signal CQ via the level shifter 54. The level shifter 54 performs a level shift, converting the drive power supply voltage level of the electro-optical panel 200 to the logic power supply voltage level. For example, the comparison circuit 50 outputs a signal CQ, which is a high level, at the first logic level, when the voltage of the monitor signal SM is higher than the high-potential reference voltage VRH. The comparison circuit 50 also outputs a signal CQ, which is a low level, at the second logic level, when the voltage of the monitor signal SM is lower than the low-potential reference voltage VRL. The comparison circuit 50 may also output a signal CQ indicating a test error when the voltage of the monitor signal SM is between the high-potential reference voltage VRH and the low-potential reference voltage VRH.

[0047] The judgment circuit 56 receives the data DQ from the latch 72 as the expected value EV. For example, if the driver circuit 30 outputs a high-level drive signal SD, the high-level expected value EV is input to the judgment circuit 56. If the driver circuit 30 outputs a low-level drive signal SD, the low-level expected value EV is input to the judgment circuit 56. The judgment circuit 56 then compares the expected value EV with the comparison result signal CQ from the comparison circuit 50 to determine whether or not an abnormality has occurred.

[0048] For example, the determination circuit 56 determines that no abnormality has occurred when the drive signal SD is at a high level, the expected value EV is at a high level, the voltage of the monitor signal SM is higher than the reference voltage VRH, and the signal CQ is at a high level. On the other hand, when the expected value EV is at a high level, the circuit determines that an abnormality has occurred if the signal CQ is at a low level or is a signal indicating a detection error.

[0049] Furthermore, the determination circuit 56 determines that no abnormality has occurred if the drive signal SD is at a low level and the expected value EV is at a low level, and the voltage of the monitor signal SM is lower than the reference voltage VRL and the signal CQ is at a low level. On the other hand, if the expected value EV is at a low level and the signal CQ is at a high level or is a signal indicating a detection error, the circuit determines that an abnormality has occurred.

[0050] In this way, the determination circuit 56 can determine that no abnormality has occurred when the driver circuit 30 is outputting a high-level drive signal SD to the display electrode EL, and the voltage of the monitor signal SM from the display electrode EL is the voltage corresponding to the high level. Also, the determination circuit 56 can determine that no abnormality has occurred when the driver circuit 30 is outputting a low-level drive signal SD to the display electrode EL, and the voltage of the monitor signal SM from the display electrode EL is the voltage corresponding to the low level.

[0051] 3. Potential setting circuit Next, the configuration and operation of the potential setting circuit 60 of this embodiment will be described in detail. Figures 7, 8, and 9 are explanatory diagrams of the configuration and operation of the potential setting circuit 60.

[0052] In Figure 7, the potential setting circuit 60 includes a pull-up resistor RU and switch SWU, and a pull-down resistor RD and switch SWD. The pull-up resistor RU and switch SWU are connected in series between the node of the high-potential power supply voltage VCC and node N1 of the signal line L2 of the monitor signal SM. The pull-down resistor RD and switch SWD are connected in series between the node of the low-potential power supply voltage VSS and node N1 of the signal line L2 of the monitor signal SM.

[0053] The reference voltage generation circuit 58 also includes resistors RA1 and RA2 connected in series between the node for the high-potential power supply voltage VCC and the node for the low-potential power supply voltage VSS. The reference voltage VR is then generated and output at the connection node N2 between resistors RA1 and RA2. As shown in Figures 5 and 6, it is desirable to generate two reference voltages, VRH and VRL, for the high-potential and low-potential sides for accurate anomaly detection, but for the sake of simplicity, the following explanation will mainly use the case where there is only one reference voltage VR as an example.

[0054] The driver circuit 30 includes a pre-buffer circuit 33 composed of an inverter circuit, and an output driver 34 that receives the output signal from the pre-buffer circuit 33 and outputs a drive signal SD.

[0055] For example, in Figure 8, the driver circuit 30 outputs a high-level drive signal SD, but a break has occurred in the signal line L1. Due to this break, the signal line L2 of the monitor signal SM is no longer driven by the driver circuit 30, and therefore, unless the potential setting circuit 60 is provided, the potential of the monitor signal SM will become unstable.

[0056] In this embodiment, when the drive signal SD output by the driver circuit 30 is at a high level, the pull-down switch SWD of the potential setting circuit 60 is turned on. When switch SWD is turned on in this way, the signal line L2 of the monitor signal SM is pulled down to a low level by the pull-down resistor RD. When the comparison circuit 50 receives the monitor signal SM which has been pulled down to a low level, it outputs a signal CQ indicating a low level as the comparison result because the voltage of the monitor signal SM is lower than the reference voltage VR. On the other hand, when the drive signal SD is at a high level, the expected value EV indicating a high level is input to the judgment circuit 56. As a result, the judgment circuit 56 determines that an abnormality has occurred because the level of the comparison result signal CQ does not match the expected value EV. Therefore, a break in the signal line L1 can be properly determined as an abnormality.

[0057] Furthermore, in Figure 9, the driver circuit 30 outputs a low-level drive signal SD, but a break has occurred in the signal line L1. Due to this break, the signal line L2 of the monitor signal SM is no longer driven by the driver circuit 30, and therefore, unless the potential setting circuit 60 is provided, the potential of the monitor signal SM will become unstable.

[0058] In this embodiment, when the drive signal SD output by the driver circuit 30 is at a low level, the pull-up switch SWU of the potential setting circuit 60 is turned on. When the switch SWU is turned on in this way, the signal line L2 of the monitor signal SM is pulled up to a high level by the pull-up resistor RU. When the comparison circuit 50 receives the monitor signal SM which has been pulled down to a high level, it outputs a signal CQ indicating a high level as the comparison result because the voltage of the monitor signal SM is higher than the reference voltage VR. On the other hand, when the drive signal SD is at a low level, the expected value EV indicating a low level is input to the judgment circuit 56. As a result, the judgment circuit 56 determines that an abnormality has occurred because the level of the comparison result signal CQ does not match the expected value EV. Therefore, a break in the signal line L1 can be properly determined as an abnormality.

[0059] As described above, the potential setting circuit 60 includes a pull-up resistor RU and a switch SWU provided in series between the node of the high-potential power supply voltage VCC and node N1 of the signal line L2 of the monitor signal SM, and a pull-down resistor RD and a switch SWD provided in series between the node of the low-potential power supply voltage VSS and node N1 of the signal line L2 of the monitor signal SM. In this configuration, for example, when the pull-down switch SWD is turned on by the control signal SC2 from the control circuit 100, the signal line L2 of the monitor signal SM can be pulled down by the pull-down resistor RD. Also, when the pull-up switch SWU is turned on by the control signal SC1 from the control circuit 100, the signal line L2 of the monitor signal SM can be pulled up by the pull-up resistor RU. Therefore, even if an abnormality such as a break in the signal line L1 occurs and the potential of the signal line L2 becomes unstable, the signal line L2 of the monitor signal SM can be pulled down or pulled up by turning on the pull-down switch SWD or the pull-up switch SWU. This prevents situations in which the judgment circuit 56 is unable to correctly detect abnormalities.

[0060] Additionally, the pull-down switch SWD turns on when the drive signal SD is at a high level, and the pull-up switch SWU turns on when the drive signal SD is at a low level.

[0061] In this way, when the drive signal SD of the driver circuit 30 is at a high level, the pull-down switch SWD is turned on, which pulls down the signal line L2 of the monitor signal SM and sets it to a low level. As a result, the comparison circuit 50 outputs a comparison result corresponding to the low level. When the drive signal SD is at a high level, the judgment circuit 56 receives the expected value EV corresponding to the high level, so it can correctly detect that an abnormality has occurred. Also, when the drive signal SD of the driver circuit 30 is at a low level, the pull-up switch SWU is turned on, which pulls up the signal line L2 of the monitor signal SM and sets it to a high level. As a result, the comparison circuit 50 outputs a comparison result corresponding to the high level. When the drive signal SD is at a low level, the judgment circuit 56 receives the expected value EV corresponding to the low level, so it can correctly detect that an abnormality has occurred.

[0062] Furthermore, the resistance values ​​of the pull-down resistor RD and the pull-up resistor RU are higher than the on-resistance value of the drive transistor of the driver circuit 30. For example, the drive transistor is a P-type or N-type transistor that constitutes the output driver 34 of the driver circuit 30 shown in Figures 7 to 9. For example, in normal operation when no abnormality occurs, when the drive signal SD is at a high level, if the pull-down switch SWD is turned on, the drive signal SD is pulled down to a low potential via the pull-down resistor RD. Also, when the drive signal SD is at a low level, if the pull-up switch SWU is turned on, the drive signal SD is pulled up to a high potential via the pull-up resistor RU. At this time, if the resistance values ​​of the pull-down resistor RD and the pull-up resistor RU are lower than the on-resistance value of the drive transistor of the driver circuit 30, it may adversely affect the driving of the display electrode EL by the drive signal SD. In this embodiment, the resistance values ​​of the pull-down resistor RD and the pull-up resistor RU are higher than the on-resistance value of the drive transistor of the driver circuit 30, and are set to a resistance value of, for example, 2 to 10 times or more. For example, the on-resistance of the drive transistor is, for instance, around 1kΩ to several kΩ, while the resistances of resistors RD and RU are, for example, around several tens to several hundred kΩ. In this way, even when the drive signal SD is pulled down via the pull-down resistor RD when it is at a high level, or pulled up via the pull-up resistor RU when the drive signal SD is at a low level, it is possible to sufficiently reduce the adverse effects on the driving of the display electrode EL.

[0063] Figure 10 shows another configuration example of the potential setting circuit 60. In Figure 10, instead of the pull-up resistor RU and switch SWU, and the pull-down resistor RD and switch SWD shown in Figures 7 to 9, the potential setting circuit 60 has a pull-up transistor TRU and a pull-down transistor TRD. Similar to resistors RD and RU, the on-resistance values ​​of transistors TRU and TRD are higher than the on-resistance values ​​of the drive transistors of the driver circuit 30. The pull-up transistor TRU is provided between the node of the high-potential power supply voltage VCC and node N1 of the signal line L2 of the monitor signal SM. For example, in a P-type pull-up transistor TRU, the source is connected to the node of VCC, the drain is connected to node N1, and the control signal SC1 is input to the gate. The pull-down transistor TRD is provided between the node of the low-potential power supply voltage VSS and node N1 of the signal line L2 of the monitor signal SM. For example, in an N-type pull-down transistor TRD, the source is connected to the VSS node, the drain is connected to node N1, and the control signal SC2 is input to the gate.

[0064] When the drive signal SD is at a high level, the control signal SC2 from the control circuit 100 turns on the pull-down transistor TRD, causing the signal line L2 of the monitor signal SM to be pulled down. As a result, the comparison circuit 50 outputs a signal CQ indicating a low level. When the drive signal SD is at a high level, the judgment circuit 56 receives an expected value EV indicating a high level, which does not match the signal CQ indicating a low level, and therefore correctly determines that an abnormality has occurred.

[0065] Furthermore, when the drive signal SD is at a low level, the control signal SC1 from the control circuit 100 turns on the pull-up transistor TRU, which pulls up the signal line L2 of the monitor signal SM. As a result, the comparator circuit 50 outputs a signal CQ indicating a high level. When the drive signal SD is at a low level, the judgment circuit 56 receives an expected value EV indicating a low level, which does not match the signal CQ indicating a high level, and therefore correctly determines that an abnormality has occurred.

[0066] Thus, the potential setting circuit 60 includes a pull-up transistor TRU provided between the node of the high-potential power supply voltage VCC and node N1 of the signal line L2 of the monitor signal SM, and a pull-down transistor TRD provided between the node of the low-potential power supply voltage VSS and node N1 of the signal line L2 of the monitor signal SM.

[0067] In this way, for example, the control signal SC2 from the control circuit 100 turns on the pull-down transistor TRD, allowing the signal line L2 of the monitor signal SM to be pulled down. Also, the control signal SC1 from the control circuit 100 turns on the pull-up transistor TRU, allowing the signal line L2 of the monitor signal SM to be pulled up. Therefore, even if an abnormality such as a break in the signal line L1 occurs and the potential of the signal line L2 becomes unstable, the pull-down transistor TRD or the pull-up transistor TRU will turn on, allowing the signal line L2 of the monitor signal SM to be pulled down or pulled up. This prevents a situation in which the judgment circuit 56 cannot correctly detect an abnormality.

[0068] Figure 11 is a signal waveform diagram illustrating the operation of this embodiment. As shown in A1 and A2 of Figure 11, the display data DI is latched to the latch 72 in Figure 5 and output to the driver circuit 30 as data DQ. As a result, as shown in A3 and A4, the drive signal SD is output to the display electrode EL, and the monitor signal SM corresponding to the drive signal SD is input to the comparison circuit 50 of the inspection circuit 40.

[0069] In other words, as shown in A3, when the drive signal SD is low level, the monitor signal SM is also low level, and as shown in A4, when the drive signal SD is high level, the monitor signal SM is also high level. When the drive signal SD is low level, the switch SWU of the potential setting circuit 60 in Figure 7 is turned on, and the signal line L2 of the monitor signal SM is pulled up. However, since the on-resistance of the N-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance of resistor RU, the low level of the monitor signal SM is maintained. Also, when the drive signal SD is high level, the switch SWD of the potential setting circuit 60 is turned on, and the signal line L2 of the monitor signal SM is pulled down. However, since the on-resistance of the P-type drive transistor of the driver circuit 30 is sufficiently lower than the resistance of resistor RD, the high level of the monitor signal SM is maintained.

[0070] In A5, since the voltage of the monitor signal SM is lower than the reference voltage VRL (or VR), the signal CQ output by the comparator circuit 50 becomes low level. In A6, since the voltage of the monitor signal SM is higher than the reference voltage VRH (or VR), the signal CQ becomes high level. In A5 and A6, the voltage level of the expected value EV corresponding to DQ matches the voltage level of the signal CQ, so as shown in A7 and A8, the judgment result signal JQ of the judgment circuit 56 becomes a voltage level (e.g., low level) indicating that no abnormality has occurred.

[0071] In Figure 11, at A9, a disconnection occurs in the signal line L1, etc. When such a disconnection occurs, the signal line L2 of the monitor signal SM is not driven by the driver circuit 30, and therefore the signal line L2 becomes high impedance. If a signal line near signal line L2 is driven by the same drive signal as the drive signal SD, then when the drive signal of the nearby signal line becomes high level, the monitor signal SM will also become high level due to the coupling of capacitances between the wires. Conversely, when the drive signal of the nearby signal line becomes low level, the monitor signal SM will also become low level due to the coupling of capacitances between the wires. As a result, the judgment circuit 56 may mistakenly determine that no abnormality has occurred because the voltage level of the monitor signal SM matches the expected value EV.

[0072] In this embodiment, as shown in A10, when the drive signal SD is at a high level, the switch SWD in Figure 7 is turned on, and the signal line L2, which is in a high impedance state, is pulled down. As a result, as shown in A11, the voltage of the monitor signal SM becomes low, and as shown in A12, the comparison result signal CQ of the comparison circuit 50 also becomes low. Therefore, the high level, which is the voltage level of the expected value EV of the drive signal SD, and the low level, which is the voltage level of the signal CQ, do not match, so as shown in A13, the judgment result signal JQ of the judgment circuit 56 becomes a voltage level (for example, a high level) that indicates that an abnormality has occurred.

[0073] Similarly, as shown in A14, when the drive signal SD is at a low level, the switch SWU in Figure 7 is turned on, and the signal line L2, which is in a high impedance state, is pulled up. As a result, as shown in A15, the voltage of the monitor signal SM becomes high, and as shown in A16, the signal CQ of the comparator circuit 50 also becomes high. Therefore, the low level, which is the voltage level of the expected value EV of the drive signal SD, and the high level, which is the voltage level of the signal CQ, do not match, so as shown in A17, the signal JQ of the judgment result of the judgment circuit 56 becomes a voltage level that indicates an abnormality has occurred.

[0074] In this embodiment, the determination circuit 56 determines that a break has occurred in the signal line L1 of the drive signal SD if the comparison result of the comparison circuit 50 does not correspond to the expected value EV. For example, in A12 and A13 of Figure 11, the low level, which is the voltage level of signal CQ, the comparison result of the comparison circuit 50, does not match the high level, which is the voltage level of the expected value EV of the drive signal SD, so the determination circuit 56 determines that an abnormality such as a break has occurred. Also, in A16 and A17, the high level, which is the voltage level of signal CQ of the comparison circuit 50, does not match the low level, which is the voltage level of the expected value EV of the drive signal SD, so the determination circuit 56 determines that an abnormality such as a break has occurred. In this way, the determination circuit 56 can determine whether an abnormality such as a break has occurred in the signal line L1 of the drive signal SD simply by determining whether the comparison result of the comparison circuit 50 matches the expected value EV corresponding to the voltage level of the drive signal SD. In this embodiment, even if the potential of signal line L2 becomes unstable due to a break in signal line L1 or the like, the potential setting circuit 60 performs a pull-down when the drive signal SD is at a high level and a pull-up when the drive signal SD is at a low level. Therefore, the determination circuit 56, which determines whether the comparison result of the comparison circuit 50 matches the expected value EV as described above, is prevented from correctly detecting the occurrence of a break in the wire.

[0075] As described above, the display driver of this embodiment includes a driver circuit that outputs a drive signal, an output terminal that outputs a drive signal to the display electrodes of an electro-optical panel, an input terminal that receives a monitor signal from the display electrodes, and a test circuit. The test circuit includes a comparison circuit that compares the voltage of the monitor signal with a reference voltage, a determination circuit that determines an abnormality based on the expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit, and a potential setting circuit that pulls down or pulls up the signal line of the monitor signal according to the voltage level of the drive signal.

[0076] According to this embodiment, the comparison circuit of the inspection circuit compares the voltage of the monitor signal with the reference voltage, and the judgment circuit determines whether there is an abnormality such as a broken wire based on the expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit. The potential setting circuit then pulls down or pulls up the signal line of the monitor signal according to the voltage level of the drive signal. Therefore, even if an abnormality such as a broken wire occurs and the potential of the signal line of the monitor signal becomes unstable, the potential setting circuit pulls down or pulls up the signal line of the monitor signal, preventing the judgment circuit from failing to correctly detect the abnormality.

[0077] In this embodiment, the potential setting circuit may pull down the signal line of the monitor signal when the drive signal is at a high level, and pull up the signal line of the monitor signal when the drive signal is at a low level.

[0078] In this way, when the drive signal is at a high level, the potential setting circuit pulls down the signal line of the monitor signal, preventing the monitor signal's potential from being pulled to the high level side due to coupling of capacitances between wires, etc. Also, when the drive signal is at a low level, the potential setting circuit pulls up the signal line of the monitor signal, preventing the monitor signal's potential from being pulled to the low level side due to coupling of capacitances between wires, etc.

[0079] In this embodiment, the potential setting circuit may also include a pull-up resistor and a pull-up switch provided in series between the high-potential power supply voltage node and the monitor signal line node, and a pull-down resistor and a pull-down switch provided in series between the low-potential power supply voltage node and the monitor signal line node.

[0080] In this way, even if an abnormality such as a broken wire occurs and the potential of the monitor signal line becomes unstable, the pull-down or pull-up switch will turn on, allowing the monitor signal line to be pulled down or pulled up, thus preventing a situation where the judgment circuit cannot correctly detect the abnormality.

[0081] In this embodiment, the pull-down switch may be turned on when the drive signal is at a high level, and the pull-up switch may be turned on when the drive signal is at a low level.

[0082] In this configuration, when the drive signal is at a high level, the pull-down switch turns on, pulling down the monitor signal line and setting it to a low level. Conversely, when the drive signal is at a low level, the pull-up switch turns on, pulling up the monitor signal line and setting it to a high level.

[0083] In this embodiment, the resistance values ​​of the pull-down resistor and the pull-up resistor may be higher than the on-resistance value of the drive transistor of the driver circuit.

[0084] In this way, even when the drive signal is at a high level and pulled down by a pull-down resistor, or when the drive signal is at a low level and pulled up by a pull-up resistor, the adverse effects on driving the display electrodes can be reduced.

[0085] In this embodiment, the potential setting circuit may also include a pull-up transistor provided between the high-potential power supply voltage node and the monitor signal line node, and a pull-down transistor provided between the low-potential power supply voltage node and the monitor signal line node.

[0086] In this way, even if an abnormality such as a broken wire occurs and the potential of the monitor signal line becomes unstable, the pull-down or pull-up transistor will turn on, allowing the monitor signal line to be pulled down or pulled up, thus preventing a situation where the judgment circuit cannot correctly detect the abnormality.

[0087] In this embodiment, the determination circuit may also determine that a break has occurred in the signal line of the drive signal when the comparison result of the comparison circuit does not correspond to the expected value.

[0088] In this way, the judgment circuit can determine the occurrence of a wire break simply by determining whether the comparison result of the comparison circuit matches the expected value corresponding to the voltage level of the drive signal.

[0089] Furthermore, the display device of this embodiment includes the display driver described above and an electro-optical panel.

[0090] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of the display driver and display device, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of Symbols]

[0091] 10…Display device, 20…Display driver, 30…Driver circuit, 31…Segment driver circuit, 32…Common driver circuit, 33…Pre-buffer circuit, 34…Output driver, 36…Level shifter, 40…Test circuit, 41…Segment test circuit, 42…Common test circuit, 50…Comparison circuit, 52…Comparator, 54…Level shifter, 56…Decision circuit, 58…Reference voltage generation circuit, 60…Potential setting circuit, 70…Line latch, 72…Latch, 74… Polarity inversion circuit, 80...Data storage circuit, 100...Control circuit, 110...Interface circuit, 120...Oscillator circuit, 200...Electro-optic panel, 300...Processing unit, EL...Display electrode, EV...Expected value, L1, L2...Signal line, LT...Latch signal, RA, RA2, RD, RU...Resistor, SD...Drive signal, SM...Monitor signal, SW, SWD, SWU...Switch, TI...Input terminal, TQ...Output terminal, TRD, TRU...Transistor, VR, VRH, VRL...Reference voltage

Claims

1. A driver circuit that outputs a drive signal, The display electrode of the electro-optical panel has an output terminal that outputs the drive signal, An input terminal into which a monitor signal is input from the aforementioned display electrode, Test circuit and, Includes, The aforementioned test circuit is A comparison circuit that compares the voltage of the monitor signal with a reference voltage, A determination circuit that determines an abnormality based on the expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit, A potential setting circuit that pulls down or pulls up the signal line of the monitor signal according to the voltage level of the drive signal, A display driver characterized by including the following.

2. In the display driver described in claim 1, The aforementioned potential setting circuit is When the drive signal is at a high level, the signal line of the monitor signal is pulled down. A display driver characterized by performing a pull-up on the signal line of the monitor signal when the drive signal is at a low level.

3. In the display driver described in claim 2, The aforementioned potential setting circuit is A pull-up resistor and a pull-up switch are provided in series between the node of the high-potential power supply voltage and the node of the signal line of the monitor signal. A pull-down resistor and a pull-down switch are provided in series between the low-potential power supply voltage node and the signal line node of the monitor signal, A display driver characterized by including the following.

4. In the display driver described in claim 3, The aforementioned pull-down switch turns on when the drive signal is at a high level. The indicator driver is characterized in that the pull-up switch turns on when the drive signal is at a low level.

5. In the display driver described in claim 3, A display driver characterized in that the resistance values ​​of the pull-down resistor and the pull-up resistor are higher than the on-resistance value of the drive transistor of the driver circuit.

6. In the display driver described in claim 2, The aforementioned potential setting circuit is A pull-up transistor is provided between the node of the high-potential power supply voltage and the node of the signal line of the monitor signal, A pull-down transistor is provided between the low-potential power supply voltage node and the signal line node of the monitor signal, A display driver characterized by including the following.

7. In the display driver described in claim 1, The aforementioned determination circuit is A display driver characterized in that, when the comparison result of the comparison circuit does not correspond to the expected value, it is determined that a break has occurred in the signal line of the drive signal.

8. A display driver as described in any one of claims 1 to 7, The aforementioned electro-optical panel, A display device characterized by including

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