Liquid dispensing device and capacitive load drive circuit

Abstract

To provide a liquid dispensing device that can increase the frequency of the drive signal. [Solution] A capacitive load drive circuit that outputs a drive signal to displace a capacitive load comprises: an amplification circuit that outputs an amplified modulated signal by driving a first transistor that is driven in accordance with a first gate drive signal corresponding to a modulated signal obtained by modulating a base drive signal output by a modulation circuit, and a second transistor that is driven in accordance with a second gate drive signal corresponding to the modulated signal; and a demodulation circuit that outputs a drive signal obtained by demodulating the amplified modulated signal, wherein at least one of the first transistor and the second transistor comprises a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer, in a liquid dispensing device.

Description

Technical Field

[0001] The present invention relates to a liquid ejection device and a capacitive load drive circuit.

Background Art

[0002] In a liquid ejection device that ejects liquid by driving a capacitive load such as a piezoelectric element, as a capacitive circuit drive circuit that outputs a drive signal for driving the capacitive load, a so-called class D amplifier circuit that modulates a signal waveform defined by a base drive signal that is the basis of the drive signal, amplifies the modulated signal, and generates a drive signal by demodulating the amplified signal is known. Such a capacitive load drive circuit using a class D amplifier circuit has an advantage that it can reduce power consumption compared to a capacitive load drive circuit using a class A amplifier circuit, a class B amplifier circuit, and a class AB amplifier circuit.

[0003] For example, Patent Document 1 discloses a liquid ejection device that outputs a drive signal for driving a piezoelectric element as a capacitive load and includes a drive signal output circuit including a class D amplifier circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In response to the increasing market demand for improving the productivity of recent liquid ejection devices, the liquid ejection device is required to shorten the liquid ejection cycle and increase the frequency of the drive signal for driving the capacitive load so that the liquid is ejected.

[0006] However, in liquid dispensing devices such as the one described in Patent Document 1, when increasing the frequency of the drive signal output by the capacitive load drive circuit (drive signal output circuit) including a Class D amplifier circuit, it is necessary to increase the drive frequency of the amplifier circuit that amplifies the modulated signal obtained by modulating the signal waveform defined by the base drive signal. If the drive frequency of the amplifier circuit is increased, the losses in the amplifier circuit increase, which may negate one of the advantages of a capacitive load drive circuit using a Class D amplifier circuit, which is that power consumption can be reduced.

[0007] In particular, in a configuration where a liquid discharge device controls the amount of liquid discharged by driving a capacitive load with a drive signal and controlling the position of the meniscus of the discharge section by driving the capacitive load, the waveform accuracy of the drive signal greatly contributes to the liquid discharge accuracy. Therefore, the capacitive negative drive circuit is required to output a drive signal containing a signal waveform with a sharp change in voltage value with high waveform accuracy. To achieve a higher frequency drive signal while maintaining high waveform accuracy, it is necessary to further increase the drive frequency of the amplification circuit in the capacitive load drive circuit. As a result, the losses in the amplification circuit increase further, and the power consumption of the capacitive load drive circuit increases further.

[0008] In other words, from the perspective of increasing the frequency of the drive signal output by a capacitive load drive circuit using a Class D amplifier circuit, the technology described in Patent Document 1 alone was insufficient, and there was room for further improvement. [Means for solving the problem]

[0009] One embodiment of the liquid dispensing device according to the present invention is: A capacitive load that is displaced by the supply of a drive signal, A discharge unit that discharges liquid in accordance with the displacement of the capacitive load, A capacitive load drive circuit that outputs the aforementioned drive signal, Equipped with, The capacitive load drive circuit is, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer.

[0010] One embodiment of the capacitive load drive circuit according to the present invention is: A capacitive load drive circuit that outputs a drive signal to a capacitive load that is displaced so as to discharge liquid from a discharge section when a drive signal is supplied, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer. [Brief explanation of the drawing]

[0011] [Figure 1] It is a diagram showing an example of the schematic configuration of a liquid ejection device. [Figure 2] It is a diagram showing an example of the functional configuration of a liquid ejection device. [Figure 3] It is a diagram showing a schematic structure of one of the ejection parts 600. [Figure 4] It is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC. [Figure 5] It is a diagram showing an example of the configuration of a selection control circuit and a selection circuit. [Figure 6] It is a diagram showing an example of the decoding content in a decoder. [Figure 7] It is a diagram showing an example of the configuration of a selection circuit. [Figure 8] It is a diagram for explaining the operations of a selection control circuit and a selection circuit. [Figure 9] It is a diagram showing an example of the configuration of a drive circuit. [Figure 10] It is a diagram showing an example of the structure of transistor M1. [Figure 11] It is a diagram showing an example of the configuration of the drive circuit of the second embodiment. [Figure 12] It is a diagram showing an example of the configuration of the drive circuit of the third embodiment.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0013] 1. First Embodiment 1.1 Outline of the Liquid Ejection Device Figure 1 shows an example of the schematic configuration of a liquid ejection device 1. The liquid ejection device 1 is a serial printing inkjet printer in which a carriage 21 equipped with a head unit 20 that ejects ink as an example of a liquid moves back and forth along the scanning axis and ejects ink onto a medium P that is transported along the transport direction, thereby forming a desired image on the medium P. Any printing target such as printing paper, resin film, or fabric can be used as the medium P used in such a liquid ejection device 1. Note that the liquid ejection device 1 is not limited to a serial printing inkjet printer, but may also be a line printing inkjet printer. Furthermore, the liquid ejection device 1 is not limited to an inkjet printer, but may also be a colorant ejection device used in the manufacture of color filters for liquid crystal displays, an electrode material ejection device used in the formation of electrodes for organic EL displays and FEDs (surface-emitting displays), a bio-organic material ejection device used in the manufacture of biochips, a 3D modeling device, or a textile printing device.

[0014] As shown in Figure 1, the liquid dispensing device 1 comprises an ink container 2, a control unit 10, a head unit 20, a moving unit 30, and a transport unit 40.

[0015] The ink container 2 stores multiple types of ink that are dispensed onto the medium P. The colors of the ink stored in the ink container 2 include black, cyan, magenta, yellow, red, and gray. The ink container 2 can be an ink cartridge, a bag-shaped ink pack made of flexible film, or an ink tank that allows for ink replenishment.

[0016] The control unit 10 includes, for example, processing circuits such as a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array), storage circuits such as semiconductor memory, and various other circuits, and controls each element of the liquid dispensing device 1, including the head unit 20.

[0017] The print head unit 20 is mounted on the carriage 21. The carriage 21 is fixed to an endless belt 32 included in the moving unit 30. In addition to the print head unit 20, the carriage 21 may also be equipped with an ink container 2.

[0018] The head unit 20 mounted on the carriage 21 receives a control signal Ctrl-H, output by the control unit 10, to control the head unit 20. Ink stored in the ink container 2 is supplied to the head unit 20 via a tube (not shown). The head unit 20 then ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H.

[0019] The moving unit 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 is driven based on a control signal Ctrl-C input from the control unit 10. The endless belt 32 rotates in accordance with the drive of the carriage motor 31. This causes the carriage 21, which is fixed to the endless belt 32, to reciprocate along the scanning axis. In other words, the liquid ejection device 1 is a medium, described later, to which the ink ejected from the head unit 20 lands. The carriage 21 is equipped with a carriage that reciprocates along a scanning axis that intersects with the transport direction in which P is transported.

[0020] The transport unit 40 includes a transport motor 41 and transport rollers 42. The transport motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The transport rollers 42 rotate in accordance with the drive of the transport motor 41. As the transport rollers 42 rotate, the medium P is transported in the transport direction.

[0021] In the liquid dispensing device 1 configured as described above, the transport unit 40 transports the medium P and the moving unit 30 moves the carriage 21 back and forth in conjunction with the head unit 20 mounted on the carriage 21, which dispenses ink onto the medium P. As a result, the ink dispensed from the head unit 20 lands at any desired position on the surface of the medium P. Consequently, a desired image is formed on the medium P.

[0022] A specific example of the functional configuration of the liquid dispensing device 1, which is configured as described above, will now be explained. Figure 2 is a diagram showing an example of the functional configuration of the liquid dispensing device 1. As shown in Figure 2, the liquid dispensing device 1 has a control unit 10, a head unit 20, a moving unit 30, and a transport unit 40.

[0023] The control unit 10 has a control circuit 100.

[0024] The control circuit 100 receives an image signal from an external device such as a host computer, generates various control signals corresponding to the image signal, and outputs them to the corresponding configuration.

[0025] Specifically, the control circuit 100 generates control signals Ctrl-T and Ctrl-C when an image signal is input and printing is performed on the medium P. The control signal Ctrl-T output by the control circuit 100 is input to the transport motor 41 included in the transport unit 40. The transport motor 41 is driven according to the control signal Ctrl-T. The medium P is transported along the transport direction by the driving force of this transport motor 41. The control signal Ctrl-C output by the control circuit 100 is input to the carriage motor 31 included in the moving unit 30. The carriage motor 31 is driven according to the control signal Ctrl-C. The carriage 21 on which the head unit 20 is mounted moves back and forth along the scanning axis by the driving force of this carriage motor 31. The transport unit 40 may include one or more transport rotors in addition to the transport motor 41. The transport unit 40 may also include a transport motor driver circuit for converting the control signal Ctrl-T into a predetermined signal to drive the transport motor 41. Furthermore, the mobile unit 30 may include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal for driving the carriage motor 31.

[0026] Furthermore, the control circuit 100 generates a control signal Ctrl-H, consisting of a clock signal SCK, a print data signal SI, a latch signal LAT, and digital base drive signals dA, dB, and dC, based on the image signal input from an external device, and outputs them to the head unit 20.

[0027] The head unit 20 includes drive circuits 50a, 50b, 50c, a reference voltage output circuit 52, a selection control circuit 210, a plurality of selection circuits 230, and a plurality of discharge units 600. The plurality of discharge units 600 are provided corresponding to each of the plurality of selection circuits 230.

[0028] In other words, the carriage 21 is equipped with a head unit 20 which includes a piezoelectric element 60, a discharge section 600, and drive circuits 50a, 50b, and 50c.

[0029] The base drive signal dA is input to the drive circuit 50a. The drive circuit 50a converts the input base drive signal dA from digital to analog, and generates and outputs the drive signal COMA as the drive signal COM by amplified in Class D of the converted analog signal. The base drive signal dB is input to the drive circuit 50b. The drive circuit 50b converts the input base drive signal dB from digital to analog, and generates and outputs the drive signal COMB as the drive signal COM by amplified in Class D of the converted analog signal. The base drive signal dC is input to the drive circuit 50c. The drive circuit 50c converts the input base drive signal dC from digital to analog, and generates and outputs the drive signal COMC as the drive signal COM by amplified in Class D of the converted analog signal.

[0030] The reference voltage output circuit 52 generates and outputs a reference voltage signal VBS, which is a constant DC voltage with a voltage value of 5.5V, 6V, etc., by boosting or lowering the power supply voltage (not shown). This reference voltage signal VBS functions as the reference potential for driving the piezoelectric element 60 of the discharge unit 600, which will be described later. Note that the voltage value of the reference voltage signal VBS is not limited to 5.5V or 6V, but may also be the ground potential.

[0031] The clock signal SCK, the print data signal SI, and the latch signal LAT are input to the selection control circuit 210. Based on the input clock signal SCK, print data signal SI, and latch signal LAT, the selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230 and outputs it to the corresponding selection circuit 230.

[0032] Each selection circuit 230 receives the drive signals COMA, COMB, and COMC, and the corresponding selection signal S output by the selection control circuit 210. Based on the input selection signal S, the selection circuit 230 selects or deselects each of the drive signals COMA, COMB, and COMC, thereby generating a drive signal VOUT corresponding to each of the multiple dispensing units 600 and supplying it to the corresponding dispensing unit 600.

[0033] Each of the multiple ejection units 600 includes a piezoelectric element 60. A drive signal VOUT, output by the corresponding selection circuit 230, is supplied to one end of the piezoelectric element 60 in each of the multiple ejection units 600. A reference voltage signal VBS, output by the reference voltage output circuit 52, is supplied to the other end of the piezoelectric element 60 in each of the multiple ejection units 600. The piezoelectric element 60 is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the drive of the piezoelectric element 60 is ejected from the ejection unit 600.

[0034] Here, an example of the structure of the discharge section 600 of the head unit 20 will be described. Figure 3 is a schematic diagram of one of the multiple discharge sections 600 of the head unit 20. As shown in Figure 3, the discharge section 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651.

[0035] Cavity 631 is filled with ink supplied from reservoir 641. Ink is also introduced into reservoir 641 from ink container 2 via an ink tube (not shown) and supply port 661. In other words, cavity 631 is filled with ink stored in the corresponding ink container 2.

[0036] The diaphragm 621 is displaced by the drive of the piezoelectric element 60 located on its upper surface in Figure 3. As the diaphragm 621 is displaced, the internal volume of the cavity 631, where the ink is filled, expands and contracts. In other words, the diaphragm 621 functions as a diaphragm that changes the internal volume of the cavity 631.

[0037] The nozzle 651 is provided on the nozzle plate 632 and is an opening that communicates with the cavity 631. As the internal volume of the cavity 631 changes, an amount of ink corresponding to the change in internal volume is ejected from the nozzle 651.

[0038] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In a piezoelectric body 601 with this structure, the central portion of the electrodes 611 and 612 flexes vertically together with the diaphragm 621 in accordance with the potential difference of the signal supplied to the electrodes 611 and 612.

[0039] For example, a drive signal VOUT is supplied to one end of the piezoelectric element 60, to either electrode 611 or electrode 612, and a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60, to the other electrode 611 or electrode 612. When the voltage value of the drive signal VOUT increases, the piezoelectric element 60 bends upward. As the piezoelectric element 60 bends upward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is drawn in from the reservoir 641. On the other hand, when the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 bends downward. As the piezoelectric element 60 bends downward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 shrinks. As a result, an amount of ink corresponding to the degree of shrinkage is ejected from the nozzle 651.

[0040] In other words, the ejection unit 600 includes a piezoelectric element 60 that is driven by a drive signal VOUT based on a drive signal COM, and the piezoelectric element 60 is driven to eject ink. In other words, the head unit 20 ejects ink according to the drive signals COMA, COMB, and COMC.

[0041] In this embodiment, the liquid ejection device 1 is assumed to have a head unit 20 with 3,000 or more ejection units 600, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more ejection units 600, with the aim of improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. Specifically, the head unit 20 is assumed to have 3,000 or more piezoelectric elements 60, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more piezoelectric elements 60. This increases the amount of ink that can be ejected at once, which in turn increases the number of dots that can be formed on the medium P at once, thereby improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. Specifically, the head unit 20 includes 3,000 or more piezoelectric elements 60, and these 3,000 or more piezoelectric elements 60 are driven by the drive signal COM output by the drive circuit 50.

[0042] The structure of the piezoelectric element 60 is not limited to the example shown in Figure 3; any structure that allows ink to be ejected from the ejection unit 600 is acceptable. Therefore, the structure of the piezoelectric element 60 is not limited to the bending vibration structure described above; for example, a structure using longitudinal vibration may also be used. Furthermore, the piezoelectric element 60 may be configured to bend downward when the voltage value of the drive signal VOUT increases, and to bend upward when the voltage value of the drive signal VOUT decreases.

[0043] As described above, the liquid dispensing device 1 of this embodiment includes a piezoelectric element 60 that is displaced when a drive signal VOUT based on drive signals COMA, COMB, and COMC is supplied, a dispensing unit 600 that dispenses ink in accordance with the displacement of the piezoelectric element 60, and a drive circuit 50a that outputs a drive signal COMA, a drive circuit 50b that outputs a drive signal COMB, and a drive circuit 50c that outputs a drive signal COMC.

[0044] 1.2 Signal waveform of the drive signal Next, the drive signals COMA, COMB, CO output by the drive circuits 50a, 50b, and 50c. An example of each signal waveform of the MC will be explained. Figure 4 shows an example of the signal waveforms of the drive signals COMA, COMB, and COMC. As shown in Figure 4, each of the drive signals COMA, COMB, and COMC includes drive waveforms Adp, Bdp, and Cdp, which are arranged in the period tp from when the latch signal LAT rises until when the latch signal LAT rises again. Then, the selection control circuit 210 and the selection circuit 230 select one of the drive signals COMA, COMB, or COMC and one of the drive waveforms Adp, Bdp, or Cdp based on the clock signal SCK and the print data signal SI for each period tp, and output it as the drive signal VOUT.

[0045] As shown in Figure 4, the drive waveform Adp drives the corresponding piezoelectric element 60 by changing the voltage value between voltages va1 and va5 during the period tp. This driving of the piezoelectric element 60 causes a predetermined amount of ink to be ejected from the corresponding nozzle 651. In other words, the drive waveform Adp included in the drive signal COMA is a signal waveform for driving the corresponding piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600. Hereinafter, in the explanation, we will assume that voltage va1 is 36V, voltage va2 is 15V, voltage va3 is 12V, voltage va4 is 8V, and voltage va5 is 5V, but the values ​​of voltages va1 to va5 are not limited to these.

[0046] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Adp is constant at voltage va3. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta1 and becomes constant at voltage va1 at time ta2. Then, the voltage value of the drive waveform Adp begins to fall at time ta3, becomes constant at voltage va2 at time ta4, begins to fall again at time ta5, and becomes constant at voltage va5 at time ta6. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta7, becomes constant at voltage va4 at time ta8, begins to rise again at time ta9, and becomes constant at voltage va3 at time ta10. After that, the period tp ends as the latch signal LAT rises.

[0047] In the ejection unit 600 to which the drive waveform Adp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time ta1, when the voltage value of the drive waveform Adp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0048] Subsequently, at time ta2, the voltage value of the drive waveform Adp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the discharge unit 600. Then, at time ta3, when the voltage value of the drive waveform Adp decreases, the piezoelectric element 60 in the discharge unit 600 to which the drive waveform Adp is supplied bends downward as shown in Figure 3, and the internal volume of the cavity 631 decreases. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3.

[0049] At time ta4, when the voltage value of the drive waveform Adp becomes constant, the liquid column formed in the center of the meniscus tends to extend downwards due to inertial force, as shown in Figure 3. Then, at time t In step a5, the voltage value of the drive waveform Adp decreases, reducing the internal volume of the cavity 631, which in turn pressurizes the ink stored in the cavity 631. As a result, the ink separates from the liquid column and is ejected as droplets.

[0050] Subsequently, at time ta6, the voltage value of the drive waveform Adp becomes constant, and from time ta7 to ta10, the voltage value of the drive waveform Adp increases and becomes constant at voltage va3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0051] Furthermore, as shown in Figure 4, the drive waveform Bdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vb1 and voltage vb5 during the period tp. This driving of the piezoelectric element 60 causes a smaller amount of ink than the predetermined amount described above to be ejected from the corresponding nozzle 651. In other words, the drive waveform Bdp included in the drive signal COMB is a signal waveform for driving the corresponding piezoelectric element 60 so that a smaller amount of ink than the predetermined amount is ejected from the ejection unit 600. Hereinafter, in the following explanation, we will assume that voltage vb1 is 36V, voltage vb2 is 20V, voltage vb3 is 12V, voltage vb4 is 10V, and voltage vb5 is 7V, but the values ​​of voltages vb1 to vb5 are not limited to these.

[0052] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Bdp is constant at voltage vb3. Subsequently, the voltage value of the drive waveform Bdp begins to rise at time tb1 and becomes constant at voltage vb1 at time tb2. Then, the voltage value of the drive waveform Bdp begins to fall at time tb3, becomes constant at voltage vb4 at time tb4, then begins to rise at time tb5, becomes constant at voltage vb2 at time tb6, then begins to fall at time tb7, and becomes constant at voltage vb5 at time tb8. Finally, the voltage value of the drive waveform Bdp begins to rise at time tb9 and becomes constant at voltage vb3 at time tb10. After that, the latch signal LAT rises, ending period tp.

[0053] In the ejection unit 600 to which the drive waveform Bdp is supplied as described above, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time tb1, when the voltage value of the drive waveform Bdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0054] Subsequently, at time tb2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the ejection unit 600. Then, at time tb3, when the voltage value of the drive waveform Bdp decreases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied bends downward as shown in Figure 3, reducing the internal volume of the cavity 631. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3. It will be accomplished.

[0055] At time tb4, when the voltage value of the drive waveform Bdp becomes constant, the liquid column formed in the center of the meniscus tries to extend downward due to inertia, as shown in Figure 3. Then, at time tb5, as the voltage value of the drive waveform Bdp increases and the internal volume of the cavity 631 increases, the liquid column that was trying to extend downward due to inertia is pulled in. Subsequently, at time tb6, after the voltage value of the drive waveform Bdp becomes constant, at time tb7, as the voltage value of the drive waveform Bdp decreases, the internal volume of the cavity 631 decreases, the ink stored in the cavity 631 is pressurized, the ink separates from the liquid column and is ejected as droplets. At this time, at time tb5, the liquid column that was trying to extend downward as shown in Figure 3 is pulled in by inertial force, and then at time tb7, the pressurized ink droplets separated from the liquid column are ejected. As a result, the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Bdp is less than the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Adp.

[0056] Subsequently, at time tb8, the voltage value of the drive waveform Bdp becomes constant, and at times tb9 to tb10, the voltage value of the drive waveform Bdp increases and becomes constant at voltage vb3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0057] Furthermore, as shown in Figure 4, the drive waveform Cdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vc1 and voltage vc2 during the period tp. This driving of the piezoelectric element 60 prevents ink from being ejected from the corresponding nozzle 651, and causes the ink near the opening of the nozzle 651 to vibrate. This reduces the risk of an increase in the viscosity of the ink near the opening of the nozzle 651. In other words, the drive waveform Cdp included in the drive signal COMC is a signal waveform for driving the piezoelectric element 60 so that ink is not ejected from the ejection unit 600, and the ink near the opening of the nozzle 651 of the ejection unit 600 vibrates. Hereinafter, in the following explanation, we will assume that voltage vc1 is 15V and voltage vc2 is 12V, but the values ​​of voltage vc1 and voltage vc2 are not limited to these.

[0058] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Cdp is constant at voltage vc2. Subsequently, the voltage value of the drive waveform Cdp begins to rise at time tc1 and becomes constant at voltage vc1 at time tc2. Then, the voltage value of the drive waveform Cdp begins to fall at time tc3 and becomes constant at voltage vc1 at time tc4. After that, the period tp ends when the latch signal LAT rises.

[0059] In the ejection unit 600 to which the drive waveform Cdp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, and the position of the meniscus in the nozzle 651, is approximately the same as the position of the tip of the nozzle 651. Then, at time tc1, when the voltage value of the drive waveform Cdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Cdp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 is approximately the same as the position shown in Figure 3. The element moves upward as shown in Figure 3. Then, at time tc2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the ejection unit 600. Then, at time tc3, when the voltage value of the drive waveform Cdp decreases, the piezoelectric element 60 in the ejection unit 600 supplied with the drive waveform Cdp bends downward as shown in Figure 3, reducing the internal volume of the cavity 631. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3. Then, at time tc4, the voltage value of the drive waveform Bdp becomes constant. At this time, the change in the voltage value of the drive waveform Cdp is smaller than the change in the voltage value of the drive waveform Adp and the change in the voltage value of the drive waveform Bdp, and therefore, the ink does not separate from the liquid column. Therefore, the ink from nozzle 651 only vibrates and is not ejected.

[0060] Furthermore, at time tc4, as the voltage value of the drive waveform Cdp becomes constant at voltage vc2, the displacement of the piezoelectric element 60 in the discharge section 600 to which the drive waveform Cdp is supplied, and the internal volume of the cavity 631, are in the rising edge state of the latch signal LAT.

[0061] As described above, the drive circuit 50a outputs a drive signal COMA including a drive waveform Adp that drives the piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600, the drive circuit 50b outputs a drive signal COMB including a drive waveform Bdp that drives the piezoelectric element 60 so that a smaller amount than a predetermined amount of ink is ejected from the ejection unit 600, and the drive circuit 50c outputs a drive signal COMC including a drive waveform Cdp that drives the piezoelectric element 60 so that no ink is ejected from the ejection unit 600, but the ink near the opening of the corresponding nozzle 651 vibrates. In the following description, when the drive waveform Adp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a large amount, and when the drive waveform Bdp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a small amount. Furthermore, when the drive waveform Cdp is supplied to one end of the piezoelectric element 60, the operation that vibrates the ink near the nozzle opening of the ejection unit 600 corresponding to the piezoelectric element 60 is sometimes referred to as micro-vibration.

[0062] In this embodiment, the liquid ejection device 1 aims to improve the speed of image formation on the medium P and, from the viewpoint of improving productivity in the liquid ejection device 1, assumes that the period tp during which ink is ejected from the ejection unit 600 by the drive signals COMA, COMB, COMC is 10 μs or less. That is, assume that the frequency of the period tp, which is the frequency of the drive signals COMA, COMB, COMC output by the drive circuits 50a, 50b, 50c, is 100 kHz or higher. As a result, the liquid ejection device 1 of this embodiment can improve the speed of image formation on the medium P and improve productivity in the liquid ejection device 1.

[0063] 1.3 Configuration and Operation of Selection Control Circuit and Selection Circuit Next, the configuration and operation of the selection control circuit 210 and selection circuit 230, which generate the drive signal VOUT by selecting or deselecting the signal waveforms included in the drive signals COMA, COMB, and COMC and outputting it to the corresponding output unit 600, will be described. Figure 5 shows an example of the configuration of the selection control circuit 210 and selection circuit 230. In the following description, the more than 3000 piezoelectric elements 60 in the head unit 20 will be described as n piezoelectric elements 60.

[0064] The selection control circuit 210 receives the clock signal SCK, the print data signal SI, and the latch signal LAT. Furthermore, the selection control circuit 210 is equipped with a set of a shift register (S / R) 212, a latch circuit 214, and a decoder 216, corresponding to each of the n piezoelectric elements 60. That is, the selection control circuit 210 has n shift registers 212, It includes n latch circuits 214 and n decoders 216.

[0065] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. The print data signal SI also serially includes 2 bits of print data [SIH,SIL] corresponding to each of the n piezoelectric elements 60 for selecting one of the following: "large dot LD", "small dot SD", "non-recorded ND", and "micro-vibration BSD". The print data [SIH,SIL] included in the print data signal SI is held in n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are connected in cascading order, and the serially input print data signal SI is sequentially transferred to the subsequent shift registers 212 according to the clock signal SCK. When the print data [SIH,SIL] is held in the corresponding shift register 212, the clock signal SCK stops. As a result, the print data [SIH,SIL] included in the print data signal SI is held in the corresponding shift register 212. In Figure 5, the n shift registers 212 are labeled as 1st stage, 2nd stage, ..., nth stage in order from the upstream side where the print data signal SI is input, in order to distinguish them.

[0066] Each of the n latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the corresponding shift register 212 on the rising edge of the latch signal LAT. The print data [SIH,SIL] latched by the latch circuits 214 is then input to the corresponding decoder 216. Figure 6 shows an example of the decoding content in the decoder 216. At period tp, the decoder 216 outputs selection signals S1, S2, and S3 as selection signals S of a logic level defined by the input print data [SIH,SIL]. For example, if print data [SIH,SIL]=[1,0] is input to the decoder 216, the decoder 216 outputs an L-level selection signal S1, an H-level selection signal S2, and an L-level selection signal S3 at period tp.

[0067] The selection signals S1, S2, and S3 output by the decoder 216 are input to the selection circuit 230. The selection circuit 230 is provided corresponding to each of the n output units 600. Figure 7 shows an example of the configuration of the selection circuit 230. As shown in Figure 7, the selection circuit 230 includes inverters 232a, 232b, and 232c, which are NOT gates, and transfer gates 234a, 234b, and 234c.

[0068] The selection signal S1 is input to the positive control terminal of the transfer gate 234a that is not marked with a circle, and after its logic level is inverted by the inverter 232a, it is also input to the negative control terminal of the transfer gate 234a that is marked with a circle. In addition, the drive signal COMA is supplied to the input terminal of the transfer gate 234a. The transfer gate 234a conducts between its input terminal and output terminal when a high-level selection signal S1 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S1 is input. That is, the transfer gate 234a outputs the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is high, and does not output the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is low.

[0069] The selection signal S2 is input to the positive control terminal of the transfer gate 234b that is not marked with a circle, and after its logic level is inverted by the inverter 232b, it is also input to the negative control terminal of the transfer gate 234b that is marked with a circle. In addition, the drive signal COMB is supplied to the input terminal of the transfer gate 234b. When a high-level selection signal S2 is input to the transfer gate 234b, the input terminal and output terminal become conductive, and when a low-level selection signal S2 is input to the transfer gate 234b, the input terminal and output terminal become non-conductive. In other words, the transfer gate 234b receives the selection signal S2 When the logic level of the selection signal S2 is high, the drive waveform Bdp included in the drive signal COMB is output from the output terminal. When the logic level of the selection signal S2 is low, the drive waveform Bdp included in the drive signal COMB is not output from the output terminal.

[0070] The selection signal S3 is input to the positive control terminal of the transfer gate 234c that is not marked with a circle, and after its logic level is inverted by the inverter 232c, it is also input to the negative control terminal of the transfer gate 234c that is marked with a circle. In addition, the drive signal COMC is supplied to the input terminal of the transfer gate 234c. The transfer gate 234c conducts between its input terminal and output terminal when a high-level selection signal S3 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S3 is input. That is, the transfer gate 234c outputs the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is high, and does not output the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is low.

[0071] Then, in the selection circuit 230, the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common. The signal at this connection point where the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common is output as the drive signal VOUT.

[0072] Here, the operation of the selection control circuit 210 and the selection circuit 230 will be explained using Figure 8. Figure 8 is a diagram illustrating the operation of the selection control circuit 210 and the selection circuit 230. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK, and in synchronization with the clock signal SCK, it is sequentially transferred to the n shift registers 212 corresponding to the n piezoelectric elements 60. After that, when the input of the clock signal SCK stops, the shift registers 212 hold the print data [SIH, SIL] corresponding to each of the n piezoelectric elements 60. The print data signal SI is input in the order corresponding to the nth, ..., 2nd, and 1st stages of the piezoelectric elements 60 in the shift registers 212.

[0073] Then, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the shift register 212. Note that LT1, LT2, ..., LTn shown in Figure 8 represent the print data [SIH,SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stage shift register 212.

[0074] The decoder 216 outputs selection signals S1, S2, and S3, whose logic levels are defined by the latched print data [SIH, SIL], at each period tp. The selection circuit 230 then generates the drive signal VOUT by selecting or deselecting the drive signals COMA, COMB, and COMC according to the logic levels of the selection signals S1, S2, and S3 output by the decoder 216.

[0075] Specifically, when the decoder 216 receives print data [SIH,SIL]=[1,1], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to H, L, and L levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Adp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, a large amount of ink is ejected from the corresponding ejection unit 600. This large amount of ink ejected from the ejection unit 600 lands on the medium P, forming a large dot LD on the medium P.

[0076] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[1,0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to L, H, and L levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Bdp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, a small amount of ink is ejected from the corresponding ejection unit 600. This small amount of ink ejected from the ejection unit 600 lands on the medium P, forming small dots SD on the medium P.

[0077] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,1], the decoder 216 sets the logic levels of the selection signals S1, S2, S3 at period tp to L, L, L. As a result, the selection circuit 230 does not select any of the drive waveforms Adp, Bdp, or Cdp at period tp. At this time, the piezoelectric element 60 of the corresponding ejection unit 600 is supplied with a signal of a constant voltage value held by the capacitive component of the piezoelectric element 60. That is, at period tp, the selection circuit 230 supplies a drive signal VOUT of a constant voltage value to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, the piezoelectric element 60 of the corresponding ejection unit 600 is not driven, and no ink is ejected from this ejection unit 600. Therefore, no ink lands on the medium P, and non-recording ND is performed, which does not form dots on the medium P.

[0078] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to L, L, and H levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Cdp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, no ink is ejected from the corresponding ejection unit 600, and a micro-vibration BSD is performed, which vibrates the ink near the opening of the nozzle 651 of the ejection unit 600.

[0079] As described above, the selection control circuit 210 and the selection circuit 230 generate the drive signal VOUT by selecting or deselecting the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c, and output it to the piezoelectric element 60 of the corresponding discharge unit 600.

[0080] 1.4 Configuration and Operation of the Drive Circuit Next, the configuration and operation of the drive circuits 50a, 50b, and 50c of the liquid dispensing device 1 of this embodiment will be described. Here, the drive circuits 50a, 50b, and 50c have the same configuration, differing only in the input signals and output signals. Therefore, in the following description, the drive circuits 50a, 50b, and 50c will not be distinguished and will simply be referred to as drive circuit 50. In this description, the drive circuit 50 will be described as receiving a base drive signal dO as base drive signals dA, dB, and dC, and outputting a drive signal COM as drive signals COMA, COMB, and COMC.

[0081] Figure 9 shows an example of the configuration of the drive circuit 50. As shown in Figure 9, the drive circuit 50 includes a DAC (Digital to Analog Converter) 511, a modulation circuit 510, a gate drive circuit 520, an amplification circuit 550, a demodulation circuit 560, feedback circuits 570, 572, and several other circuit elements.

[0082] The DAC511 receives a base drive signal dO, which is a digital signal that defines the signal waveform of the drive signal COM. The DAC511 converts the input base drive signal dO into an analog signal, the base drive signal aO, and outputs it to the modulation circuit 510. The amplified signal of the base drive signal aO output by the DAC511 corresponds to the drive signal COM. In other words, the base drive signal aO is the target signal before amplification of the drive signal COM, and the base drive signal dO is the amplified signal of the drive signal COM. This is the target signal before the width setting, and is a digital signal that defines the shape of the signal waveform of the drive signal COM. The voltage amplitude of the base drive signal aO output by this DAC511 is set to, for example, 1V to 2V.

[0083] The modulation circuit 510 generates a modulated signal Ms by modulating the base drive signal aO and outputs it to the gate drive circuit 520. The modulation circuit 510 includes adders 512, 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0084] The integrating attenuator 516 attenuates and integrates a signal corresponding to the voltage value of the drive signal COM input via the feedback circuit 570 (described later), and outputs the integrated signal to the negative input terminal of the adder 512. The base drive signal aO is input to the positive input terminal of the adder 512. The adder 512 generates a signal with a voltage value obtained by subtracting the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal and integrating it, and outputs this signal to the positive input terminal of the adder 513. Here, while the maximum voltage amplitude of the base drive signal aO is about 2V as described above, the voltage value of the drive signal COM can exceed 40V at its maximum value. In order to determine the deviation, the integrating attenuator 516 attenuates the drive signal COM input via the feedback circuit 570 (described later) in order to match the range of the voltage amplitude of the base drive signal aO with the range of the voltage value amplitude of the drive signal COM.

[0085] The attenuator 517 supplies a voltage obtained by attenuating the high-frequency component of the drive signal COM, which is input via the feedback circuit 572 described later, to the negative input terminal of the adder 513. The signal output by the adder 512 is input to the positive input terminal of the adder 513. The adder 513 generates a voltage signal As by subtracting the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal, and outputs it to the comparator 514. In other words, the voltage signal As is obtained by subtracting the voltage value of the signal input via the feedback circuit 570 described later from the voltage value of the base drive signal aO, and then further subtracting the voltage value of the signal input via the feedback circuit 572 described later. Therefore, the voltage signal As is a signal in which the deviation obtained by subtracting the attenuation voltage of the drive signal COM from the target voltage value of the base drive signal aO is corrected by the high-frequency component of the drive signal COM.

[0086] The comparator 514 pulse-modulates the voltage signal As and outputs it as a modulated signal Ms. Specifically, the comparator 514 outputs a modulated signal Ms that is high level when the voltage value of the voltage signal As rises and exceeds a predetermined threshold Vth1, and low level when the voltage value of the voltage signal As falls below a predetermined threshold Vth2 during the period when the voltage value of the voltage signal As is falling. Here, the thresholds Vth1 and Vth2 are set such that threshold Vth1 > threshold Vth2. The frequency and duty cycle of this modulated signal Ms change in accordance with the base drive signals dO and aO. That is, by adjusting the modulation gain corresponding to the sensitivity of the attenuator 517, the amount of change in the frequency and duty cycle of the modulated signal Ms can be adjusted.

[0087] The modulated signal Ms is input to the gate driver 521 included in the gate drive circuit 520. Furthermore, the modulated signal Ms is inverted at a logic level by the inverter 515 and then input to the gate driver 522 also included in the gate drive circuit 520. In other words, signals with mutually exclusive logic levels are input to gate driver 521 and gate driver 522.

[0088] Here, the timing of the signals input to gate drivers 521 and 522 may be controlled so that their logic levels do not simultaneously reach a high level. In other words, the "mutually exclusive relationship of logic levels" mentioned above means that the logic level of the signal input to gate driver 521 and the logic level of the signal input to gate driver 522 are not simultaneously at a high level. This does not require that the logic level of the signal input to gate driver 521 and the logic level of the signal input to gate driver 522 be at L level simultaneously.

[0089] The gate drive circuit 520 includes gate driver 521 and gate driver 522.

[0090] The gate driver 521 generates and outputs a gate signal Hgd by level-shifting the modulated signal Ms output by the comparator 514. The high-potential side of the power supply voltage of the gate driver 521 is electrically connected to one end of capacitor C5 and the cathode of diode D1. The other end of capacitor C5 is electrically connected to the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2. A voltage signal Vm, which is a DC voltage of, for example, 7.5V generated by a power supply circuit (not shown), is supplied to the anode of diode D1. As a result, a potential difference approximately equal to the voltage value of the voltage signal Vm is created across the capacitor C5. The low-potential side of the power supply voltage of the gate driver 521 is electrically connected to the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2. Therefore, the gate driver 521 generates and outputs a gate signal Hgd such that, according to the logic level of the input modulation signal Ms, the H level voltage value is greater than the voltage value at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2 by the voltage value of the voltage signal Vm, and the L level voltage value is the voltage value at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2.

[0091] The gate driver 522 operates at a lower potential than the gate driver 521. The gate driver 522 generates and outputs a gate signal Lgd by level-shifting the signal obtained by inverting the logic level of the modulated signal Ms output by the comparator 514 using the inverter 515. Of the power supply voltage of the gate driver 522, the voltage signal Vm is supplied to the high potential side, and the ground potential is supplied to the low potential side. The gate driver 522 then generates and outputs a gate signal Lgd where the H level voltage value is the voltage value of the voltage signal Vm and the L level voltage value is the ground potential, according to the logic level of the input signal.

[0092] As described above, the gate signal Hgd is a signal obtained by level-shifting the voltage value of the modulated signal Ms, and the gate signal Lgd is a signal obtained by level-shifting the voltage value of the inverted signal after inverting the logic level of the modulated signal Ms. In light of this, the gate signals Hgd and Lgd output by the gate drive circuit 520 can also be considered as signals obtained by modulating the base drive signals dO and aO, respectively.

[0093] The amplification circuit 550 includes a transistor pair consisting of transistor M1 and transistor M2.

[0094] A voltage signal VHV, for example, a DC voltage of 42V, is supplied to the drain terminal of transistor M1. The voltage value of the voltage signal VHV is not limited to 42V and only needs to be greater than the maximum voltage value of the drive signal COM output by the drive circuit 50. The gate terminal of transistor M1 is electrically connected to one end of resistor R1. The gate signal Hgd is input to the other end of resistor R1. In other words, the gate signal Hgd is input to the gate terminal of transistor M1 via resistor R1. The source terminal of transistor M1 is electrically connected to the drain terminal of transistor M2. The conduction state between the drain terminal and the source terminal of transistor M1 is controlled by the gate signal Hgd input to the gate terminal.

[0095] The drain terminal of transistor M2 is electrically connected to the source terminal of transistor M1. The gate terminal of transistor M2 is electrically connected to one end of resistor R2. The other end of resistor R2 receives the gate signal Lgd. That is, the gate signal Lgd is input to the gate terminal of transistor M2 via resistor R2. Ground potential is supplied to the source terminal of transistor M2. The conduction state between the drain terminal and the source terminal of transistor M2 is controlled by the gate signal Lgd input to the gate terminal.

[0096] In the following explanation, the state in which the drain and source terminals of transistors M1 and M2 are controlled to conduct is referred to as "on," and the state in which the drain and source terminals of transistors M1 and M2 are controlled to not conduct is referred to as "off."

[0097] In the amplifier circuit 550 configured as described above, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the voltage value at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2 is at ground potential. At this time, the voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the voltage value at the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2 is at voltage signal VHV. At this time, the voltage value of the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. In other words, the gate driver 521 that drives transistor M1 uses capacitor C5 as a floating power supply, and the voltage value at the other end of capacitor C5, which is the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2, changes to ground potential or the voltage value of voltage signal VHV according to the operation of transistors M1 and M2. As a result, the gate driver 521 generates a gate signal Hgd where the L level is the voltage value of voltage signal VHV and the H level is the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm, and supplies it to the gate terminal of transistor M1.

[0098] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd where the L level is ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2.

[0099] As described above, the amplifier circuit 550 operates transistors M1 and M2 in response to gate signals Hgd and Lgd, thereby amplifying the modulated signal Ms, which is obtained by modulating the base drive signals dO and aO, based on the voltage signal VHV. The amplifier circuit 550 then outputs the amplified signal as the amplified modulated signal AMs from the connection point where the source terminal of transistor M1 and the drain terminal of transistor M2 are commonly connected.

[0100] The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing them and generates a drive signal COM. The demodulation circuit 560 then outputs the generated drive signal COM from the drive circuit 50.

[0101] The demodulation circuit 560 includes a coil L1 and a capacitor C1. One end of coil L1 is electrically connected to the source terminal of transistor M1 and the drain terminal of transistor M2. As a result, the amplified modulation signal AMs is input to one end of coil L1. The other end of coil L1 is connected to the output terminal Out of the drive circuit 50. The other end of coil L1 is also connected to one end of capacitor C1. The other end of capacitor C1 is supplied with ground potential. In other words, coil L1 and capacitor C1 constitute a low-pass filter. The amplified modulation signal AMs is smoothed by the low-pass filter in the demodulation circuit 560, generating the drive signal COM. It will be done.

[0102] The feedback circuit 570 includes resistors R3 and R4. One end of resistor R3 is connected to terminal Out, where the drive signal COM is output, and the other end of resistor R3 is connected to the integral attenuator 516 of the modulation circuit 510 and one end of resistor R4. A voltage signal VHV is supplied to the other end of resistor R4. As a result, the drive signal COM, which has passed through the feedback circuit 570 from terminal Out, is fed back to the integral attenuator 516 of the modulation circuit 510 in a pulled-up state.

[0103] The feedback circuit 572 includes capacitors C2, C3, and C4, and resistors R5 and R6. One end of capacitor C2 is connected to the Out terminal, where the drive signal COM is output, and the other end of capacitor C2 is connected to one end of resistor R5 and one end of resistor R6. Ground potential is supplied to the other end of resistor R5. As a result, capacitor C2 and resistor R5 function as a high-pass filter.

[0104] Furthermore, the other end of resistor R6 is connected to one end of capacitor C4 and one end of capacitor C3. Ground potential is supplied to the other end of capacitor C3. As a result, resistor R6 and capacitor C3 function as a low-pass filter.

[0105] As described above, the feedback circuit 572 is configured with a high-pass filter and a low-pass filter. As a result, the feedback circuit 572 functions as a band-pass filter that allows a predetermined frequency range of the drive signal COM to pass through. The other end of the capacitor C4 included in the feedback circuit 572 is connected to the attenuator 517 of the modulation circuit 510. As a result, the attenuator 517 of the modulation circuit 510 receives back a signal from which the DC component of the high-frequency components of the drive signal COM, which has passed through the feedback circuit 572 (which functions as a band-pass filter that allows predetermined frequency components to pass through), has been filtered out.

[0106] Incidentally, the drive signal COM output from terminal Out is a signal demodulated by the demodulation circuit 560 smoothing the amplified modulated signal AMs based on the base drive signal dO. The drive signal COM output by the demodulation circuit 560 is then integrated and attenuated via the feedback circuit 570 and fed back to the adder 512. As a result, the drive circuit 50 self-oscillates at a frequency determined by the feedback delay and the feedback transfer function. However, the feedback path via the integrating attenuator 516 of the modulation circuit 510 alone results in a large delay, and the self-oscillation frequency may not be high enough to ensure sufficient accuracy of the drive signal COM with only the feedback via the integrating attenuator 516 of the modulation circuit 510.

[0107] In this embodiment, the drive circuit 50 has a separate path for feeding back the high-frequency components of the drive signal COM via the feedback circuit 572 and the attenuator 517 of the modulation circuit 510, in addition to the path via the integral attenuator 516 of the modulation circuit 510. As a result, in the drive circuit 50 of this embodiment, the delay when considering the entire circuit constituting the drive circuit 50 is reduced, and the frequency of the voltage signal As can be increased to a level that sufficiently ensures the accuracy of the drive signal COM.

[0108] As described above, the drive circuit 50 of this embodiment includes a modulation circuit 510 that outputs a modulated signal Ms obtained by modulating the base drive signals dO and aO which are the basis of the drive signal COM; a gate drive circuit 520 including a gate driver 521 that outputs a gate signal Hgd corresponding to the modulated signal Ms and a gate driver 522 that outputs a gate signal Lgd corresponding to the modulated signal Ms; an amplification circuit 550 including a transistor M1 that is driven according to the gate signal Hgd and a transistor M2 that is driven according to the gate signal Lgd, which outputs an amplified modulated signal AMs by driving transistors M1 and M2; a demodulation circuit 560 that outputs a drive signal COM obtained by demodulating the amplified modulated signal AMs; and a circuit that feeds the drive signal COM back to the modulation circuit 510. It has feedback circuits 570 and 572.

[0109] Here, when the oscillation frequency of the self-oscillation of the drive circuit 50, which is the drive frequency of transistors M1 and M2, increases, the switching loss generated in transistors M1 and M2 increases, and as a result, the amount of heat generated by transistors M1 and M2 may increase. When the amount of heat generated by transistors M1 and M2 increases, the operational stability of the drive circuit 50, including transistors M1 and M2, decreases, and the waveform accuracy of the drive signal COM output by the drive circuit 50 decreases. In particular, the switching loss generated in transistors M1 and M2 is greatly contributed to by the turn-on time and turn-off time of transistors M1 and M2 and the drain current flowing through transistors M1 and M2. Therefore, as in the liquid discharge device 1 of this embodiment, when the drive circuit 50 supplies a high-frequency drive signal COM of 100 kHz or higher to a large number of piezoelectric elements 60, such as 3,000 or more piezoelectric elements 60, the amount of current flowing through transistors M1 and M2 increases, and the drive frequency of transistors M1 and M2 may exceed 8 MHz, so the switching loss of transistors M1 and M2 increases significantly. As a result, the risk of increased heat generation from transistors M1 and M2 increases, further increasing the risk of decreased operational stability of the drive circuit 50.

[0110] To address this problem, it is possible to reduce the risk of increased switching losses in transistors M1 and M2 and the risk of increased heat generation in transistors M1 and M2 by setting the driving frequency of transistors M1 and M2 to the same driving frequency as when the frequency of the driving signal COM is 100 kHz or less. However, in the case of a liquid ejection device 1 that controls the position of the meniscus of the ejection unit 600 and controls the amount of ink ejected from the ejection unit 600 by driving a piezoelectric element 60 as shown in this embodiment, it is necessary to finely control the driving of the piezoelectric element 60 in period tp from the viewpoint of precisely controlling the amount of ink ejected, and the voltage value of the driving signal COM needs to be changed significantly in a short time, as shown in Figure 4. When the frequency of the driving signal COM is a high frequency of 100 kHz or more, the change in the voltage value of the driving signal COM per 1 μs may be abrupt, exceeding 20 V, and the period during which the voltage value of the driving signal COM is kept constant may be less than 0.25 μs. Therefore, in the drive circuit 50 that outputs the drive signal COM, if the drive frequencies of transistors M1 and M2 are set to the same values ​​as when the frequency of the drive signal COM is 100 kHz or less, it may not be possible to secure a sufficient number of samples to maintain the waveform accuracy of the drive signal COM. This could lead to a decrease in the waveform accuracy of the output drive signal COM and a decrease in the ink ejection accuracy.

[0111] In other words, from the standpoint of improving productivity in the liquid dispensing device 1, when the drive circuit 50 supplies a drive signal COM of a high frequency of 100 kHz or higher to a large number of piezoelectric elements 60, specifically 3,000 or more piezoelectric elements 60, in order to maintain high waveform accuracy of the drive signal COM, it is necessary to further increase the drive frequency of transistors M1 and M2. Therefore, even when the drive frequency of transistors M1 and M2 is increased, the drive circuit 50 is required to reduce the amount of heat generated in the drive circuit 50 while reducing the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0112] In response to this, it might be possible to select a transistor with low switching loss from among the silicon-based transistors that have been conventionally used as transistors M1 and M2. However, since the switching loss in a transistor is in a trade-off relationship with the conduction loss, if a transistor with low switching loss is selected, the conduction loss will increase, and the amount of heat generated in the drive circuit 50 cannot be reduced. In other words, in order for the drive circuit 50 of the liquid discharge device 1 to supply a drive signal COM of a high frequency of 100 kHz or more to a large number of piezoelectric elements 60, which number 3,000 or more piezoelectric elements 60, a transistor with reduced conduction loss and switching loss is required. Therefore, a transistor with a Barriga figure of merit that surpasses that of silicon-based transistors is required. A changer is needed.

[0113] Therefore, in the drive circuit 50 of this embodiment, the transistors M1 and M2 have a distinctive structure, which reduces losses in transistors M1 and M2 even when they are driven at high frequencies. As a result, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC of 100 kHz or higher to a large number of piezoelectric elements 60, such as 3,000 or more piezoelectric elements 60, it is possible to reduce the amount of heat generated in the drive circuit 50 while reducing the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0114] An example of the structure of transistors M1 and M2 will be described below. Here, transistors M1 and M2 have similar structures. Therefore, in the following explanation, only the structure of transistor M1 will be described, and the illustration and explanation of the structure of transistor M2 will be simplified or omitted.

[0115] Figure 10 shows an example of the structure of transistor M1. The structure of transistor M1 will be explained using mutually orthogonal X and Y axes. Furthermore, in the following explanation, the starting point of the X-axis arrow will be referred to as the -X side and the tip as the +X side, and the starting point of the Y-axis arrow will be referred to as the -Y side and the tip as the +Y side.

[0116] As shown in Figure 10, transistor M1 has layers 701-705, a source electrode 760, a gate electrode 770, and a drain electrode 780.

[0117] Layer 701 is located on the -Y side of transistor M1 and includes a semiconductor substrate 710. Examples of such semiconductor substrates 710 include silicon (Si) substrates, silicon carbide (SiC) substrates, gallium nitride (GaN) substrates, and sapphire substrates.

[0118] Layer 702 is located above layer 701 on the +Y side and includes a buffer layer 720. The buffer layer 720 is composed of one or more nitride semiconductors. This buffer layer 720 reduces the risk of warping of the semiconductor substrate 710 and cracks occurring in the transistor M1 due to mismatch in thermal expansion coefficients between the semiconductor substrate 710 and the electron transport layer 730 described later. Such a buffer layer 720 can be composed of, for example, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and grated AlGaN with different aluminum (Al) compositions.

[0119] Layer 703 is located above layer 702 and on the +Y side, and includes an electron transport layer 730. Such an electron transport layer 730 is a nitride semiconductor, and is composed of, for example, GaN. Here, in order to reduce leakage current, the electron transport layer 730 may have a semi-insulating region other than the surface region located on the +Y side by introducing impurities in part.

[0120] Layer 704 is located above layer 703 and on the +Y side, and includes an electron supply layer 740. Such an electron supply layer 740 is a nitride semiconductor having a larger band gap than the electron transport layer 730, and is composed of, for example, AlGaN.

[0121] Here, the electron transport layer 730 and the electron supply layer 740 are composed of nitride semiconductors having different lattice constants. Therefore, a lattice-mismatched heterojunction is formed between the GaN nitride semiconductor constituting the electron transport layer 730 and the AlGaN nitride semiconductor constituting the electron supply layer 740. At this time, the spontaneous polarization of the electron transport layer 730 and the electron supply layer 740, and the piezoelectric polarization caused by crystal strain near the interface of the heterojunction, As a result, the energy level of the conductor in the electron transport layer 730 near the heterojunction interface becomes lower than the Fermi level. This causes the secondary electron gas 790 to spread in the electron transport layer 730 in the region close to the heterojunction interface between the electron transport layer 730 and the electron supply layer 740.

[0122] Layer 705 is located above layer 704 on the +Y side and includes a gate layer 750. Such a gate layer 750 is a nitride semiconductor containing acceptor-type impurities, and is composed of, for example, gallium nitride (p-type GaN) doped with acceptor-type impurities. In this case, examples of acceptor-type impurities that can be used for doping include zinc (Zn), magnesium (Mg), carbon (C), etc.

[0123] The gate electrode 770 is located above the gate layer 750 included in layer 705, on the +Y side, and is electrically connected to the gate terminal of transistor M1. Such a gate electrode 770 is composed of one or more metal layers, for example, titanium nitride (TiN), and forms a Schottky junction with the gate layer 750. The gate electrode 770 may also be composed of, for example, a first metal layer made of titanium (Ti) and a second metal layer made of TiN provided above the first metal layer.

[0124] The source electrode 760 is located above layer 704 on the +Y side, on the -X side of the gate layer 750 and gate electrode 770, and is electrically connected to the source terminal of transistor M1. The drain electrode 780 is also located above layer 704 on the +Y side, on the +X side of the gate layer 750 and gate electrode 770, and is electrically connected to the drain terminal of transistor M1. The source electrode 760 and drain electrode 780 are composed of one or more metal layers, which can be any combination of materials such as Ti, TiN, and Al. The source electrode 760 and drain electrode 780 may also be composed of alloys such as aluminum-silicon-copper alloy (Al-Si-Cu) or aluminum-copper alloy (AlCu).

[0125] In other words, each of transistors M1 and M2 includes a layer 703 which contains an electron transport layer 730 made of a nitride semiconductor, for example, GaN; a layer 704 which contains a nitride semiconductor having a larger band gap than the electron transport layer 730, for example, AlGaN; a source electrode 760 which is electrically connected to the source terminal of transistor M1; a drain electrode 780 which is electrically connected to the drain terminal of transistor M1; and a gate electrode 770 which is electrically connected to the gate terminal of transistor M1. The layer 704 is positioned above the layer 703, and the source electrode 760, gate electrode 770, and gate electrode 770 are positioned above the layer 704, with at least a portion of the gate electrode 770 located between the source electrode 760 and the drain electrode 780 when viewed along the Y axis.

[0126] Next, the operation of transistors M1 and M2 configured as described above will be explained. When a 0V signal is supplied to the gate electrode 770, and the potential of the gate electrode 770 is the same as that of the source electrode 760, the gate layer 750 raises the potential of the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740. As a result, the conduction band located in the -Y type of the gate electrode 770 within the conduction band of the heterojunction interface between the electron transport layer 730 and the electron supply layer 740 becomes higher in energy than the Fermi level. Therefore, the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740 becomes depleted. That is, when a 0V signal is supplied to the gate electrode 770, and the gate electrode 770 and the source electrode 760 are at the same potential, there is no conduction between the source electrode 760 and the drain electrode 780 of transistors M1 and M2, and between the drain terminal and the source terminal of transistors M1 and M2.

[0127] On the other hand, a signal with a positive voltage value is supplied to the gate electrode 770, and the voltage value of this signal is a predetermined threshold When the voltage exceeds a certain value, the potential at the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740 decreases. At this time, electrons are generated at the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740, and transistors M1 and M2 operate in the same way as ordinary FETs (Field Effect Transistors).

[0128] Then, as the voltage value of the signal supplied to the gate electrode 770 increases and exceeds the forward on-voltage of the pn junction, hole injection from the gate electrode 770 into the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740 begins. At this time, due to the potential barrier of the heterojunction, most electrons do not flow into the gate electrode 770. Therefore, to satisfy the charge neutrality condition, the same amount of electrons as the holes injected from the gate electrode 770 are attracted from the source electrode 760 to the heterojunction interface between the channel electron transport layer 730 and the electron supply layer 740. These electrons attracted from the source electrode 760 move rapidly toward the drain electrode 780 due to the voltage supplied to the drain electrode 780. On the other hand, because the mobility of holes is small compared to the mobility of electrons, most of the holes remain in the vicinity of the gate electrode 770. Therefore, to satisfy the charge neutrality condition, an additional amount of electrons equal to the number of holes is generated. Therefore, the ratio of the number of injected holes to the number of generated electrons is approximately equal to the ratio of electron mobility to hole mobility, and the drain current increases even though almost no gate current flows.

[0129] As described above, transistors M1 and M2 contain GaN and have the structure shown in Figure 10, and are devices that utilize conductivity modulation by hole injection from the gate electrode 770. They exhibit normally-off characteristics and are GaN transistors with a low on-resistance HEMT (High Electron Mobility Transistor) structure that can drive large currents. Here, transistors M1 and M2 are GaN transistors with a HEMT structure, and are not limited to the configuration shown in Figure 10 as long as normally-off characteristics can be obtained. For example, a configuration may have a cascode-connected MOS-FET instead of the gate layer 750 included in layer 705.

[0130] Here, a GaN transistor is a compound semiconductor that uses GaN as the semiconductor material. GaN, used as a semiconductor material, exhibits larger differences in band gap, dielectric breakdown field strength, electron mobility, and saturation electron velocity compared to Si, the mainstream semiconductor material. Therefore, the Barriga figure of merit, determined by a comprehensive evaluation of multiple physical properties such as dielectric breakdown field strength and electron mobility of GaN used as a semiconductor material, reaches "900" when Si is set to "1" as the semiconductor material. GaN transistors, using GaN as the semiconductor material, can achieve high-speed switching with lower on-resistance compared to Si transistors, which use Si as the semiconductor material. Furthermore, by adopting a HEMT structure for GaN transistors, high-speed electron movement becomes possible, and the risk of high-speed switching being hindered by parasitic capacitance is reduced, enabling even faster switching.

[0131] By using such HEMT structured GaN transistors as transistors M1 and M2 in the amplification circuit 550 included in the drive circuit 50 of the liquid dispensing device 1 of this embodiment, losses in transistors M1 and M2 can be reduced even when transistors M1 and M2 are driven at high frequencies. That is, even when the drive circuit 50 outputs a drive signal of 100 kHz or higher, and transistors M1 and M2 are driven at a high frequency of, for example, 8 MHz or higher, the amount of heat generated in transistors M1 and M2 is reduced, and the risk of a decrease in the operational stability of the drive circuit 50 is reduced. Therefore, from the viewpoint of improving productivity in the liquid dispensing device 1, even when the drive circuit 50 supplies a high-frequency drive signal COM of 100 kHz or higher to a large number of piezoelectric elements 60, such as 3,000 or more piezoelectric elements 60, the waveform accuracy of the output drive signal COM is reduced. This is reduced.

[0132] Furthermore, by using HEMT structured GaN transistors as transistors M1 and M2, even when transistors M1 and M2 are driven at high frequencies, the losses incurred in transistors M1 and M2 are reduced, which in turn reduces the power consumption of the drive circuit 50. Moreover, because transistors M1 and M2 can be driven at high frequencies, it becomes possible to increase the frequency of the feedback signal that is fed back to the modulation circuit 510 via the feedback circuit 572. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is further improved.

[0133] Furthermore, because transistors M1 and M2 can be driven at high frequencies, the frequency of the amplified modulation signal AMs output by transistors M1 and M2 also increases. This makes it possible to miniaturize the coil L1 in the demodulation circuit 560, thereby enabling miniaturization of the drive circuit 50. Additionally, by reducing the product of the coil L1 and capacitor C1 in the demodulation circuit 560, the output bandwidth of the drive circuit 50 can be widened, allowing for the output of a drive signal COM with high waveform accuracy even when the voltage value of the drive signal COM changes rapidly.

[0134] In other words, in the drive circuit 50 of this embodiment, the transistors M1 and M2 have the characteristic structure shown in Figure 10, which reduces losses in transistors M1 and M2 even when they are driven at high frequencies. As a result, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, and COMC of 100 kHz or higher to a large number of piezoelectric elements 60, such as 3,000 or more piezoelectric elements 60, it is possible to reduce the amount of heat generated in the drive circuit 50 while reducing the risk of a decrease in the waveform accuracy of the output drive signal COM. Therefore, in the drive circuit 50 of this embodiment, if the drive frequency of transistor M1 is set such that the shortest period in the drive cycle of transistor M1 is shorter than the shortest period in which the voltage value of the drive signal COM changes, and the voltage value of the drive signal COM is shorter than the shortest period in which it is constant, and the drive frequency of transistor M2 is set such that the shortest period in the drive cycle of transistor M2 is shorter than the shortest period in which the voltage value of the drive signal COM changes, and the voltage value of the drive signal COM is shorter than the shortest period in which it is constant, even if the drive frequencies of transistors M1 and M2 during the period in which transistors M1 and M2 output amplified modulation signals AMs exceed 8 MHz, the losses incurred in transistors M1 and M2 can be reduced. As a result, the amount of heat generated in the drive circuit 50 can be reduced, and the risk of a decrease in the waveform accuracy of the output drive signal COM can also be reduced.

[0135] Here, when considering only the Barriga figure of merit for the semiconductor materials constituting transistors M1 and M2, SiC and gallium oxide (Ga2O3) also have a large Barriga figure of merit compared to Si as semiconductor materials. However, SiC and Ga2O3 are semiconductor materials intended for use at high voltages of several hundred volts to several kilovolts, and their switching performance at high frequencies is inferior to that of GaN. Therefore, they are not suitable semiconductor materials for application to transistors M1 and M2 in the drive circuit 50 of the liquid discharge device 1, which is intended for use at high frequencies of several MHz at voltage values ​​below 100V. Furthermore, when GaN is used as the semiconductor material and a vertical structure is adopted instead of a HEMT structure, parasitic capacitance occurring between the gate and source, etc., hinders use at high frequencies of several MHz. Therefore, for the drive circuit 50 of the liquid dispensing device 1, which is expected to be used at high frequencies of several MHz at voltage values ​​of 100V or less, it can be said that the optimal choice for transistors M1 and M2 is to use HEMT-structured GaN transistors, taking into account not only the Barriga merit index of the semiconductor material but also other physical properties and structures.

[0136] Here, the drive signal COM is an example of a drive signal, and the piezoelectric element 60 is an example of a capacitive load. Yes, the drive circuit 50 is an example of a capacitive load drive circuit, the gate signal Hgd is an example of a first gate drive signal, transistor M1 is an example of a first transistor, the gate signal Lgd is an example of a second gate drive signal, transistor M2 is an example of a second transistor, layer 703 is an example of a first layer, gallium nitride (GaN), which is the nitride semiconductor of the electron transport layer 730, is an example of a first nitride semiconductor, layer 704 is an example of a second layer, aluminum gallium nitride (AlGaN), which is the nitride semiconductor of the electron supply layer 740, is an example of a second nitride semiconductor, source electrode 760 is an example of a first conductor, drain electrode 780 is an example of a second conductor, gate electrode 770 is an example of a third conductor, period tp is an example of an ejection period, and the reciprocal of the drive frequencies of transistors M1 and M2 is an example of a drive period.

[0137] 1.5 Effects In the liquid dispensing device 1 configured as described above, the drive circuit 50 includes a modulation circuit 510 that outputs a modulation signal Ms obtained by modulating the base drive signals dO and aO which form the basis of the drive signal COM, a gate drive circuit 520 including a gate driver 521 that outputs a gate signal Hgd corresponding to the modulation signal Ms, and a gate driver 522 that outputs a gate signal Lgd corresponding to the modulation signal Ms, an amplification circuit 550 that includes a transistor M1 that is driven according to the gate signal Hgd and a transistor M2 that is driven according to the gate signal Lgd, and outputs an amplified modulation signal AMs by driving transistors M1 and M2, and a demodulation circuit 560 that outputs a drive signal COM obtained by demodulating the amplified modulation signal AMs, and at least one, preferably both, of the transistors M1 and M2 in the amplification circuit 550 is made of a nitride semiconductor, for example G The transistor M1 and M2 include a layer 703 containing an electron transport layer 730 made of aN, a layer 704 made of a nitride semiconductor having a larger band gap than the electron transport layer 730, for example, AlGaN, a source electrode 760 electrically connected to the source terminal of transistor M1, a drain electrode 780 electrically connected to the drain terminal of transistor M1, and a gate electrode 770 electrically connected to the gate terminal of transistor M1, with layer 704 positioned above layer 703, and the source electrode 760, gate electrode 770, and gate electrode 770 positioned above layer 704, and the gate electrode 770 is configured such that at least a portion of it is located between the source electrode 760 and the drain electrode 780 when viewed along the Y axis, thereby reducing losses in transistors M1 and M2 even when they are driven at high frequencies. As a result, even when the frequency of the drive signal COM output by the drive circuit 50 using a Class D amplifier circuit is high, for example, when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, COMC of 100 kHz or higher to a large number of piezoelectric elements 60, namely 3,000 or more piezoelectric elements 60, in response to market demands for increased productivity in liquid dispensing devices 1, it is possible to reduce the amount of heat generated in the drive circuit 50 while reducing the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0138] In other words, by making at least one, preferably both, of the transistors M1 and M2 in the amplification circuit 550 HEMT structured GaN transistors, losses in transistors M1 and M2 can be reduced even when transistors M1 and M2 are driven at high frequencies. Therefore, in response to the market demand for increased productivity in the liquid dispensing device 1, even when the drive circuit 50 supplies high-frequency drive signals COMA, COMB, COMC of 100 kHz or higher to a large number of piezoelectric elements 60, specifically 3,000 or more piezoelectric elements 60, it is possible to reduce the amount of heat generated in the drive circuit 50 while reducing the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0139] Furthermore, the drive circuit 50 of the liquid discharge device 1 has feedback circuits 570 and 572 that feed back the drive signal COM to the modulation circuit 510, and because transistors M1 and M2 are driven at a high frequency, the response speed of the drive circuit 50 when viewed as an entire system The degree can be increased. This makes it possible to improve the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0140] Furthermore, in the liquid dispensing device 1 of this embodiment, even when transistors M1 and M2 are driven at a high frequency, the losses incurred in transistors M1 and M2 can be reduced, thus reducing the heat generated in the drive circuit 50 including transistors M1 and M2. Therefore, even when the drive circuit 50 is mounted on the carriage 21 together with the dispensing unit 600, the risk of changes in the physical properties of the dispensed ink due to the heat generated in the drive circuit 50 including transistors M1 and M2 is reduced. Also, by mounting the drive circuit 50 on the carriage 21 together with the dispensing unit 600, it is possible to shorten the propagation path of the drive signal COM output by the drive circuit 50 until it is supplied to the dispensing unit 600, improving the waveform accuracy of the drive signal COM supplied to the dispensing unit 600 and improving the ink dispensing accuracy from the dispensing unit 600.

[0141] 2. Second Embodiment Next, the liquid dispensing device 1 of the second embodiment will be described. In describing the liquid dispensing device 1 of the second embodiment, components similar to those of the liquid dispensing device 1 of the first embodiment will be denoted by the same reference numerals, and their detailed descriptions will be simplified or omitted.

[0142] Figure 11 shows an example of the configuration of the drive circuit 50 of the second embodiment. The liquid dispensing device 1 of the second embodiment differs from the liquid dispensing device 1 of the first embodiment in that, in the drive circuit 50, the gate drive circuit 520 that outputs gate signals Hgd and Lgd, and the transistors M1 and M2 are mounted on a single integrated circuit device 500.

[0143] As shown in Figure 11, the integrated circuit device 500 includes terminals Tvm, Tsi, Td, Ts, Tout, Tbt, a gate drive circuit 520, an amplification circuit 550, a diode D1, and an inverter 515.

[0144] The modulation signal Ms output by the modulation circuit 510 is input to terminal Tsi. The voltage signal Vm is supplied to terminal Tvm. The voltage signal VHV is supplied to terminal Td. The ground potential is supplied to terminal Ts. One end of capacitor C5 is electrically connected to terminal Tbt. The other end of capacitor C5 is electrically connected to terminal Tout. Terminal Tout is electrically connected to one end of coil L1 of the demodulation circuit 560.

[0145] The modulated signal Ms is input to the gate driver 521 included in the gate drive circuit 520 via terminal Tsi. The modulated signal Ms is also input to the inverter 515 via terminal Tsi, where its logic level is inverted, and then input to the gate driver 522 also included in the gate drive circuit 520. In other words, signals with mutually exclusive logic levels are input to gate driver 521 and gate driver 522.

[0146] The gate driver 521 generates and outputs the gate signal Hgd by level-shifting the modulated signal Ms. The high-potential side of the gate driver 521's power supply voltage is electrically connected to the cathode of diode D1 and also to one end of capacitor C5 via terminal Tbt. The other end of capacitor C5 is electrically connected to terminal Tout, which is electrically connected to the connection point between the source terminal of transistor M1 and the drain terminal of transistor M2. The anode of diode D1 is supplied with a voltage signal Vm via terminal Tvm. As a result, a potential difference approximately equal to the voltage value of the voltage signal Vm is generated across capacitor C5. The low-potential side of the gate driver 521's power supply voltage is connected to the source terminal of transistor M1 and the drain terminal of transistor M2. This is the connection point, and is electrically connected to terminal Tout. Therefore, the gate driver 521 generates and outputs a gate signal Hgd in which the H level voltage value is greater than the voltage value of terminal Tout by the voltage value of voltage signal Vm, and the L level voltage value is the voltage value of terminal Tout, according to the logic level of the input modulation signal Ms.

[0147] The gate driver 522 operates at a lower potential than the gate driver 521. The gate driver 522 generates and outputs a gate signal Lgd by level-shifting the signal, which is the inverted logic level of the modulated signal Ms input via terminal Tsi by the inverter 515. Of the power supply voltage of the gate driver 522, the voltage signal Vm is supplied via terminal Tvm to the high potential side, and the ground potential is supplied via terminal Ts to the low potential side. The gate driver 522 then generates and outputs a gate signal Lgd where the H level voltage value is the voltage value of the voltage signal Vm and the L level voltage value is the ground potential, according to the logic level of the input signal.

[0148] The amplification circuit 550 includes a transistor pair consisting of transistor M1 and transistor M2.

[0149] A voltage signal VHV is supplied to the drain terminal of transistor M1 via terminal Td. A gate signal Hgd is input to the gate terminal of transistor M1. The source terminal of transistor M1 is electrically connected to terminal Tout and the drain terminal of transistor M2. The conduction state between the drain terminal and source terminal of transistor M1 is controlled by the gate signal Hgd input to the gate terminal.

[0150] The drain terminal of transistor M2 is electrically connected to terminal Tout and the source terminal of transistor M1. The gate terminal of transistor M2 is input to the gate terminal Lgd. The source terminal of transistor M2 is supplied with ground potential via terminal Ts. The conduction state between the drain terminal and the source terminal of transistor M2 is controlled by the gate signal Lgd input to the gate terminal.

[0151] In the amplifier circuit 550 configured as described above, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the voltage value at terminal Tout is at ground potential. At this time, the voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the voltage value at terminal Tout is at voltage signal VHV. At this time, the voltage value of the voltage signal VHV and the voltage value of voltage signal Vm are supplied to the high potential side of the power supply voltage of the gate driver 521. In other words, the gate driver 521 that drives transistor M1 uses capacitor C5 as a floating power supply, and the voltage value at the other end of capacitor C5, terminal Tout, changes to ground potential or the voltage value of voltage signal VHV in accordance with the operation of transistors M1 and M2. This generates a gate signal Hgd where the L level is the voltage value of voltage signal VHV and the H level is the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm, and supplies this gate signal Hgd to the gate terminal of transistor M1.

[0152] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd where the L level is ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2.

[0153] As described above, the amplifier circuit 550 operates by having transistors M1 and M2 operate in accordance with the gate signals Hgd and Lgd, thereby modulating the base drive signals dO and aO into a modulated signal Ms, which is then converted into a voltage. The signal is amplified based on the VHV signal. The amplification circuit 550 then outputs the amplified signal as an amplified modulated signal AMs from terminal Tout.

[0154] The demodulation circuit 560 then demodulates the amplified modulation signal AMs by smoothing them, generating a drive signal COM. The demodulation circuit 560 then outputs the generated drive signal COM from the drive circuit 50.

[0155] Even with the drive circuit 50 of the second embodiment configured as described above, the transistors M1 and M2 have the structure shown in Figure 10, which provides the same effects as the liquid dispensing device 1 of the first embodiment.

[0156] In this case, the liquid dispensing device 1 of the second embodiment has an integrated circuit device 500 in which a gate drive circuit 520 that outputs gate signals Hgd and Lgd and transistors M1 and M2 are housed in a single package. This shortens the propagation path of each of the gate signals Hgd and Lgd, improving the waveform accuracy of the gate signal Hgd input to transistor M1 and the waveform accuracy of the gate signal Lgd input to transistor M2.

[0157] As explained with reference to Figure 10, transistors M1 and M2 are HEMT-structured GaN transistors having a configuration in which layer 703 includes an electron transport layer 730 made of a nitride semiconductor, for example, GaN, layer 704 is made of a nitride semiconductor with a larger band gap than the electron transport layer 730, for example, AlGaN, a source electrode 760 electrically connected to the source terminal of transistor M1, a drain electrode 780 electrically connected to the drain terminal of transistor M1, and a gate electrode 770 electrically connected to the gate terminal of transistor M1, with layer 704 positioned above layer 703, and the source electrode 760, gate electrode 770, and gate electrode 770 positioned above layer 704, and at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780 when viewed along the Y axis, and with this configuration, high-speed switching and high-frequency driving can be achieved.

[0158] However, if the wiring through which the gate signals Hgd and Lgd propagate is long, the impedance component of the wiring may cause distortion in the waveforms of the gate signals Hgd and Lgd. Therefore, if the wiring through which the gate signals Hgd and Lgd propagate is long, the drive frequency of transistors M1 and M2 may be limited by the waveform distortion of the gate signals Hgd and Lgd. In particular, this problem is more pronounced in GaN transistors with a HEMT structure, such as transistors M1 and M2 in the drive circuit 50 shown in this embodiment, because they are capable of high-speed switching.

[0159] In contrast, in the liquid dispensing device 1 of the second embodiment, the wiring through which the gate signals Hgd and Lgd propagate can be shortened, thereby reducing the risk of distortion in the signal waveforms of the gate signal Hgd input to transistor M1 and the gate signal Lgd input to transistor M2. Therefore, it becomes possible to further increase the driving frequency of transistors M1 and M2, and to further improve the waveform accuracy of the driving signal COM output by the driving circuit 50.

[0160] Here, the gate drive circuit 520 is an example of a gate drive circuit, and the integrated circuit device 500 is an example of a semiconductor device.

[0161] 3. Third Embodiment Next, the liquid dispensing device 1 of the third embodiment will be described. Liquid dispensing device 1 of the third embodiment In explaining this, components similar to those in the liquid dispensing device 1 of the first and second embodiments are denoted by the same reference numerals, and their detailed descriptions are simplified or omitted.

[0162] Figure 12 shows an example of the configuration of the drive circuit 50 of the third embodiment. The liquid dispensing device 1 of the third embodiment differs from the liquid dispensing device 1 of the first and second embodiments in that, in the drive circuit 50, the gate driver 521 that outputs the gate signal Hgd and the transistor M1 are mounted on one integrated circuit device 500a, and the gate driver 522 that outputs the gate signal Lgd and the transistor M2 are mounted on one integrated circuit device 500b.

[0163] As shown in Figure 12, the integrated circuit device 500a includes terminals Tvma, Tsia, Tda, Tsa, gate driver 521, and transistor M1, and the integrated circuit device 500b includes terminals Tvmb, Tsib, Tdb, Tsb, gate driver 522, and transistor M2.

[0164] The modulation signal Ms output by the modulation circuit 510 is input to terminal Tsia. Terminal Tvma is electrically connected to the cathode of diode D1 and one end of capacitor C5. The voltage signal VHV is supplied to terminal Tda. Terminal Tsa is electrically connected to terminal Tdb of integrated circuit device 500b. The modulation signal Ms output by the modulation circuit 510 is input to terminal Tsib via inverter 515. The voltage signal Vm is input to terminal Tvmb. Terminal Tdb is electrically connected to terminal Tsa of integrated circuit device 500a. The ground potential is supplied to terminal Tsb.

[0165] The modulated signal Ms is input to gate driver 521 via terminal Tsia. Furthermore, the modulated signal Ms is inverted at a logic level by inverter 515 and then input to gate driver 522 via terminal Tsib. In other words, gate drivers 521 and 522 receive signals with mutually exclusive logic levels.

[0166] The gate driver 521 generates and outputs a gate signal Hgd by level-shifting the modulated signal Ms. The high-potential side of the gate driver 521's power supply voltage is electrically connected to the cathode of diode D1 and one end of capacitor C5 via terminal Tvma. The other end of capacitor C5 is electrically connected to terminal Tsa, which is electrically connected to the source terminal of transistor M1. A voltage signal Vm is supplied to the anode of diode D1. As a result, a potential difference approximately equal to the voltage value of the voltage signal Vm is created across capacitor C5. The low-potential side of the gate driver 521's power supply voltage is the source terminal of transistor M1, which is electrically connected to terminal Tsa. Therefore, the gate driver 521 generates and outputs a gate signal Hgd in which the H-level voltage value is greater than the voltage value of terminal Tsa by the voltage value of the voltage signal Vm, and the L-level voltage value is the voltage value of terminal Tsa, according to the logic level of the input modulated signal Ms.

[0167] The gate driver 522 generates and outputs a gate signal Lgd by level-shifting the signal obtained by the inverter 515 when the logic level of the modulated signal Ms input via terminal Tsib is inverted. Of the power supply voltage of the gate driver 522, the voltage signal Vm is supplied via terminal Tvmb to the high potential side, and the ground potential is supplied via terminal Tsb to the low potential side. The gate driver 522 then generates and outputs a gate signal Lgd where the H level voltage value is the voltage value of the voltage signal Vm and the L level voltage value is the ground potential, according to the logic level of the input signal.

[0168] A voltage signal VHV is supplied to the drain terminal of transistor M1 via terminal Tda. The gate terminal of transistor M1 receives a gate signal Hgd. The source terminal of transistor M1 is electrically connected to terminal Tsa. The conduction state between the drain terminal and the source terminal of transistor M1 is controlled by the gate signal Hgd input to the gate terminal.

[0169] The drain terminal of transistor M2 is electrically connected to terminal Tdb. Terminal Tdb is electrically connected to terminal Tsa. That is, the source terminal of transistor M1 and the drain terminal of transistor M2 are electrically connected via terminals Tsa and Tdb. The gate terminal of transistor M2 receives the gate signal Lgd. The source terminal of transistor M2 is supplied with ground potential via terminal Tsb. The conduction state between the drain terminal and source terminal of transistor M2 is controlled by the gate signal Lgd input to the gate terminal.

[0170] When transistor M1 is controlled to be OFF and transistor M2 is controlled to be ON, the voltage value at the connection point between terminals Tsa and Tdb is at ground potential. At this time, the voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. On the other hand, when transistor M1 is controlled to be ON and transistor M2 is controlled to be OFF, the voltage value at the connection point between terminals Tsa and Tdb is at voltage signal VHV. At this time, the voltage value of the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm is supplied to the high potential side of the power supply voltage of the gate driver 521. In other words, the gate driver 521 that drives transistor M1 uses capacitor C5 as a floating power supply, and the voltage value at the other end of capacitor C5, at the connection point between terminal Tsa and terminal Tdb, changes to ground potential or the voltage value of voltage signal VHV according to the operation of transistors M1 and M2. This generates a gate signal Hgd where the L level is the voltage value of voltage signal VHV and the H level is the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm, and supplies this gate signal Hgd to the gate terminal of transistor M1.

[0171] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd where the L level is ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2.

[0172] As described above, transistors M1 and M2 operate in accordance with the gate signals Hgd and Lgd, thereby amplified the modulated signal Ms, which is amplified based on the voltage signal VHV, by modulating the base drive signals dO and aO. The signal amplified by transistors M1 and M2 is then output as the amplified modulated signal AMs from the connection point between terminals Tsa and Tdb.

[0173] The demodulation circuit 560 then demodulates the amplified modulation signal AMs by smoothing them, generating a drive signal COM. The demodulation circuit 560 then outputs the generated drive signal COM from the drive circuit 50.

[0174] Even with the drive circuit 50 of the third embodiment configured as described above, the transistors M1 and M2 have the structure shown in Figure 10, which provides the same effects as the liquid dispensing device 1 of the first and second embodiments.

[0175] In this case, in the liquid dispensing device 1 of the third embodiment, a gate driver 521 that outputs a gate signal Hgd and a transistor M1 constitute an integrated circuit device 500a housed in one package, and a gate driver 522 that outputs a gate signal Lgd and a transistor M2 constitute an integrated circuit device 500b housed in one package. This shortens the propagation path of each of the gate signals Hgd and Lgd. As a result, the waveform accuracy of the gate signal Hgd input to transistor M1 and the waveform accuracy of the gate signal Lgd input to transistor M2 are improved.

[0176] As explained with reference to Figure 10, transistors M1 and M2 are HEMT-structured GaN transistors having a configuration in which layer 703 includes an electron transport layer 730 made of a nitride semiconductor, for example, GaN, layer 704 is made of a nitride semiconductor with a larger band gap than the electron transport layer 730, for example, AlGaN, a source electrode 760 electrically connected to the source terminal of transistor M1, a drain electrode 780 electrically connected to the drain terminal of transistor M1, and a gate electrode 770 electrically connected to the gate terminal of transistor M1, with layer 704 positioned above layer 703, and the source electrode 760, gate electrode 770, and gate electrode 770 positioned above layer 704, and at least a portion of the gate electrode 770 is located between the source electrode 760 and the drain electrode 780 when viewed along the Y axis, and with this configuration, high-speed switching and high-frequency driving can be achieved.

[0177] However, if the wiring through which the gate signals Hgd and Lgd propagate is long, the impedance component of the wiring may cause distortion in the waveforms of the gate signals Hgd and Lgd. Therefore, if the wiring through which the gate signals Hgd and Lgd propagate is long, the drive frequency of transistors M1 and M2 may be limited by the waveform distortion of the gate signals Hgd and Lgd. In particular, this problem is more pronounced in GaN transistors with a HEMT structure, such as transistors M1 and M2 in the drive circuit 50 shown in this embodiment, because they are capable of high-speed switching.

[0178] In contrast, in the liquid dispensing device 1 of the third embodiment, similar to the liquid dispensing device 1 of the second embodiment, the wiring through which the gate signals Hgd and Lgd propagate can be shortened, thereby reducing the risk of distortion in the signal waveforms of the gate signal Hgd input to transistor M1 and the gate signal Lgd input to transistor M2. Therefore, it becomes possible to further increase the driving frequency of transistors M1 and M2, and to further improve the waveform accuracy of the driving signal COM output by the driving circuit 50.

[0179] Here, gate driver 521 is an example of a first gate drive circuit, gate driver 522 is an example of a second gate drive circuit, integrated circuit device 500a is a first semiconductor device, and integrated circuit device 500b is a second semiconductor device.

[0180] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0181] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0182] The following conclusions can be drawn from the embodiments described above.

[0183] One embodiment of a liquid dispensing device is: A capacitive load that is displaced by the supply of a drive signal, A discharge unit that discharges liquid in accordance with the displacement of the capacitive load, A capacitive load drive circuit that outputs the aforementioned drive signal, Equipped with, The capacitive load drive circuit is, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer.

[0184] In this liquid dispensing device, at least one of the first and second transistors in the amplification circuit, which outputs a first gate drive signal corresponding to a modulation signal and an amplified modulation signal corresponding to a second gate drive signal, includes a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer. As a result, even when at least one of the first and second transistors is driven at high speed as the output drive signal becomes higher frequency, the losses due to the drive are reduced. Consequently, heat generation in the amplification circuit is reduced. Consequently, the risk of the stability of the capacitive load drive circuit being reduced due to heat generation in the amplification circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0185] In one embodiment of the liquid dispensing device, At least one of the first transistor and the second transistor is A first conductor electrically connected to the source terminal, A second conductor electrically connected to the drain terminal, A third conductor electrically connected to the gate terminal, Includes, The first conductor, the second conductor, and the third conductor are arranged above the second layer. The third conductor may be located at least partially between the first conductor and the second conductor.

[0186] In one embodiment of the liquid dispensing device, The discharge period for which liquid is discharged from the discharge section may be 10 μs or less.

[0187] In this liquid dispensing device, because the dispensing period of liquid from the dispensing section is 10 μs or less, even when the drive signal output by the capacitive load drive circuit becomes high frequency, the heat generated in the amplification circuit is reduced. As a result, the risk of the operation stability of the capacitive load drive circuit being reduced due to the heat generated in the amplification circuit is reduced, and the risk of the waveform accuracy of the drive signal output by the capacitive load drive circuit being reduced is also reduced.

[0188] In one embodiment of the liquid dispensing device, During the period when the amplification circuit outputs the amplified modulated signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher. You may do so.

[0189] In this liquid dispensing device, even at high frequencies of 8 MHz or higher for the drive frequencies of the first and second transistors, the loss due to the drive of at least one of the first and second transistors is reduced, thus reducing heat generation in the amplification circuit. Therefore, the risk of reduced operational stability of the capacitive load drive circuit due to heat generation in the amplification circuit is reduced, and the risk of reduced waveform accuracy of the drive signal output by the capacitive load drive circuit is reduced.

[0190] In one embodiment of the liquid dispensing device, The shortest period within the driving cycle of the first transistor may be shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal remains constant.

[0191] In this liquid dispensing device, the shortest period within the drive cycle of the first transistor is shorter than the shortest period within the period in which the drive signal voltage value changes, and shorter than the shortest period within the period in which the drive signal voltage value remains constant. Therefore, even when the drive frequencies of the first and second transistors become high frequencies, the loss due to the drive of at least one of the first and second transistors is reduced, thus reducing the heat generated in the amplification circuit. Consequently, the risk of the stability of the capacitive load drive circuit being reduced due to the heat generated in the amplification circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0192] In one embodiment of the liquid dispensing device, The capacitive load drive circuit may have a feedback circuit that feeds the drive signal back to the modulation circuit.

[0193] In this liquid dispensing device, even when the drive frequencies of the first and second transistors are set to high frequencies, the risk of a decrease in the operational stability of the capacitive load drive circuit is reduced. Therefore, the responsiveness of the capacitive load drive circuit via the feedback circuit can be improved. As a result, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0194] In one embodiment of the liquid dispensing device, The carriage comprises a main running axis that moves along a main running axis intersecting the transport direction in which the medium to which the liquid discharged from the discharge section is transported, The capacitive load, the discharge unit, and the capacitive load drive circuit may be mounted on the carriage.

[0195] In this liquid dispensing device, the losses due to the driving of at least one of the first and second transistors are reduced, and the heat generated in the amplification circuit is reduced. Therefore, even when a capacitive load drive circuit is mounted on the carriage, the heat generated in the amplification circuit contributes to the liquid, and the risk of the liquid's properties changing is reduced.

[0196] In one embodiment of the liquid dispensing device, The capacitive load drive circuit has a gate drive circuit that outputs the first gate drive signal and the second gate drive signal, The gate drive circuit, the first transistor, and the second transistor may constitute a semiconductor device housed in a single package.

[0197] In this liquid dispensing device, the gate drive circuit and the first and second transistors are composed of a semiconductor device housed in a single package, thereby the first gate signal and This reduces the wiring length through which the second gate signal propagates. As a result, the risk of waveform distortion occurring in the first and second gate signals input to the first and second transistors is reduced, improving the driving accuracy of the first and second transistors. Furthermore, the risk of the driving frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further increases in the driving frequency of the first and second transistors.

[0198] In one embodiment of the liquid dispensing device, The capacitive load drive circuit includes a first gate drive circuit that outputs the first gate drive signal, and a second gate drive circuit that outputs the second gate drive signal. The first gate drive circuit and the first transistor are housed in a single package, constituting a first semiconductor device. The second gate drive circuit and the second transistor may be housed in a single package, constituting a second semiconductor device.

[0199] In this liquid dispensing device, the first gate drive circuit and the first transistor are composed of a first semiconductor device housed in a single package, and the second gate drive circuit and the second transistor are composed of a second semiconductor device housed in a single package. This allows for a reduction in the wiring length through which the first and second gate signals propagate. As a result, the risk of waveform distortion occurring in the first and second gate signals input to the first and second transistors is reduced, improving the driving accuracy of the first and second transistors. Furthermore, the risk of the driving frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further increases in the driving frequency of the first and second transistors.

[0200] One embodiment of a capacitive load drive circuit is: A capacitive load drive circuit that outputs a drive signal to a capacitive load that is displaced so as to discharge liquid from a discharge section when a drive signal is supplied, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer.

[0201] In this capacitive load drive circuit, at least one of the first and second transistors in the amplifier circuit, which outputs a first gate drive signal corresponding to the modulation signal and an amplified modulation signal corresponding to the second gate drive signal, includes a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer. As a result, even when at least one of the first and second transistors is driven at high speed as the output drive signal becomes higher frequency, the losses due to such driving are reduced. Therefore, heat generation in the amplifier circuit is reduced. Consequently, the risk of the stability of operation of the capacitive load drive circuit being reduced due to heat generation in the amplifier circuit is reduced. This reduces the waveform accuracy of the drive signal output by the capacitive load drive circuit.

[0202] In one embodiment of the capacitive load drive circuit, At least one of the first transistor and the second transistor is A first conductor electrically connected to the source terminal, A second conductor electrically connected to the drain terminal, A third conductor electrically connected to the gate terminal, Includes, The first conductor, the second conductor, and the third conductor are arranged above the second layer. The third conductor may be located at least partially between the first conductor and the second conductor.

[0203] In one embodiment of the capacitive load drive circuit, The liquid may be discharged from the discharge unit with a discharge cycle of 10 μs or less.

[0204] In this capacitive load drive circuit, even when the drive signal output by the capacitive load drive circuit becomes high frequency in order to discharge liquid from the discharge section with a discharge period of 10 μs or less, the heat generated in the amplification circuit is reduced. Therefore, the risk of the operation stability of the capacitive load drive circuit being reduced due to the heat generated in the amplification circuit is reduced, and the risk of the waveform accuracy of the drive signal output by the capacitive load drive circuit being reduced is also reduced.

[0205] In one embodiment of the capacitive load drive circuit, During the period when the amplification circuit outputs the amplified modulated signal, the first transistor may be driven at a frequency of 8 MHz or higher, and the second transistor may be driven at a frequency of 8 MHz or higher.

[0206] In this capacitive load drive circuit, even at high frequencies of 8 MHz or higher, the loss due to the driving of at least one of the first and second transistors is reduced, thus reducing heat generation in the amplification circuit. Therefore, the risk of reduced operational stability of the capacitive load drive circuit due to heat generation in the amplification circuit is reduced, and the risk of reduced waveform accuracy of the drive signal output by the capacitive load drive circuit is reduced.

[0207] In one embodiment of the capacitive load drive circuit, The shortest period within the driving cycle of the first transistor may be shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal remains constant.

[0208] In this capacitive load drive circuit, the shortest period within the drive cycle of the first transistor is shorter than the shortest period within the period in which the drive signal voltage value changes, and shorter than the shortest period within the period in which the drive signal voltage value remains constant. Therefore, even when the drive frequencies of the first and second transistors become high frequencies, the loss due to the drive of at least one of the first and second transistors is reduced, thus reducing heat generation in the amplification circuit. Consequently, the risk of the operation stability of the capacitive load drive circuit being reduced due to heat generation in the amplification circuit is reduced, and the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0209] In one embodiment of the capacitive load drive circuit, The system may also include a feedback circuit that feeds the drive signal back to the modulation circuit.

[0210] In this capacitive load drive circuit, even when the drive frequencies of the first and second transistors are set to high frequencies, the risk of a decrease in the operational stability of the capacitive load drive circuit is reduced. Therefore, the responsiveness via the feedback circuit in the capacitive load drive circuit can be improved. As a result, the waveform accuracy of the drive signal output by the capacitive load drive circuit is improved.

[0211] In one embodiment of the capacitive load drive circuit, The liquid discharged from the discharge unit may be mounted on a carriage that moves along a main drive axis intersecting the transport direction in which the medium to which the liquid is delivered is transported.

[0212] In this capacitive load drive circuit, the losses due to the driving of at least one of the first and second transistors are reduced, and the heat generated in the amplification circuit is reduced. Therefore, even when the capacitive load drive circuit is mounted on a carriage, the heat generated in the amplification circuit contributes to the liquid, and the risk of the liquid's properties changing is reduced.

[0213] In one embodiment of the capacitive load drive circuit, The device has a gate drive circuit that outputs a first gate drive signal and a second gate drive signal, The gate drive circuit, the first transistor, and the second transistor may constitute a semiconductor device housed in a single package.

[0214] In this capacitive load drive circuit, the gate drive circuit and the first and second transistors are housed in a single semiconductor device package, thereby shortening the wiring length for the propagation of the first and second gate signals. As a result, the risk of waveform distortion occurring in the first and second gate signals input to the first and second transistors is reduced, improving the drive accuracy of the first and second transistors. Furthermore, the risk of the drive frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further increases in the drive frequency of the first and second transistors.

[0215] In one embodiment of the capacitive load drive circuit, The system includes a first gate drive circuit that outputs a first gate drive signal, and a second gate drive circuit that outputs a second gate drive signal. The first gate drive circuit and the first transistor are housed in a single package, constituting a first semiconductor device. The second gate drive circuit and the second transistor may be housed in a single package, constituting a second semiconductor device.

[0216] In this capacitive load drive circuit, the first gate drive circuit and the first transistor are comprised of a first semiconductor device housed in a single package, and the second gate drive circuit and the second transistor are comprised of a second semiconductor device housed in a single package. This allows for a shorter wiring length for the propagation of the first and second gate signals. As a result, the risk of waveform distortion occurring in the first and second gate signals input to the first and second transistors is reduced, improving the drive accuracy of the first and second transistors. Furthermore, the risk of the drive frequency of the first and second transistors being limited by waveform distortion in the first and second gate signals is reduced, enabling further increases in the drive frequency of the first and second transistors. [Explanation of Symbols]

[0217] 1…Liquid dispensing device, 2…Ink container, 10…Control unit, 20…Head unit, 21…Carriage, 30…Movement unit, 31…Carriage motor, 32…Endless belt, 40…Conveying unit, 41…Conveying motor, 42…Conveying roller, 50, 50a, 50b, 50c…Drive circuit, 52…Reference voltage output circuit, 60…Piezoelectric element, 100…Control circuit, 210…Selection control circuit, 212…Shift register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232a, 232b, 232c…Inverter, 234a, 234b, 234c…Transfer gate, 500, 500a, 500b…Integrated circuit device, 510…Modulation circuit, 512, 513…Adder, 514…Comparator, 515…Inverter 516...Integrating attenuator, 517...Attenuator, 520...Gate drive circuit, 521,522...Gate driver, 550...Amplifier circuit, 560...Demodulation circuit, 570,572...Feedback circuit, 600...Discharge section, 601...Piezoelectric element, 611,612...Electrodes, 621...Diaphragm, 631...Cavity, 632...Nozzle plate, 641...Reservoir, 651...Nozzle, 661...Supply port, 701~705...Layer, 710...Semiconductor substrate, 720...Buffer layer, 730...Electron transport layer, 740...Electron supply layer, 750...Gate layer, 760...Source electrode, 770...Gate electrode, 780...Drain electrode, 790...Secondary electron gas, C1~C5...Capacitor, D1...Diode, L1...Inductor, M1,M2...Transistor, P...Medium, R1~R6...Resistor

Claims

1. A capacitive load that is displaced by the supply of a drive signal, A discharge unit that discharges liquid in accordance with the displacement of the capacitive load, A capacitive load drive circuit that outputs the aforementioned drive signal, Equipped with, The capacitive load drive circuit is, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer. A liquid dispensing device characterized by the following features.

2. At least one of the first transistor and the second transistor is A first conductor electrically connected to the source terminal, A second conductor electrically connected to the drain terminal, A third conductor electrically connected to the gate terminal, Includes, The first conductor, the second conductor, and the third conductor are arranged above the second layer. The third conductor is located at least partially between the first conductor and the second conductor. The liquid dispensing device according to feature 1.

3. The discharge cycle in which liquid is discharged from the discharge unit is 10 μs or less. The liquid dispensing device according to feature 1.

4. During the period when the amplification circuit outputs the amplified modulated signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher. The liquid dispensing device according to feature 1.

5. The shortest period within the driving cycle of the first transistor is shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal remains constant. The liquid dispensing device according to feature 1.

6. The capacitive load drive circuit has a feedback circuit that feeds the drive signal back to the modulation circuit. The liquid dispensing device according to feature 1.

7. The carriage comprises a main running axis that moves along a main running axis intersecting the transport direction in which the medium to which the liquid discharged from the discharge section is transported, The capacitive load, the discharge unit, and the capacitive load drive circuit are mounted on the carriage. The liquid dispensing device according to feature 1.

8. The capacitive load drive circuit has a gate drive circuit that outputs the first gate drive signal and the second gate drive signal, The gate drive circuit, the first transistor, and the second transistor constitute a semiconductor device housed in a single package. A liquid dispensing device according to any one of claims 1 to 7.

9. The capacitive load drive circuit includes a first gate drive circuit that outputs the first gate drive signal, and a second gate drive circuit that outputs the second gate drive signal. The first gate drive circuit and the first transistor are housed in a single package, constituting a first semiconductor device. The second gate drive circuit and the second transistor are housed in a single package, constituting a second semiconductor device. A liquid dispensing device according to any one of claims 1 to 7.

10. A capacitive load drive circuit that outputs a drive signal to a capacitive load that is displaced so as to discharge liquid from a discharge section when a drive signal is supplied, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit includes a first transistor driven in accordance with a first gate drive signal corresponding to the modulation signal, and a second transistor driven in accordance with a second gate drive signal corresponding to the modulation signal, and outputs an amplified modulation signal by driving the first transistor and the second transistor, A demodulation circuit that outputs the drive signal obtained by demodulating the amplified modulated signal, It has, At least one of the first transistor and the second transistor is A first layer containing a first nitride semiconductor, A second layer comprising a second nitride semiconductor having a larger band gap than the first nitride semiconductor, Includes, The second layer is positioned above the first layer. A capacitive load drive circuit characterized by the following features.

11. At least one of the first transistor and the second transistor is A first conductor electrically connected to the source terminal, A second conductor electrically connected to the drain terminal, A third conductor electrically connected to the gate terminal, The first conductor, the second conductor, and the third conductor are arranged above the second layer. The third conductor is located at least partially between the first conductor and the second conductor. Capacitive load drive circuit according to feature 10.

12. The liquid is discharged from the discharge unit with a discharge cycle of 10 μs or less. Capacitive load drive circuit according to feature 10.

13. During the period when the amplification circuit outputs the amplified modulated signal, the first transistor is driven at a frequency of 8 MHz or higher, and the second transistor is driven at a frequency of 8 MHz or higher. Capacitive load drive circuit according to feature 10.

14. The shortest period within the driving cycle of the first transistor is shorter than the shortest period within the period during which the voltage value of the driving signal changes, and shorter than the shortest period within the period during which the voltage value of the driving signal remains constant. Capacitive load drive circuit according to feature 10.

15. The system has a feedback circuit that feeds back the drive signal to the modulation circuit. Capacitive load drive circuit according to feature 10.

16. The liquid discharged from the discharge unit is mounted on a carriage that moves along a main drive axis intersecting the transport direction in which the medium to be transported is transported. Capacitive load drive circuit according to feature 10.

17. The system has a gate drive circuit that outputs a first gate drive signal and a second gate drive signal, The gate drive circuit, the first transistor, and the second transistor constitute a semiconductor device housed in a single package. A capacitive load drive circuit according to any one of claims 10 to 16.

18. The system includes a first gate drive circuit that outputs a first gate drive signal, and a second gate drive circuit that outputs a second gate drive signal. The first gate drive circuit and the first transistor are housed in a single package, constituting a first semiconductor device. The second gate drive circuit and the second transistor are housed in a single package, constituting a second semiconductor device. A capacitive load drive circuit according to any one of claims 10 to 16.

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