Drive circuit, voltage converter, and control method thereof

Abstract

The present invention provides a drive circuit, a voltage converter, and a control method thereof. [Solution] The drive circuit generates first and second control signals and provides them to the respective control electrodes of first and second power semiconductor elements connected in parallel. The safe operating region of the first power semiconductor element is greater than the safe operating region of the second power semiconductor element. The drive circuit includes a time delay circuit, a control logic circuit, and a buffer. The time delay circuit compares the voltage level of the second control signal with a first reference voltage, or compares the drain-source voltage of the first power semiconductor element with the second reference voltage, and generates a first voltage based on the comparison result. The first and second reference voltages are related to the temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal based on the first voltage. The buffer generates a first or second control signal based on the logic signal.

Description

Technical Field

[0001] The present invention relates to a voltage converter, and particularly to a drive circuit, a voltage converter, and a control method thereof.

Background Art

[0002] In order to realize a voltage converter with a higher breakdown voltage, a method of connecting two power semiconductor devices in the upper / lower bridge portions in a cascode manner is known. However, when the cascode connection method is adopted, the on-resistance increases, so the switching efficiency deteriorates.

Summary of the Invention

[0003] An object of the present invention is to generate a first control signal and a second control signal and provide the first and second control signals to the control electrodes of a first power semiconductor device and a second power semiconductor device connected in parallel to each other in a voltage converter, respectively. The range of the safe operating region of the first power semiconductor device is larger than the range of the safe operating region of the second power semiconductor device. A drive circuit includes a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compare the drain-source voltage of the first power semiconductor device with a second reference voltage and generate a corresponding second comparison result, and generate a first voltage based on the first comparison result or the second comparison result. The first and second reference voltages are related to the temperature of the first and second power semiconductor devices. A first time delay circuit, a control logic circuit coupled to the first time delay circuit and generating a first logic signal based on the first voltage, and a first buffer coupled to the control logic circuit and generating one of the first and second control signals based on the first logic signal. The purpose is to propose a drive circuit including these components.

[0004] An object of the present invention is to further propose a voltage converter comprising: a first power semiconductor element having a control electrode for receiving a first control signal; a second power semiconductor element connected in parallel to the first power semiconductor element and having a control electrode for receiving a second control signal, wherein the range of the safe operating region is smaller than the range of the safe operating region of the first power semiconductor element; a first time delay circuit that performs a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or compares the first drain-source voltage of the first power semiconductor element with the second reference voltage and generates a corresponding second comparison result, and generates a first voltage based on the first or second comparison result, wherein the first and second reference voltages are related to the first temperatures of the first and second power semiconductor elements; a control logic circuit coupled to the first time delay circuit for generating a first logic signal based on the first voltage and a pulse width modulation signal; and a first buffer coupled to the control logic circuit for generating one of the first and second control signals based on the first logic signal.

[0005] An object of the present invention is to propose a method for controlling a voltage converter used to generate a first control signal and a second control signal and provide them to the control electrodes of a first power semiconductor element and a second power semiconductor element, respectively, which are connected in parallel to each other in a voltage converter, wherein the safe operating region of the first power semiconductor element is greater than the safe operating region of the second power semiconductor element, the method comprising: receiving a pulse-width modulated signal; performing a first comparison operation to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or comparing the drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, wherein the first and second reference voltages are related to the temperatures of the first and second power semiconductor elements; generating a first voltage based on the first or second comparison result; generating a first logic signal based on the first voltage; and buffering the first logic signal to generate one of the first and second control signals.

[0006] To make the above-mentioned features and advantages of the present invention clearer and easier to understand, examples are given below and described in detail with reference to the attached drawings. [Brief explanation of the drawing]

[0007] The embodiments of the present invention will be better understood by the detailed description below, accompanied by the attached drawings. Note that, in accordance with industry standards, each feature is not depicted proportionally. In fact, for the sake of clarity in the discussion, the dimensions of each feature can be arbitrarily increased or decreased. [Figure 1] This is a circuit diagram of a voltage converter according to an embodiment of the present invention. [Figure 2] This is a timing chart of the signal from a voltage converter according to an embodiment of the present invention. [Figure 3] This is an exemplary circuit diagram of a control logic circuit according to an embodiment of the present invention. [Figure 4A] This is an exemplary circuit diagram of a temperature sensor and time delay circuit according to an embodiment of the present invention. [Figure 4B] This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 5] This is a signal timing chart of the upper bridge portion of the voltage converter according to an embodiment of the present invention during the conduction phase. [Figure 6A] This is an exemplary circuit diagram of a temperature sensor and time delay circuit according to an embodiment of the present invention. [Figure 6B] This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 7] This is a signal timing chart of the upper bridge portion of the voltage converter according to an embodiment of the present invention during the cutoff phase. [Figure 8] This is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 9] This is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 10A] This is an exemplary circuit diagram of a temperature sensor and time delay circuit according to an embodiment of the present invention. [Figure 10B]This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 11A] This is an exemplary circuit diagram of a temperature sensor and time delay circuit according to an embodiment of the present invention. [Figure 11B] This is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 12] This is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 13] This is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 14] This is a circuit diagram of a voltage converter according to an embodiment of the present invention. [Modes for carrying out the invention]

[0008] The embodiments of the present invention will be discussed in detail below. However, for clarity, the embodiments provide many applicable concepts that can be implemented in various specific contexts. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of the present invention. The terms "first," "second," etc., used herein do not imply any particular order or sequence, but are used solely to distinguish elements or operations described using the same technical terminology.

[0009] Figure 1 is a circuit diagram of a voltage converter 1 according to an embodiment of the present invention. In the embodiment of Figure 1, the voltage converter 1 is a buck converter. The voltage converter 1 includes temperature sensors 122 and 162, time delay circuits 120, 140, 160 and 180, a control logic circuit 220, a buffer BF, power semiconductor elements NM1 to NM4, an inductor L, and an output capacitor Cout. Power semiconductor elements NM1 and NM2 constitute the upper bridge portion of the voltage converter 1, and power semiconductor elements NM3 and NM4 constitute the lower bridge portion of the voltage converter 1.

[0010] The temperature sensor 122 is installed adjacent to the power semiconductor elements NM1 and NM2, thereby sensing the temperature of the power semiconductor elements NM1 and NM2 (i.e., the temperature of the upper bridge portion) and outputting a sensing voltage Vtemp1 corresponding to this temperature (i.e., sensing voltage Vtemp1 indicates the temperature of the power semiconductor elements NM1 and NM2). In this embodiment, as the temperature of the power semiconductor elements NM1 and NM2 rises, the sensing voltage Vtemp1 rises accordingly. For example, different voltage values ​​of the sensing voltage Vtemp1 correspond to different temperature values ​​or different temperature ranges of the power semiconductor elements NM1 and NM2. The temperature sensor 162 is installed adjacent to the power semiconductor elements NM3 and NM4, thereby sensing the temperature of the power semiconductor elements NM3 and NM4 (i.e., the temperature of the lower bridge portion) and outputting a sensing voltage Vtemp2 corresponding to this temperature (i.e., sensing voltage Vtemp2 indicates the temperature of the power semiconductor elements NM3 and NM4). In this embodiment, as the temperature of the power semiconductor elements NM3 and NM4 rises, the sensing voltage Vtemp2 rises accordingly. For example, different voltage values ​​of the sensing voltage Vtemp2 correspond to different temperature values ​​or different temperature ranges of the power semiconductor elements NM3 and NM4.

[0011] Time delay circuits 140 and 120 are coupled to the temperature sensor 122 to receive a sensing voltage Vtemp1 from the temperature sensor 122 and provide or generate voltages VG1 and VG2, respectively, based on the sensing voltage Vtemp1. Time delay circuits 180 and 160 are coupled to the temperature sensor 162 to receive a sensing voltage Vtemp2 from the temperature sensor 162 and provide voltages VG3 and VG4, respectively, based on the sensing voltage Vtemp2. ​​As can be seen from the above, time delay circuits 140, 120, 180 and 160 are used to provide voltages VG1, VG2, VG3 and VG4, respectively.

[0012] The control logic circuit 220 receives a pulse-width modulation (PWM) signal SPWM and is coupled to time delay circuits 120, 140, 160, and 180 to receive voltages VG1, VG2, VG3, and VG4, respectively. As shown in Figure 1, the control logic circuit 220 provides or generates logic signals SG1 to SG4 based on the PWM signal SPWM and voltages VG1 to VG4. Buffer BF buffers the logic signals SG1 to SG4, respectively. In detail, the signal strength of the logic signals SG1 to SG4 is enhanced (their driving capability is enhanced) by buffer BF. The enhanced logic signals SG1, SG2, SG3, and SG4 are designated as control signals SG10, SG20, SG30, and SG40, respectively. In other words, the control signals SG10, SG20, SG30, and SG40 are obtained by processing the logic signals SG1, SG2, SG3, and SG4 with the buffer BF (i.e., the control signals SG10, SG20, SG30, and SG40 are derived from the logic signals SG1, SG2, SG3, and SG4, respectively). The buffer BF provides the control signals SG10, SG20, SG30, and SG40 to the gates (also called control electrodes) G1, G2, G3, and G4 of the power semiconductor elements NM1, NM2, NM3, and NM4, respectively, to control or determine the conduction / conduction (on / off) state of the power semiconductor elements NM1, NM2, NM3, and NM4, respectively. In the embodiment shown in Figure 1, the temperature sensors 122 and 162, time delay circuits 120, 140, 160 and 180, buffer BF, and control logic circuit 220 constitute the drive circuit 100, which provides or generates control signals SG10, SG20, SG30 and SG40, and is used to drive the power semiconductor elements NM1, NM2, NM3 and NM4, respectively. In other embodiments, the drive circuit 100 consists of time delay circuits 120, 140, 160 and 180, buffer BF, and control logic circuit 220, and the temperature sensors 122 and 162 are provided outside the drive circuit 100.

[0013] The PWM signal SPWM is a signal provided by a front-stage circuit (not shown in FIG. 1). The PWM signal SPWM can be switched or converted between a high voltage level and a low voltage level. When the PWM signal SPWM is switched or converted to the high voltage level, it instructs the voltage converter 1 to perform a conduction operation on its upper bridge portion (i.e., the power semiconductor elements NM1 and NM2). At this time, this upper bridge portion charges the output capacitor Cout through the inductor L. When the PWM signal SPWM is switched or converted to the low voltage level, it instructs the voltage converter 1 to perform a conduction operation on its lower bridge portion (i.e., the power semiconductor elements NM3 and NM4). At this time, the lower bridge portion discharges the output capacitor Cout through the inductor L. Through the charging and discharging operations on the output capacitor Cout, the voltage converter 1 generates the output voltage VOUT.

[0014] In the voltage converter 1, since the power semiconductor element NM1 is connected in parallel with the power semiconductor element NM2, the power semiconductor elements NM1 and NM2 have a common drain D1 and a common source S1. In an embodiment of the present invention, since the range of the safe operation area (SOA) of the power semiconductor element NM1 is larger than the range of the safe operation area of the power semiconductor element NM2, the power semiconductor element NM1 has a higher breakdown voltage than the power semiconductor element NM2. In an embodiment of the present invention, the power semiconductor elements NM1 and NM2 are metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present invention is not limited thereto.

[0015] In the voltage converter 1, since the power semiconductor device NM3 is connected in parallel with the power semiconductor device NM4, the power semiconductor devices NM3 and NM4 have a common drain D3 and a common source S3. In an embodiment of the present invention, since the range of the safe operating area (SOA) of the power semiconductor device NM3 is larger than the range of the safe operating area of the power semiconductor device NM4, the power semiconductor device NM3 has a higher breakdown voltage than the power semiconductor device NM4. In an embodiment of the present invention, the power semiconductor devices NM3 and NM4 are metal-oxide-semiconductor field-effect transistors, but the present invention is not limited thereto. Refer to FIG. 1. The source S1 and the drain D3 are the same electrode point, and the source S3 is coupled to the ground GND.

[0016] In a well-known voltage converter, in order to increase the breakdown voltage, two power semiconductor devices in the upper bridge portion (the same applies to the lower bridge portion and will not be described further) are connected in a cascode manner. However, when the cascode connection method is adopted, the on-resistance of the upper bridge portion increases, so the switching efficiency of the upper bridge portion deteriorates. In contrast, in the present invention, two power semiconductor devices in the upper bridge portion (the same applies to the lower bridge portion and will not be described further) are changed to be connected in parallel, so as to greatly reduce the resistance during conduction. Therefore, compared with the above well-known voltage converter, the voltage converter of the present invention can obtain a small on-resistance using the same chip usage area, and can also realize a voltage converter with a similarly high breakdown voltage, so it can be used for high-voltage voltage conversion applications. Since the on-resistance is small, the loss during conduction is small and the switching efficiency is high. On the other hand, as can be understood, on the premise that the on-resistance of the above well-known voltage converter and the voltage converter of the present invention is the same, the voltage converter of the present invention can be realized using a small chip usage area, and the benefit cost is high.

[0017] Specifically, the voltage converter of the present invention achieves a large safe operating area (SOA) by connecting two power semiconductor elements in parallel, each having a different safe operating area in the upper and lower bridge sections, thereby reducing conduction resistance, decreasing power loss and chip usage area during switching, increasing overall efficiency, and enabling low-cost operation.

[0018] It should be noted that, in order for the voltage converter 1 to operate correctly, the conduction and disconnection of the power semiconductor elements NM1 and NM2 in the upper bridge section and the power semiconductor elements NM3 and NM4 in the lower bridge section must follow a specific priority order. This is explained below.

[0019] Figure 2 is a signal timing chart of a voltage converter 1 according to an embodiment of the present invention. As shown in Figure 2, time zones t1, t2, and t3 represent the process of conducting the upper bridge portion (i.e., power semiconductor elements NM1 and NM2) of the voltage converter 1. At the start of time zone t1, the PWM signal SPWM is switched or converted from a low voltage level to a high voltage level, indicating an attempt to conduct the upper bridge portion of the voltage converter 1, and the logic signal SG4 is simultaneously converted from a high voltage level to a low voltage level, blocking the power semiconductor element NM4 by the corresponding buffer BF. At the start of time zone t2, the logic signal SG3 is converted from a high voltage level to a low voltage level and blocked by the corresponding buffer BF. At the start of time zone t3 (i.e., time T1), the logic signal SG1 is converted from a low voltage level to a high voltage level, conducting the power semiconductor element NM1 by the corresponding buffer BF. Then, at the end of time zone t3 (i.e., time point T2), the logic signal SG2 is converted from a low voltage level to a high voltage level, and the corresponding buffer BF conducts power through the power semiconductor element NM2.

[0020] Specifically, before conducting the upper bridge portion of the voltage converter 1, it is necessary to shut off the lower bridge portion of the voltage converter 1. In the embodiment of the present invention, since the safe operating region of power semiconductor element NM3 is larger than that of power semiconductor element NM4, the shut-off point of power semiconductor element NM3 must be later than the shut-off point of power semiconductor element NM4, thereby reducing the avalanche multiplication effect of the MOSFET. Specifically, the shut-off point of power semiconductor element NM3 must be later than the shut-off point of power semiconductor element NM4 in order to reach the optimal timing point for shutting off the lower bridge portion, and it is necessary to ensure that power semiconductor elements NM3 and NM4 are within the normal operating range without damage. Therefore, as shown in Figure 2, power semiconductor element NM4 is shut off before the start of time period t1, and power semiconductor element NM3 is shut off at the start of time period t2.

[0021] Furthermore, in order to ensure that the voltage converter 1 can operate normally, a time delay (i.e., time zone t2) is required to conduct electricity to the upper bridge portion of the voltage converter 1 after the lower bridge portion of the voltage converter 1 has been shut off. This prevents the upper bridge portion from conducting electricity if the lower bridge portion is not shut off. Therefore, as shown in Figure 2, after shutting off the power semiconductor element NM3 at the start of time zone t2, there is a time delay (i.e., time zone t2), and then the power semiconductor element NM1 is conducted electricity to the start of time zone t3 (i.e., time point T1).

[0022] After disconnecting the lower bridge portion of the voltage converter 1, the upper bridge portion of the voltage converter 1 is made conductive. In this embodiment of the present invention, the safe operation area (SOA) of power semiconductor element NM1 is larger than that of power semiconductor element NM2. Therefore, the conductive moment of power semiconductor element NM1 must be earlier than the conductive moment of power semiconductor element NM2 in order to reach the optimal timing point for making the upper bridge portion conductive and to ensure that power semiconductor elements NM1 and NM2 are within the normal operating range without damage. Accordingly, as shown in Figure 2, power semiconductor element NM1 is made conductive before the start of time period t3, and power semiconductor element NM2 is made conductive at the end of time period t3.

[0023] As shown in Figure 2, time zones t4, t5, and t6 represent the process of conducting the lower bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM3 and NM4). At the start of time zone t4 (i.e., time T3), the PWM signal SPWM is converted from a high voltage level to a low voltage level, indicating that the lower bridge portion of the voltage converter 1 is about to begin conducting at this point. Simultaneously, the logic signal SG2 is converted from a high voltage level to a low voltage level, blocking the power semiconductor element NM2 by the corresponding buffer BF. Then, at the start of time zone t5 (i.e., time T4), the logic signal SG1 is converted from a high voltage level to a low voltage level, blocking the power semiconductor element NM1 by the corresponding buffer BF. Then, at the start of time zone t6, the logic signal SG3 is converted from a low voltage level to a high voltage level, conducting the power semiconductor element NM3 by the corresponding buffer BF. Finally, at the end of time zone t6, the logic signal SG4 is converted from a low voltage level to a high voltage level, conducting the power semiconductor element NM4 by the corresponding buffer BF.

[0024] Specifically, before conducting the lower bridge portion of the voltage converter 1, it is necessary to shut off the upper bridge portion of the voltage converter 1. In the embodiment of the present invention, since the safe operating region of power semiconductor element NM1 is larger than the safe operating region of power semiconductor element NM2, the shut-off point of power semiconductor element NM1 must be later than the shut-off point of power semiconductor element NM2, thereby reducing the avalanche multiplication effect of the MOSFET. Specifically, the shut-off point of power semiconductor element NM1 must be later than the shut-off point of power semiconductor element NM2 in order to reach the optimal timing point for shutting off the upper bridge portion and to ensure that power semiconductor elements NM1 and NM2 are within the normal operating range. Therefore, as shown in Figure 2, power semiconductor element NM2 is shut off before the start of time period t4, and power semiconductor element NM1 is shut off at the start of time period t5.

[0025] Furthermore, in order to ensure that the voltage converter 1 can operate normally, a time delay (i.e., time zone t5) is required to conduct electricity to the lower bridge portion of the voltage converter 1 after the upper bridge portion of the voltage converter 1 has been shut off. This prevents the lower bridge portion from conducting electricity if the upper bridge portion is not shut off. Therefore, as shown in Figure 2, after the power semiconductor element NM1 is shut off at the start of time zone t5 (i.e., time point T4), there is a time delay (i.e., time zone t5), and then the power semiconductor element NM3 is conducted at the start of time zone t6.

[0026] After disconnecting the upper bridge portion of the voltage converter 1, the lower bridge portion of the voltage converter 1 is made conductive. In this embodiment of the present invention, since the safe operating region of power semiconductor element NM3 is larger than the safe operating region of power semiconductor element NM4, the conductive moment of power semiconductor element NM3 must be earlier than the conductive moment of power semiconductor element NM4. This ensures that when power semiconductor element NM4 is made conductive, it is within the normal operating range, reaching the optimal timing point for making the lower bridge portion conductive, and that power semiconductor elements NM3 and NM4 are within the normal operating range. Therefore, as shown in Figure 2, power semiconductor element NM3 is made conductive before the start of time period t6, and power semiconductor element NM4 is made conductive at the end of time period t6.

[0027] Figure 3 is an exemplary circuit diagram of a control logic circuit 220 according to an embodiment of the present invention. The control logic circuit 220 includes AND gates AND1 to AND4, OR gates OR1 and OR2, and delays DL1 and DL2. AND gate AND1 receives the PWM signal SPWM, the inverted signal of logic signal SG3 (as shown in Figure 3, logic signal SG3 is received by AND gate AND1 after passing through an inverter), and the inverted signal of logic signal SG4. The input terminal of OR gate OR1 is coupled to the output terminal of AND gate AND1 via delays DL1 (i.e., this input terminal of OR gate OR1 is coupled to the output terminal of AND gate AND1), and its other input terminal receives the voltage VG1, which OR gate OR1 then outputs the logic signal SG1 based on. In other words, the control logic circuit 220 provides the logic signal SG1 based on the voltage VG1, logic signals SG3 and SG4, and the PWM signal SPWM. Delays DL1 provide a delay time. In one embodiment, the length of the delay provided by the delay element DL1 is equal to the length of time zone t2 in Figure 2, so time zone t2 is also called the delay time. The AND gate AND2 receives the inverted signal of the PWM signal SPWM, the inverted signal of the logic signal SG1, and the inverted signal of the logic signal SG2. The input terminal of the OR gate OR2 is coupled to the output terminal of the AND gate AND2 via the delay element DL2 (i.e., this input terminal of the OR gate OR2 is coupled to the output terminal of the AND gate AND2), and its other input terminal receives the voltage VG3, so that the OR gate OR2 outputs the logic signal SG3 based on this. In other words, the control logic circuit 220 provides the logic signal SG3 based on the voltage VG3, the logic signals SG1 and SG2, and the PWM signal SPWM. The delay element DL2 provides the delay time. In one embodiment, the length of the delay provided by the delay element DL2 is equal to the length of time zone t5 in Figure 2, so time zone t5 is also called the delay time. The AND gate AND3 receives the PWM signal SPWM and the voltage VG2 and outputs the logic signal SG2 based on them (in other words, the control logic circuit 220 provides the logic signal SG2 based on the PWM signal SPWM and the voltage VG2).The AND gate AND4 receives the inverted signal of the PWM signal SPWM and the voltage VG4, and outputs the logic signal SG4 based on these (in other words, the control logic circuit 220 provides the logic signal SG4 based on the PWM signal SPWM and the voltage VG4).

[0028] Figure 4A is an exemplary circuit diagram of a temperature sensor 122 and a time delay circuit 120 according to an embodiment of the present invention. As shown in Figure 4A, the time delay circuit 120 receives a sensing voltage Vtemp1 from the temperature sensor 122. The time delay circuit 120 generates a reference voltage Vds1_adj based on the sensing voltage Vtemp1, and compares the reference voltage Vds1_adj with the drain-source voltage VDS1 of the power semiconductor element NM1 (i.e., the voltage difference between drain D1 and source S1 in Figure 1) to generate a comparison result, and outputs a voltage VG2 based on the comparison result.

[0029] More specifically, as shown in Figure 4A, the time delay circuit 120 includes a current source ITH1, a resistor Rds1_adj, and a comparator CMP1. The current source ITH1 has the resistor Rds1_adj connected in series between the system voltage VDD and ground GND. The positive input terminal (+) of the comparator CMP1 is connected to the node between the current source ITH1 and the resistor Rds1_adj to receive the reference voltage Vds1_adj, and its negative input terminal (-) receives the drain-source voltage VDS1. The comparator CMP1 performs a comparison operation on the reference voltage Vds1_adj and the drain-source voltage VDS1. If the reference voltage Vds1_adj is greater than the drain-source voltage VDS1, the voltage VG2 output or generated at the output terminal of the comparator CMP1 based on the comparison result is at a high voltage level. When the reference voltage Vds1_adj is less than the drain-source voltage VDS1, the voltage VG2 output or generated at its output terminal by the comparator CMP1 based on the comparison result is at a low voltage level.

[0030] As shown in Figure 4A, the resistor Rds1_adj receives the sensing voltage Vtemp1. In the embodiment of Figure 4A, the resistor Rds1_adj is a voltage control element (i.e., a voltage control resistor) that responds to the sensing voltage Vtemp1. As the sensing voltage Vtemp1 increases, the resistance value of the resistor Rds1_adj increases accordingly. The current output by the current source ITH1 does not change with temperature changes. In other words, since the sensing voltage Vtemp1 increases as the temperatures of the power semiconductor elements NM1 and NM2 rise, the resistance value of the resistor Rds1_adj also increases as the temperatures of the power semiconductor elements NM1 and NM2 rise. Thus, the reference voltage Vds1_adj increases as the temperatures of the power semiconductor elements NM1 and NM2 rise.

[0031] Figure 5 is a signal timing chart of the conduction phase of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention. The detailed process of the conduction phase of the upper bridge portion of the voltage converter 1 will be further explained below, referring to Figures 1 to 4A and Figure 5 together. First, before time T1, logic signals SG1 and SG2 are all at low voltage levels (shown in Figure 2), and accordingly, control signals SG10 and SG20 generated by buffer BF are also at low voltage levels (shown in Figure 5). As shown in Figure 1, control signals SG10 and SG20 are supplied to gate G1 of power semiconductor element NM1 and gate G2 of power semiconductor element NM2, respectively, so that power semiconductor elements NM1 and NM2 are shut off.

[0032] Then, at time T1, the logic signal SG1 is converted from a low voltage level to a high voltage level (as shown in Figure 2), and consequently the control signal SG10 is also converted from a low voltage level to a high voltage level (as shown in Figure 5). As a result, the high-voltage control signal SG10 conducts through the power semiconductor element NM1.

[0033] Then, after time T1, the power semiconductor element NM1 becomes conductive, and the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases (shown in Figure 5). As shown in Figure 4A, the temperatures of power semiconductor elements NM1 and NM2 gradually increase due to the conduction of power semiconductor element NM1, and as a result, the reference voltage Vds1_adj gradually increases. By time T2, the drain-source voltage VDS1 of the power semiconductor element NM1 is already smaller than the reference voltage Vds1_adj (shown in Figure 5), and the voltage VG2 output by the comparator CMP1 is converted from a low voltage level to a high voltage level accordingly. As can be seen from Figure 2, at time T2, the PWM signal SPWM is at a high voltage level. Therefore, by operating the AND gate AND3 in Figure 3, the logic signal SG2 is switched to a high voltage level at time T2, and as a result the control signal SG20 is also at a high voltage level, the high-voltage control signal SG20 conducts the power semiconductor element NM2.

[0034] Specifically, the time delay circuit 120 controls the reference voltage Vds1_adj to be within the safe operating range of the power semiconductor element NM2, thereby ensuring that the drain-source voltage VDS1 when the power semiconductor element NM2 is conducting is also within the safe operating range of the power semiconductor element NM2, and thus ensuring that the power semiconductor elements NM1 and NM2 are within the normal operating range.

[0035] In this invention, the time delay circuit 120 dynamically adjusts the time delay (i.e., time zone t3) between the conduction time of power semiconductor element NM2 (i.e., time zone T2) and the conduction time of power semiconductor element NM1 (i.e., time zone T1) in accordance with the temperatures of power semiconductor elements NM1 and NM2. In other words, the above time delay is not a fixed time length. Specifically, the upper bridge portion of the voltage converter 1 of this invention has a mechanism that automatically adjusts its conduction delay to reach the optimal timing point for conducting in the upper bridge portion by dynamically adjusting its conduction delay according to different temperatures.

[0036] Based on the above, the reference voltage Vds1_adj is related to the temperatures of power semiconductor elements NM1 and NM2. More specifically, the reference voltage Vds1_adj increases as the temperatures of power semiconductor elements NM1 and NM2 rise, and is controlled to remain within the safe operating region of power semiconductor element NM2. Generally, the safe operating region of a power semiconductor element changes with temperature and / or process changes during its operation.

[0037] Therefore, in other embodiments of the present invention (for example, the embodiment in Figure 4B), the voltage converter 1 may be coupled to or included in a memory that stores a lookup table. The aforementioned memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. This lookup table includes a plurality of different preset sensing voltage values ​​as indices and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sensing voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the plurality of different preset reference voltages correspond to different safe operating ranges of the power semiconductor element. In the lookup table, each of the plurality of different preset sensing voltage values ​​may correspond to each of the plurality of different preset reference voltage values, i.e., each may correspond to a different safe operating range, or at least two of the plurality of different preset sensing voltage values ​​may correspond to the same preset reference voltage value, i.e., to the same safe operating range.

[0038] Refer to Figure 4B. In some embodiments, the time delay circuit 120 includes only the comparator CMP1, but does not include the current source ITH1 resistor Rds1_adj as in the embodiment of Figure 4A. The positive input terminal (+) of the comparator CMP1 receives the reference voltage Vds1_adj, and its negative input terminal (-) receives the drain-source voltage VDS1. The voltage converter 1 (or drive circuit 100 or control logic circuit 220) looks up the lookup table in the aforementioned memory based on the value of the sensing voltage Vtemp1 generated by the temperature sensor 122 (corresponding to one preset sensing voltage value in the lookup table above) and obtains the corresponding preset reference voltage value as the reference voltage Vds1_adj. As can be seen from the above, the reference voltage Vds1_adj in Figure 4B increases as the temperatures of the power semiconductor elements NM1 and NM2 rise, and corresponds to the range of the safe operating region of the power semiconductor element NM2 at the temperatures of the power semiconductor elements NM1 and NM2.

[0039] Please refer to Figures 1, 2, 4B, and 5. At time T1, the logic signal SG1 is converted from a low voltage level to a high voltage level (shown in Figure 2), and the control signal SG10 is also converted from a low voltage level to a high voltage level (shown in Figure 5), causing the power semiconductor element NM1 to conduct. In response to the conduction of the power semiconductor element NM1, the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases (shown in Figure 5). As shown in Figure 4B, the temperatures of power semiconductor elements NM1 and NM2 gradually increase due to the conduction of power semiconductor element NM1, and the reference voltage Vds1_adj gradually increases as a result. By time T2, the drain-source voltage VDS1 is already less than the reference voltage Vds1_adj (shown in Figure 5), and the voltage VG2 output by the comparator CMP1 is converted from a low voltage level to a high voltage level accordingly. As can be seen from Figure 2, at time T2, the PWM signal SPWM is at a high voltage level. Therefore, by operating the AND gate AND3 in Figure 3, the logic signal SG2 is switched to a high voltage level at time T2, and as a result the control signal SG20 is also at a high voltage level, the high-voltage control signal SG20 conducts through the power semiconductor element NM2. In this way, the time delay circuit 120 realizes that the time delay (i.e., time period t3) between the time when power semiconductor element NM2 conducts through (i.e., time T2) and the time when power semiconductor element NM1 conducts through (i.e., time T1) is dynamically adjusted according to the temperatures of power semiconductor elements NM1 and NM2.

[0040] Figure 6A is an exemplary circuit diagram of a temperature sensor 122 and a time delay circuit 140 according to an embodiment of the present invention. As shown in Figure 6A, the time delay circuit 140 receives a sensing voltage Vtemp1 from the temperature sensor 122 and a control signal SG20. The time delay circuit 140 generates a reference voltage Vgs2_adj based on the sensing voltage Vtemp1, compares the voltage levels of the reference voltage Vgs2_adj and the control signal SG20 to generate a comparison result, and outputs a voltage VG1 based on the comparison result.

[0041] More specifically, as shown in Figure 6A, the time delay circuit 140 includes a current source ITH2, a resistor Rgs2_adj, and a comparator CMP2. The current source ITH2 has the resistor Rgs2_adj connected in series between the system voltage VDD and ground GND. The negative input terminal (-) of the comparator CMP2 is connected to the node between the current source ITH2 and the resistor Rgs2_adj to receive the reference voltage Vgs2_adj, and its positive input terminal (+) receives the control signal SG20. The comparator CMP2 performs a comparison operation between the voltage level of the control signal SG20 and the reference voltage Vgs2_adj. If the voltage level of the control signal SG20 is greater than the reference voltage Vgs2_adj, the voltage VG1 output or generated at the output terminal of the comparator CMP2 based on the comparison result is a high voltage level. When the voltage level of the control signal SG20 is lower than the reference voltage Vgs2_adj, the voltage VG1 output or generated at the output terminal of the comparator CMP2 based on the comparison result is at a low voltage level.

[0042] As shown in Figure 6A, the resistor Rgs2_adj receives the sensing voltage Vtemp1. In the embodiment of Figure 6A, the resistor Rgs2_adj is a voltage control element (i.e., a voltage control resistor) that responds to the sensing voltage Vtemp1. As the sensing voltage Vtemp1 decreases, the resistance value of the resistor Rgs2_adj increases accordingly. The current output by the current source ITH2 does not change with temperature. In other words, since the sensing voltage Vtemp1 decreases as the temperatures of the power semiconductor elements NM1 and NM2 decrease, the resistance value of the resistor Rgs2_adj increases as the temperatures of the power semiconductor elements NM1 and NM2 decrease. Thus, the reference voltage Vgs2_adj increases as the temperatures of the power semiconductor elements NM1 and NM2 decrease.

[0043] Figure 7 is a signal timing chart of the cutoff stage of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention. The detailed process of the cutoff stage of the upper bridge portion of the voltage converter 1 will be further explained below, referring to Figures 1 to 3, Figure 6A and Figure 7 together. First, before time T3, logic signals SG1 and SG2 are all at high voltage levels (shown in Figure 2), and accordingly, control signals SG10 and SG20 generated by buffer BF are also at high voltage levels (shown in Figure 7). As shown in Figure 1, control signals SG10 and SG20 are supplied to gate G1 of power semiconductor element NM1 and gate G2 of power semiconductor element NM2, respectively, thus conducting power semiconductor elements NM1 and NM2.

[0044] Then, at time T3, the logic signal SG2 is converted from a high voltage level to a low voltage level (as shown in Figure 2), and consequently, the control signal SG20 also gradually decreases from a high voltage level to a low voltage level (as shown in Figure 7), so the control signal SG20 gradually shuts off the power semiconductor element NM2.

[0045] Furthermore, after time point T3, the power semiconductor element NM2 is gradually shut off, so the temperatures of power semiconductor elements NM1 and NM2 gradually decrease as power semiconductor element NM2 is gradually shut off, and the reference voltage Vgs2_adj gradually increases. By time point T4, the voltage level of the control signal SG20 is already lower than the reference voltage Vgs2_adj (shown in Figure 7), and the voltage VG1 output by the comparator CMP2 is converted from a high voltage level to a low voltage level accordingly. As can be seen from Figure 2, at time point T4, the PWM signal SPWM is at a low voltage level. Therefore, by operating the AND gate AND1 and OR gate OR1 in Figure 3, the logic signal SG1 is switched from a high voltage level to a low voltage level at time point T4, and the control signal SG10 also gradually decreases from a high voltage level to a low voltage level accordingly (shown in Figure 7), so the control signal SG10 gradually shuts off the power semiconductor element NM1.

[0046] Specifically, the time delay circuit 140 controls the reference voltage Vgs2_adj to be within the off-operation range of the power semiconductor element NM2. Furthermore, by dynamically adjusting the cutoff delay of the power semiconductor element NM1, it is ensured that the power semiconductor element NM2 has already been reliably cut off, and then the power semiconductor element NM1 is cut off. In this way, the power semiconductor elements NM1 and NM2 can be maintained within their normal operating range without damage.

[0047] In this invention, the time delay circuit 140 dynamically adjusts the time delay (i.e., time period t4) between the cutoff time of power semiconductor element NM1 (i.e., time period T4) and the cutoff time of power semiconductor element NM2 (i.e., time period T3) in accordance with the temperatures of power semiconductor elements NM1 and NM2. In other words, the above time delay is not a fixed time length. Specifically, the upper bridge portion of the voltage converter 1 of this invention has a mechanism that automatically adjusts its cutoff delay to reach the optimal timing point for cutting off the upper bridge portion by dynamically adjusting its cutoff delay according to different temperatures.

[0048] Based on the above, the reference voltage Vgs2_adj is generated by the current source ITH2 and the resistor Rgs2_adj based on the sensing voltage Vtemp1 and is related to the temperatures of power semiconductor elements NM1 and NM2. In detail, the reference voltage Vgs2_adj increases as the temperatures of power semiconductor elements NM1 and NM2 decrease. In other embodiments, the reference voltage Vgs2_adj represents the threshold voltage (Vth) of power semiconductor element NM2. Generally, the threshold voltage of a power semiconductor element changes with its operating temperature and / or process changes.

[0049] In another embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory for storing a lookup table. The memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. The lookup table includes a plurality of different preset sensing voltage values ​​as indices and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sensing voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the plurality of different preset reference voltages correspond to different threshold voltages of the power semiconductor element. In the lookup table, each of the plurality of different preset sensing voltage values ​​may correspond to one of the plurality of different preset reference voltage values, i.e., each may correspond to a different threshold voltage, or at least two of the plurality of different preset sensing voltage values ​​may correspond to the same preset reference voltage value, i.e., the same threshold voltage.

[0050] Refer to Figure 6B. In some embodiments, the time delay circuit 140 includes only the comparator CMP2 and does not include the current source ITH2 resistor Rgs2_adj in the embodiment of Figure 6A. The positive input terminal (+) of the comparator CMP1 receives the control signal SG20, and its negative input terminal (-) receives the reference voltage Vgs2_adj. The voltage converter 1 (or drive circuit 100 or control logic circuit 220) looks up the lookup table in the aforementioned memory based on the value of the sensing voltage Vtemp1 generated by the temperature sensor 122 (corresponding to one preset sensing voltage value in the lookup table above) and obtains the corresponding preset reference voltage value as the reference voltage Vgs2_adj. As can be seen from the above, the reference voltage Vgs2_adj in Figure 6B increases as the temperature of power semiconductor elements NM1 and NM2 decreases and corresponds to the threshold voltage of power semiconductor element NM2 at the temperatures of power semiconductor elements NM1 and NM2.

[0051] Refer to Figures 1, 2, 6B, and 7. At times T1 and T3, the logic signal SG2 is converted from a high voltage level to a low voltage level (shown in Figure 2), and the control signal SG20 also gradually decreases from a high voltage level to a low voltage level (shown in Figure 7), gradually shutting off the power semiconductor element NM2. In response to the gradual shutting off of the power semiconductor element NM2, the temperatures of the power semiconductor elements NM1 and NM2 gradually decrease as the power semiconductor element NM2 is gradually shut off, and the reference voltage Vgs2_adj gradually increases. By time T4, the control signal SG20 is already lower than the reference voltage Vgs2_adj (shown in Figure 7), and the voltage VG1 output by the comparator CMP2 is converted from a high voltage level to a low voltage level. As can be seen from Figure 2, at time T4, the PWM signal SPWM is at a low voltage level. Therefore, by operating the AND gate AND1 and OR gate OR1 in Figure 3, the logic signal SG1 is switched from a high voltage level to a low voltage level at time T4, and consequently the control signal SG10 also gradually decreases from a high voltage level to a low voltage level (as shown in Figure 7), so the control signal SG10 gradually shuts off the power semiconductor element NM1. In this way, the time delay circuit 140 realizes that the time delay (i.e., time period t4) between the shut-off point of power semiconductor element NM1 (i.e., time T4) and the shut-off point of power semiconductor element NM2 (i.e., time T3) is dynamically adjusted according to the temperatures of power semiconductor elements NM1 and NM2.

[0052] Figure 8 is another exemplary circuit diagram of a time delay circuit 120 according to an embodiment of the present invention. The time delay circuit 120 in Figure 8 is similar to the time delay circuit 120 in Figure 4A, the difference being that the current source ITH1 and resistor Rds1_adj in the time delay circuit 120 of Figure 4A are replaced by a current source ITH1_adj and resistor Rds1 in the time delay circuit 120 of Figure 8. Specifically, since the time delay circuit 120 in Figure 8 has similar functionality to the time delay circuit 120 in Figure 4A, the time delay circuit 120 of the embodiment shown in Figure 1 may be implemented using the time delay circuit 120 in Figure 8.

[0053] In detail, as shown in Figure 8, the current source ITH1_adj has a resistor Rds1 connected in series between the system voltage VDD and ground GND, and the current source ITH1_adj receives a sensing voltage Vtemp1. In the embodiment of Figure 8, the current source ITH1_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensing voltage Vtemp1. As the sensing voltage Vtemp1 increases, the current from the current source ITH1_adj increases accordingly. The resistance value of resistor Rds1 does not change with temperature. In other words, since the sensing voltage Vtemp1 increases as the temperatures of the power semiconductor elements NM1 and NM2 rise, the current output by the current source ITH1_adj also increases as the temperatures of the power semiconductor elements NM1 and NM2 rise. Thus, the reference voltage Vds1_adj increases as the temperatures of the power semiconductor elements NM1 and NM2 rise.

[0054] Figure 9 is another exemplary circuit diagram of a time delay circuit 140 according to an embodiment of the present invention. The time delay circuit 140 in Figure 9 is similar to the time delay circuit 140 in Figure 6A, the difference being that the current source ITH2 and resistor Rgs2_adj in the time delay circuit 140 of Figure 6A are replaced by a current source ITH2_adj and resistor Rgs2 in the time delay circuit 140 of Figure 9. Specifically, since the time delay circuit 140 in Figure 9 has similar functionality to the time delay circuit 140 in Figure 6A, the time delay circuit 140 of the embodiment shown in Figure 1 may be implemented using the time delay circuit 140 in Figure 9.

[0055] In detail, as shown in Figure 9, the current source ITH2_adj has a resistor Rgs2 connected in series between the system voltage VDD and ground GND, and the current source ITH2_adj receives a sensing voltage Vtemp1. In the embodiment of Figure 9, the current source ITH2_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensing voltage Vtemp1. As the sensing voltage Vtemp1 decreases, the current from the current source ITH2_adj increases accordingly. The resistance value of resistor Rgs2 does not change with temperature. In other words, since the sensing voltage Vtemp1 decreases as the temperatures of power semiconductor elements NM1 and NM2 decrease, the current output by the current source ITH2_adj also increases as the temperatures of power semiconductor elements NM1 and NM2 decrease. Thus, the reference voltage Vgs2_adj increases as the temperatures of power semiconductor elements NM1 and NM2 decrease.

[0056] Figure 10A is an exemplary circuit diagram of a temperature sensor 162 and a time delay circuit 160 according to an embodiment of the present invention. As shown in Figure 10A, the time delay circuit 160 receives a sensing voltage Vtemp2 from the temperature sensor 162. The time delay circuit 160 generates a reference voltage Vds3_adj based on the sensing voltage Vtemp2, and compares the reference voltage Vds3_adj with the drain-source voltage VDS3 of the power semiconductor element NM3 (i.e., the voltage difference between drain D3 and source S3 in Figure 1) to generate a comparison result, and outputs a voltage VG4 based on the comparison result.

[0057] More specifically, as shown in Figure 10A, the time delay circuit 160 includes a current source ITH3, a resistor Rds3_adj, and a comparator CMP3. The current source ITH3 has the resistor Rds3_adj connected in series between the system voltage VDD and ground GND. The positive input terminal (+) of the comparator CMP3 is connected to the node between the current source ITH3 and the resistor Rds3_adj to receive the reference voltage Vds3_adj, and its negative input terminal (-) receives the drain-source voltage VDS3 of the power semiconductor element NM3. The comparator CMP3 performs a comparison operation on the reference voltage Vds3_adj and the drain-source voltage VDS3. If the reference voltage Vds3_adj is greater than the drain-source voltage VDS3, the voltage VG4 output or generated at the output terminal of the comparator CMP3 based on the comparison result is at a high voltage level. When the reference voltage Vds3_adj is less than the drain-source voltage VDS3, the voltage VG4 output or generated at its output terminal by the comparator CMP3 based on the comparison result is at a low voltage level.

[0058] As shown in Figure 10A, the resistor Rds3_adj receives the sensing voltage Vtemp2. ​​In the embodiment of Figure 10A, the resistor Rds3_adj is a voltage control element (i.e., a voltage control resistor) that responds to the sensing voltage Vtemp2. ​​As the sensing voltage Vtemp2 increases, the resistance value of the resistor Rds3_adj increases accordingly. The current output by the current source ITH3 does not change with temperature changes. In other words, since the sensing voltage Vtemp2 increases as the temperatures of the power semiconductor elements NM3 and NM4 rise, the resistance value of the resistor Rds3_adj also increases as the temperatures of the power semiconductor elements NM3 and NM4 rise. Thus, the reference voltage Vds3_adj increases as the temperatures of the power semiconductor elements NM3 and NM4 rise. The operating logic of the time delay circuit 160 is similar to the operation of the time delay circuit 120 in Figure 4A, and a detailed explanation of its operation is omitted here.

[0059] Based on the above, the reference voltage Vds3_adj is related to the temperatures of power semiconductor elements NM3 and NM4. More specifically, the reference voltage Vds3_adj increases as the temperatures of power semiconductor elements NM3 and NM4 rise, and is controlled to remain within the safe operating region of power semiconductor element NM2. Generally, the safe operating region of a power semiconductor element changes with temperature and / or process changes during its operation.

[0060] Therefore, in other embodiments of the present invention (for example, the embodiment in Figure 10B), the voltage converter 1 may be coupled to or included in a memory that stores a lookup table. The aforementioned memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. This lookup table includes a plurality of different preset sensing voltage values ​​as indices and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sensing voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the plurality of different preset reference voltages correspond to different safe operating ranges of the power semiconductor element.

[0061] Refer to Figure 10B. In some embodiments, the time delay circuit 160 includes only the comparator CMP3, but does not include the current source ITH3 resistor Rds3_adj as in the embodiment of Figure 10A. The positive input terminal (+) of the comparator CMP3 receives the reference voltage Vds3_adj, and its negative input terminal (-) receives the drain-source voltage VDS3. The voltage converter 1 (or drive circuit 100 or control logic circuit 220) looks up the lookup table in the aforementioned memory based on the value of the sensing voltage Vtemp2 generated by the temperature sensor 162 (corresponding to one preset sensing voltage value in the lookup table above) and obtains the corresponding preset reference voltage value as the reference voltage Vds3_adj. The reference voltage Vds3_adj in Figure 10B increases as the temperatures of the power semiconductor elements NM3 and NM4 rise, and corresponds to the range of the safe operating region of the power semiconductor element NM4 at the temperatures of the power semiconductor elements NM3 and NM4. The operating logic of the time delay circuit 160 in Figure 10B is similar to that of the time delay circuit 120 in Figure 4B, and a detailed explanation of its operation is omitted here. According to the embodiment in Figure 10B, the time delay circuit 160 can dynamically adjust the time delay (i.e., time zone t6) between the conduction time of power semiconductor element NM4 and the conduction time of power semiconductor element NM3 in accordance with the temperatures of power semiconductor elements NM3 and NM4.

[0062] In some embodiments, when the embodiments of Figure 4B and Figure 10B are adopted simultaneously, the voltage converter 1 may be coupled to or include a memory that stores a lookup table for obtaining the reference voltages Vds1_adj and Vds3_adj.

[0063] Figure 11A is an exemplary circuit diagram of a temperature sensor 162 and a time delay circuit 180 according to an embodiment of the present invention. As shown in Figure 11A, the time delay circuit 180 receives a sensing voltage Vtemp2 from the temperature sensor 162. The time delay circuit 180 is used to generate a reference voltage Vgs4_adj based on the sensing voltage Vtemp2, compare the voltage level of the reference voltage Vgs4_adj with the voltage level of the control signal SG40 to generate a comparison result, and output a voltage VG3 based on the comparison result.

[0064] More specifically, as shown in Figure 11A, the time delay circuit 180 includes a current source ITH4, a resistor Rgs4_adj, and a comparator CMP4. The current source ITH4 has the resistor Rgs4_adj connected in series between the system voltage VDD and ground GND. The negative input terminal (-) of the comparator CMP4 is connected to the node between the current source ITH4 and the resistor Rgs4_adj to receive the reference voltage Vgs4_adj, and its positive input terminal (+) also receives the reference voltage Vgs4_adj. The comparator CMP4 performs a comparison operation between the voltage level of the control signal SG40 and the reference voltage Vgs4_adj. If the voltage level of the control signal SG40 is greater than the reference voltage Vgs4_adj, the voltage VG3 output or generated at the output terminal of the comparator CMP4 based on the comparison result is a high voltage level. When the voltage level of the control signal SG40 is lower than the reference voltage Vgs4_adj, the voltage VG3 output or generated at the output terminal of the comparator CMP4 based on the comparison result is at a low voltage level.

[0065] As shown in Figure 11A, the resistor Rgs4_adj receives the sensing voltage Vtemp2. ​​In the embodiment of Figure 11A, the resistor Rgs4_adj is a voltage control element (i.e., a voltage control resistor) that responds to the sensing voltage Vtemp2. ​​As the sensing voltage Vtemp2 decreases, the resistance value of the resistor Rgs4_adj increases accordingly. Also, the current output by the current source ITH4 does not change with temperature changes. In other words, since the sensing voltage Vtemp2 decreases as the temperatures of the power semiconductor elements NM3 and NM4 decrease, the resistance value of the resistor Rgs4_adj also increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease, and thus the reference voltage Vgs4_adj increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease. The operating logic of the time delay circuit 180 is similar to the operation of the time delay circuit 140 in Figure 6A, and a detailed explanation of the operation is omitted here.

[0066] Based on the above, the reference voltage Vgs4_adj is generated by the current source ITH4 and the resistor Rgs4_adj based on the sensing voltage Vtemp2 and is related to the temperatures of the power semiconductor elements NM3 and NM4. In detail, the reference voltage Vgs4_adj increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease. In other embodiments, the reference voltage Vgs4_adj represents the threshold voltage of the power semiconductor element NM4. Generally, the threshold voltage of a power semiconductor element changes with its operating temperature and / or process changes.

[0067] In another embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory for storing a lookup table. The aforementioned memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. This lookup table includes a plurality of different preset sensing voltage values ​​as indices and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sensing voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor element, while the plurality of different preset reference voltages correspond to different threshold voltages of the power semiconductor element.

[0068] Refer to Figure 11B. In some embodiments, the time delay circuit 180 includes only the comparator CMP4, but does not include the current source ITH4 resistor Rgs4_adj as in the embodiment of Figure 11A. The positive input terminal (+) of the comparator CMP4 receives the control signal SG40, and its negative input terminal (-) receives the reference voltage Vgs4_adj. The voltage converter 1 (or drive circuit 100 or control logic circuit 220) looks up the lookup table in the aforementioned memory based on the value of the sensing voltage Vtemp2 generated by the temperature sensor 162 (corresponding to one preset sensing voltage value in the lookup table above) and obtains the corresponding preset reference voltage value as the reference voltage Vgs4_adj. As can be seen from the above, the reference voltage Vgs4_adj in Figure 11B increases as the temperature of power semiconductor elements NM3 and NM4 decreases, and corresponds to the threshold voltage of power semiconductor element NM4 at the temperatures of power semiconductor elements NM3 and NM4. The operating logic of the time delay circuit 180 in Figure 11B is similar to that of the time delay circuit 140 in Figure 6B, and a detailed explanation of its operation is omitted here. According to the embodiment in Figure 11B, the time delay circuit 180 can dynamically adjust the time delay (i.e., time zone t1) between the cutoff time of power semiconductor element NM3 and the cutoff time of power semiconductor element NM4 in accordance with the temperatures of power semiconductor elements NM3 and NM4.

[0069] In some embodiments, when the embodiments of Figure 6B and Figure 11B are adopted simultaneously, the voltage converter 1 may be coupled to or include a memory that stores a lookup table for obtaining the reference voltages Vgs2_adj and Vgs4_adj.

[0070] In another embodiment, when the embodiments of Figures 4B, 6B, 10B, and 11B are adopted simultaneously, the voltage converter 1 may be coupled to or include a memory that stores two lookup tables, one of which is used to obtain the reference voltages Vds1_adj and Vds3_adj, and the other lookup table is used to obtain the reference voltages Vgs2_adj and Vgs4_adj. When the embodiments of Figures 4B, 6B, 10B, and 11B are adopted simultaneously, the time intervals t1, t3, t4, and t6 can be shortened, and the delays DL1 and DL2 in Figure 3 can be omitted, thereby improving the operational efficiency of the voltage converter 1. When the delays DL1 and DL2 in Figure 3 are omitted, the input terminal of OR gate OR1 is directly coupled to the output terminal of AND gate AND1, and the input terminal of OR gate OR2 is directly coupled to the output terminal of AND gate AND2.

[0071] Figure 12 is another exemplary circuit diagram of a time delay circuit 160 according to an embodiment of the present invention. The time delay circuit 160 in Figure 12 is similar to the time delay circuit 160 in Figure 10A, the difference being that the current source ITH3 and resistor Rds3_adj in the time delay circuit 160 of Figure 10A are replaced by a current source ITH3_adj and resistor Rds3 in the time delay circuit 160 of Figure 12. Specifically, since the time delay circuit 160 in Figure 12 has similar functionality to the time delay circuit 160 in Figure 10A, the time delay circuit 160 of the embodiment shown in Figure 1 may be implemented using the time delay circuit 160 in Figure 12.

[0072] In detail, as shown in Figure 12, the current source ITH3_adj has a resistor Rds3 connected in series between the system voltage VDD and ground GND, and the current source ITH3_adj receives a sensing voltage Vtemp2. ​​In the embodiment of Figure 12, the current source ITH3_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensing voltage Vtemp2. ​​As the sensing voltage Vtemp2 increases, the current from the current source ITH3_adj increases accordingly. The resistance value of resistor Rds3 does not change with temperature. In other words, since the sensing voltage Vtemp2 increases as the temperatures of the power semiconductor elements NM3 and NM4 rise, the current output by the current source ITH3_adj also increases as the temperatures of the power semiconductor elements NM3 and NM4 rise. Thus, the reference voltage Vds3_adj increases as the temperatures of the power semiconductor elements NM3 and NM4 rise.

[0073] Figure 13 is another exemplary circuit diagram of a time delay circuit 180 according to an embodiment of the present invention. The time delay circuit 180 in Figure 13 is similar to the time delay circuit 180 in Figure 11A, the difference being that the current source ITH4 and resistor Rgs4_adj in the time delay circuit 180 of Figure 11A are replaced by a current source ITH4_adj and resistor Rgs4 in the time delay circuit 180 of Figure 13. Specifically, since the time delay circuit 180 in Figure 13 has similar functionality to the time delay circuit 180 in Figure 11A, the time delay circuit 180 of the embodiment shown in Figure 1 may be implemented using the time delay circuit 180 in Figure 13.

[0074] In detail, as shown in Figure 13, the current source ITH4_adj has a resistor Rgs4 connected in series between the system voltage VDD and ground GND, and the current source ITH4_adj receives a sensing voltage Vtemp2. ​​In the embodiment of Figure 13, the current source ITH4_adj is a voltage-controlled element (i.e., a voltage-controlled current source) that responds to the sensing voltage Vtemp2. ​​As the sensing voltage Vtemp2 decreases, the current from the current source ITH4_adj increases accordingly. The resistance value of resistor Rgs4 does not change with temperature. In other words, since the sensing voltage Vtemp2 decreases as the temperatures of the power semiconductor elements NM3 and NM4 decrease, the current output by the current source ITH4_adj also increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease. Thus, the reference voltage Vgs4_adj increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease.

[0075] The following provides a detailed explanation of the various stages of the voltage converter 1, using Figures 1-4A, 6A, 10A, and 11A together. Before the start of time zone t1, logic signals SG1 and SG2 are at low voltage levels. At the start of time zone t1, the PWM signal SPWM is converted from a low voltage level to a high voltage level, indicating an attempt to conduct through the upper bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM1 and NM2). Therefore, it is necessary to first shut off the lower bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM3 and NM4). Note that the safe operating region of power semiconductor element NM3 is larger than that of power semiconductor element NM4, so the shut-off point for power semiconductor element NM3 must be later than the shut-off point for power semiconductor element NM4. As can be seen from Figure 3, at this time, the inverted signal of the PWM signal SPWM received by the AND gate AND4 is converted from a high voltage level to a low voltage level, so the logic signal SG4 output by the AND gate AND4 is converted from a high voltage level to a low voltage level.

[0076] As described above, at the start of time period t1, the logic signal SG4 is converted from a high voltage level to a low voltage level, and consequently, during time period t1, the control signal SG40 also gradually decreases from a high voltage level to a low voltage level, so the control signal SG40 gradually shuts off the power semiconductor element NM4. As the power semiconductor element NM4 is gradually shut off, the temperatures of the power semiconductor elements NM3 and NM4 gradually decrease, and consequently the reference voltage Vgs4_adj gradually increases. By the end of time period t1, the control signal SG40 is already lower than the reference voltage Vgs4_adj, and the voltage VG3 output by the comparator CMP4 of the time delay circuit 180 in Figure 11A is converted accordingly from a high voltage level to a low voltage level. As can be seen in Figure 2, at the end of time zone t1, the PWM signal SPWM is at a high voltage level. Based on the operation of the AND gate AND2, delay element DL2, and OR gate OR2 in Figure 3, the logic signal SG3 is converted from a high voltage level to a low voltage level. Consequently, the control signal SG30 also gradually decreases from a high voltage level to a low voltage level, and therefore the control signal SG30 gradually shuts off the power semiconductor element NM3.

[0077] As described above, at the start of time zone t2 (i.e., the end of time zone t1), the logic signal SG3 is converted from a high voltage level to a low voltage level. During time zone t2, based on the operation of the time delay circuit 140, the output voltage VG1 is at a low voltage level, and thus the OR gate OR1 depends on the output signal of the AND gate AND1. As the logic signal SG3 is converted to a low voltage level by the operation of the AND gate AND1 and OR gate OR1 in Figure 3, the logic signal SG1 is converted from a low voltage level to a high voltage level at the end of time zone t2, thereby conducting the power semiconductor element NM1. By the way, since the delay element DL1 is coupled between the AND gate AND1 and the OR gate OR1 (i.e., the input terminal of the OR gate OR1 is coupled to the output terminal of the AND gate AND1 via the delay element DL1), the AND gate AND1 needs to go through a time period t2 (i.e., the delay time of the delay element DL1) to convert its output signal from a low voltage level to a high voltage level, and then convert the logic signal SG3 from a low voltage level to a high voltage level.

[0078] Then, during time period t3, the power semiconductor element NM1 becomes conductive, so the drain-source voltage VDS1 of the power semiconductor element NM1 gradually decreases, and the temperatures of power semiconductor elements NM1 and NM2 rise, causing the reference voltage Vds1_adj to gradually increase accordingly. By the end of time period t3 (time T2), the drain-source voltage VDS1 of the power semiconductor element NM1 is already smaller than the reference voltage Vds1_adj, and the voltage VG2 output by the comparator CMP1 of the time delay circuit 120 in Figure 4A is converted from a low voltage level to a high voltage level accordingly. Therefore, by operating the AND gate AND3 in Figure 3, at the end of time period t3, the logic signal SG2 is converted from a low voltage level to a high voltage level, thereby causing the power semiconductor element NM2 to conduct.

[0079] Then, at the start of time zone t4, the PWM signal SPWM is converted from a high voltage level to a low voltage level, indicating an attempt to conduct through the lower bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM3 and NM4). Therefore, it is necessary to first shut off the upper bridge portion of the voltage converter 1 (i.e., power semiconductor elements NM1 and NM2). Note that the safe operating region of power semiconductor element NM1 is larger than that of power semiconductor element NM2, so the shut-off point for power semiconductor element NM1 must be later than the shut-off point for power semiconductor element NM2. As can be seen from Figure 3, at this time, the PWM signal SPWM received by the AND gate AND3 is converted from a high voltage level to a low voltage level, so the logic signal SG2 output by the AND gate AND3 is converted from a high voltage level to a low voltage level.

[0080] As described above, at the start of time period t4 (i.e., time T3), the logic signal SG2 is converted from a high voltage level to a low voltage level, and consequently, during time period t4, the control signal SG20 also gradually decreases from a high voltage level to a low voltage level. Therefore, the control signal SG20 gradually shuts off the power semiconductor element NM2. As the power semiconductor element NM2 is gradually shut off, the temperatures of power semiconductor elements NM1 and NM2 gradually decrease, and consequently, the reference voltage Vgs2_adj gradually increases. By the end of time period t4 (i.e., time T4), the control signal SG20 is already lower than the reference voltage Vgs2_adj, and the voltage VG1 output by the comparator CMP2 of the time delay circuit 140 in Figure 6A is converted accordingly from a high voltage level to a low voltage level. As can be seen from Figure 2, at the end of time zone t4, the PWM signal SPWM is at a low voltage level. Therefore, the logic signal SG1 is converted from a high voltage level to a low voltage level by the operation of the AND gate AND1 and OR gate OR1 in Figure 3. Consequently, the control signal SG10 also gradually decreases from a high voltage level to a low voltage level, and the control signal SG10 gradually shuts off the power semiconductor element NM1.

[0081] As described above, at the start of time period t5 (i.e., time T4), the logic signal SG1 is converted from a high voltage level to a low voltage level. During time period t5, based on the operation of the time delay circuit 180, the output voltage VG3 is at a low voltage level, and thus the OR gate OR2 depends on the output signal of the AND gate AND2. As the logic signal SG1 is converted to a low voltage level by the operation of the AND gate AND2 and OR gate OR2 in Figure 3, the logic signal SG3 is converted from a low voltage level to a high voltage level at the end of this time period t5, thereby conducting the power semiconductor element NM3. Incidentally, since the delay element DL2 is coupled between the AND gate AND2 and the OR gate OR2 (i.e., the input terminal of the OR gate OR2 is coupled to the output terminal of the AND gate AND2 via the delay element DL2), the AND gate AND2 needs to go through a time period t5 (i.e., the delay time of the delay element DL2) to convert its output signal from a low voltage level to a high voltage level in response to the logic signal SG1 being converted from a high voltage level to a low voltage level, and then further convert the logic signal SG3 from a low voltage level to a high voltage level.

[0082] Then, during time period t6, the power semiconductor element NM3 becomes conductive, so the drain-source voltage VDS3 of the power semiconductor element NM3 gradually decreases, and the temperatures of the power semiconductor elements NM3 and NM4 rise, causing the reference voltage Vds3_adj to gradually increase accordingly. By the end of time period t6, the drain-source voltage VDS3 of the power semiconductor element NM3 is already smaller than the reference voltage Vds3_adj, and the voltage VG4 output by the comparator CMP3 of the time delay circuit 160 in Figure 10A is converted from a low voltage level to a high voltage level accordingly. Therefore, by operating the AND gate AND4 in Figure 3, at the end of time period t6, the logic signal SG4 is converted from a low voltage level to a high voltage level, thereby causing the power semiconductor element NM4 to conduct.

[0083] Figure 14 is a circuit diagram of a voltage converter 14 according to an embodiment of the present invention. The voltage converter 14 is similar to the voltage converter 1 shown in Figure 1, but the difference is that the voltage converter 14 is a boost converter.

[0084] Please refer to Figure 14. When the PWM signal SPWM is at a low voltage level, the voltage converter 14 conducts through its lower bridge section (i.e., power semiconductor elements NM3 and NM4), and the current from the system voltage VDD flows through the inductor L and stores energy. When the PWM signal SPWM is at a high voltage level, the voltage converter 14 conducts through its upper bridge section (i.e., power semiconductor elements NM1 and NM2), and the current flowing through the inductor L charges the output capacitor Cout through this upper bridge section, causing the voltage converter 14 to output the voltage VOUT based on this charge.

[0085] The signal timing chart for the voltage converter 14 is the same as that shown in Figure 2, and the illustrative circuit diagram of the control logic circuit 220 for the voltage converter 14 is the same as that shown in Figure 3; therefore, the operation process will not be explained further here.

[0086] According to the embodiments described above, the control method for the voltage converter of the present invention receives a PWM signal SPWM by the control logic circuit 220 and controls the operation of the upper bridge portion and the lower bridge portion of the voltage converter 1 using the PWM signal SPWM as the basic signal. The control method of the present invention will be described below by the operation of controlling the upper bridge portion.

[0087] According to the control method of the present invention, the time delay circuit 140 performs a comparison operation to compare the voltage level of the control signal SG20 with the reference voltage Vgs2_adj and generate a corresponding comparison result, and the time delay circuit 140 generates voltage VG1 based on this comparison result. The time delay circuit 120 performs another comparison operation to compare the drain-source voltage VDS1 of the power semiconductor element NM1 with the reference voltage Vds1_adj and generate a corresponding comparison result, and generates voltage VG2 based on this comparison result. In the embodiment of the present invention, the reference voltages Vgs2_adj and Vds1_adj are all related to the temperatures of the power semiconductor elements NM1 and NM2. The control logic circuit 220 generates logic signal SG1 based on voltage VG1 and PWM signal SPWM, and logic signal SG2 based on voltage VG2 and PWM signal SPWM. The logic signals SG1 and SG2 are buffered by two buffers respectively to generate control signals SG10 and SG20. The control signals SG10 and SG20 are provided to the gates (control electrodes) of the power semiconductor elements NM1 and NM2, respectively, to control the timing of their conduction / blocking.

[0088] Having outlined the features of several embodiments above, those skilled in the art will be able to better understand aspects of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the present invention, thereby achieving the same objectives and / or advantages as these embodiments described herein. Those skilled in the art should understand that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and variations can be made without departing from the spirit and scope of the present invention. [Explanation of Symbols]

[0089] 1, 14: Voltage converter 100: Drive circuit 120, 140, 160, 180: Time delay circuits 122, 162: Temperature sensor 220: Control Logic Circuits AND1, AND2, AND3, AND4: AND gate BF: Buffer CMP1, CMP2, CMP3, CMP4: Comparators Cout: Output Capacitor D1, D3: Drain DL1, DL2: Delay devices G1, G2, G3, G4: Gate GND: Ground ITH1, ITH1_adj, ITH2, ITH2_adj, ITH3, ITH3_adj, ITH4, ITH4_adj: Current source L: Inductor NM1, NM2, NM3, NM4: Power semiconductor devices OR1, OR2: OR gate Rds1, Rds3, Rds1_adj, Rds3_adj, Rgs2, Rgs4, Rgs2_adj, Rgs4_adj: Resistance S1, S3: Source SG1, SG2, SG3, SG4: Logic signals SG10, SG20, SG30, SG40: Control signals SPWM: Pulse Width Modulation (PWM) signal T1, T2, T3, T4: point in time t1, t2, t3, t4, t5, t6: Time zones VDD: System voltage VDS1, VDS3: Drain-Source Voltage Vds1_adj, Vds3_adj, Vgs2_adj, Vgs4_adj: Reference voltage VG1, VG2, VG3, VG4: Voltage VOUT: Output voltage Vtemp1, Vtemp2: Sensing voltage

Claims

1. A drive circuit used to generate a first control signal and a second control signal, and to provide the first and second control signals to the control electrodes of a first power semiconductor element and a second power semiconductor element, respectively, which are connected in parallel to each other in a voltage converter, wherein the safe operating region of the first power semiconductor element is larger than the safe operating region of the second power semiconductor element, A first comparison operation is performed to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or to compare the drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and a first voltage is generated based on the first comparison result or the second comparison result, and the first and second reference voltages are related to the temperatures of the first and second power semiconductor elements in a first time delay circuit, A control logic circuit coupled to the first time delay circuit and which generates a first logic signal based on the first voltage, A first buffer coupled to the control logic circuit and generating one of the first and second control signals based on the first logic signal, A drive circuit including this.

2. The drive circuit according to claim 1, wherein the first reference voltage increases as the temperature of the first and second power semiconductor elements decreases, and the second reference voltage increases as the temperature of the first and second power semiconductor elements increases.

3. The first time delay circuit performs the first comparison operation to generate a first comparison result and generates a first voltage based on the first comparison result, and the first buffer generates a first control signal based on the first logic signal. The aforementioned drive circuit is A second time delay circuit that performs a second comparison operation to compare the drain-source voltage with the second reference voltage and generate the second comparison result, generates a second voltage based on the second comparison result, is coupled to the control logic circuit and generates a second logic signal based on the second voltage, A second buffer coupled to the control logic circuit and which generates the second control signal based on the second logic signal, The drive circuit according to claim 1, further comprising:

4. The drive circuit according to claim 3, wherein the first time delay circuit includes a first current source, a first resistor, and a first comparator, the first current source being coupled in series with the first resistor, the negative input terminal of the first comparator being coupled to a node between the first current source and the first resistor to receive the first reference voltage, the positive input terminal of the first comparator receiving the second control signal, and the first comparator generating the first voltage at its output terminal based on the first comparison result.

5. The drive circuit according to claim 4, wherein one of the first resistor and the first current source is a voltage control element that receives and responds to a sensing voltage, and the sensing voltage indicates the temperature of the first and second power semiconductor elements.

6. The drive circuit according to claim 3, wherein the second time delay circuit includes a second current source, a second resistor, and a second comparator, the second current source being coupled in series with the second resistor, the positive input terminal of the second comparator being coupled to a node between the second current source and the second resistor to receive the second reference voltage, the negative input terminal of the second comparator receiving the drain-source voltage, and the second comparator generating the second voltage at its output terminal based on the second comparison result.

7. The drive circuit according to claim 6, wherein one of the second resistor and the second current source is a voltage control element that receives and responds to a sensing voltage, and the sensing voltage indicates the temperature of the first and second power semiconductor elements.

8. The drive circuit according to claim 3, wherein the first time delay circuit includes a first comparator, the negative input terminal of the first comparator receives the first reference voltage, the positive input terminal of the first comparator receives the second control signal, the first comparator generates the first voltage at its output terminal based on the first comparison result, and the first reference voltage corresponds to the threshold voltage of the second power semiconductor element at the temperature of the first and second power semiconductor elements.

9. The drive circuit according to claim 3, wherein the second time delay circuit includes a second comparator, the positive input terminal of the second comparator receiving the second reference voltage, the negative input terminal of the second comparator receiving the drain-source voltage, the second comparator generating the second voltage at its output terminal based on the second comparison result, and the second reference voltage corresponds to the range of the safe operating regions of the second power semiconductor element at the temperature of the first and second power semiconductor elements.

10. A voltage converter, A first power semiconductor element having a control electrode that receives a first control signal, A second power semiconductor element is connected in parallel to the first power semiconductor element and has a control electrode that receives a second control signal, and the range of its safe operating region is smaller than the range of the safe operating region of the first power semiconductor element. A first comparison operation is performed to compare the voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or to compare the first drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and a first voltage is generated based on the first comparison result or the second comparison result, and the first and second reference voltages are related to a first time delay circuit relating to the first temperature of the first and second power semiconductor elements, A control logic circuit coupled to the first time delay circuit and for generating a first logic signal based on the first voltage and a pulse width modulation signal, A first buffer coupled to the control logic circuit and generating one of the first and second control signals based on the first logic signal, A voltage converter that includes a voltage converter.

11. The first time delay circuit performs the first comparison operation to generate a first comparison result and generates a first voltage based on the first comparison result, and the first buffer generates a first control signal based on the first logic signal. The aforementioned voltage converter is A second time delay circuit that performs a second comparison operation to compare the first drain-source voltage with the second reference voltage and generate the second comparison result, generates a second voltage based on the second comparison result, is coupled to the control logic circuit and generates a second logic signal based on the second voltage and the pulse width modulation signal, A second buffer coupled to the control logic circuit and which generates the second control signal based on the second logic signal, The voltage converter according to claim 10, further comprising:

12. The voltage converter according to claim 11, wherein the first time delay circuit includes a first comparator, the negative input terminal of the first comparator receives the first reference voltage, the positive input terminal of the first comparator receives the second control signal, the first comparator generates the first voltage at its output terminal based on the first comparison result, and the first reference voltage increases as the first temperature of the first and second power semiconductor elements decreases.

13. The voltage converter according to claim 12, wherein, in response to the second power semiconductor element being shut off based on the second control signal, the first comparison result indicates that the voltage level of the second control signal is less than the first reference voltage, the first comparator generates the first voltage having a first voltage level, and the first power semiconductor element is shut off based on the first voltage of the first voltage level.

14. The voltage converter according to claim 11, wherein the second time delay circuit includes a second comparator, the positive input terminal of the second comparator receives the second reference voltage, the negative input terminal of the second comparator receives the first drain-source voltage, the second comparator generates the second voltage at its output terminal based on the second comparison result, and the second reference voltage increases as the first temperature of the first and second power semiconductor elements rises.

15. The voltage converter according to claim 14, wherein, in response to the first power semiconductor element conducting based on the first control signal, the second comparator generates the second voltage having a second voltage level when the second comparison result indicates that the first drain-source voltage is less than the second reference voltage, and the second power semiconductor element conducts based on the second voltage of the second voltage level.

16. A third power semiconductor element having a control electrode that receives a third control signal, A fourth power semiconductor element connected in parallel to the third power semiconductor element and having a control electrode for receiving a fourth control signal, wherein the safe operating region of the third power semiconductor element is larger than the safe operating region of the fourth power semiconductor element, the first and second power semiconductor elements constitute the upper bridge portion of the voltage converter, and the third and fourth power semiconductor elements constitute the lower bridge portion of the voltage converter, A third time delay circuit that performs a third comparison operation to compare the voltage level of the fourth control signal with a third reference voltage and generate a corresponding third comparison result, and generates a third voltage based on the third comparison result, A fourth time delay circuit that performs a fourth comparison operation to compare the second drain-source voltage of the third power semiconductor element with a fourth reference voltage and generate a corresponding fourth comparison result, and generates a fourth voltage based on the fourth comparison result, wherein the third and fourth reference voltages are related to the second temperature of the third and fourth power semiconductor elements, and the control logic circuit is coupled to the third and fourth time delay circuit, and the fourth time delay circuit generates a third logic signal based on the third voltage and the pulse width modulation signal, and generates a fourth logic signal based on the fourth voltage and the pulse width modulation signal, A third buffer coupled to the control logic circuit and which generates the third control signal based on the third logic signal, A fourth buffer is coupled to the control logic circuit and generates the fourth control signal based on the fourth logic signal, The voltage converter according to claim 11, further comprising:

17. The control logic circuit is, A first AND gate that receives the pulse width modulated signal, the inverted signal of the third logic signal, and the inverted signal of the fourth logic signal, A first OR gate is coupled to the output terminal of the first AND gate and receives the first voltage, thereby outputting the first logic signal based on it. A second AND gate that receives the pulse width modulated signal and the second voltage and outputs the second logic signal based on them, A voltage converter according to claim 16, including the following:

18. The control logic circuit is A third AND gate that receives the inverted signal of the pulse width modulated signal, the inverted signal of the first logic signal, and the inverted signal of the second logic signal, A second OR gate is coupled to the output terminal of the third AND gate and receives the third voltage, thereby outputting the third logic signal based on it. A fourth AND gate receives the inverted signal of the pulse width modulated signal and the fourth voltage, and outputs the fourth logic signal based on these, A voltage converter according to claim 17, including the following:

19. A control method for a voltage converter used to generate a first control signal and a second control signal and provide them to the control electrodes of a first power semiconductor element and a second power semiconductor element, respectively, which are connected in parallel to each other in a voltage converter, wherein the safe operating region of the first power semiconductor element is greater than the safe operating region of the second power semiconductor element, Receiving pulse width modulated signals, A first comparison operation is performed to compare the voltage level of the second control signal with the first reference voltage and generate a corresponding first comparison result, or to compare the drain-source voltage of the first power semiconductor element with the second reference voltage and generate a corresponding second comparison result, provided that the first and second reference voltages are related to the temperatures of the first and second power semiconductor elements. A first voltage is generated based on the first comparison result or the second comparison result, To generate a first logic signal based on the first voltage, The first logic signal is buffered to generate one of the first and second control signals, A control method for a voltage converter, including the following:

20. When the first comparison operation is performed to compare the voltage level of the second control signal with the first reference voltage and generate the first comparison result, and the first control signal is generated by buffering the first logic signal, the control method of the voltage converter is: Perform a second comparison operation to compare the drain-source voltage of the first power semiconductor element with the second reference voltage and generate the second comparison result, A second voltage is generated based on the second comparison result, To generate a second logic signal based on the second voltage, The second logic signal is buffered to generate the second control signal, A method for controlling a voltage converter according to claim 19, further comprising:

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