Semiconductor device, and method for manufacturing a semiconductor device.

Abstract

To improve the degree of freedom in controlling the depletion layer. [Solution] The semiconductor device comprises a channel stopper region of a first conductivity type formed on the surface of the drift layer in the termination region, a first termination trench formed in the drift layer in the termination region, a plurality of termination electrodes provided within the first termination trench surrounded by a first termination insulating film, and a channel stopper electrode provided on the upper surface of the drift layer in an electrically connected state to the channel stopper region and the termination electrodes, wherein the plurality of termination electrodes include a first termination electrode and a second termination electrode.

Description

Technical Field

[0001] The technology disclosed in the present specification relates to semiconductor technology.

Background Art

[0002] In a semiconductor device, an active region and a termination region surrounding the active region in a plan view are provided, and the extension of the depletion layer spreading from the PN junction is controlled by a termination structure provided in the termination region (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In semiconductor devices handling large currents such as power semiconductor devices, it is increasingly important to finely control the extension of the depletion layer according to the application.

[0005] The technology disclosed in the present specification has been made in view of the problems described above, and is a technology for improving the degree of freedom in controlling the depletion layer.

Means for Solving the Problems

[0006] A semiconductor device according to a first aspect of the technology disclosed in this specification comprises an active region and a termination region surrounding the active region in a plan view, the semiconductor device comprising: a drift layer of a first conductivity type; a channel stopper region of a first conductivity type having a higher impurity concentration than the drift layer, formed on the surface layer of the drift layer in the termination region; a first termination trench formed in the drift layer in the termination region; a plurality of termination electrodes provided within the first termination trench, surrounded by a first termination insulating film; a channel stopper electrode provided on the upper surface of the drift layer, electrically connected to the channel stopper region and at least one of the termination electrodes; an impurity region of a second conductivity type formed on the surface layer of the drift layer in the active region; and the The device comprises a gate trench formed in a drift layer, a plurality of gate electrodes provided within the gate trench surrounded by a gate insulating film, an interlayer insulating film provided covering the gate trench, an upper electrode provided covering the upper surface of the drift layer and the interlayer insulating film, and a lower electrode provided on the lower surface of the drift layer in at least the active region, wherein the plurality of terminal electrodes in the first terminal trench include a first terminal electrode and a second terminal electrode, the plurality of gate electrodes include a first gate electrode and a second gate electrode, the first terminal electrode and the second terminal electrode are provided spaced apart from each other within the first terminal trench, and the first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. [Effects of the Invention]

[0007] According to at least a first aspect of the technology disclosed in this specification, the degree of freedom in controlling the depletion layer can be improved by providing a plurality of terminal electrodes in a single terminal trench.

[0008] Furthermore, the purposes, features, aspects, and advantages related to the technology disclosed in this specification will become even clearer from the detailed description and accompanying drawings provided below. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] Figure 1 is a perspective view showing an example of some of the components in the active region. [Figure 3] Figure 2 is a cross-sectional view showing an example of the configuration in the BB section. [Figure 4] Figure 2 is a cross-sectional view showing an example of the configuration in a cross-section of CC. [Figure 5] This is a cross-sectional view showing an example of the configuration in section AA of Figure 1. [Figure 6] This is a cross-sectional view showing another example of the configuration in section AA of Figure 1. [Figure 7] Figure 6 is a cross-sectional view showing an example of the configuration in the DD section. [Figure 8] Figure 6 is a cross-sectional view showing another example of the configuration in the DD section. [Figure 9] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 17]It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 18] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 19] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 20] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 21] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 22] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 23] It is a diagram for explaining a method of manufacturing a termination electrode in a termination trench shown in FIG. 8 among semiconductor devices according to an embodiment. [Figure 24] It is a cross-sectional view showing another example of the configuration in the A-A cross section of FIG. 1 of a semiconductor device according to an embodiment. [Figure 25] It is a cross-sectional view showing another example of the configuration in the A-A cross section of FIG. 1 of a semiconductor device according to an embodiment. [Figure 26] It is a cross-sectional view showing another example of the configuration in the D-D cross section of FIG. 6. [Figure 27] It is a cross-sectional view showing another example of the configuration in the A-A cross section of FIG. 1 of a semiconductor device according to an embodiment. [Figure 28] It is a cross-sectional view showing another example of the configuration in the A-A cross section of FIG. 1 of a semiconductor device according to an embodiment.

Embodiments for Carrying Out the Invention

[0010] The embodiments will be described below with reference to the attached drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are illustrative, and not all of them are necessarily essential features for the embodiments to be implementable.

[0011] Please note that the drawings are for illustrative purposes only, and for the sake of clarity, some components may be omitted or simplified as appropriate. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately represented and may be modified as appropriate. In addition, hatching may be used in drawings other than cross-sectional views, such as plan views, to facilitate understanding of the embodiment.

[0012] Furthermore, in the following explanations, similar components will be denoted by the same symbols, and their names and functions will also be the same. Therefore, detailed explanations of them may be omitted to avoid redundancy.

[0013] Furthermore, in the descriptions contained in this specification, when a certain component is described as "equipped with," "includes," or "has," unless otherwise specified, it is not an exclusive expression that excludes the existence of other components.

[0014] Furthermore, even if ordinal numbers such as "first" or "second" are used in the descriptions contained herein, these terms are used for convenience to facilitate understanding of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0015] Furthermore, when the description in this specification states "A or B," such statement shall include both cases where only A or B is indicated, and cases where both A and B are indicated, as long as there is no contradiction.

[0016] Furthermore, in the descriptions contained in this specification, expressions such as "positive direction of the ... axis" or "negative direction of the ... axis" mean that the direction along the arrow of the illustrated ... axis is the positive direction, and the direction opposite to the arrow of the illustrated ... axis is the negative direction.

[0017] Furthermore, even if terms such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back" are used in the descriptions of this specification to indicate a specific position or direction, these terms are used for convenience to facilitate understanding of the embodiments and are not related to the actual position or direction in which the embodiments are carried out.

[0018] Furthermore, in the descriptions contained herein, when a "top surface of..." or "bottom surface of..." is used, it includes not only the top surface or bottom surface of the component in question itself, but also the state in which other components are formed on the top surface or bottom surface of the component in question. That is, for example, when it is stated that "B is provided on the top surface of A", this does not preclude the presence of another component "C" between A and B.

[0019] <First Embodiment> The semiconductor device and the method for manufacturing the semiconductor device according to this embodiment will be described below.

[0020] <About the configuration of semiconductor devices> Figure 1 is a plan view showing an example of the configuration of a semiconductor device according to this embodiment. As shown in the example in Figure 1, the semiconductor device 100 includes an active region 2 and a terminal region 4 formed surrounding the active region 2 in a plan view. Gate pads 6 are arranged at the ends of the active region 2. The gate pads 6 are connected to gate wiring 8 formed surrounding the active region 2 in a plan view.

[0021] Figure 2 is a perspective view showing an example of some of the components in the active region 2 in Figure 1. For convenience, the electrodes formed on the upper surface of the components are omitted from the illustration in Figure 1.

[0022] As shown in Figure 2, the semiconductor device 100 is, for example, an insulated gate bipolar transistor (i.e., an IGBT). The semiconductor device 100 comprises, in its active region 2, an n-type drift layer 10, an n+-type charge storage region 12 formed on the upper surface of the n-type drift layer 10, a p-type channel doped region 14 formed on the surface of the n+-type charge storage region 12, an n+-type source region 16 formed on a part of the surface of the p-type channel doped region 14, a p+-type impurity region 18 formed on another part of the surface of the p-type channel doped region 14, a gate trench 20 formed extending from the upper surface of the n+-type source region 16 and the upper surface of the p+-type impurity region 18 into the interior of the n-type drift layer 10, a gate electrode 24 arranged within the gate trench 20 surrounded by a gate insulating film 22, an interlayer insulating film 26 covering the gate electrode 24, a p+-type collector layer 28 formed on the lower surface of the n-type drift layer 10, and a collector electrode 30 formed on the lower surface of the p+-type collector layer.

[0023] The n-type drift layer 10 is made of, for example, Si or SiC. The impurity concentration in the n+-type charge storage region 12 is higher than the impurity concentration in the n-type drift layer 10.

[0024] The p-type channel doped region 14 is formed by ion implantation of impurities such as boron.

[0025] The impurity concentration in the n+ type source region 16 is higher than that in the n-type drift layer 10. The impurity concentration in the p+ type impurity region 18 is higher than that in the p-type channel doped region 14. The n+ type source region 16 and the p+ type impurity region 18 are arranged alternately, and each extends in the Y-axis direction.

[0026] The gate trench 20 is adjacent to an n+-type source region 16 or a p+-type impurity region 18, a p-type channel doping region 14, and an n+-type charge storage region 12. The gate trench 20 is formed extending in the X-axis direction and multiple trenches are arranged in the Y-axis direction. However, the direction in which the gate trenches 20 extend and the direction in which they are arranged are not limited to those shown in Figure 2, and the positional relationship with the termination trenches (in other words, the combination of extension directions) described later is not limited to those shown in this embodiment. The gate insulating film 22 is formed on the inner wall and bottom surface of the gate trench 20, and is also formed surrounding the gate electrode 24 within the gate trench 20.

[0027] Multiple gate electrodes 24 are provided within a single gate trench 20. The multiple gate electrodes 24 are spaced apart from each other, and a gate insulating film 22 is interposed between them. In Figure 2, the gate electrode 24 located on the positive Z-axis side is designated as gate electrode 24A, and the gate electrode 24 located on the negative Z-axis side is designated as gate electrode 24B.

[0028] The arrangement of the multiple gate electrodes 24 within the gate trench 20 may be such that they overlap in a plan view as shown in Figure 2, in other words, they may be arranged along the Z-axis, the Y-axis, or the X-axis.

[0029] Figure 3 is a cross-sectional view showing an example of the configuration in the BB section of Figure 2. As shown in the example in Figure 3, the semiconductor device 100 comprises, in the active region 2, an n-type drift layer 10, an n+-type charge storage region 12, a p-type channel doped region 14, an n+-type source region 16, a gate trench 20 formed from the upper surface of the n+-type source region 16 to the interior of the n-type drift layer 10, a gate electrode 24, an interlayer insulating film 26, an emitter electrode 32 covering the interlayer insulating film 26 and the n+-type source region 16, a p+-type collector layer 28, and a collector electrode 30. In Figure 3, the emitter electrode 32, which is not shown in Figure 2, is also shown.

[0030] Figure 4 is a cross-sectional view showing an example of the configuration in the CC cross section of Figure 2. As shown in the example in Figure 4, the semiconductor device 100 comprises, in the active region 2, an n-type drift layer 10, an n+-type charge storage region 12, a p-type channel doping region 14, a p+-type impurity region 18, a gate trench 20 formed from the upper surface of the p+-type impurity region 18 to the interior of the n-type drift layer 10, a gate electrode 24, an interlayer insulating film 26, an emitter electrode 32 covering the interlayer insulating film 26 and the p+-type impurity region 18, a p+-type collector layer 28, and a collector electrode 30. In Figure 4, the emitter electrode 32, which is not shown in Figure 2, is also shown.

[0031] Figure 5 is a cross-sectional view showing an example of the configuration in section AA of Figure 1. In Figure 5, in the X-axis direction, the area where the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the terminal region 4.

[0032] As shown in Figure 5 as an example, the semiconductor device 100 has a p+ type impurity region 34 formed on the surface of the n-type drift layer 10 extending from the active region 2 to the termination region 4, an n+ type charge storage region 12 formed on the surface of the n-type drift layer 10 at a position further from the active region 2 than the p+ type impurity region 34, a p-type impurity region 36 formed on the surface of the n+ type charge storage region 12, an n+ type channel stopper region 38 formed on the surface of the p-type impurity region 36, a termination trench 40 formed extending from the upper surface of the n+ type channel stopper region 38 into the interior of the n-type drift layer 10, and a termination arranged within the termination trench 40 surrounded by a termination insulating film 42. The device comprises an electrode 44, a field insulating film 46 formed on the upper surface of the n-type drift layer 10 of the termination region 4, a gate electrode 48 formed in contact with the upper surface of the exposed gate electrode 24A in the gate trench 20 and extending to the upper surface of the field insulating film 46, a field plate electrode 50 formed on the upper surface of the field insulating film 46 at a position further from the active region 2 than the gate electrode 48, spaced apart from the gate electrode 48, a channel stopper electrode 52 formed on the upper surface of the field insulating film 46 at a position further from the active region 2 than the field plate electrode 50, spaced apart from the field plate electrode 50, a p+-type collector layer 28, and a collector electrode 30. Note that the p-type impurity region 36 and the n+-type charge storage region 12 may not be provided.

[0033] The p+-type impurity region 34 and the p-type impurity region 36 are formed by ion implantation of impurities such as boron.

[0034] The impurity concentration in the n+ type channel stopper region 38 is higher than that in the n-type drift layer 10. The impurity concentration in the n+ type charge storage region 12 is higher than that in the n-type drift layer 10 and lower than that in the n+ type channel stopper region 38.

[0035] The termination trench 40 is formed extending in the Y-axis direction. The termination trench 40 is adjacent to an n+-type channel stopper region 38, a p-type impurity region 36, and an n+-type charge storage region 12. The termination insulating film 42 is formed on the inner wall and bottom surface of the termination trench 40, and also surrounds the termination electrode 44 within the termination trench 40. The termination electrode 44 is exposed from the termination insulating film 42 near the top surface of the termination trench 40, but is surrounded by the termination insulating film 42 within the termination trench 40.

[0036] Multiple termination electrodes 44 are provided within a single termination trench 40. The multiple termination electrodes 44 are spaced apart from each other, and a termination insulating film 42 is interposed between the multiple termination electrodes 44. In Figure 5, the termination electrode 44 located on the positive Z-axis side is designated as termination electrode 44A, and the termination electrode 44 located on the negative Z-axis side is designated as termination electrode 44B.

[0037] The arrangement of the multiple terminal electrodes 44 within the terminal trench 40 may be such that they overlap in a plan view as shown in Figure 5, in other words, they may be arranged along the Z-axis, the Y-axis, or the X-axis.

[0038] As shown in Figure 5, multiple field plate electrodes 50 may be formed in the X-axis direction, and each may be formed surrounding the active region 2 in a plan view. Note that the field plate electrodes 50 are not necessarily required.

[0039] The channel stopper electrode 52 is formed in contact with the upper surface of the exposed terminal electrode 44A within the terminal trench 40 and is electrically connected to the terminal electrode 44A. The channel stopper electrode 52 is also formed in contact with the upper surface of the n+ type channel stopper region 38 exposed from the field insulating film 46 and is electrically connected to the n+ type channel stopper region 38.

[0040] Figure 6 is a cross-sectional view showing another example of the configuration in section AA of Figure 1. In Figure 6, in the X-axis direction, the area where the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the terminal region 4.

[0041] In the example shown in Figure 6, a field plate 54 is provided in addition to the configuration shown in Figure 5. Note that if the field plate 54 is not provided as shown in Figure 5, the photomask for forming the field plate 54 can be omitted.

[0042] The field plate 54 is provided on the upper surface of the n-type drift layer 10 of the terminal region 4, surrounded on its upper, lower, and side surfaces by the field insulating film 46A. The thickness of the field insulating film 46A enclosing the field plate 54 is formed to be thicker than that of the field insulating film 46. Multiple field plates 54 may be formed in the X-axis direction, as shown in Figure 6, and each may be formed to surround the active region 2 in a plan view.

[0043] Furthermore, the field plate 54 may be provided at a position corresponding to the space between the field plate electrodes 50 in a plan view.

[0044] Furthermore, in the example shown in Figure 6, the terminal electrode 144 located on the positive Z-axis side of the terminal trench 40 has a connection portion 144A that extends to the upper surface of the field insulating film 46A, in other words, to the upper surface of the n-type drift layer 10. The connection portion 144A, like the terminal electrode 144, is formed of, for example, polysilicon. The channel stopper electrode 52 contacts the connection portion 144A of the exposed terminal electrode 144 in the terminal trench 40. Note that the connection portion 144A may be formed at the same time as the field plate 54.

[0045] Figure 7 is a cross-sectional view showing an example of the configuration in the DD section of Figure 6. As shown in the example in Figure 7, the terminal electrode 44A may be in contact with the channel stopper electrode 52, thereby electrically connecting the two. In this case, the terminal electrode 44B becomes a floating electrode.

[0046] Figure 8 is a cross-sectional view showing another example of the configuration in the DD section of Figure 6. As illustrated in the example in Figure 8, the three components may be electrically connected by both the termination electrode 44A and the termination electrode 44B contacting the channel stopper electrode 52. In this case, the termination electrode 44A, the termination electrode 44B, and the channel stopper electrode 52 are at the same potential. Note that there may be multiple points where the termination electrode 44B contacts the channel stopper electrode 52. Furthermore, the configuration in Figure 8 may be modified so that only the termination electrode 44B is electrically connected to the channel stopper electrode 52.

[0047] <Regarding the manufacturing method of semiconductor devices> Figures 9 to 16 are diagrams illustrating a method for manufacturing a semiconductor device according to this embodiment.

[0048] In the process shown in Figure 9, an n+ type charge storage region 12, a p-type channel doping region 14, a p-type impurity region 36, an n+ type channel stopper region 38, and a p+ type impurity region 34 are formed on the surface of the n-type drift layer 10, and a field insulating film 46A is formed on a portion of the upper surface of the n-type drift layer 10 corresponding to the termination region 4, specifically, in the area excluding the upper surface of the n+ type channel stopper region 38.

[0049] The n+-type charge storage region 12 and the n+-type channel stopper region 38 are formed, for example, by implanting impurities such as phosphorus or arsenic into the surface layer of the n-type drift layer 10 using an ion implantation method, and then by thermal diffusion of the implanted impurities.

[0050] Next, in the process shown in Figure 10, for example, a gate trench 20 is formed in the active region 2 adjacent to the n+ type charge storage region 12 and the p-type channel doped region 14 by photolithography and anisotropic dry etching, and a terminal trench 40 is formed on the upper surface of the n+ type channel stopper region 38 of the terminal region 4.

[0051] Next, in the process shown in Figure 11, an insulating film is formed on the surface (top and side) of the n-type drift layer 10, including within the gate trench 20 and the terminal trench 40. This insulating film is, for example, a silicon oxide film. The insulating film in the gate trench 20 corresponds to the gate insulating film 22. The insulating film in the terminal trench 40 corresponds to the terminal insulating film 42.

[0052] Next, in the process shown in Figure 12, electrodes are formed in a portion of the gate trench 20 and a portion of the terminal trench 40 by chemical vapor deposition (CVD) or the like, while limiting the formation area using a mask or the like. These electrodes are made of, for example, polysilicon. The electrodes in the gate trench 20 correspond to the gate electrode 24B. The electrodes in the terminal trench 40 correspond to the terminal electrode 44B. In Figure 12, electrodes are formed in approximately the lower half of the gate trench 20 and approximately the lower half of the terminal trench 40, respectively. However, for example, electrodes may be formed only on the positive X-axis side of both trenches, or only on the positive Y-axis side of both trenches. Alternatively, a combination such as forming electrodes only on the positive X-axis side of one trench and approximately the lower half of the other trench may also be used.

[0053] Next, in the process shown in Figure 13, insulating films are formed on the upper surfaces inside the gate trench 20 and the end trench 40. These insulating films are, for example, silicon oxide films. The insulating film inside the gate trench 20 corresponds to the gate insulating film 22. The insulating film inside the end trench 40 corresponds to the end insulating film 42.

[0054] Next, in the process shown in Figure 14, electrodes are formed by CVD or the like within the gate trench 20, on the upper surface of the field insulating film 46A in the termination region 4, and within the termination trench 40, while limiting the formation area using a mask or the like. These electrodes are, for example, made of polysilicon. The electrodes within the gate trench 20 correspond to the gate electrode 24A. The electrodes within the termination trench 40 correspond to the termination electrode 144. Here, the termination electrode 144 has a connection portion 144A that extends from the upper surface of the n-type drift layer 10 via an insulating film. The electrodes on the upper surface of the field insulating film 46A correspond to the field plate 54.

[0055] Next, in the process shown in Figure 15, an insulating film is formed so as to cover a portion of the gate electrode 24A and the field plate 54. This insulating film is, for example, a silicon oxide film. The insulating film formed while exposing a portion of the gate electrode 24A corresponds to the interlayer insulating film 26. The insulating film covering the field plate 54 becomes the field insulating film 46A. Here, the field insulating film 46A is formed while exposing a portion of the n+ type channel stopper region 38.

[0056] Next, in the process shown in Figure 16, a metal film is formed over the entire surface by sputtering or the like, and then the electrode is formed by patterning the metal film by photogravure and anisotropic dry etching or the like. The electrode is, for example, aluminum. The electrode provided on the upper surface of the gate trench 20 via the interlayer insulating film 26 corresponds to the emitter electrode 32. The electrode provided in contact with the exposed gate electrode 24A corresponds to the gate electrode 48. The electrode provided on the upper surface of the field insulating film 46A corresponding to the field plate 54 corresponds to the field plate electrode 50. The electrode provided in contact with the connection portion 144A of the terminal electrode 144 and the exposed n+ type channel stopper region 38 corresponds to the channel stopper electrode 52.

[0057] In addition to the above, a p+ type collector layer 28 is formed on the lower surface of the n type drift layer 10, and a collector electrode 30 is further formed on the lower surface of the p+ type collector layer, thereby manufacturing the semiconductor device shown in Figure 6.

[0058] Figures 17 to 23 illustrate the method for manufacturing the termination electrodes in the termination trench shown in Figure 8, which is part of the semiconductor device according to this embodiment.

[0059] In the process shown in Figure 17, a termination trench 40 is formed in the termination region 4 of the n-type drift layer 10, and a termination insulating film 42 is formed within the termination trench 40.

[0060] Next, in the process shown in Figure 18, a terminal electrode 44B is formed in a portion of the terminal trench 40 by CVD or the like, while limiting the formation area using a mask or the like. The terminal electrode 44B is formed such that the height of the upper surface differs in some parts, for example, by performing electrode formation multiple times while changing the formation area with different masks. In Figure 18, the central part in the Y-axis direction is formed to be higher in height than the ends in the Y-axis direction, and the higher part becomes the part that contacts the channel stopper electrode 52 even after the terminal electrode 144 is formed.

[0061] Next, in the process shown in Figure 19, a terminal insulating film 42 is formed on the upper surface within the terminal trench 40. The terminal insulating film 42 is formed over the entire upper surface of the terminal electrodes 44B, which have different heights. This insulating film is, for example, a silicon oxide film.

[0062] Next, in the process shown in Figure 20, a terminal electrode 144 is formed in the terminal trench 40 by a CVD method or the like. The terminal electrode 144 is formed on the lower part of the upper surface of the terminal electrode 44B, in other words, on the ends in the positive and negative directions of the Y axis.

[0063] Next, in the process shown in Figure 21, a terminal insulating film 42 is formed on the upper surface of the terminal trench 40. The terminal insulating film 42 is formed on the upper surface of the terminal electrode 144 and the upper surface of the exposed terminal electrode 44B. The insulating film is, for example, a silicon oxide film.

[0064] Next, in the process shown in Figure 22, the terminating insulating film 42 is patterned to expose a portion of the upper surface of the terminating electrode 44B and the upper surface of the terminating electrode 144.

[0065] Next, in the process shown in Figure 23, a channel stopper electrode 52 is formed. The channel stopper electrode 52 is made of, for example, aluminum. The channel stopper electrode 52 is in contact with both the terminal electrode 144 and the terminal electrode 44B.

[0066] <Second Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0067] <About the configuration of semiconductor devices> Figure 24 is a cross-sectional view showing another example of the configuration of the semiconductor device according to this embodiment in the AA section of Figure 1. In Figure 24, in the X-axis direction, the area in which the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the termination region 4.

[0068] In the example shown in Figure 24, in addition to the configuration shown in Figure 6, a termination trench 41 is provided that extends from the upper surface of the n+-type channel stopper region 38 to the interior of the n-type drift layer 10, and a termination electrode 45 is provided that is arranged within the termination trench 41 surrounded by a termination insulating film 42.

[0069] The terminal trench 41 is formed extending in the Y-axis direction. The terminal insulating film 42 is formed on the inner wall and bottom surface of the terminal trench 41, and also surrounding the terminal electrode 45 within the terminal trench 41.

[0070] Multiple termination electrodes 45 are provided within a single termination trench 41. The multiple termination electrodes 45 are spaced apart from each other, and a termination insulating film 42 is interposed between the multiple termination electrodes 45. In Figure 24, the termination electrode 45 located on the positive Z-axis side is designated as termination electrode 145, and the termination electrode 45 located on the negative Z-axis side is designated as termination electrode 45B.

[0071] The arrangement of the multiple terminal electrodes 45 within the terminal trench 41 may be such that they overlap in a plan view as shown in Figure 24, in other words, they may be arranged along the Z-axis, or along the Y-axis or X-axis.

[0072] Furthermore, in the example shown in Figure 24, the terminal electrode 144 located on the positive Z-axis side in the terminal trench 40 and the terminal electrode 145 located on the positive Z-axis side in the terminal trench 41 have a common connecting portion 144B that extends to the upper surface of the field insulating film 46A, or in other words, extends to the upper surface of the n-type drift layer 10. The channel stopper electrode 52 contacts the exposed terminal electrode 144 in the terminal trench 40 and the exposed terminal electrode 145 in the terminal trench 41 via the connecting portion 144B. In addition to the terminal electrode 145 in the terminal trench 41, the terminal electrode 45B may also be electrically connected to the channel stopper electrode 52, or only the terminal electrode 45B may be electrically connected to the channel stopper electrode 52 instead of the terminal electrode 145 in the terminal trench 41.

[0073] Figure 25 is a cross-sectional view showing another example of the configuration of the semiconductor device according to this embodiment in the AA section of Figure 1. In Figure 25, in the X-axis direction, the area in which the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the termination region 4.

[0074] In the example shown in Figure 25, in addition to the configuration shown in Figure 6, a termination trench 41A is provided that extends from the upper surface of the n+-type channel stopper region 38 to the interior of the n-type drift layer 10, and a termination electrode 45A is provided that is arranged within the termination trench 41A surrounded by a termination insulating film 42.

[0075] The terminal trench 41A is formed at a position further from the active region 2 than the terminal trench 40. Furthermore, the depth of the terminal trench 41A is greater than the depth of the terminal trench 40. The terminal trench 41A extends in the Y-axis direction. The terminal insulating film 42 is formed on the inner wall and bottom surface of the terminal trench 41A, and also surrounds the terminal electrode 45A within the terminal trench 41A.

[0076] Multiple termination electrodes 45A are provided within a single termination trench 41A. The multiple termination electrodes 45A are spaced apart from each other, and a termination insulating film 42 is interposed between the multiple termination electrodes 45A. In Figure 25, the termination electrode 45A located on the positive Z-axis side is designated as termination electrode 145, and the termination electrode 45A located on the negative Z-axis side is designated as termination electrode 45C.

[0077] The arrangement of the multiple terminal electrodes 45A within the terminal trench 41A may be such that they overlap in a plan view as shown in Figure 25, in other words, they may be arranged along the Z-axis, the Y-axis, or the X-axis.

[0078] Furthermore, in the example shown in Figure 25, the terminal electrode 144 located on the positive Z-axis side in the terminal trench 40 and the terminal electrode 145 located on the positive Z-axis side in the terminal trench 41A both have a common connecting portion 144B that extends to the upper surface of the field insulating film 46A, or in other words, extends to the upper surface of the n-type drift layer 10. The channel stopper electrode 52 contacts the exposed terminal electrode 144 in the terminal trench 40 and the exposed terminal electrode 145 in the terminal trench 41A via the connecting portion 144B.

[0079] <Third Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0080] <About the configuration of semiconductor devices> Figure 26 is a cross-sectional view showing another example of the configuration in the DD section of Figure 6. For convenience, only some of the configurations included in the DD section are shown in Figure 26.

[0081] As shown in Figure 26, multiple termination electrodes are provided within a single termination trench 41B. The multiple termination electrodes are spaced apart from each other, and a termination insulating film 42 is interposed between them. In Figure 26, the termination electrode located furthest towards the positive Z-axis is designated as termination electrode 144, the termination electrode located furthest towards the negative Z-axis is designated as termination electrode 44D, and the termination electrode located between termination electrode 144 and termination electrode 44D is designated as termination electrode 44C. Although Figure 26 shows a case where three termination electrodes are formed within a single termination trench, the number of termination electrodes formed within a single termination trench is not limited to the case in Figure 26; for example, four or more termination electrodes may be formed.

[0082] The arrangement of the multiple terminal electrodes within the terminal trench 41B may be an arrangement where they overlap in a plan view as shown in Figure 26, in other words, an arrangement along the Z-axis, an arrangement along the Y-axis, an arrangement along the X-axis, or a matrix-like arrangement along multiple axes.

[0083] Multiple termination electrodes within the termination trench 41B may all be electrically connected by contacting the channel stopper electrode 52. In this case, termination electrode 144, termination electrode 44C, termination electrode 44D, and channel stopper electrode 52 will be at the same potential. On the other hand, at least one of the multiple termination electrodes within the termination trench 41B may not be in contact with the channel stopper electrode 52.

[0084] <Fourth Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0085] <About the configuration of semiconductor devices> Figure 27 is a cross-sectional view showing another example of the configuration of the semiconductor device according to this embodiment in the AA section of Figure 1. In Figure 27, in the X-axis direction, the area in which the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the termination region 4.

[0086] In the example shown in Figure 27, in addition to the configuration shown in Figure 6, a protective film 60 is formed covering at least the channel stopper electrode 52. In Figure 27, the protective film 60 covers not only the channel stopper electrode 52 but also a portion of the emitter electrode 32, the gate electrode 48, and the field plate electrode 50. The protective film 60 is formed of, for example, a silicon nitride film, a silicon oxide film, or polyimide.

[0087] <Fifth Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0088] <About the configuration of semiconductor devices> Figure 28 is a cross-sectional view showing another example of the configuration of the semiconductor device according to this embodiment in the AA section of Figure 1. In Figure 28, in the X-axis direction, the area in which the gate trench 20 is formed corresponds to the active region 2, and the area in the positive X-axis direction beyond the gate trench 20 corresponds to the termination region 4.

[0089] In the example shown in Figure 28, an n+-type channel stopper region 38A is formed instead of the n+-type channel stopper region 38 shown in Figure 6.

[0090] In Figure 28, the termination trench 40 is formed in the n-type drift layer 10 at a position closer to the active region 2 than the end (outer end) of the n+-type channel stopper region 38A opposite to the active region 2. In other words, the outer end of the n+-type channel stopper region 38A is located further from the active region 2 than the termination trench 40.

[0091] In Figure 28, the n+ type channel stopper region 38A is formed on the surface of the n+ type charge storage region 12 in the terminal region 4, in other words, on the surface of the n-type drift layer 10. The n+ type channel stopper region 38A is located further from the active region 2 than the connection portion 144A, and does not overlap with the connection portion 144A in a plan view. In the case where a connection portion 144B spanning two terminal trenches is formed, as shown in Figures 24 and 25, the n+ type channel stopper region 38A is located further from the active region 2 than the connection portion 144B, and does not overlap with the connection portion 144B in a plan view.

[0092] The impurity concentration in the n+-type channel stopper region 38A is higher than that in the n-type drift layer 10. The channel stopper electrode 52 contacts the upper surface of the n+-type channel stopper region 38A that is exposed from the field insulating film 46.

[0093] Here, a p-type channel stopper region may be provided instead of the n+-type channel stopper region 38A. The position where the p-type channel stopper region is provided is the same as that of the n+-type channel stopper region 38A, and the impurity concentration of the p-type channel stopper region is higher than the impurity concentration of the n-type drift layer 10.

[0094] According to the configuration shown in Figure 28, after forming a terminal electrode in the terminal trench and, if necessary, forming the field plate 54 and connection portion 144A, the impurity region where the channel stopper region 38A is formed can be activated. In other words, activation increases the degree of freedom in the timing of forming the channel stopper region 38A. If the channel stopper region 38A is an n-type impurity region, for example, the channel stopper region 38A can be activated simultaneously with the n+-type source region 16 or the n+-type charge storage region 12 in the active region 2. Also, if the channel stopper region 38A is a p-type impurity region, for example, the channel stopper region 38A can be activated simultaneously with the p+-type impurity region 18 or the p-type channel dope region 14 in the active region 2.

[0095] <Regarding the effects resulting from the multiple embodiments described above> Next, examples of the effects produced by the multiple embodiments described above will be shown. In the following description, the effects will be described based on the specific configurations illustrated in the multiple embodiments described above, but they may be replaced with other specific configurations illustrated in this specification to the extent that similar effects are produced. That is, for convenience, in the following, only one of the corresponding specific configurations may be described as representative, but the specific configuration described as representative may be replaced with other corresponding specific configurations.

[0096] Furthermore, such substitutions may be made across multiple embodiments. That is, the respective configurations exemplified in different embodiments may be combined to produce similar effects.

[0097] According to the embodiment described above, the semiconductor device is a semiconductor device comprising an active region 2 and a termination region 4 that surrounds the active region 2 in a plan view. The semiconductor device comprises a drift layer 10 of a first conductivity type (n-type), a channel stopper region 38 (or channel stopper region 38A) of a first conductivity type, a first termination trench, a plurality of termination electrodes, a channel stopper electrode 52, an impurity region of a second conductivity type, a gate trench 20, a plurality of gate electrodes, an interlayer insulating film 26, an upper electrode, and a lower electrode. Here, the first termination trench corresponds to, for example, a termination trench 40 or a termination trench 41B. The impurity region of the second conductivity type corresponds to, for example, a p-type channel doped region 14. The upper electrode corresponds to, for example, an emitter electrode 32. The lower electrode corresponds to, for example, a collector electrode 30. The channel stopper region 38 is formed on the surface of the drift layer 10 in the termination region 4. The channel stopper region 38 has a higher impurity concentration than the drift layer 10. The termination trench 40 is formed in the drift layer 10 in the termination region 4. Multiple termination electrodes are provided within the termination trench 40, surrounded by a first termination insulating film. Here, the first termination insulating film corresponds to, for example, a termination insulating film 42. The channel stopper electrode 52 is electrically connected to the channel stopper region 38 and at least one termination electrode. The channel stopper electrode 52 is also provided on the upper surface of the drift layer 10. The p-type channel dope region 14 is formed on the surface of the drift layer 10 in the active region 2. The gate trench 20 is formed in the drift layer 10 adjacent to the p-type channel dope region 14. Multiple gate electrodes are provided within the gate trench 20, surrounded by a gate insulating film 22. The interlayer insulating film 26 is provided covering the gate trench 20. The emitter electrode 32 is provided covering the upper surface of the drift layer 10 and the interlayer insulating film 26. The collector electrode 30 is provided on the lower surface of the drift layer 10 in at least the active region 2. The multiple termination electrodes within the termination trench 40 include a first termination electrode and a second termination electrode.Here, the first termination electrode corresponds to, for example, termination electrode 44A or termination electrode 144. The second termination electrode corresponds to, for example, termination electrode 44B or termination electrode 44D. The plurality of gate electrodes include the first gate electrode and the second gate electrode. Here, the first gate electrode corresponds to, for example, gate electrode 24A. The second gate electrode corresponds to, for example, gate electrode 24B. Termination electrodes 44A and 44B are provided spaced apart from each other within the termination trench 40. Gate electrodes 24A and 24B are provided spaced apart from each other within the gate trench 20.

[0098] This configuration allows for greater freedom in controlling the depletion layer by providing multiple termination electrodes within a single termination trench. Furthermore, it offers greater flexibility in the formation position of the channel stopper region. Additionally, if the direction in which the multiple termination electrodes in the termination trench are aligned is the same as the direction in which the multiple gate electrodes in the gate trench are aligned, the termination electrodes and gate electrodes can be easily manufactured in the same process.

[0099] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are added to the above configuration as appropriate, that is, if other configurations in this specification that were not mentioned as the above configuration are added as appropriate.

[0100] Furthermore, according to the embodiment described above, the semiconductor device is a semiconductor device comprising an active region 2 and a termination region 4 that surrounds the active region 2 in a plan view. The semiconductor device comprises an n-type drift layer 10, a channel stopper region 38A, a termination trench 40, a plurality of termination electrodes, a channel stopper electrode 52, a p-type channel doped region 14, a gate trench 20, a plurality of gate electrodes, an interlayer insulating film 26, an emitter electrode 32, and a collector electrode 30. The channel stopper region 38A is formed on the surface layer of the drift layer 10 in the termination region 4. The channel stopper region 38A has a higher impurity concentration than the drift layer 10. The termination trench 40 is formed in the drift layer 10 in the termination region 4. The plurality of termination electrodes are provided within the termination trench 40, surrounded by the termination insulating film 42. The channel stopper electrode 52 is electrically connected to the channel stopper region 38A and at least one termination electrode. Furthermore, the channel stopper electrode 52 is provided on the upper surface of the drift layer 10. The p-type channel doped region 14 is formed on the surface of the drift layer 10 in the active region 2. The gate trench 20 is formed in the drift layer 10 adjacent to the p-type channel doped region 14. Multiple gate electrodes are provided within the gate trench 20, surrounded by the gate insulating film 22. The interlayer insulating film 26 is provided covering the gate trench 20. The emitter electrode 32 is provided covering the upper surface of the drift layer 10 and the interlayer insulating film 26. The collector electrode 30 is provided on the lower surface of the drift layer 10 in at least the active region 2. The termination trench 40 is formed in the drift layer 10 at a position closer to the active region 2 than the outer end, which is the end of the channel stopper region 38A opposite to the active region 2. Multiple termination electrodes within the termination trench 40 include the termination electrode 144 and the termination electrode 44B. Multiple gate electrodes include gate electrode 24A and gate electrode 24B. Termination electrodes 44A and 44B are spaced apart from each other within the termination trench 40. Gate electrode 24A and gate electrode 24B are spaced apart from each other within the gate trench 20.

[0101] This configuration allows for greater flexibility in controlling the depletion layer by providing multiple termination electrodes within a single termination trench. Furthermore, the conductivity type of the channel stopper region is not restricted. Additionally, if the direction in which the multiple termination electrodes in the termination trench are aligned is the same as the direction in which the multiple gate electrodes in the gate trench are aligned, the termination electrodes and gate electrodes can be easily manufactured in the same process.

[0102] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are appropriately added to the above configuration, that is, if other configurations in this specification that are not mentioned as the above configuration are appropriately added.

[0103] Furthermore, according to the embodiments described above, at least a portion of the terminal electrode 44A is provided so as to overlap with the terminal electrode 44B in a plan view. At least a portion of the gate electrode 24A is provided so as to overlap with the gate electrode 24B in a plan view. With this configuration, since the multiple terminal electrodes in the terminal trench and the multiple gate electrodes in the gate trench are arranged so as to overlap in a plan view (in other words, they are aligned in the same direction), the terminal electrodes and gate electrodes can be easily manufactured in the same process.

[0104] Furthermore, according to the embodiment described above, at least one termination electrode connected to the channel stopper electrode 52 further comprises a connection portion 144A (or connection portion 144B) extending to the upper surface of the drift layer 10. With this configuration, the contact area between the channel stopper electrode 52 and the termination electrode 144 is increased, so the connection between them becomes stable and the reliability of the semiconductor device can be improved.

[0105] Furthermore, according to the embodiment described above, the channel stopper region 38A is located further from the active region 2 than the connection portion 144A (or connection portion 144B), and does not overlap with the connection portion 144A (or connection portion 144B) in a plan view. With this configuration, the impurity region where the channel stopper region 38A is formed can be activated after forming the terminal electrode in the terminal trench and, if necessary, forming the field plate 54 and the connection portion 144A (or connection portion 144B). In other words, the degree of freedom in the timing of forming the channel stopper region 38A by activation can be increased.

[0106] Furthermore, according to the embodiments described above, both the termination electrode 44A and the termination electrode 44B are electrically connected to the channel stopper electrode 52. With this configuration, the potentials of multiple termination electrodes placed in a single termination trench become the same and stable, thereby improving the accuracy of depletion layer control.

[0107] Furthermore, according to the embodiment described above, the terminal electrode 44B is not electrically connected to the channel stopper electrode 52. With this configuration, by making the terminal electrode 44B a floating electrode, the degree of freedom in depletion layer control can be increased. In addition, since it is not necessary to form a contact portion for bringing the terminal electrode 44B into contact with the channel stopper electrode 52, it is not necessary to change the formation range by using different masks when forming the terminal electrode 44B, and the number of masks and processes can be reduced.

[0108] Furthermore, according to the embodiments described above, the semiconductor device includes a second termination trench formed in the drift layer 10 in the termination region 4. Here, the second termination trench corresponds to, for example, a termination trench 41 or a termination trench 41A. Multiple termination electrodes are provided within the termination trench 41, surrounded by a second termination insulating film. Here, the second termination insulating film corresponds to, for example, a termination insulating film 42. The channel stopper electrode 52 is provided on the upper surface of the drift layer 10, electrically connected to the channel stopper region 38, at least one termination electrode within the termination trench 40, and at least one termination electrode within the termination trench 41. The multiple termination electrodes within the termination trench 41 include a third termination electrode and a fourth termination electrode. Here, the third termination electrode corresponds to, for example, a termination electrode 145. The fourth termination electrode corresponds to, for example, a termination electrode 45B or a termination electrode 45C. The terminal electrode 145 and the terminal electrode 45B are provided spaced apart from each other within the terminal trench 41. With this configuration, the degree of freedom in depletion layer control can be increased by providing multiple terminal electrodes in each of the multiple terminal trenches.

[0109] Furthermore, according to the embodiments described above, at least a portion of the terminal electrode 145 is provided overlapping with the terminal electrode 45B in a plan view. With this configuration, if the multiple terminal electrodes in each of the multiple terminal trenches and the multiple gate electrodes in the gate trench are arranged to overlap in a plan view (in other words, they are aligned in the same direction), the terminal electrodes and gate electrodes can be easily manufactured in the same process.

[0110] Furthermore, according to the embodiments described above, the terminal trench 41 is formed at a position further from the active region 2 than the terminal trench 40. Also, the terminal trench 41 is formed deeper than the terminal trench 40. With this configuration, it becomes easier to position the terminal electrode along the outer edge of the depletion layer extending from the upper surface of the n-type drift layer 10 toward the terminal region 4. Therefore, the elongation of the depletion layer can be effectively suppressed.

[0111] Furthermore, according to the embodiment described above, the multiple termination electrodes within the termination trench 41B further include a fifth termination electrode. Here, the fifth termination electrode corresponds to, for example, a termination electrode 44C. The termination electrode 44C is provided within the termination trench 40, spaced apart from the termination electrodes 144 and 44D. With this configuration, the degree of freedom for depletion layer control can be increased by providing three termination electrodes within a single termination trench.

[0112] Furthermore, according to the embodiments described above, the semiconductor device includes a protective film 60 that covers the channel stopper electrode 52. With this configuration, the voltage resistance and reliability of the semiconductor device can be improved by covering the channel stopper electrode 52 with the protective film 60.

[0113] Furthermore, according to the embodiments described above, the semiconductor device includes an n-type charge storage region 12 provided in the lower layer of the channel stopper region 38 adjacent to the termination trench 40. The impurity concentration of the charge storage region 12 is higher than that of the drift layer 10 and lower than that of the channel stopper region 38. With such a configuration, the depletion layer can be effectively suppressed.

[0114] According to the embodiment described above, in the method for manufacturing a semiconductor device, a p-type channel-doped region 14 is formed on the surface of the n-type drift layer 10 in the active region 2. A first-conductivity channel-stopper region 38 with a higher impurity concentration than the drift layer 10 is formed on the surface of the drift layer 10 in the termination region 4. A gate trench 20 is formed in the drift layer 10 adjacent to the p-type channel-doped region 14 in the active region 2, and a termination trench 40 is formed in the drift layer 10 in the termination region 4. A gate insulating film 22 is formed in the gate trench 20, and a termination insulating film 42 is formed in the termination trench 40. Multiple gate electrodes surrounded by the gate insulating film 22 are formed in the gate trench 20, and multiple termination electrodes surrounded by the termination insulating film 42 are formed in the termination trench 40. An interlayer insulating film 26 is formed to cover the gate trench 20. A channel-stopper electrode 52 electrically connected to the channel-stopper region 38 and at least one termination electrode is formed on the upper surface of the drift layer 10. Then, an emitter electrode 32 is formed covering the upper surface of the drift layer 10 and the interlayer insulating film 26. Then, a collector electrode 30 is formed on the lower surface of the drift layer 10 in at least the active region 2. Here, the plurality of termination electrodes include termination electrode 44A and termination electrode 44B. The plurality of gate electrodes include gate electrode 24A and gate electrode 24B. Furthermore, termination electrode 44A and termination electrode 44B are provided spaced apart from each other within the termination trench 40. Furthermore, gate electrode 24A and gate electrode 24B are provided spaced apart from each other within the gate trench 20.

[0115] This configuration allows for greater freedom in controlling the depletion layer by providing multiple termination electrodes within a single termination trench. Furthermore, it offers greater flexibility in the formation position of the channel stopper region. Additionally, if the direction in which the multiple termination electrodes in the termination trench are aligned is the same as the direction in which the multiple gate electrodes in the gate trench are aligned, the termination electrodes and gate electrodes can be easily manufactured in the same process.

[0116] Unless otherwise specified, the order in which each process is performed can be changed.

[0117] Furthermore, the same effect can be achieved even if other configurations illustrated in the present specification are added to the above configuration as appropriate, that is, if other configurations in the present specification that were not mentioned as the above configuration are added as appropriate.

[0118] Furthermore, according to the embodiment described above, in the method for manufacturing a semiconductor device, a p-type channel-doped region 14 is formed on the surface of the n-type drift layer 10 in the active region 2. Then, a channel stopper region 38A with a higher impurity concentration than the drift layer 10 is formed on the surface of the drift layer 10 in the termination region 4. Then, a gate trench 20 is formed in the drift layer 10 adjacent to the p-type channel-doped region 14 in the active region 2, and a termination trench 40 is formed in the drift layer 10 in the termination region 4. Then, a gate insulating film 22 is formed in the gate trench 20, and a termination insulating film 42 is formed in the termination trench 40. Then, a plurality of gate electrodes surrounded by the gate insulating film 22 are formed in the gate trench 20, and a plurality of termination electrodes surrounded by the termination insulating film 42 are formed in the termination trench 40. Then, an interlayer insulating film 26 is formed to cover the gate trench 20. Then, a channel stopper electrode 52 electrically connected to the channel stopper region 38A and at least one termination electrode is formed on the upper surface of the drift layer 10. Next, an emitter electrode 32 is formed covering the upper surface of the drift layer 10 and the interlayer insulating film 26. Then, a collector electrode 30 is formed on the lower surface of the drift layer 10 in at least the active region 2. Here, the termination trench 40 is formed in the drift layer 10 at a position closer to the active region 2 than the outer end, which is the end of the channel stopper region 38A opposite to the active region 2. The plurality of termination electrodes include termination electrode 44A and termination electrode 44B. The plurality of gate electrodes include gate electrode 24A and gate electrode 24B. The termination electrode 44A and termination electrode 44B are provided spaced apart from each other within the termination trench 40. The gate electrode 24A and gate electrode 24B are provided spaced apart from each other within the gate trench 20.

[0119] This configuration allows for greater flexibility in controlling the depletion layer by providing multiple termination electrodes within a single termination trench. Furthermore, the conductivity type of the channel stopper region is not restricted. Additionally, if the direction in which the multiple termination electrodes in the termination trench are aligned is the same as the direction in which the multiple gate electrodes in the gate trench are aligned, the termination electrodes and gate electrodes can be easily manufactured in the same process.

[0120] Unless otherwise specified, the order in which each process is performed can be changed.

[0121] Furthermore, the same effect can be achieved even if other configurations illustrated in the present specification are added to the above configuration as appropriate, that is, if other configurations in the present specification that were not mentioned as the above configuration are added as appropriate.

[0122] Furthermore, according to the embodiments described above, forming multiple termination electrodes means forming at least one termination electrode connected to the channel stopper electrode 52 such that it has a connection portion 144A (or connection portion 144B) extending to the upper surface of the drift layer 10, and forming the channel stopper region 38A means forming the channel stopper region 38A at a position further from the active region 2 than the connection portion 144A (or connection portion 144B) and at a position that does not overlap with the connection portion in a plan view. Then, after forming the multiple termination electrodes, the region with the same conductivity type in the active region 2 and the channel stopper region 38A are activated simultaneously. With this configuration, termination electrodes can be formed in the termination trench, and further, after forming the field plate 54 and the connection portion 144A (or connection portion 144B) as needed, the impurity region at the location where the channel stopper region 38A is formed can be activated. In other words, the degree of freedom in the timing of forming the channel stopper region 38A by activation can be increased. If the channel stopper region 38A is an n-type impurity region, for example, the channel stopper region 38A can be activated simultaneously with the n+-type source region 16 or the n+-type charge storage region 12 in the active region 2. Also, if the channel stopper region 38A is a p-type impurity region, for example, the channel stopper region 38A can be activated simultaneously with the p+-type impurity region 18 or the p-type channel doping region 14 in the active region 2.

[0123] <Modifications of the multiple embodiments described above> In the various embodiments described above, the material, dimensions, shape, relative arrangement, or implementation conditions of each component may also be described, but these are all examples and not limiting.

[0124] Accordingly, countless variations and equivalents not shown are envisioned within the scope of the art disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component from at least one embodiment and its combination with a component from another embodiment.

[0125] Furthermore, in at least one embodiment described above, if a material name or the like is mentioned without further specification, it is assumed that the material includes other additives, such as an alloy, unless otherwise specified, to avoid any inconsistencies.

[0126] Furthermore, unless contradictory, when it is stated that "one" component is provided in the embodiments described above, "one or more" such components may be provided.

[0127] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component consists of multiple structures, where one component corresponds to a part of a structure, and where multiple components are provided in a single structure.

[0128] Furthermore, each component in the embodiments described above shall include structures having other structures or shapes, as long as they perform the same function.

[0129] Furthermore, the descriptions in this specification are referenced for all purposes related to the present technology and are not considered to be prior art.

[0130] Furthermore, although the semiconductor substrate was n-type in the embodiments described above, it may also be p-type. Also, although IGBTs were described as an example of a semiconductor device in the embodiments described above, it is also possible to consider metal-oxide-semiconductor field-effect transistors (i.e., MOSFETs) as examples of semiconductor devices.

[0131] In the case where the semiconductor device is a MOSFET, the emitter electrode corresponds to the source electrode, and the collector electrode corresponds to the drain electrode.

[0132] Furthermore, although the embodiments described above have been explained assuming that the first conductivity type is n-type and the second conductivity type is p-type, the opposite may also be true: the first conductivity type may be p-type and the second conductivity type may be n-type.

[0133] The various aspects of this disclosure are summarized below as an appendix.

[0134] (Note 1) A semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A first conductive drift layer, A first conductive channel stopper region is formed on the surface of the drift layer in the terminal region, having a higher impurity concentration than the drift layer, A first termination trench formed in the drift layer in the termination region, A plurality of termination electrodes are provided within the first termination trench, surrounded by a first termination insulating film, A channel stopper electrode provided on the upper surface of the drift layer, electrically connected to the channel stopper region and at least one of the terminal electrodes, A second conductive impurity region formed on the surface layer of the drift layer in the active region, A gate trench formed in the drift layer adjacent to the impurity region, Within the gate trench, a plurality of gate electrodes are provided surrounded by a gate insulating film, An interlayer insulating film is provided covering the gate trench, An upper electrode provided in a state that covers the upper surface and the interlayer insulating film of the drift layer, The system comprises at least a lower electrode provided on the lower surface of the drift layer in the active region, The plurality of terminal electrodes in the first terminal trench include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. Semiconductor equipment.

[0135] (Note 2) A semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A first conductive drift layer, A channel stopper region is formed on the surface of the drift layer in the terminal region, having a higher impurity concentration than the drift layer, A first termination trench formed in the drift layer in the termination region, A plurality of termination electrodes are provided within the first termination trench, surrounded by a first termination insulating film, A channel stopper electrode provided on the upper surface of the drift layer, electrically connected to the channel stopper region and at least one of the terminal electrodes, A second conductive impurity region formed on the surface layer of the drift layer in the active region, A gate trench formed in the drift layer adjacent to the impurity region, Within the gate trench, a plurality of gate electrodes are provided surrounded by a gate insulating film, An interlayer insulating film is provided covering the gate trench, An upper electrode provided in a state that covers the upper surface and the interlayer insulating film of the drift layer, The system comprises at least a lower electrode provided on the lower surface of the drift layer in the active region, The first termination trench is formed in the drift layer at a position closer to the active region than the outer end, which is the end of the channel stopper region opposite to the active region. The plurality of terminal electrodes in the first terminal trench include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. Semiconductor equipment.

[0136] (Note 3) A semiconductor device as described in Appendix 1 or 2, At least a portion of the first termination electrode is provided so as to overlap with the second termination electrode in a plan view. At least a portion of the first gate electrode is provided so as to overlap with the second gate electrode in a plan view. Semiconductor equipment.

[0137] (Note 4) A semiconductor device described in any one of the appendices 1 to 3, At least one of the termination electrodes connected to the channel stopper electrode further comprises a connecting portion extending to the upper surface of the drift layer. Semiconductor equipment.

[0138] (Note 5) The semiconductor device is as described in Appendix 4. The channel stopper region is located further from the active region than the connection portion, and does not overlap with the connection portion in a plan view. Semiconductor equipment.

[0139] (Note 6) A semiconductor device described in any one of the appendices 1 to 5, Both the first termination electrode and the second termination electrode are electrically connected to the channel stopper electrode. Semiconductor equipment.

[0140] (Note 7) A semiconductor device described in any one of the appendices 1 to 5, The second termination electrode is not electrically connected to the channel stopper electrode. Semiconductor equipment.

[0141] (Note 8) A semiconductor device described in any one of the appendices 1 to 7, The terminal region further comprises a second terminal trench formed in the drift layer in the terminal region, Multiple termination electrodes are provided within the second termination trench, surrounded by a second termination insulating film. The channel stopper electrode is provided on the upper surface of the drift layer, electrically connected to the channel stopper region, at least one of the terminal electrodes in the first terminal trench, and at least one of the terminal electrodes in the second terminal trench. The plurality of terminal electrodes in the second terminal trench include a third terminal electrode and a fourth terminal electrode, The third termination electrode and the fourth termination electrode are provided spaced apart from each other within the second termination trench. Semiconductor equipment.

[0142] (Note 9) The semiconductor device described in Appendix 8, At least a portion of the third termination electrode is provided so as to overlap with the fourth termination electrode in a plan view. Semiconductor equipment.

[0143] (Note 10) The semiconductor device described in Appendix 8 or 9, The second terminal trench is formed at a position further from the active region than the first terminal trench. The second terminal trench is formed deeper than the first terminal trench. Semiconductor equipment.

[0144] (Note 11) A semiconductor device described in any one of the appendices 1 to 10, The plurality of termination electrodes in the first termination trench further include a fifth termination electrode, The fifth termination electrode is provided within the first termination trench, spaced apart from the first termination electrode and the second termination electrode. Semiconductor equipment.

[0145] (Note 12) A semiconductor device described in any one of the appendices 1 to 11, The system further includes a protective film that covers the channel stopper electrode. Semiconductor equipment.

[0146] (Note 13) A semiconductor device described in any one of the appendices 1 to 12, The present invention further comprises a first conductivity type charge storage region provided in the lower layer of the channel stopper region adjacent to the first termination trench, The impurity concentration in the charge storage region is higher than that of the drift layer and lower than that of the channel stopper region. Semiconductor equipment.

[0147] (Note 14) A method for manufacturing a semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A second impurity region of the conductivity type is formed on the surface of the first conductivity type drift layer in the active region. A first conductive channel stopper region having a higher impurity concentration than the drift layer is formed on the surface of the drift layer in the terminal region. A gate trench is formed in the drift layer at a position adjacent to the impurity region in the active region, and a first terminal trench is formed in the drift layer in the terminal region. A gate insulating film is formed in the gate trench, and a first terminal insulating film is formed in the first terminal trench. Multiple gate electrodes surrounded by the gate insulating film are formed within the gate trench, and multiple terminal electrodes surrounded by the first terminal insulating film are formed within the first terminal trench, An interlayer insulating film is formed to cover the gate trench, The channel stopper region and the channel stopper electrode electrically connected to at least one of the terminal electrodes are formed on the upper surface of the drift layer. An upper electrode is formed to cover the upper surface of the drift layer and the interlayer insulating film, A bottom electrode is formed on the lower surface of the drift layer in at least the active region. The plurality of terminal electrodes include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. A method for manufacturing a semiconductor device.

[0148] (Note 15) A method for manufacturing a semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A second impurity region of the conductivity type is formed on the surface of the first conductivity type drift layer in the active region. A channel stopper region with a higher impurity concentration than the drift layer is formed on the surface of the drift layer in the terminal region. A gate trench is formed in the drift layer at a position adjacent to the impurity region in the active region, and a first terminal trench is formed in the drift layer in the terminal region. A gate insulating film is formed in the gate trench, and a first terminal insulating film is formed in the first terminal trench. Multiple gate electrodes surrounded by the gate insulating film are formed within the gate trench, and multiple terminal electrodes surrounded by the first terminal insulating film are formed within the first terminal trench. An interlayer insulating film is formed to cover the gate trench, The channel stopper region and the channel stopper electrode electrically connected to at least one of the terminal electrodes are formed on the upper surface of the drift layer. An upper electrode is formed to cover the upper surface of the drift layer and the interlayer insulating film, A bottom electrode is formed on the lower surface of the drift layer in at least the active region. The first termination trench is formed in the drift layer at a position closer to the active region than the outer end, which is the end of the channel stopper region opposite to the active region. The plurality of terminal electrodes include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. A method for manufacturing a semiconductor device.

[0149] (Note 16) The method for manufacturing a semiconductor device as described in Appendix 15, Forming a plurality of the termination electrodes means that at least one of the termination electrodes connected to the channel stopper electrode has a connecting portion that extends to the upper surface of the drift layer, The channel stopper region is formed at a location that is further from the active region than the connection portion and does not overlap with the connection portion in a plan view. After forming multiple terminal electrodes, the regions with the same conductivity type in the active region and the channel stopper region are activated simultaneously. A method for manufacturing a semiconductor device. [Explanation of Symbols]

[0150] 2 Active region, 4 Termination region, 6 Gate pad, 8 Gate wiring, 10 Drift layer, 12 Charge storage region, 14 Channel dope region, 16 Source region, 18 Impurity region, 20 Gate trench, 22 Gate insulating film, 24 Gate electrode, 24A Gate electrode, 24B Gate electrode, 26 Interlayer insulating film, 28 Collector layer, 30 Collector electrode, 32 Emitter electrode, 34 Impurity region, 36 Impurity region, 38 Channel stopper region, 38A Channel stopper region, 40 Termination trench, 41 Termination trench, 41A Termination trench, 41B Termination trench, 42 Termination insulating film, 44 Termination electrode, 44A Termination electrode, 44B Termination electrode, 44C Termination electrode, 44D Termination electrode, 45 Termination electrode, 45A Termination electrode, 45B Termination electrode, 45C Termination electrode, 46 Field insulating film, 46A Field insulating film, 48 gate electrode, 50 field plate electrode, 52 channel stopper electrode, 54 field plate, 60 protective film, 100 semiconductor device, 144 termination electrode, 144A connector, 144B connector, 145 termination electrode.

Claims

1. A semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A first conductive drift layer, A first conductive channel stopper region is formed on the surface of the drift layer in the terminal region, having a higher impurity concentration than the drift layer, A first termination trench formed in the drift layer in the termination region, A plurality of termination electrodes are provided within the first termination trench, surrounded by a first termination insulating film, A channel stopper electrode provided on the upper surface of the drift layer, electrically connected to the channel stopper region and at least one of the terminal electrodes, A second conductive impurity region formed on the surface layer of the drift layer in the active region, A gate trench formed in the drift layer adjacent to the impurity region, Within the gate trench, a plurality of gate electrodes are provided surrounded by a gate insulating film, An interlayer insulating film is provided covering the gate trench, An upper electrode provided in a state that covers the upper surface and the interlayer insulating film of the drift layer, The system comprises at least a lower electrode provided on the lower surface of the drift layer in the active region, The plurality of terminal electrodes in the first terminal trench include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. Semiconductor equipment.

2. A semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A first conductive drift layer, A channel stopper region is formed on the surface of the drift layer in the terminal region, having a higher impurity concentration than the drift layer, A first termination trench formed in the drift layer in the termination region, A plurality of termination electrodes are provided within the first termination trench, surrounded by a first termination insulating film, A channel stopper electrode provided on the upper surface of the drift layer, electrically connected to the channel stopper region and at least one of the terminal electrodes, A second conductive impurity region formed on the surface layer of the drift layer in the active region, A gate trench formed in the drift layer adjacent to the impurity region, Within the gate trench, a plurality of gate electrodes are provided surrounded by a gate insulating film, An interlayer insulating film is provided covering the gate trench, An upper electrode provided in a state that covers the upper surface and the interlayer insulating film of the drift layer, The system comprises at least a lower electrode provided on the lower surface of the drift layer in the active region, The first termination trench is formed in the drift layer at a position closer to the active region than the outer end, which is the end of the channel stopper region opposite to the active region. The plurality of terminal electrodes in the first terminal trench include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. Semiconductor equipment.

3. A semiconductor device according to claim 1 or 2, At least a portion of the first termination electrode is provided so as to overlap with the second termination electrode in a plan view. At least a portion of the first gate electrode is provided so as to overlap with the second gate electrode in a plan view. Semiconductor equipment.

4. A semiconductor device according to claim 1 or 2, At least one of the termination electrodes connected to the channel stopper electrode further comprises a connecting portion extending to the upper surface of the drift layer. Semiconductor equipment.

5. The semiconductor device according to claim 4, The channel stopper region is located further from the active region than the connection portion, and does not overlap with the connection portion in a plan view. Semiconductor equipment.

6. A semiconductor device according to claim 1 or 2, Both the first termination electrode and the second termination electrode are electrically connected to the channel stopper electrode. Semiconductor equipment.

7. A semiconductor device according to claim 1 or 2, The second termination electrode is not electrically connected to the channel stopper electrode. Semiconductor equipment.

8. A semiconductor device according to claim 1 or 2, The terminal region further comprises a second terminal trench formed in the drift layer in the terminal region, The multiple termination electrodes are provided within the second termination trench, surrounded by the second termination insulating film. The channel stopper electrode is provided on the upper surface of the drift layer, electrically connected to the channel stopper region, at least one of the terminal electrodes in the first terminal trench, and at least one of the terminal electrodes in the second terminal trench. The plurality of terminal electrodes in the second terminal trench include a third terminal electrode and a fourth terminal electrode, The third termination electrode and the fourth termination electrode are provided spaced apart from each other within the second termination trench. Semiconductor equipment.

9. The semiconductor device according to claim 8, At least a portion of the third termination electrode is provided so as to overlap with the fourth termination electrode in a plan view. Semiconductor equipment.

10. The semiconductor device according to claim 8, The second terminal trench is formed at a position further from the active region than the first terminal trench. The second terminal trench is formed deeper than the first terminal trench. Semiconductor equipment.

11. A semiconductor device according to claim 1 or 2, The plurality of terminal electrodes in the first terminal trench further include a fifth terminal electrode, The fifth termination electrode is provided within the first termination trench, spaced apart from the first termination electrode and the second termination electrode. Semiconductor equipment.

12. A semiconductor device according to claim 1 or 2, The system further includes a protective film that covers the channel stopper electrode. Semiconductor equipment.

13. A semiconductor device according to claim 1 or 2, The present invention further comprises a first conductivity type charge storage region provided in the lower layer of the channel stopper region adjacent to the first termination trench, The impurity concentration in the charge storage region is higher than that of the drift layer and lower than that of the channel stopper region. Semiconductor equipment.

14. A method for manufacturing a semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A second impurity region of the conductivity type is formed on the surface of the first conductivity type drift layer in the active region. A first conductive channel stopper region having a higher impurity concentration than the drift layer is formed on the surface of the drift layer in the terminal region. A gate trench is formed in the drift layer at a position adjacent to the impurity region in the active region, and a first terminal trench is formed in the drift layer in the terminal region. A gate insulating film is formed in the gate trench, and a first terminal insulating film is formed in the first terminal trench. Multiple gate electrodes surrounded by the gate insulating film are formed within the gate trench, and multiple terminal electrodes surrounded by the first terminal insulating film are formed within the first terminal trench. An interlayer insulating film is formed to cover the gate trench, The channel stopper region and the channel stopper electrode electrically connected to at least one of the terminal electrodes are formed on the upper surface of the drift layer. An upper electrode is formed to cover the upper surface of the drift layer and the interlayer insulating film, A bottom electrode is formed on the lower surface of the drift layer in at least the active region. The plurality of terminal electrodes include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. A method for manufacturing a semiconductor device.

15. A method for manufacturing a semiconductor device comprising an active region and a terminal region that surrounds the active region in a plan view, A second impurity region of the conductivity type is formed on the surface of the first conductivity type drift layer in the active region. A channel stopper region with a higher impurity concentration than the drift layer is formed on the surface of the drift layer in the terminal region. A gate trench is formed in the drift layer at a position adjacent to the impurity region in the active region, and a first terminal trench is formed in the drift layer in the terminal region. A gate insulating film is formed in the gate trench, and a first terminal insulating film is formed in the first terminal trench. Multiple gate electrodes surrounded by the gate insulating film are formed within the gate trench, and multiple terminal electrodes surrounded by the first terminal insulating film are formed within the first terminal trench. An interlayer insulating film is formed to cover the gate trench, The channel stopper region and the channel stopper electrode electrically connected to at least one of the terminal electrodes are formed on the upper surface of the drift layer. An upper electrode is formed to cover the upper surface of the drift layer and the interlayer insulating film, A bottom electrode is formed on the lower surface of the drift layer in at least the active region. The first termination trench is formed in the drift layer at a position closer to the active region than the outer end, which is the end of the channel stopper region opposite to the active region. The plurality of terminal electrodes include a first terminal electrode and a second terminal electrode, The plurality of gate electrodes include a first gate electrode and a second gate electrode, The first termination electrode and the second termination electrode are provided spaced apart from each other within the first termination trench. The first gate electrode and the second gate electrode are provided spaced apart from each other within the gate trench. A method for manufacturing a semiconductor device.

16. A method for manufacturing a semiconductor device according to claim 15, Forming a plurality of the termination electrodes means that at least one of the termination electrodes connected to the channel stopper electrode has a connecting portion that extends to the upper surface of the drift layer, The channel stopper region is formed at a location that is further from the active region than the connection portion and does not overlap with the connection portion in a plan view. After forming multiple terminal electrodes, the regions with the same conductivity type in the active region and the channel stopper region are activated simultaneously. A method for manufacturing a semiconductor device.

Images