Semiconductor devices and power converters

Abstract

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2023-85505 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a frame wiring formed of aluminum and located outside in a plan view than a termination structure that secures the breakdown voltage of an active cell. Further, in the semiconductor device described in Patent Document 1, an insulating film does not reach the outer peripheral edge of a silicon carbide substrate in a plan view, and a passivation film is in contact with the silicon carbide substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device described in Patent Document 1, there is a concern about a decrease in the HBT (Thermal Humidity Bias) withstand voltage due to reliability, more specifically, silicon carbide products generated from aluminum contained in the frame wiring and silicon carbide contained in the silicon carbide substrate. The present disclosure provides a semiconductor device with improved HBT withstand voltage.

Means for Solving the Problems

[0005] The semiconductor device of this disclosure comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface to the first main surface. In a plan view, the second main surface has a cell region and a peripheral region located between the cell region and the outer edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view. The insulating film is formed on the second main surface so as to cover the field oxide film. The wiring layer is formed on the insulating film so that it is located inside the termination structure in a plan view. [Effects of the Invention]

[0006] The semiconductor device described herein improves HBT withstand capability. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of the semiconductor device 100. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 1. [Figure 4] This is a manufacturing process diagram for semiconductor device 100. [Figure 5A] This is a first cross-sectional view illustrating the impurity diffusion region formation process S2. [Figure 5B] This is a second cross-sectional view illustrating the impurity diffusion region formation process S2. [Figure 6] This is a cross-sectional view illustrating the field oxide film formation process S3. [Figure 7] This is a cross-sectional view illustrating the gate insulating film formation process S4. [Figure 8A] It is a first cross-sectional view for explaining the gate electrode formation step S5. [Figure 8B] It is a second cross-sectional view for explaining the gate electrode formation step S5. [Figure 9A] It is a first cross-sectional view for explaining the insulating film formation step S6. [Figure 9B] It is a second cross-sectional view for explaining the insulating film formation step S6. [Figure 10A] It is a first cross-sectional view for explaining the wiring layer formation step S7. [Figure 10B] It is a second cross-sectional view for explaining the wiring layer formation step S7. [Figure 11] It is a cross-sectional view for explaining the passivation film formation step S8. [Figure 12A] It is a first cross-sectional view for explaining the impurity diffusion region formation step S9. [Figure 12B] It is a second cross-sectional view for explaining the impurity diffusion region formation step S9. [Figure 13A] It is a first cross-sectional view for explaining the drain electrode formation step S10. [Figure 13B] It is a second cross-sectional view for explaining the drain electrode formation step S10. [Figure 14] It is a cross-sectional view of the semiconductor device 100A. [Figure 15] It is a table showing the results of the THB endurance test. [Figure 16] It is a cross-sectional view of the semiconductor device 100 according to Modification 1. [Figure 17A] It is a cross-sectional view of the semiconductor device 100 according to Modification 2. [Figure 17B] It is a cross-sectional view of the semiconductor device 100 according to Modification 3. [Figure 18] It is a cross-sectional view of the semiconductor device 100 according to Modification 4. [Figure 19] It is a cross-sectional view of the semiconductor device 100 according to Modification 5. [Figure 20] It is an enlarged plan view of the semiconductor device 100 according to Modification 6. <000009�>It is an enlarged plan view of the semiconductor device 100 according to Modification 7. [Figure 22] It is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 2 is applied.

Embodiments for Carrying Out the Invention

[0008] Details of embodiments of the present disclosure will be described while referring to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and overlapping descriptions will not be repeated.

[0009] Embodiment 1. A semiconductor device according to Embodiment 1 will be described. The semiconductor device according to Embodiment 1 is referred to as semiconductor device 100.

[0010] (Configuration of Semiconductor Device 100) The configuration of semiconductor device 100 will be described below.

[0011] FIG. 1 is a plan view of semiconductor device 100. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. As shown in FIGS. 1 to 3, semiconductor device 100 includes a silicon carbide substrate 10, a field oxide film 20, a gate insulating film 30, a gate electrode 40, an insulating film 50, a wiring layer 60, a passivation film 70, a protective film 80, and a drain electrode 90.

[0012] Silicon carbide substrate 10 is formed of single crystal silicon carbide. Silicon carbide substrate 10 has a main surface 10a and a main surface 10b. Main surface 10a and main surface 10b form end faces in the thickness direction of silicon carbide substrate 10. Main surface 10b is the opposite surface of main surface 10a. Main surface 10b has a cell region 10ba and an outer peripheral region 10bb in plan view. Outer peripheral region 10bb is a region located between cell region 10ba and the outer peripheral edge of main surface 10b. <00001X19> The silicon carbide substrate 10 has a base layer 11, an epitaxial layer 12, and a buffer layer 13. The lower surface of the base layer 11 is the main surface 10a. The upper surface of the epitaxial layer 12 is the main surface 10b. The epitaxial layer 12 is formed on the base layer 11 with the buffer layer 13 interposed between them. The conductivity type of the base layer 11, the conductivity type of the epitaxial layer 12, and the conductivity type of the buffer layer 13 is a first conductivity type. The first conductivity type is, for example, n-type.

[0014] The silicon carbide substrate 10 has a drain region 14, a source region 15, and a body region 16. The drain region 14 is formed on the main surface 10a within the silicon carbide substrate 10 (underlayer 11). The source region 15 is formed on the main surface 10b located in the cell region 10ba within the silicon carbide substrate 10 (epitaxial layer 12). The body region 16 is formed on the main surface 10b located in the cell region 10ba within the silicon carbide substrate 10 (epitaxial layer 12) so as to surround the source region 15. The conductivity type of the drain region 14 and the source region 15 is a first conductivity type. The conductivity type of the body region 16 is a second conductivity type. The second conductivity type is, for example, p-type.

[0015] The silicon carbide substrate 10 further has a back gate region 17. The back gate region 17 is formed on the main surface 10b located in the cell region 10ba within the silicon carbide substrate 10 (epitaxial layer 12). In a plan view, the back gate region 17 is located on the outer edge of the cell region 10ba. The back gate region 17 is surrounded by the body region 16. The conductivity type of the back gate region 17 is second conductivity type.

[0016] The silicon carbide substrate 10 further includes a plurality of guard rings 18 and a channel stopper 19. The guard rings 18 are formed on the main surface 10b located in the outer peripheral region 10bb within the silicon carbide substrate 10 (epitaxial layer 12). In a plan view, the plurality of guard rings 18 are spaced apart along the direction from the inner peripheral edge of the outer peripheral region 10bb toward the outer peripheral edge of the outer peripheral region 10bb (the outer peripheral edge of the main surface 10b). In a plan view, the guard rings 18 are formed in an annular shape. The conductivity type of the guard rings 18 is second conductivity type. The plurality of guard rings 18 form a termination structure for maintaining the dielectric breakdown voltage of the semiconductor device 100. The channel stopper 19 is formed on the main surface 10b located in the outer peripheral region 10bb within the silicon carbide substrate 10 (epitaxial layer 12). In a plan view, the channel stopper 19 is located outside the above-mentioned termination structure (the plurality of guard rings 18). The conductivity type of the channel stopper 19 is the first conductivity type. The channel stopper 19 is formed in an annular shape in plan view.

[0017] The field oxide film 20 is formed of, for example, a silicon oxide that does not contain boron and phosphorus. The field oxide film 20 is formed on the main surface 10b. The inner and outer edges of the field oxide film 20 are located on the cell region 10ba and the outer region 10bb, respectively. That is, the field oxide film 20 crosses the boundary between the cell region 10ba and the outer region 10bb. In a plan view, the field oxide film 20 overlaps with the above-mentioned termination structure (multiple guard rings 18). In a plan view, the field oxide film 20 partially overlaps with the channel stopper 19. An opening 20a is formed in the field oxide film 20. The opening 20a penetrates the field oxide film 20. In a plan view, the opening 20a overlaps with the back gate region 17.

[0018] The gate insulating film 30 is made of, for example, silicon oxide. The gate insulating film 30 is formed on the main surface 10b located between two adjacent source regions 15. The gate electrode 40 is made of, for example, polycrystalline silicon. The gate electrode 40 is formed on the gate insulating film 30. The gate electrode 40 is also formed on the field oxide film 20. The drain region 14 and the source region 15 constitute the drain region and source region of the vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), respectively. The body region 16 constitutes the body region of the vertical MOSFET. The epitaxial layer 12 constitutes the drift region of the vertical MOSFET.

[0019] The insulating film 50 is formed on the main surface 10b so as to cover the field oxide film 20, the gate insulating film 30, and the gate electrode 40. In a plan view, the insulating film 50 extends to the outer edge of the main surface 10b and covers the remainder of the channel stopper 19 that is not covered by the field oxide film 20. The insulating film 50 may have multiple layers. In the example shown in Figures 1 to 3, the insulating film 50 has a first layer 51 and a second layer 52 formed on the first layer 51. The first layer 51 is made of, for example, BPSG (Boron Phosphorous Silicate Glass). The second layer 52 is made of, for example, a silicon oxide that does not contain boron and phosphorus. In other words, the uppermost layer of the multiple layers of the insulating film 50 is made of a material that does not contain boron and phosphorus.

[0020] Contact holes 50a, 50b, and 50c are formed in the insulating film 50. Contact holes 50a, 50b, and 50c penetrate the insulating film 50. In a plan view, contact hole 50a overlaps with the source region 15. The source region 15 is exposed through contact hole 50a. In a plan view, contact hole 50b overlaps with the opening 20a and the back gate region 17. The back gate region 17 is exposed through contact hole 50b. In a plan view, contact hole 50c overlaps with the gate electrode 40 located on the field oxide film 20. The gate electrode 40 located on the field oxide film 20 is exposed through contact hole 50b.

[0021] The wiring layer 60 is formed of, for example, aluminum or an aluminum alloy. The wiring layer 60 is formed on an insulating film 50 located on the cell region 10ba. In other words, the wiring layer 60 does not have any portion formed inside the outer peripheral region 10bb in a plan view. The wiring layer 60 has a gate wiring 61, a source electrode 62, and a gate pad 63. The gate wiring 61 is located on the outer peripheral edge of the cell region 10ba in a plan view. The source electrode 62 is surrounded by the gate wiring 61 in a plan view. The gate pad 63 is surrounded by the gate wiring 61 and the source electrode 62 in a plan view and is connected to the gate wiring 61.

[0022] Although not shown in the diagram, barrier metals are formed between the wiring layer 60 and the insulating film 50, between the wiring layer 60 and the silicon carbide substrate 10 (source region 15, back gate region 17), and between the wiring layer 60 and the gate electrode 40. The barrier metals are, for example, titanium nitride films, titanium films, or laminates thereof.

[0023] The gate wiring 61 is also formed within the contact hole 50c. This electrically connects the gate wiring 61 to the gate electrode 40. The source electrode 62 is also formed within the contact hole 50a and the contact hole 50b. This electrically connects the source electrode 62 to the source region 15 and the back gate region 17.

[0024] The passivation film 70 is made of, for example, silicon nitride. The passivation film 70 is formed on the insulating film 50 so as to cover the wiring layer 60. In a plan view, the outer edge of the passivation film 70 is separated from the outer edge of the main surface 10b. That is, the insulating film 50 located at the outer edge is exposed from the passivation film 70. The passivation film 70 has openings for exposing the source electrode 62 and openings for exposing the gate pad 63.

[0025] The protective film 80 is made of, for example, polyimide. The protective film 80 is formed on the insulating film 50 with a passivation film 70 interposed between them so as to cover the wiring layer 60. In a plan view, the outer edge of the protective film 80 is located inward from the outer edge of the passivation film 70. The protective film 80 does not overlap with any steps in the insulating film 50. The protective film 80 has openings for exposing the source electrode 62 and for exposing the gate pad 63. The drain electrode 90 is made of, for example, titanium or titanium nitride. The drain electrode 90 is formed on the main surface 10a. The drain electrode 90 is electrically connected to the drain region 14.

[0026] (Method of manufacturing semiconductor device 100) The manufacturing method for the semiconductor device 100 is described below.

[0027] Figure 4 is a diagram of the manufacturing process for the semiconductor device 100. As shown in Figure 4, the manufacturing method for the semiconductor device 100 includes a preparation step S1, an impurity diffusion region formation step S2, a field oxide film formation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, an insulating film formation step S6, a wiring layer formation step S7, a passivation film formation step S8, an impurity diffusion region formation step S9, a drain electrode formation step S10, a protective film formation step S11, and a fractionation step S12.

[0028] In preparation step S1, a silicon carbide substrate 10 is prepared. Figure 5A is a first cross-sectional view illustrating the impurity diffusion region formation step S2. Figure 5B is a second cross-sectional view illustrating the impurity diffusion region formation step S2. As shown in Figures 5A and 5B, in the impurity diffusion region formation step S2, a source region 15, a body region 16, a back gate region 17, a guard ring 18, and a channel stopper 19 are formed by ion implantation, for example, from the main surface 10b side.

[0029] Figure 6 is a cross-sectional view illustrating the field oxide film formation process S3. As shown in Figure 6, a field oxide film 20 is formed in the field oxide film formation process S3. In the field oxide film formation process S3, firstly, the constituent material of the field oxide film 20 is deposited on the main surface 10b by, for example, the TEOS (Tetra EthOxy Silane)-CVD (Chemical Vapor Deposition) method. Secondly, a resist pattern is formed on the constituent material of the field oxide film 20. The resist pattern is formed by coating a photoresist and then patterning the photoresist using a photolithography method. Thirdly, the constituent material of the field oxide film 20 is patterned by dry etching through the openings in the resist pattern, thereby forming the field oxide film 20.

[0030] Figure 7 is a cross-sectional view illustrating the gate insulating film formation process S4. As shown in Figure 7, the gate insulating film 30 is formed by, for example, thermal oxidation of the main surface 10b. Figure 8A is a first cross-sectional view illustrating the gate electrode formation process S5. Figure 8B is a second cross-sectional view illustrating the gate electrode formation process S5. As shown in Figures 8A and 8B, the gate electrode 40 is formed in the gate electrode formation process S5. In the gate electrode formation process S5, firstly, the constituent materials of the gate electrode 40 are formed on the field oxide film 20 and the gate insulating film 30 by, for example, a CVD method. Secondly, a resist pattern is formed on the constituent materials of the gate electrode 40. Thirdly, the constituent materials of the gate electrode 40 are patterned by dry etching of the constituent materials of the gate electrode 40 through openings in the resist pattern, thereby forming the gate electrode 40.

[0031] Figure 9A is a first cross-sectional view illustrating the insulating film formation process S6. Figure 9B is a second cross-sectional view illustrating the insulating film formation process S6. As shown in Figures 9A and 9B, an insulating film 50 is formed in the insulating film formation process S6. In the insulating film formation process S6, firstly, a first layer 51 is formed, for example by the CVD method. Secondly, the constituent material (BPSG) of the first layer 51 is flowed by heat treatment, and the first layer 51 is planarized. Thirdly, a second layer 52 is formed, for example by the TEOS-CVD method.

[0032] Figure 10A is a first cross-sectional view illustrating the wiring layer formation process S7. Figure 10B is a second cross-sectional view illustrating the wiring layer formation process S7. As shown in Figures 10A and 10B, a wiring layer 60 is formed in the wiring layer formation process S7. In the wiring layer formation process S7, firstly, a resist pattern is formed on the insulating film 50, and secondly, dry etching is performed on the insulating film 50 through the openings in the resist pattern, thereby forming contact holes 50a, 50b, and 50c.

[0033] Thirdly, a barrier metal is formed on the insulating film 50, on the inner wall surface of the contact hole 50a, on the inner wall surface of the contact hole 50b, on the inner wall surface of the contact hole 50c, on the source region 15 exposed from the contact hole 50a, on the back gate region 17 exposed from the contact hole 50b, and on the gate electrode 40 exposed from the contact hole 50c, for example by sputtering. Thirdly, the constituent material of the wiring layer 60 is formed on the barrier metal, for example by sputtering. Fourthly, a resist pattern is formed on the constituent material of the wiring layer 60. Fifthly, the constituent material of the wiring layer 60 and the barrier metal are patterned by dry etching of the constituent material of the wiring layer 60 through the openings in the resist pattern, thereby forming the wiring layer 60.

[0034] Figure 11 is a cross-sectional view illustrating the passivation film formation process S8. As shown in Figure 11, in the passivation film formation process S8, a passivation film 70 is formed. In the passivation film formation process S8, firstly, the constituent material of the passivation film 70 is formed, for example by a CVD method. Secondly, a resist pattern is formed on the constituent material of the passivation film 70. Thirdly, the constituent material of the passivation film 70 is patterned by dry etching through the openings in the resist pattern, thereby forming the passivation film 70.

[0035] Figure 12A is a first cross-sectional view illustrating the impurity diffusion region formation process S9. Figure 12B is a second cross-sectional view illustrating the impurity diffusion region formation process S9. As shown in Figures 12A and 12B, in the impurity diffusion region formation process S9, a drain region 14 is formed by ion implantation, for example, from the main surface 10a side. Figure 13A is a first cross-sectional view illustrating the drain electrode formation process S10. Figure 13B is a second cross-sectional view illustrating the drain electrode formation process S10. As shown in Figures 13A and 13B, a drain electrode 90 is formed on the main surface 10a, for example, by sputtering. In the protective film formation process S11, the protective film 80 is formed by coating the constituent materials of the protective film 80 onto the passivation film 70 and curing the constituent materials of the protective film 80. In the dicing process S12, the silicon carbide substrate 10 and the insulating film 50 are cut along the dicing line, thereby dicing the wafer that has gone through the processes up to the protective film formation process S11 into a plurality of semiconductor devices 100. Based on the above, a semiconductor device 100 with the structure shown in Figures 1 to 3 can be obtained.

[0036] (Effects of semiconductor device 100) The effects of semiconductor device 100 will be explained below in comparison with a semiconductor device related to the comparative example. The semiconductor device related to the comparative example will be referred to as semiconductor device 100A.

[0037] Figure 14 is a cross-sectional view of the semiconductor device 100A. Note that Figure 14 shows a cross-section at the position corresponding to line II-II in Figure 1. As shown in Figure 14, in the semiconductor device 100A, the outer edge of the insulating film 50 is separated from the outer edge of the main surface 10b in a plan view. That is, in the semiconductor device 100A, the outer edge of the main surface 10b is exposed from the insulating film 50. In the semiconductor device 100A, the wiring layer 60 has a portion that is located outside the termination structure (multiple guard rings 18) in a plan view. More specifically, in the semiconductor device 100A, the wiring layer 60 further has frame wiring 64. The frame wiring 64 is formed spanning the outer edge of the main surface 10b exposed from the insulating film 50 and the outer edge of the insulating film 50.

[0038] In semiconductor device 100A, the frame wiring 64 is susceptible to corrosion due to reaction with moisture. In particular, because semiconductor device 100A uses a silicon carbide substrate 10, an electric field is easily applied to the outer edge of the semiconductor device 100A, and this electric field accelerates the corrosion of the frame wiring 64. As a result, silicon carbide products may be generated from the silicon carbide contained in the silicon carbide substrate 10 and the aluminum contained in the wiring layer 60 (frame wiring 64), and these products may reduce the THB withstand capability. Note that silicon carbide products are corrosion products derived from silicon carbide or silicon oxides produced when silicon carbide corrodes.

[0039] On the other hand, in the semiconductor device 100, the wiring layer 60 is located inside the termination structure in a plan view and does not have a frame wiring 64. Therefore, even if a strong electric field is applied to the outer edge of the semiconductor device 100, corrosion of the wiring layer 60 and the formation of silicon carbide products are unlikely to occur, and the THB withstand capability of the semiconductor device 100 is ensured.

[0040] Figure 15 is a table showing the results of the THB withstand test. Sample 1 and Sample 2 were prepared for the THB withstand test. Sample 1 and Sample 2 correspond to semiconductor device 100 and semiconductor device 100A, respectively. That is, Sample 2 has frame wiring 64, while Sample 1 does not. Both Sample 1 and Sample 2 have a passivation film 70. As shown in Figure 15, dielectric breakdown occurred in 6 out of 10 samples in Sample 2, while dielectric breakdown occurred in only 2 out of 10 samples in Sample 1. From this, it was found that the THB withstand capability is improved by not having a portion of the wiring layer 60 that is located outside the termination structure (multiple guard rings 18) in a plan view (i.e., not having frame wiring 64).

[0041] In the semiconductor device 100, the insulating film 50 is formed to reach the outer edge of the main surface 10b. Therefore, when the semiconductor device 100 is sealed with molding resin, the molding resin contacts the insulating film 50 rather than the silicon carbide substrate 10. As a result, the semiconductor device 100 can improve the adhesion between the molding resin and the semiconductor device 100.

[0042] Materials containing boron and phosphorus are highly hygroscopic. However, in the semiconductor device 100, the second layer 52 (the uppermost of the multiple layers of the insulating film 50) is made of a material that does not contain boron or phosphorus. As a result, the insulating film 50 of the semiconductor device 100 is less likely to absorb moisture, improving moisture resistance, waterproofing performance and adhesion to the molding resin, and suppressing corrosion of the silicon carbide substrate 10.

[0043] (Variation 1) Figure 16 is a cross-sectional view of the semiconductor device 100 according to Modification 1. Note that Figure 16 shows a cross-section at the position corresponding to line II-II in Figure 1. In plan view, the outer edge of the silicon carbide substrate 10 forms part of the dicing line (see dicing process S12). The insulating film 50 does not necessarily have to cover the main surface 10b located on the dicing line. In other words, the outer edge of the insulating film 50 may be located inside the outer edge of the main surface 10b. If the insulating film 50 is also formed on the main surface 10b located on the dicing line, cracks may propagate in the insulating film 50 during dicing. Therefore, by not covering the main surface 10b located on the dicing line with the insulating film 50, the propagation of cracks in the insulating film 50 as described above can be suppressed, and consequently, the waterproof performance of the insulating film 50 can be maintained.

[0044] (Variation 2 and Variation 3) Figure 17A is a cross-sectional view of the semiconductor device 100 according to Modification 2. Figure 17A shows a cross-section at the position corresponding to II-II in Figure 1. As shown in Figure 17A, the outer edge of the protective film 80 may be outside the outer edge of the passivation film 70 in a plan view. In this case, by ensuring that the outer edge of the protective film 80 does not overlap with the step of the insulating film 50, the adhesion between the protective film 80 and the insulating film 50 is improved.

[0045] Figure 17B is a cross-sectional view of the semiconductor device 100 according to Modification 3. Figure 17B shows a cross-section at the position corresponding to II-II in Figure 1. As shown in Figure 17B, the insulating film 50 is composed of a single layer, and this single layer may be made of a material that does not contain boron and phosphorus (silicon oxide).

[0046] (Modification 4) Figure 18 is a cross-sectional view of the semiconductor device 100 according to Modification 4. Note that Figure 18 shows a cross-section at the position corresponding to II-II in Figure 1. As shown in Figure 18, the field oxide film 20 may extend such that, in a plan view, the outer edge of the field oxide film 20 reaches the outer edge of the main surface 10b. The field oxide film 20 may be thicker than any of the multiple layers of the insulating film 50. In this case, since the thickest field oxide film 20 reaches the outer edge of the main surface 10b, moisture is less likely to come into contact with the silicon carbide substrate 10 at the position where a strong electric field is applied during the operation of the semiconductor device 100. In addition, in this case, even if corrosion occurs, the corrosion will stagnate at the tip of the thickest field oxide film 20, thus suppressing the progression of corrosion to the active cell.

[0047] Furthermore, as the field oxide film 20 extends to the outer edge of the main surface 10b, the insulating film 50 and the passivation film 70 are formed flatly and without steps on the outer peripheral region 10bb. Therefore, in this case, the adhesion of the protective film 80 and the adhesion of the molding resin can be improved.

[0048] (Variation 5) Figure 19 is a cross-sectional view of the semiconductor device 100 according to Modification 5. Note that Figure 19 shows a cross-section at the position corresponding to II-II in Figure 1. As shown in Figure 19, the channel stopper 19 does not have to be formed to reach the outer edge of the main surface 10b in a plan view. That is, the channel stopper 19 may be covered with the field oxide film 20. In this case, there is no interface between the mold resin and the channel stopper 19. As a result, no electron transfer occurs at the interface between the mold resin and the channel stopper 19, and peeling of the mold resin caused by chemical reactions at the interface can be suppressed.

[0049] (Variations 6 and 7) Figure 20 is an enlarged plan view of the semiconductor device 100 according to Modification 6. Note that Figure 20 shows an enlarged plan view at the position corresponding to XX-XX in Figure 1. As shown in Figure 20, in plan view, the corner of the outer edge of the protective film 80 may have multiple surfaces. Two adjacent surfaces forming the corner of the outer edge of the protective film 80 form an angle greater than 90°. In the example shown in Figure 20, the corner of the outer edge of the protective film 80 has surfaces 80a, 80b, and 80c. Surface 80c is connected to surface 80a at one end and to surface 80b at the other end. The angles formed by surface 80a and surface 80c, and the angles formed by surface 80b and surface 80c are greater than 90°.

[0050] Figure 21 is an enlarged plan view of the semiconductor device 100 according to Modification 7. Figure 21 shows an enlarged plan view at the position corresponding to X in Figure 1. As shown in Figure 21, in plan view, the corners of the outer edge of the protective film 80 may be arc-shaped. Cracks may occur at the corners of the outer edge of the protective film 80 due to thermal stress from the molding resin. In these cases, chamfering the corners of the protective film 80 or making the corners of the protective film 80 arc-shaped alleviates stress concentration at the corners of the protective film 80, thereby preventing the occurrence of the cracks and improving water resistance.

[0051] (Variation 8) In the above description, a case in which a vertical MOSFET is formed as a semiconductor element on the semiconductor device 100 was explained as an example. However, the semiconductor device 100 may also have other power semiconductor elements such as a Schottky barrier diode or an IGBT (Insulated Gate Bipolar Transistor) formed on it.

[0052] Embodiment 2. This embodiment applies the semiconductor device according to Embodiment 1 described above to a power converter. Although this disclosure is not limited to a specific power converter, Embodiment 2 will be described below, in which the disclosure is applied to a three-phase inverter.

[0053] Figure 22 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 2 is applied.

[0054] The power conversion system shown in Figure 22 consists of a power converter 200, a power supply 300, and a load 310. The power supply 300 is a DC power supply that supplies DC power to the power converter 200. The power supply 300 can be made up of various components, such as a DC grid, a solar cell, or a battery, or it may be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 300 may be made up of a DC / DC converter that converts the DC power output from the DC grid into a predetermined power.

[0055] The power converter 200 is a three-phase inverter connected between the power supply 300 and the load 310. It converts the DC power supplied from the power supply 300 into AC power and supplies the AC power to the load 310. As shown in Figure 22, the power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0056] Load 310 is a three-phase motor driven by AC power supplied from power converter 200. Note that load 310 is not limited to a specific application; it is a motor mounted in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0057] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 300 into AC power and supplies it to the load 310. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to Embodiment 1 is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. At least one of each switching element and each freewheeling diode of the main conversion circuit 201 is a switching element or freewheeling diode that is part of a semiconductor device 202 corresponding to any of the semiconductor devices of Embodiment 1 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 310.

[0058] Furthermore, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built into the semiconductor device 202, or it may be configured to be a separate drive circuit from the semiconductor device 202. The drive circuit generates a drive signal to drive the switching elements of the main conversion circuit 201 and supplies it to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs a drive signal to turn on the switching element and a drive signal to turn off the switching element to the control electrodes of each switching element. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching element, and when the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching element.

[0059] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 310. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 310. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit of the main converter circuit 201 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0060] In the power conversion device according to Embodiment 2, the semiconductor device (semiconductor device 100) according to Embodiment 1 is used as the semiconductor device 202 constituting the main conversion circuit 201, thereby ensuring the HBT withstand capability of the semiconductor device 202.

[0061] Embodiment 1 describes an example of applying the present disclosure to a two-level three-phase inverter, but the present disclosure is not limited to this and can be applied to various power conversion devices. Although Embodiment 1 uses a two-level power conversion device, it may also be a three-level or multi-level power conversion device, and the present disclosure may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter when supplying power to a DC load, etc.

[0062] Furthermore, the power conversion device to which this disclosure is applied is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0063] [Note] The various aspects of this disclosure are summarized in the appendix.

[0064] <Note 1> Silicon carbide substrate and Field oxide film and insulating film and It comprises a wiring layer, The silicon carbide substrate has a first main surface and a second main surface which is the surface opposite to the first main surface. The second principal surface, in plan view, has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second principal surface. The silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region within the silicon carbide substrate. The channel stopper is located outside the terminal structure in a plan view. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper are the first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type, The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the terminal structure in a plan view and at least partially overlaps the channel stopper in a plan view. The insulating film is formed on the second main surface so as to cover the field oxide film. A semiconductor device wherein the wiring layer is formed on the insulating film such that, in a plan view, it is located inside the termination structure.

[0065] <Note 2> The semiconductor device according to Appendix 1, wherein the outer edge of the insulating film is located inward from the outer edge of the second main surface in a plan view.

[0066] <Note 3> The semiconductor device according to Appendix 1 or Appendix 2, wherein the insulating film is formed of a material that does not contain boron and phosphorus.

[0067] <Note 4> The insulating film has multiple layers stacked together, The insulating film extends to the outer edge of the second main surface in a plan view, The semiconductor device according to Appendix 1 or Appendix 2, wherein the uppermost layer of the plurality of layers is made of a material that does not contain boron and phosphorus.

[0068] <Note 5> With an additional protective film, The semiconductor device according to any one of Appendix 1 to Appendix 4, wherein the protective film is formed on the insulating film such that, in a plan view, the outer edge of the protective film does not overlap with the step of the insulating film.

[0069] <Note 6> The insulating film has multiple layers stacked together, The field oxide film is thicker than any of the plurality of layers. The semiconductor device according to Appendix 1, wherein the field oxide film extends to the outer edge of the second main surface in a plan view.

[0070] <Note 7> The semiconductor device according to Appendix 1, wherein the field oxide film is formed on the second main surface so as to cover the channel stopper.

[0071] <Note 8> With an additional protective film, The protective film is formed on the insulating film, In a plan view, the corners of the outer edge of the protective film have multiple surfaces. The semiconductor device according to any one of the appendices 1 to 7, wherein the angle between two adjacent faces among the aforementioned multiple faces is greater than 90°.

[0072] <Note 9> With an additional protective film, The protective film is formed on the insulating film, In a plan view, the corners of the outer edge of the protective film are arc-shaped, as described in any one of Appendix 1 to Appendix 7, the semiconductor device.

[0073] <Note 10> A main conversion circuit having the semiconductor device described in any one of the appendices 1 to 9, and converting and outputting the input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A power conversion device comprising a control circuit that outputs a control signal to the drive circuit to control the drive circuit.

[0074] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0075] 10 Silicon carbide substrate, 10a, 10b Main surface, 10ba Cell region, 10bb Outer periphery region, 11 Underlayer, 12 Epitaxial layer, 13 Buffer layer, 14 Drain region, 15 Source region, 16 Body region, 17 Back gate region, 18 Guard ring, 19 Channel stopper, 20 Field oxide film, 20a Aperture, 30 Gate insulating film, 40 Gate electrode, 50 Insulating film, 50a, 50b, 50c Contact holes, 51 First layer, 52 Second layer, 60 Wiring layer, 61 Gate wiring, 62 Source electrode, 63 Gate pad, 64 Frame wiring, 70 Passivation film, 80 Protective film, 80a, 80b, 80c Surface, 90 Drain electrode, 100, 100A, 202 Semiconductor device, 200 Power converter, 201 Main conversion circuit, 203 control circuit, 300 power supply, 310 load, S1 preparation process, S2 impurity diffusion region formation process, S3 field oxide film formation process, S4 gate insulating film formation process, S5 gate electrode formation process, S6 insulating film formation process, S7 wiring layer formation process, S8 passivation film formation process, S9 impurity diffusion region formation process, S10 drain electrode formation process, S11 protective film formation process, S12 piece formation process.

Claims

1. Silicon carbide substrate and Field oxide film and insulating film and It comprises a wiring layer, The silicon carbide substrate has a first main surface and a second main surface which is the surface opposite to the first main surface. The second principal surface, in plan view, has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second principal surface. The silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region within the silicon carbide substrate. The channel stopper is located outside the terminal structure in a plan view. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper have a first conductivity type. The termination structure is a second conductivity type opposite to the first conductivity type, The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the terminal structure in a plan view and at least partially overlaps the channel stopper in a plan view. The insulating film is formed on the second main surface so as to cover the field oxide film. A semiconductor device wherein the wiring layer is formed on the insulating film such that, in a plan view, it is located inside the termination structure.

2. The semiconductor device according to claim 1, wherein the outer edge of the insulating film is located inward from the outer edge of the second main surface in a plan view.

3. The semiconductor device according to claim 1, wherein the insulating film is formed of a material that does not contain boron and phosphorus.

4. The insulating film has multiple layers stacked together, The insulating film extends to the outer edge of the second main surface in a plan view, The semiconductor device according to claim 1, wherein the uppermost layer of the plurality of layers is made of a material that does not contain boron and phosphorus.

5. With an additional protective film, The semiconductor device according to claim 1, wherein the protective film is formed on the insulating film such that, in a plan view, the outer edge of the protective film does not overlap with the step of the insulating film.

6. The insulating film has multiple layers stacked together, The field oxide film is thicker than any of the plurality of layers. The semiconductor device according to claim 1, wherein the field oxide film extends to the outer edge of the second main surface in a plan view.

7. The semiconductor device according to claim 1, wherein the field oxide film is formed on the second main surface so as to cover the channel stopper.

8. With an additional protective film, The protective film is formed on the insulating film, In a plan view, the corners of the outer edge of the protective film have multiple surfaces. The semiconductor device according to claim 1, wherein the angle between two adjacent faces among the plurality of faces is greater than 90°.

9. With an additional protective film, The protective film is formed on the insulating film, The semiconductor device according to claim 1, wherein, in a plan view, the corners of the outer edge of the protective film are arc-shaped.

10. A main conversion circuit having the semiconductor device described in any one of claims 1 to 9, and converting and outputting the input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A power conversion device comprising a control circuit that outputs a control signal to the drive circuit to control the drive circuit.

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