Display drivers and display devices

Abstract

To provide display drivers and other components that can prevent the occurrence of excessive current and deterioration of judgment accuracy. [Solution] The display driver 20 includes a driver circuit 30 that outputs a drive signal SD to the display electrode EL of the electro-optic panel 200, a driver control circuit 60 that controls the driver circuit 30, and a test circuit 40. The test circuit 40 includes a comparison circuit 50 that compares the voltage of the drive signal SD with a reference voltage VR, and a determination circuit 56 that determines an abnormality based on the expected value EV corresponding to the level of the drive signal SD and the comparison result of the comparison circuit 50. In the determination mode, the driver control circuit 60 controls the gate of the drive transistor TR of the driver circuit 30 so that the drive transistor TR outputs the drive signal SD with a constant current.

Description

Technical Field

[0005]

[0001] The present invention relates to a display driver, a display device, and the like.

Background Art

[0002] Patent Document 1 discloses a liquid crystal driver that supplies a drive signal to a segment electrode based on a segment signal and detects a drive abnormality of the segment electrode by comparing a monitor signal input from the segment electrode with the segment signal.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a short circuit occurs in a signal line in an electro-optical panel such as a liquid crystal panel driven by such a liquid crystal driver, depending on the resistance value of the shorted path, there may be problems such as an excessive current flowing through the path or a change in the voltage of the monitor signal of the drive signal, resulting in deterioration of the determination accuracy.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a display driver including a driver circuit that outputs a drive signal to a display electrode of an electro-optical panel, a driver control circuit that controls the driver circuit, and an inspection circuit. The inspection circuit includes a comparison circuit that compares the voltage of the drive signal with a reference voltage, and a determination circuit that determines an abnormality based on an expected value corresponding to the level of the drive signal and the comparison result of the comparison circuit. The driver control circuit controls the gate of the drive transistor so that the drive transistor of the driver circuit outputs the drive signal at a constant current in a determination mode.

[0006] Other aspects of this disclosure relate to a display device including the display driver described above and the electro-optical panel. [Brief explanation of the drawing]

[0007] [Figure 1] An example configuration of the display device according to this embodiment. [Figure 2] Detailed configuration example of a display device. [Figure 3] Examples of segment electrode placement and segment signal line wiring. [Figure 4] Examples of common electrode placement and common signal line wiring. [Figure 5] Detailed configuration examples of test circuits and driver circuits. [Figure 6] Detailed configuration examples of test circuits and driver circuits. [Figure 7] Diagram illustrating the configuration and operation of the driver control circuit. [Figure 8] Example configuration of a comparative example. [Figure 9] Diagram illustrating the configuration and operation of the driver control circuit. [Figure 10] Diagram illustrating the configuration and operation of the driver control circuit. [Figure 11] An example configuration of a current setting circuit. [Figure 12] An example configuration of a current setting circuit. [Figure 13] This diagram shows the relationship between the short-circuit resistance value and the monitor signal voltage in the comparative example. [Figure 14] This figure shows the relationship between the short-circuit resistance value and the monitor signal voltage in this embodiment. [Figure 15] A signal waveform diagram illustrating the operation of the display device of this embodiment. [Figure 16] A signal waveform diagram illustrating the operation of the display device of this embodiment. [Modes for carrying out the invention]

[0008] The following describes this embodiment. Note that the embodiment described below does not unduly limit the scope of the claims. Furthermore, not all of the configurations described in this embodiment are necessarily essential components.

[0009] 1.Display device Figure 1 shows an example configuration of the display device 10 of this embodiment. The display device 10 includes a display driver 20 and an electro-optic panel 200. The display driver 20 includes a driver circuit 30, a test circuit 40, a driver control circuit 60, and an output terminal TQ. The electro-optic panel 200 is provided with multiple display electrodes EL. Note that the display device 10 is not limited to the configuration shown in Figure 1, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components.

[0010] The display driver 20 is a circuit that drives the electro-optic panel 200 to display an image, and is implemented by a circuit device called an IC (Integrated Circuit). The circuit device is a semiconductor chip manufactured by a semiconductor process, in which circuit elements are formed on a semiconductor substrate. The display driver 20 is mounted on the glass substrate of the electro-optic panel 200, for example. For example, the display driver 20 is mounted on the glass substrate on which the display electrodes EL are provided. Alternatively, the display driver 20 may be mounted on a circuit board, and the circuit board and the electro-optic panel 200 may be connected by a flexible substrate.

[0011] The electro-optic panel 200 is a display panel, such as a liquid crystal panel. The electro-optic panel 200 has a plurality of display electrodes EL and a plurality of electro-optic elements. The electro-optic elements are, for example, liquid crystal elements. Each pixel of the electro-optic panel 200 is composed of the display electrodes EL and the electro-optic elements, and an image is displayed on the electro-optic panel 200.

[0012] The display device 10 is a device that displays an image based on, for example, image data. The display device 10 is also called a display module or an electro-optical device. The display device 10 is, for example, a cluster display that is a display of a meter panel, a center information display, a head-up display that displays a virtual image in the user's field of view, or an in-vehicle display device such as an electronic mirror. The in-vehicle display device is a display device mounted on an automobile such as a four-wheeled or two-wheeled vehicle. Alternatively, the display device 10 may be a display device mounted on a moving body other than a vehicle such as a ship, a head-mounted display device called an HMD, a television device, or a display of an information processing device.

[0013] The display driver 20 includes a driver circuit 30, an inspection circuit 40, a driver control circuit 60, and an output terminal TQ.

[0014] The driver circuit 30 outputs a drive signal SD for driving the electro-optical panel 200. When the electro-optical panel 200 is a segment liquid crystal panel, the driver circuit 30 outputs a segment drive signal for driving the segment electrodes or a common drive signal for driving the common electrodes as the drive signal SD.

[0015] The output terminal TQ is a terminal that outputs the drive signal SD to the display electrode EL of the electro-optical panel 200. The output terminal TQ is, for example, a pad of the display driver 20 which is a circuit device. For example, in the pad region, a metal layer is exposed from a passivation film which is an insulating layer, and the exposed metal layer constitutes a pad which is a terminal of the display driver 20. The terminal may be an external connection terminal of a package in which the display driver 20 is housed.

[0016] The inspection circuit 40 is a circuit for inspecting abnormal states such as short circuits and open circuits in signal lines of the electro-optical panel 200, and includes a comparison circuit 50 and a determination circuit 56.

[0017] The comparison circuit 50 compares the voltage of the monitor signal SM of the drive signal SD with the reference voltage VR. For example, the electro-optic panel 200 has a signal line L1 connected to the display electrode EL at one end. The drive signal SD from the driver circuit 30 is output to the display electrode EL via the signal line L1.

[0018] The drive signal SD is output to the display electrode EL of the electro-optic panel 200 via the output terminal TQ, and is also input to the inspection circuit 40 as a monitor signal SM. That is, the voltage of the drive signal SD is equal to the voltage of the monitor signal SM. For example, in Figure 1, one end of a signal line connected to the connecting line between the output node NQ and the output terminal TQ of the driver circuit 30 is connected to the other end of the inspection circuit 40, and the drive signal SD is input to the inspection circuit 40 as a monitor signal SM via this signal line. The inspection circuit 40 then checks whether or not an abnormality has been detected in the signal line based on this monitor signal SM. The monitor signal SM can also be said to be a signal fed back from the display electrode EL driven by the drive signal SD. It is also possible to implement a modified version in which an input terminal (not shown) is provided on the display driver 20, a signal line connecting this input terminal and the display electrode EL is provided on the electro-optic panel 200, and the signal input from the display electrode EL via this signal line and the input terminal is input to the inspection circuit 40 as a monitor signal SM of the drive signal SD.

[0019] The comparison circuit 50 compares the voltage of the input monitor signal SM with the reference voltage VR and outputs a signal CQ indicating the comparison result, and the judgment circuit 56 detects an abnormality based on the comparison result. The reference voltage VR is a threshold voltage for judgment. In this case, the comparison circuit 50 may compare two or more reference voltages VR with the voltage of the monitor signal SM. For example, the comparison circuit 50 may compare the high-potential reference voltage with the voltage of the monitor signal SM and the low-potential reference voltage with the voltage of the monitor signal SM and output the comparison result. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information by electrical signals. The electrical connection may be a connection via a passive element or the like.

[0020] The determination circuit 56 determines an abnormality based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result from the comparison circuit 50. For example, the determination circuit 56 determines a drive abnormality where the drive of the display electrode EL is abnormal. For example, the determination circuit 56 determines an abnormality in the signal line. The determination circuit 56 then outputs a signal JQ indicating the result of the abnormality determination. For example, the determination circuit 56 determines whether an abnormal condition such as a short circuit or open circuit has occurred in the signal line L1 based on the signal of the expected value EV and the comparison result signal CQ from the comparison circuit 50, and outputs a signal JQ indicating that such an abnormality has occurred. The expected value EV is the value expected as the voltage level of the signal output as the drive signal SD by the driver circuit 30. For example, the expected value EV is the first logic level when the driver circuit 30 outputs a high-level drive signal SD, and the second logic level when the driver circuit 30 outputs a low-level drive signal SD. In the following explanation, the first logic level is assumed to be high and the second logic level is assumed to be low. However, the first logic level may be low and the second logic level may be high. Also, the high level of the drive signal SD of the driver circuit 30 corresponds to, for example, the high level of the drive power supply voltage used to drive the electro-optical panel 200, and the high level of the expected value EV corresponds to, for example, the high level of the logic power supply voltage.

[0021] The driver circuit 30 has a drive transistor TR. The drive transistor TR is a transistor that outputs a drive signal SD. For example, the drive signal SD is output from the drain of the drive transistor TR. In normal operation mode, a display signal corresponding to the display data is input to the gate of the drive transistor TR. Specifically, the driver circuit 30 is provided with a P-type drive transistor TRP and an N-type drive transistor TRN as drive transistors TR, for example, as shown in Figure 7 below. The drive signal SD is output from the output node NQ of the driver circuit 30, which is the connection node between the drain of the P-type drive transistor TRP and the drain of the N-type drive transistor TRN. In normal operation mode, a display signal DP is input to the gates of the P-type drive transistor TRP and the gates of the N-type drive transistor TRN.

[0022] The driver control circuit 60 is a circuit that controls the driver circuit 30. For example, the driver control circuit 60 controls the driver circuit 30 to output a constant current drive signal SD. Specifically, in the determination mode, the driver control circuit 60 controls the gate of the drive transistor TR of the driver circuit 30 so that the drive transistor TR outputs a constant current drive signal SD. For example, the driver control circuit 60 controls the gate of the drive transistor TR so that a constant current flows through the drive transistor TR located between the power supply voltage node and the output node NQ, thereby causing a constant current drive signal SD to be output from the output node NQ.

[0023] For example, suppose that a P-type drive transistor TRP and an N-type drive transistor TRN are provided as drive transistors TR, as shown in Figure 7 below. In this case, in the first determination mode, the driver control circuit 60 controls the gate of the P-type drive transistor TRP, which is provided between the high-potential power supply voltage VCC node and the output node NQ, so that a constant current flows through it. In the second determination mode, the driver control circuit 60 controls the gate of the N-type drive transistor TRN, which is provided between the output node NQ and the low-potential power supply voltage VSS node, so that a constant current flows through it.

[0024] For example, in the normal operation mode, the driver control circuit 60 ensures that a display signal DP based on display data is input to the gate of the drive transistor TR. On the other hand, in the judgment mode, the driver control circuit 60 controls the gate of the drive transistor TR of the driver circuit 30 so that a drive signal SD is output with a constant current. The normal operation mode is a mode in which the display driver 20 drives the electro-optic panel 200 based on display data and displays an image normally using the display electrode EL. The judgment mode is a mode in which abnormalities in the drive signal SD due to short circuits, open circuits, etc., are detected. The judgment mode can also be called the judgment period, and the normal operation mode can also be called the normal operation period. The judgment mode is set, for example, during the startup period when the display driver 20 is powered on. In the judgment mode, the inspection circuit 40 checks for abnormal conditions, and then the system transitions to the normal operation mode, where the display driver 20 drives based on the display data and displays an image on the electro-optic panel 200.

[0025] As described above, the display driver 20 of this embodiment includes a driver circuit 30, an output terminal TQ that outputs a drive signal SD from the driver circuit 30 to the display electrode EL, a test circuit 40, and a driver control circuit 60. The comparison circuit 50 of the test circuit 40 compares the voltage of the monitor signal SM of the drive signal SD with a reference voltage VR, and the determination circuit 56 determines whether there is an abnormality such as a short circuit in the signal line based on the expected value EV corresponding to the voltage level of the drive signal SD and the comparison result of the comparison circuit 50. In the determination mode, the driver control circuit 60 controls the gate of the drive transistor TR of the driver circuit 30 so that the drive transistor TR outputs the drive signal SD with a constant current. In this way, even if an abnormality such as a short circuit occurs in the signal line L1 of the drive signal SD, it is possible to prevent excessive current from flowing through the drive transistor TR, or to prevent the determination accuracy of the determination circuit 56 of the test circuit 40 from deteriorating due to voltage changes of the monitor signal SM.

[0026] For example, an abnormality may occur, such as a short circuit between the drive signal SD signal line L1 and a wire with a different potential. When such an abnormality as a short circuit occurs, an excessive current may flow from the power supply voltage node through the drive transistor TR, potentially causing damage to the transistor circuit (circuit elements such as transistors) of the display driver 20. Alternatively, an abnormality such as a short circuit may cause a change in the voltage of the monitor signal SM of the drive signal SD, potentially leading to problems such as a deterioration in the judgment accuracy of the judgment circuit 56 of the inspection circuit 40. This judgment accuracy can also be called the detection accuracy of the inspection circuit 40.

[0027] In this regard, in the display driver 20 of this embodiment, in the judgment mode, the drive transistor TR of the driver circuit 30 is controlled to output a drive signal SD with a constant current. Therefore, even if an abnormality such as a short circuit occurs, the current flowing from the power supply voltage node through the drive transistor TR is limited to a constant current, preventing excessive current from flowing and causing circuit failure. Furthermore, by outputting a constant current drive signal SD in the judgment mode, it is possible to suppress changes in the voltage of the monitor signal SM of the drive signal SD due to short-circuit resistance values, etc. Therefore, it becomes possible to realize a display driver 20 that can suppress the occurrence of excessive current and deterioration of judgment accuracy caused by abnormalities in the drive signal SD.

[0028] Figure 2 shows a detailed configuration example of the display driver 20 and display device 10 of this embodiment. In Figure 2, the display device 10 includes the display driver 20, the electro-optic panel 200, and the processing unit 300. Note that the display driver 20 and display device 10 are not limited to the configuration in Figure 2, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components.

[0029] The electro-optic panel 200 is a panel driven, for example, by a static drive method. Specifically, the electro-optic panel 200 includes a first glass substrate, a second glass substrate, and liquid crystal. The liquid crystal, which is an electro-optic element, is sealed between the first and second glass substrates. Segment electrodes are provided on the first glass substrate, and a common electrode is provided on the second glass substrate. The display driver 20 outputs a segment drive signal to the segment electrodes. The display driver 20 also outputs a common drive signal to the common electrode. As a result, a drive signal, which is the potential difference between the segment drive signal and the common drive signal, is applied to the liquid crystal between the segment electrodes and the common electrode. The segment electrodes and the common electrode are transparent electrodes, for example, ITO (Indium Tin Oxide). In the following description, the electro-optic panel 200 will mainly be described as a segment liquid crystal panel having segment electrodes and a common electrode as display electrodes EL, but this embodiment is not limited to this.

[0030] The processing unit 300 is, for example, a host device for the display driver 20, and is implemented by, for example, a processor or a display controller. The processor is a CPU or a microcomputer, etc. The processing unit 300 may also be a circuit device composed of multiple circuit components. For example, in automotive electronic equipment, the processing unit 300 may be an ECU (Electronic Control Unit).

[0031] The display driver 20 includes a segment driver circuit 31, a common driver circuit 32, a segment inspection circuit 41, a common inspection circuit 42, a line latch 70, a data storage circuit 80, a control circuit 100, an interface circuit 110, and an oscillator circuit 120. The segment driver circuit 31 and the common driver circuit 32 correspond to the driver circuit 30 in Figure 1, and each of the segment inspection circuit 41 and the common inspection circuit 42 corresponds to the inspection circuit 40 in Figure 1. In other words, in this case, the display driver 20 has multiple inspection circuits 40.

[0032] The segment driver circuit 31 outputs a segment drive signal to drive the segment electrodes of the electro-optic panel 200. For example, the segment driver circuit 31 drives the electro-optic panel 200 using a static drive method or a duty cycle drive method. For example, the display driver 20 has an output terminal to which a segment drive signal is output, and the segment drive signal is output to the segment electrodes of the electro-optic panel 200 via this output terminal. In this case, the drive signal SD, display electrode EL, and output terminal TQ in Figure 1 correspond to the segment drive signal, segment electrode, and output terminal of the segment drive signal, respectively.

[0033] The common driver circuit 32 outputs a common drive signal to drive the common electrode of the electro-optic panel 200. For example, the display driver 20 has an output terminal to which the common drive signal is output, and the common drive signal is output to the common electrode of the electro-optic panel 200 via this output terminal. In this case, the drive signal SD, the display electrode EL, and the output terminal TQ in Figure 1 correspond to the common drive signal, the common electrode, and the output terminal of the common drive signal, respectively. That is, in this case, the display driver 20 has multiple output terminals TQ.

[0034] The segment inspection circuit 41 is a circuit that inspects for abnormalities in the signal lines of the segment electrodes. For example, the segment inspection circuit 41 checks whether an abnormality such as a short circuit or open circuit has occurred in the signal lines of the segment electrodes. The common inspection circuit 42 is a circuit that inspects for abnormalities in the signal lines of the common electrode. For example, the common inspection circuit 42 checks whether an abnormality such as a short circuit or open circuit has occurred in the signal lines of the common electrode. These segment inspection circuits 41 and common inspection circuits 42 correspond to the inspection circuit 40 in Figure 1. In other words, in this case, the display driver 20 has multiple inspection circuits 40.

[0035] The data storage circuit 80 is a circuit that stores data for display purposes, and can be implemented using memory such as RAM. The data storage circuit 80 stores data for display purposes of the electro-optical panel 200. The display data includes, for example, on / off data or grayscale data for the display of a display corresponding to a segment electrode. This display data is received from, for example, the processing unit 300 via the interface circuit 110 and stored in the data storage circuit 80.

[0036] The line latch 70 latches display data from the data storage circuit 80. The line latch 70, being a data latch, latches display data from the data storage circuit 80 based on a latch signal from, for example, the control circuit 100. The segment driver circuit 31 then generates and outputs a segment drive signal based on the data latched to the line latch 70. The line latch 70 is implemented using a flip-flop circuit or the like.

[0037] The control circuit 100 is a logic circuit that operates based on a clock signal from, for example, the oscillator circuit 120. The control circuit 100 can be implemented using, for example, an ASIC (Application Specific Integrated Circuit) with automatic placement and routing such as a gate array, or a processor such as a CPU. The control circuit 100 controls the display timing, sets the operation of the display driver 20, and so on.

[0038] The interface circuit 110 is a circuit that acts as an interface with the external processing unit 300 and performs communication processing between the processing unit 300 and the display driver 20. For example, the interface circuit 110 receives various types of data from the processing unit 300, such as command data and display data. The interface circuit 110 can be implemented using a serial interface circuit such as I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface).

[0039] The oscillation circuit 120 generates an oscillation signal and outputs a clock signal based on the oscillation signal. Each circuit of the display driver 20, such as the control circuit 100, operates based on this clock signal.

[0040] Figure 3 shows an example of the arrangement of segment electrodes and wiring of segment signal lines in the electro-optic panel 200, and Figure 4 shows an example of the arrangement of common electrodes and wiring of common signal lines.

[0041] In Figure 3, the electro-optical panel 200 is provided with segment electrodes ES1 to ES7 and segment signal lines LS1 to LS14. The segment terminals TS1 and TS2 of the display driver 20 are connected to segment electrode ES1 by segment signal lines LS1 and LS2, respectively. Similarly, the segment terminals TS3 and TS4 of the display driver 20 are connected to segment electrode ES2 by segment signal lines LS3 and LS4, respectively. The connection between segment terminals TS5 to TS14 and segment electrodes ES3 to ES7 by segment signal lines LS5 to LS14 is similar. Each of the segment terminals TS1, TS3, TS5, TS7, TS9, TS11, and TS13 in Figure 3 corresponds to the output terminal TQ from which the drive signal SD in Figure 1 is output.

[0042] In Figure 3, segment signal lines LS2, LS4, LS6, LS8, LS10, LS12, and LS14 are provided on the electro-optic panel 200 for inputting monitor signals, which are feedback signals from segment electrodes ES1 to ES7, to the display driver 20. Segment terminals TS2, TS4, TS6, TS8, TS10, TS12, and TS14, which serve as input terminals for these monitor signals, are also provided on the display driver 20. The segment inspection circuit 41 can determine abnormalities based on the monitor signals input in this way, but it is not necessary to provide such feedback segment terminals and segment signal lines. Also, while Figure 3 shows an example where the segment electrodes are 7-segment display electrodes, there are various types of electrodes, such as icon electrodes for warning lights.

[0043] In Figure 4, the electro-optical panel 200 is provided with common electrodes EC1 to EC7 and common signal lines LC1 and LC2. The common terminals TC1 and TC2 of the display driver 20 are connected to the common electrodes EC1 to EC7 by common signal lines LC1 and LC2, respectively. The common terminal TC1 in Figure 4 corresponds to the output terminal TQ from which the drive signal SD in Figure 1 is output.

[0044] In Figure 4, a common signal line LC2 is provided on the electro-optic panel 200 for inputting monitor signals, which are feedback signals from common electrodes EC1 to EC7, to the display driver 20. A common terminal TC2, which is the input terminal for the monitor signals, is also provided on the display driver 20. The common inspection circuit 42 can determine abnormalities based on the monitor signals input in this way, but it is not necessary to provide such a common terminal and common signal line for feedback.

[0045] 2. Test circuit, driver circuit Figures 5 and 6 show detailed configuration examples of the test circuit 40 and driver circuit 30. Figure 5 shows a configuration example where the test circuit 40 and driver circuit 30 are the segment test circuit 41 and segment driver circuit 31 of Figure 2, respectively. Figure 6 shows a configuration example where the test circuit 40 and driver circuit 30 are the common test circuit 42 and common driver circuit 32 of Figure 2, respectively. In Figure 5, the driver circuit 30 outputs a drive signal SD for the segment based on display data from the data storage circuit 80. In contrast, in Figure 6, no such display data is input, and the driver circuit 30 outputs a drive signal SD for the common based on the control of the control circuit 100. In the following explanation, for the sake of simplicity, the configuration of Figure 5 will be used as the main example.

[0046] The polarity inversion circuit 74 performs polarity inversion processing on the data for display of the segment read from the data storage circuit 80 based on the polarity signal input from the control circuit 100. For example, the polarity inversion circuit 74 outputs data DI at the same logic level as the display data for positive polarity frames, and outputs data DI with the logic level of the display data inverted for negative polarity frames. The latch 72 latches the data DI from the polarity inversion circuit 74 based on the latch signal LT from the control circuit 100. The latch 72 is a latch that constitutes the line latch 70 in Figure 2, and is implemented by, for example, a flip-flop circuit.

[0047] The driver circuit 30 includes a level shifter 36 and an output driver 34. The level shifter 36 receives the latched data DQ from the latch 72 and performs a level shift of the data DQ signal. For example, the level shifter 36 performs a level shift from the logic power supply voltage level to the drive power supply voltage level of the electro-optic panel 200. The output driver 34 then outputs a drive signal SD based on the display signal after the level shift by the level shifter 36.

[0048] The test circuit 40 includes a comparison circuit 50, a judgment circuit 56, a reference voltage generation circuit 58, and a switch SW. The comparison circuit 50 includes a comparator 52 and a level shifter 54.

[0049] The switch SW is turned on when the inspection circuit 40 is in judgment mode, which determines whether there is a drive abnormality. As a result, the monitor signal SM corresponding to the drive signal SD is input to the comparator 52 of the comparison circuit 50 via the turned-on switch SW.

[0050] The reference voltage generation circuit 58 generates reference voltages VRH and VRL based on the power supply voltages VCC and VSS. VCC is the drive power supply voltage for the high-potential side of the electro-optic panel 200, and VSS is the power supply voltage for the low-potential side. For example, the reference voltage generation circuit 58 is composed of a ladder resistor circuit having multiple resistors connected in series to the VCC node and the VSS node, and generates reference voltages VRH and VRL by voltage division by these multiple resistors. Reference voltage VRH is the reference voltage on the high-potential side, which is the VCC side, and reference voltage VRL is the reference voltage on the low-potential side, which is the VSS side. Reference voltage VRH is, for example, about 60-90% of VCC, and reference voltage VRL is, for example, about 10-40% of VCC. As an example, reference voltage VRH is, for example, about 70% of VCC, and reference voltage VRL is, for example, about 30% of VCC.

[0051] The comparator 52 of the comparison circuit 50 compares the voltage of the monitor signal SM of the drive signal SD with the reference voltages VRH and VRL, and the comparison result is output from the comparison circuit 50 as signal CQ via the level shifter 54. The level shifter 54 performs a level shift, converting the drive power supply voltage level of the electro-optical panel 200 to the logic power supply voltage level. For example, the comparison circuit 50 outputs a signal CQ of the first logic level, which is a high level, when the voltage of the monitor signal SM is higher than the high-potential reference voltage VRH. The comparison circuit 50 also outputs a signal CQ of the second logic level, which is a low level, when the voltage of the monitor signal SM is lower than the low-potential reference voltage VRL. The comparison circuit 50 may also output a signal CQ indicating a test error when the voltage of the monitor signal SM is between the high-potential reference voltage VRH and the low-potential reference voltage VRH.

[0052] The judgment circuit 56 receives the data DQ from the latch 72 as the expected value EV. For example, if the driver circuit 30 outputs a high-level drive signal SD, the high-level expected value EV is input to the judgment circuit 56. If the driver circuit 30 outputs a low-level drive signal SD, the low-level expected value EV is input to the judgment circuit 56. The judgment circuit 56 then compares the expected value EV with the comparison result signal CQ from the comparison circuit 50 to determine whether or not an abnormality has occurred.

[0053] For example, the determination circuit 56 determines that no abnormality has occurred when the drive signal SD is at a high level, the expected value EV is at a high level, the voltage of the monitor signal SM is higher than the reference voltage VRH, and the signal CQ is at a high level. On the other hand, when the expected value EV is at a high level, the circuit determines that an abnormality has occurred if the signal CQ is at a low level or is a signal indicating a detection error.

[0054] Furthermore, the determination circuit 56 determines that no abnormality has occurred if the drive signal SD is at a low level and the expected value EV is at a low level, and the voltage of the monitor signal SM is lower than the reference voltage VRL and the signal CQ is at a low level. On the other hand, if the expected value EV is at a low level and the signal CQ is at a high level or is a signal indicating a detection error, the circuit determines that an abnormality has occurred.

[0055] In this way, the determination circuit 56 can determine that no abnormality has occurred when the driver circuit 30 is outputting a high-level drive signal SD to the display electrode EL, and the voltage of the monitor signal SM is the voltage corresponding to the high level. Also, the determination circuit 56 can determine that no abnormality has occurred when the driver circuit 30 is outputting a low-level drive signal SD to the display electrode EL, and the voltage of the monitor signal SM is the voltage corresponding to the low level.

[0056] 3. Driver control circuit Next, the configuration and operation of the driver control circuit 60 of this embodiment will be described in detail. Figure 7 is an explanatory diagram of the configuration and operation of the driver control circuit 60. Figures 9 and 10, described later, are also explanatory diagrams of the configuration and operation of the driver control circuit 60 of this embodiment.

[0057] As shown in Figure 7, the driver control circuit 60 includes a switching circuit 62 and a constant current setting circuit 64. The driver control circuit 60 may further include switch circuits SW3, SW4, SW5, and SW6. The switching circuit 62 includes switch circuits SW1 and SW2. Switch circuit SW1 is the first switch circuit, and switch circuit SW2 is the second switch circuit. The constant current setting circuit 64 includes current setting circuits 65 and 66. Current setting circuit 65 is the first current setting circuit, and current setting circuit 66 is the second current setting circuit.

[0058] The output driver 34 of the driver circuit 30 includes a P-type drive transistor TRP and an N-type drive transistor TRN. The drive transistors TRP and TRN are connected in series between the node of the high-potential power supply voltage VCC and the node of the low-potential power supply voltage VSS. The drive signal SD is output from the output node NQ, which is the connection node for the drains of the drive transistors TRP and TRN.

[0059] The reference voltage generation circuit 58 includes resistors RA1 and RA2 connected in series between the node of the high-potential power supply voltage VCC and the node of the low-potential power supply voltage VSS. A reference voltage VR is generated and output at the connection node N2 between resistors RA1 and RA2. As shown in Figures 5 and 6, it is desirable to generate two reference voltages VRH and VRL for the high-potential and low-potential sides for accurate anomaly detection, but for the sake of simplicity, the following explanation will mainly use the case where there is only one reference voltage VR as an example.

[0060] For example, Figure 8 shows a comparative example of this embodiment. In the comparative example in Figure 8, the driver control circuit 60 shown in Figure 7 is not provided. The driver circuit 30 includes a pre-buffer circuit 33 composed of an inverter circuit and an output driver 34 that receives the display signal DP output by the pre-buffer circuit 33 and outputs a drive signal SD.

[0061] In Figure 8, a short circuit occurs in the signal line L1, which outputs the drive signal SD. Specifically, in Figure 8, the signal line L1 of the drive signal SD is shorted to the potential of the VSS side. As a result, a short current flows from the VCC node to the potential of VSS via the drive transistor TRP of the driver circuit 30. In this case, if the short resistance value, which is the resistance value at the short point, is low, an excessive current will flow as a short current. Such an excessive current may cause malfunctions such as damage to the display driver 20 circuit. Also, depending on the magnitude of the short resistance value, the voltage of the monitor signal SM of the drive signal SD may change, which may worsen the judgment accuracy of the inspection circuit 40. Furthermore, in Figure 8, if the signal line L1 of the drive signal SD is shorted to the potential of the VCC side, a short current will flow from the potential of VCC to the VSS node via the drive transistor TRN of the driver circuit 30, leading to problems such as circuit failure due to excessive current and deterioration of judgment accuracy.

[0062] In this embodiment, the driver control circuit 60 controls the gates of the drive transistors TRP and TRN of the driver circuit 30 so that they output a drive signal SD with a constant current in the judgment mode. In this way, even if an abnormality such as a short circuit occurs in the signal line L1 of the drive signal SD, the short current will be limited to a constant current. Therefore, it is possible to prevent problems such as excessive current flow or deterioration of the judgment accuracy of the inspection circuit 40.

[0063] Specifically, as shown in Figure 7, the driver control circuit 60 includes a switching circuit 62 and a constant current setting circuit 64. The constant current setting circuit 64 generates gate voltages VG1 and VG2 for the drive transistors TRP and TRN of the driver circuit 30, so that they can output a drive signal SD with a constant current. For example, the constant current setting circuit 64 generates and outputs a gate voltage VG1 for a constant current to flow between the source and drain of the drive transistor TRP. The constant current setting circuit 64 also generates and outputs a gate voltage VG2 for a constant current to flow between the source and drain of the drive transistor TRN.

[0064] In normal operation mode, the switching circuit 62 outputs a display signal DP to the gates of the drive transistors TRP and TRN to cause the driver circuit 30 to output a drive signal SD. On the other hand, in judgment mode, the switching circuit 62 outputs a gate voltage VG1 or gate voltage VG2 from the constant current setting circuit 64 to the gates of the drive transistors TRP and TRN, respectively. In this way, in normal operation mode, the display signal DP is input to the gates of the drive transistors TRP and TRN by the switching circuit 62, enabling the driver circuit 30 to output a drive signal SD based on the display signal DP to the electro-optical panel 200. In judgment mode, the gate voltage VG1 or gate voltage VG2 from the constant current setting circuit 64 is input to the gates of the drive transistors TRP and TRN by the switching circuit 62, causing the driver circuit 30 to output a drive signal SD with a constant current.

[0065] For example, Figure 7 shows the switching state of the switch circuit in the normal operating mode, when an image based on the display signal DP is displayed on the electro-optic panel 200. For example, in the normal operating mode, as shown in Figure 7, the switch circuits SW1 and SW2 of the switching circuit 62 are switched to the input node side of the display signal DP by the control signals SC1 and SC2 from the control circuit 100 in Figure 5. Therefore, the display signal DP from the preceding pre-buffer circuit, etc., is input to the gates of the drive transistors TRP and TRN of the driver circuit 30 via the switch circuits SW1 and SW2. As a result, the drive signal SD based on the display signal DP is output to the electro-optic panel 200, and the normal display operation of the electro-optic panel 200 is performed.

[0066] In this case, as shown in Figure 7 of the normal operating mode, the switch circuits SW5 and SW6 located between the switching circuit 62 and the constant current setting circuit 64 are turned off. Therefore, the gate voltages VG1 and VG2 from the constant current setting circuit 64 are not input to the switching circuit 62. Also, since the pull-up switch circuit SW3 and the pull-down switch circuit SW4 are turned off, the pull-up and pull-down operations performed by these switch circuits SW3 and SW4 are not performed.

[0067] Thus, the driver circuit 30 includes a P-type drive transistor TRP and an N-type drive transistor TRN, which are connected in series between the node of the high-potential power supply voltage VCC and the node of the low-potential power supply voltage VSS, as the drive transistors TR in Figure 1. As shown in Figure 7, the switching circuit 62 includes a switch circuit SW1 that outputs a display signal DP to the gate of the P-type drive transistor TRP in normal operation mode, and a switch circuit SW2 that outputs a display signal DP to the gate of the N-type drive transistor TRN in normal operation mode. Switch circuit SW1 is the first switch circuit, and switch circuit SW2 is the second switch circuit. In this way, in normal operation mode, the display signal DP is input to the gate of the P-type drive transistor TRP via switch circuit SW1 and to the gate of the N-type drive transistor TRN via switch circuit SW2. As a result, a drive signal SD based on the display signal DP is output to the electro-optic panel 200, and normal display operation is performed.

[0068] On the other hand, Figure 9 shows the switching state of the switch circuit in the judgment mode, specifically the switching state of the switch circuit when detecting an abnormality when the signal line L1 of the drive signal SD is shorted to the potential on the VSS side. In this judgment mode, which is the first judgment mode, the switch circuits SW1 and SW2 of the switching circuit 62 are switched to the input node side of the gate voltages VG1 and VG2 from the constant current setting circuit 64 by the control signals SC1 and SC2 from the control circuit 100. Also, the switch circuit SW5 for connecting the switching circuit 62 and the constant current setting circuit 64 is turned on, and the switch circuit SW6 is turned off. In addition, the switch circuit SW4 for pull-down to VSS is turned on, and the switch circuit SW3 for pull-up to VCC is turned off.

[0069] In this way, the constant gate voltage VG1 from the constant current setting circuit 64 is input to the gate of the P-type drive transistor TRP of the driver circuit 30 via the switch circuit SW5 and the switch circuit SW1 of the switching circuit 62. As a result, a constant current flows between the source and drain of the drive transistor TRP. Therefore, as shown in Figure 9, even if the signal line L1 of the drive signal SD is shorted to the potential on the VSS side, an excessive current will flow through the drive transistor TRP, preventing circuit failure or deterioration of judgment accuracy due to a change in the voltage of the monitor signal SM input to the test circuit 40.

[0070] In Figure 9, the switch circuit SW6, to which the gate voltage VG2 from the constant current setting circuit 64 is input, is turned off, and the gate of the drive transistor TRN is pulled down to the VSS side by the pull-down switch circuit SW4. Therefore, it is possible to control the P-type drive transistor TRP to flow a constant current while turning off the N-type drive transistor TRN.

[0071] Figure 10 also shows the switching state of the switch circuit in the judgment mode, specifically the switching state of the switch circuit when detecting an abnormality when the signal line L1 of the drive signal SD is shorted to the potential on the VCC side. In this judgment mode, which is the second judgment mode, the switch circuits SW1 and SW2 of the switching circuit 62 are switched to the input node side of the gate voltages VG1 and VG2 from the constant current setting circuit 64 by the control signals SC1 and SC2 from the control circuit 100. Also, the switch circuit SW6 for connecting the switching circuit 62 and the constant current setting circuit 64 is turned on, and the switch circuit SW5 is turned off. In addition, the switch circuit SW3 for pull-up to VCC is turned on, and the switch circuit SW4 for pull-down to VSS is turned off.

[0072] In this way, the constant gate voltage VG2 from the constant current setting circuit 64 is input to the gate of the N-type drive transistor TRN of the driver circuit 30 via the switch circuit SW6 and the switch circuit SW2 of the switching circuit 62. As a result, a constant current flows between the source and drain of the drive transistor TRN. Therefore, even if the signal line L1 of the drive signal SD is shorted to the potential on the VCC side, as shown in Figure 10, an excessive current will flow through the drive transistor TRN, preventing circuit failure or deterioration of judgment accuracy due to a change in the voltage of the monitor signal SM input to the test circuit 40.

[0073] In Figure 10, the switch circuit SW5, to which the gate voltage VG1 from the constant current setting circuit 64 is input, is turned off, and the gate of the drive transistor TRP is pulled up to the VCC side by the pull-up switch circuit SW3. Therefore, it is possible to control the N-type drive transistor TRN to flow a constant current while turning off the P-type drive transistor TRP.

[0074] As shown in Figures 7, 9, and 10, the constant current setting circuit 64 also includes current setting circuits 65 and 66. Current setting circuit 65 is the first current setting circuit, and current setting circuit 66 is the second current setting circuit. Current setting circuit 65 has a P-type transistor TA1 and a current source IS1 connected in series between the node of the high-potential power supply voltage VCC and the node of the low-potential power supply voltage VSS. Current source IS1 is the first current source. The gate and drain of the P-type transistor TA1 are connected to the output node NQ1 of the current setting circuit 65. For example, the source of the P-type transistor TA1 is connected to the VCC node, and the current source IS1 is provided between the output node NQ1 and the VSS node. Current source IS1 is composed of, for example, a transistor for current sources.

[0075] The current setting circuit 66 also includes a current source IS2 and an N-type transistor TA2, which are connected in series between the VCC node and the VSS node. The current source IS2 is a second current source. The gate and drain of the N-type transistor TA2 are connected to the output node NQ2 of the current setting circuit 66. For example, the source of the N-type transistor TA2 is connected to the VSS node, and the current source IS2 is provided between the VCC node and the output node NQ2. The current source IS2 is composed of, for example, a transistor for current sources.

[0076] In the determination mode, as shown in Figure 9, switch circuit SW1 connects the output node NQ1 of the current setting circuit 65 to the gate of the P-type drive transistor TRP, or as shown in Figure 10, switch circuit SW2 connects the output node NQ2 of the current setting circuit 66 to the gate of the N-type drive transistor TRN.

[0077] In this way, by connecting the output node NQ1 of the current setting circuit 65 to the gate of the drive transistor TRP, a current mirror circuit is formed between transistor TA1 and the drive transistor TRP, and a constant current corresponding to the constant current flowing through the current source IS1 flows through the drive transistor TRP. As a result, even if the signal line L1 of the drive signal SD is shorted to the potential on the VSS side, as shown in Figure 9, the short current flowing through the drive transistor TRP is limited to a constant current, preventing the occurrence of excessive current and deterioration of judgment accuracy. Furthermore, by connecting the output node NQ2 of the current setting circuit 66 to the gate of the drive transistor TRN, a current mirror circuit is formed between transistor TA2 and the drive transistor TRN, and a constant current corresponding to the constant current flowing through the current source IS2 flows through the drive transistor TRN. As a result, even if the signal line L1 of the drive signal SD is shorted to the potential on the VCC side, as shown in Figure 10, the short current flowing through the drive transistor TRN is limited to a constant current, preventing the occurrence of excessive current and deterioration of judgment accuracy.

[0078] As shown in Figure 9, the driver control circuit 60 pulls down the gate of the N-type drive transistor TRN when the gate of the P-type drive transistor TRP is connected to the output node NQ1 of the current setting circuit 65 by the switch circuit SW1. For example, when the switch circuit SW4, which is located between the gate of the drive transistor TRN and the VSS node, is turned on, the gate of the drive transistor TRN is pulled down to the VSS side. Also, as shown in Figure 10, the driver control circuit 60 pulls up the gate of the P-type drive transistor TRP when the gate of the N-type drive transistor TRN is connected to the output node NQ2 of the current setting circuit 66 by the switch circuit SW2. For example, when the switch circuit SW3, which is located between the gate of the drive transistor TRP and the VCC node, is turned on, the gate of the drive transistor TRP is pulled up to the VCC side.

[0079] In this configuration, when the output node NQ1 of the current setting circuit 65 is connected to the gate of the P-type drive transistor TRP, the gate of the N-type drive transistor TRN is pulled down and turned off. This prevents unwanted current from flowing through the drive transistor TRN when a constant current is being supplied by the P-type drive transistor TRP. Also, when the output node NQ2 of the current setting circuit 66 is connected to the gate of the N-type drive transistor TRN, the gate of the P-type drive transistor TRP is pulled up and turned off. This prevents unwanted current from flowing through the drive transistor TRN when a constant current is being supplied by the N-type drive transistor TRN.

[0080] Figure 11 shows an example configuration of the current setting circuit 65, and Figure 12 shows an example configuration of the current setting circuit 66. In Figure 11, the current setting circuit 65 includes a plurality of P-type transistors TA11, TA12...TA1m connected in parallel between the VCC node and the output node NQ1. These unit transistors, transistors TA11, TA12...TA1m, constitute the transistor TA1 shown in Figures 7, 9, and 10. Here, m is an integer of 2 or more. The current setting circuit 65 also includes switch circuits S11, S12...S1m connected between the transistors TA11, TA12...TA1m and the output node NQ1. A current source IS1 is provided between the output node NQ1 and the VSS node. In this way, by setting the on / off states of the switch circuits S11, S12...S1m, the current mirror ratio between transistor TA1 and the drive transistor TRP can be set, making it possible to variably adjust the current value of the constant current flowing through the drive transistor TRP.

[0081] In Figure 12, the current setting circuit 66 includes multiple N-type transistors TA21, TA22...TA2m, which are connected in parallel between the output node NQ2 and the VSS node. These unit transistors, TA21, TA22...TA2m, constitute the transistor TA2 shown in Figures 7, 9, and 10. The current setting circuit 66 also includes switch circuits S21, S22...S2m, which are connected between the output node NQ2 and the transistors TA21, TA22...TA2m. A current source IS2 is provided between the VCC node and the output node NQ2. In this way, by setting the on / off state of the switch circuits S21, S22...S2m, the current mirror ratio between transistor TA2 and the drive transistor TRN can be set, making it possible to variably adjust the current value of the constant current flowing through the drive transistor TRN.

[0082] For example, Figure 13 shows the relationship between the short-circuit resistance RSH and the monitor signal voltage VSM in the comparative example in Figure 8. For example, if the on-resistance of the drive transistors TRP and TRN is RON, the resistance to the short-circuit point of the signal line L1 of the electro-optic panel 200 is RL1, and the short-circuit resistance is RSH, then the short-circuit current ISH can be expressed as shown in equation (1) below.

[0083] ISH=(VCC-VSS) / (RON+RL1+RSH) …(1)

[0084] The short-circuit resistance RSH changes depending on the contact condition at the short circuit. If the short-circuit resistance RSH is small, the short-circuit current ISH will be large, as shown in equation (1) above. If the short-circuit current ISH becomes excessive, problems such as failure of the display driver 20 circuit will occur. On the other hand, if the short-circuit resistance RSH is large, the short-circuit current ISH will be small, as shown in equation (1) above, but the voltage VSM of the monitor signal SM will become high, as shown in Figure 13.

[0085] When the voltage VSM of the monitor signal SM increases in this way, the comparison result that voltage VSM is higher than the reference voltage VR is output from the comparison circuit 50 of the inspection circuit 40. As a result, the judgment circuit 56 mistakenly determines that the comparison result of the comparison circuit 50 matches the expected value EV of the high-level drive signal SD, and is unable to correctly detect the short circuit abnormality, leading to a problem where the judgment accuracy of the judgment circuit 56 deteriorates.

[0086] Figure 14 shows the relationship between the short-circuit resistance RSH and the monitor signal voltage VSM in this embodiment. Figure 14 shows examples where the constant current value ICS flowing through the drive transistors TRP and TRN is 1 μA and 10 μA. When the constant current value is set to ICS in this way, the monitor signal voltage VSM can be expressed as shown in equation (2) below.

[0087] VSM = ICS × (RL1 + RSH) ... (2)

[0088] In the comparison example in Figure 8, as shown in equation (1) above, when the short-circuit resistance RSH changes, the short-circuit current ISH also changes. When the short-circuit resistance RSH is small, the short-circuit current ISH becomes large, causing problems such as circuit failure due to excessive current. Also, when the short-circuit resistance RSH is large, as shown in Figure 13, the voltage VSM of the monitor signal SM becomes large, causing the judgment circuit 56 to make a false judgment.

[0089] In contrast, in this embodiment, even if the short-circuit resistance value RSH is small, the short-circuit current value ISH is limited to the constant current value ICS, thus preventing circuit failure due to excessive current. Furthermore, in this embodiment, in equation (2) above, if the short-circuit resistance value RSH increases, the voltage VSM of the monitor signal SM also increases, but by adjusting the constant current value ICS, it is possible to prevent misjudgments in the judgment circuit 56 and improve judgment accuracy. That is, in Figure 14, if the constant current value ICS is set to, for example, 1 μA, the voltage VSM of the monitor signal SM can be made sufficiently small even if the short-circuit resistance value RSH increases. Therefore, for example, when a short circuit occurs in the signal line L1 of the drive signal SD, even when the expected value of the drive signal SD is at a high level, it becomes possible to make the voltage VSM of the monitor signal SM lower than the reference voltage VR in the comparison circuit 50. Therefore, it becomes possible to prevent misjudgments such as when a short-circuit abnormality occurs, but the comparison result of the comparison circuit 50 does not match the expected value EV of the high-level drive signal SD.

[0090] In this embodiment, the constant current value ICS of the constant current flowing through the drive transistors TRP and TRN is variable. For example, by using circuits with the configurations shown in Figures 11 and 12 as current setting circuits 65 and 66, the constant current value ICS can be made variable. Taking Figure 14 as an example, it becomes possible to set the constant current value ICS to 1 μA or 10 μA. In this way, as explained in Figure 14, by adjusting the constant current value ICS, the detection accuracy of the inspection circuit 40, which is the judgment accuracy, can be adjusted according to conditions such as the short-circuit resistance value RSH.

[0091] The constant current value can be adjusted to be variable by, for example, storing information in non-volatile memory or by setting a fuse in a fuse circuit. For example, the constant current value can be written to the non-volatile memory or fuse circuit during manufacturing or pre-shipment inspection of the display driver 20 or display device 10. Alternatively, the control circuit 100 of the display driver 20 may adjust the constant current value as appropriate using a control signal. For example, the control circuit 100 may measure the voltage of the monitor signal SM and adjust the constant current value based on the measurement result.

[0092] Figures 15 and 16 are signal waveform diagrams illustrating the operation of the display device 10 of this embodiment. Figure 15 is an example of a signal waveform when a short circuit occurs on the VSS side, as shown in Figure 9, and Figure 16 is an example of a signal waveform when a short circuit occurs on the VCC side, as shown in Figure 10. In reality, the judgment mode is set, for example, after startup by power-on, but before the start of normal operation. However, for the sake of simplicity, the following explanation will assume that a short circuit abnormality occurred in the middle of the judgment period set for the judgment mode.

[0093] As shown in A1 and A2 of Figure 15, the display data DI is latched to the latch 72 in Figure 5 and output to the driver circuit 30 as data DQ. As a result, as shown in A3 and A4, the drive signal SD is output to the display electrode EL, and the monitor signal SM of the drive signal SD is input to the comparison circuit 50 of the inspection circuit 40.

[0094] In other words, as shown in A3, when the drive signal SD is low level, the monitor signal SM is also low level, and as shown in A4, when the drive signal SD is high level, the monitor signal SM is also high level. In A5, since the voltage of the monitor signal SM is lower than the reference voltage VR (VRL), the signal CQ output by the comparator circuit 50 is low level. In A6, since the voltage of the monitor signal SM is higher than the reference voltage VR (VRH), the signal CQ is high level. In A5 and A6, the voltage level of the expected value EV corresponding to DQ matches the voltage level of the signal CQ, so as shown in A7 and A8, the judgment result signal JQ of the judgment circuit 56 is at a voltage level (for example, low level) indicating that no abnormality has occurred.

[0095] In Figure 15, at A9, a short circuit occurs on the VSS side, such as on the signal line L1. When such a short circuit occurs on the VSS side, the voltage of the high-level drive signal SD, as shown in A10, changes to a low level, as shown in A11, and the voltage of the monitor signal SM also changes to a low level, as shown in A12. The comparison circuit 50, which compares this low-level monitor signal SM with the reference voltage VR, outputs a low-level signal CQ, as shown in A13. Consequently, the high level, which is the voltage level of the expected value EV of the drive signal SD, and the low level, which is the voltage level of signal CQ, do not match, so the judgment result signal JQ of the judgment circuit 56 becomes a voltage level (for example, a high level) indicating that an abnormality has occurred, as shown in A14.

[0096] Next, we will explain Figure 16, which shows an example of a signal waveform when a short circuit occurs on the VCC side. B1 to B8 in Figure 16 are the same as A1 to A8 in Figure 15, so we will omit their explanation. At B9 in Figure 16, a short circuit occurs on the VCC side, such as on the signal line L1. When such a short circuit occurs on the VCC side, the voltage of the low-level drive signal SD, as shown in B10, changes to the high-level side as shown in B11, and the voltage of the monitor signal SM also changes to the high-level side as shown in B12. Then, the comparison circuit 50, which compares this high-level monitor signal SM with the reference voltage VR, outputs a high-level signal CQ as shown in B13. Consequently, the low-level voltage level of the expected value EV of the drive signal SD and the high-level voltage level of the signal CQ do not match, so the judgment result signal JQ of the judgment circuit 56 becomes a voltage level (for example, a high level) indicating that an abnormality has occurred, as shown in B14.

[0097] In this embodiment, the determination circuit 56 determines that an abnormality such as a short circuit has occurred in the signal line L1 of the drive signal SD when the comparison result of the comparison circuit 50 does not correspond to the expected value EV. For example, in A13 and A14 of Figure 15, the low level, which is the voltage level of the signal CQ, which is the comparison result of the comparison circuit 50, does not match the high level, which is the voltage level of the expected value EV of the drive signal SD, so the determination circuit 56 determines that an abnormality such as a short circuit has occurred. Similarly, in B13 and B14, the high level, which is the voltage level of the signal CQ of the comparison circuit 50, does not match the low level, which is the voltage level of the expected value EV of the drive signal SD, so the determination circuit 56 determines that an abnormality such as a short circuit has occurred. In this way, the determination circuit 56 can determine whether an abnormality such as a short circuit has occurred in the signal line L1 of the drive signal SD simply by determining whether the comparison result of the comparison circuit 50 matches the expected value EV corresponding to the voltage level of the drive signal SD. Furthermore, in this embodiment, even if a short circuit occurs in the signal line L1, the short current is limited to a constant current, thus preventing circuit failure due to excessive current. Furthermore, because a constant current independent of the short-circuit resistance is supplied, it is possible to prevent deterioration of the judgment accuracy of the inspection circuit 40.

[0098] As described above, the display driver of this embodiment includes a driver circuit that outputs a drive signal to the display electrodes of an electro-optical panel, a driver control circuit that controls the driver circuit, and a test circuit. The test circuit includes a comparison circuit that compares the voltage of the drive signal with a reference voltage, and a determination circuit that determines an abnormality based on the expected value corresponding to the level of the drive signal and the comparison result of the comparison circuit. In the determination mode, the driver control circuit controls the gate of the drive transistor of the driver circuit so that the drive transistor outputs a drive signal with a constant current.

[0099] In this embodiment, the comparison circuit of the test circuit compares the voltage of the monitor signal of the drive signal with a reference voltage, and the judgment circuit determines whether there is an abnormality such as a short circuit based on the expected value corresponding to the voltage level of the drive signal and the comparison result of the comparison circuit. Then, in the judgment mode, the driver control circuit controls the gate so that the drive transistor of the driver circuit outputs the drive signal with a constant current. In this way, even if an abnormality such as a short circuit occurs in the signal line of the drive signal, it is possible to prevent excessive current from flowing through the drive transistor, or to prevent the judgment accuracy of the test circuit from deteriorating due to changes in the voltage of the monitor signal.

[0100] In this embodiment, the driver control circuit may also include a constant current setting circuit that generates the gate voltage of the drive transistor to cause the drive transistor to output a drive signal with a constant current. The driver control circuit may also include a switching circuit that outputs an indicator signal to the gate of the drive transistor to cause the driver circuit to output a drive signal in the normal operation mode, and outputs the gate voltage from the constant current setting circuit to the gate of the drive transistor in the determination mode.

[0101] In this configuration, in normal operation mode, the switching circuit inputs a display signal to the gate of the drive transistor, allowing the driver circuit to output a drive signal based on the display signal. In judgment mode, the switching circuit inputs the gate voltage from the constant current setting circuit to the gate of the drive transistor, causing the driver circuit to output a drive signal with a constant current.

[0102] In this embodiment, the driver circuit may also include a P-type drive transistor and an N-type drive transistor as drive transistors, which are provided in series between the high-potential power supply voltage node and the low-potential power supply voltage node. The switching circuit may also include a first switch circuit that outputs a display signal to the gate of the P-type drive transistor in the normal operating mode, and a second switch circuit that outputs a display signal to the gate of the N-type drive transistor in the normal operating mode.

[0103] In this configuration, during normal operation, the display signal is input to the gate of the P-type drive transistor via the first switch circuit, and then to the gate of the N-type drive transistor via the second switch circuit. This results in a drive signal based on the display signal being output to the electro-optic panel, enabling normal display operation.

[0104] In this embodiment, the constant current setting circuit may also include a first current setting circuit having a P-type transistor and a first current source provided in series between a high-potential power supply voltage node and a low-potential power supply voltage node, with the gate and drain of the P-type transistor connected to the output node. The constant current setting circuit may also include a second current setting circuit having a second current source and an N-type transistor provided in series between a high-potential power supply voltage node and a low-potential power supply voltage node, with the gate and drain of the N-type transistor connected to the output node. In the determination mode, the first switch circuit may connect the output node of the first current setting circuit to the gate of the P-type drive transistor, or the second switch circuit may connect the output node of the second current setting circuit to the gate of the N-type drive transistor.

[0105] In this way, the output node of the first current setting circuit is connected to the gate of the P-type drive transistor, forming a current mirror circuit between the P-type transistor and the P-type drive transistor, causing a constant current to flow through the P-type drive transistor. Similarly, the output node of the second current setting circuit is connected to the gate of the N-type drive transistor, forming a current mirror circuit between the N-type transistor and the N-type drive transistor, causing a constant current to flow through the N-type drive transistor.

[0106] In this embodiment, the driver control circuit may pull down the gate of the N-type drive transistor when the output node of the first current setting circuit and the gate of the P-type drive transistor are connected by the first switch circuit. The driver control circuit may also pull up the gate of the P-type drive transistor when the output node of the second current setting circuit and the gate of the N-type drive transistor are connected by the second switch circuit.

[0107] In this configuration, when the output node of the first current setting circuit is connected to the gate of the P-type drive transistor, the gate of the N-type drive transistor is pulled down and turned off. Conversely, when the output node of the second current setting circuit is connected to the gate of the N-type drive transistor, the gate of the P-type drive transistor is pulled up and turned off.

[0108] Furthermore, in this embodiment, the constant current value may be variable.

[0109] In this way, by adjusting the constant current value, it becomes possible to appropriately adjust the judgment accuracy of the test circuit.

[0110] In this embodiment, the determination circuit may also determine that a short circuit has occurred in the signal line of the drive signal when the comparison result of the comparison circuit does not correspond to the expected value.

[0111] In this way, the judgment circuit can determine the occurrence of a short circuit simply by determining whether the comparison result of the comparison circuit matches the expected value corresponding to the voltage level of the drive signal.

[0112] Furthermore, the display device of this embodiment includes the display driver described above and an electro-optical panel.

[0113] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of the display driver and display device, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of Symbols]

[0114] 10…Display device, 20…Display driver, 30…Driver circuit, 31…Segment driver circuit, 32…Common driver circuit, 33…Pre-buffer circuit, 34…Output driver, 36…Level shifter, 40…Test circuit, 41…Segment test circuit, 42…Common test circuit, 50…Comparison circuit, 52…Comparator, 54…Level shifter, 56…Decision circuit, 58…Reference voltage generation circuit, 60…Driver control circuit, 62…Switching circuit, 64…Constant current setting circuit, 65…Current setting circuit, 66…Current setting circuit, 70…Line latch, 72…Latch, 74…Polarity inversion circuit, 80…Data storage circuit, 100…Control circuit Path, 110…Interface circuit, 120…Oscillator circuit, 200…Electro-optical panel, 300…Processing unit, EL…Display electrode, EV…Expected value, ICS…Constant current value, IS1, IS2…Current source, ISH…Short current value, L1…Signal line, LT…Latch signal, RA1, RA2…Resistor, VR…Reference voltage, RSH…Short resistance value, SD…Drive signal, SM…Monitor signal, SW…Switch, SW1, SW, SW3, SW4, SW5, SW6…Switch circuit, TA1, TA2…Transistor, TQ…Output terminal, TR, TRN, TRP…Drive transistor, VG1, VG2…Gate voltage, VR, VRH, VRL…Reference voltage

Claims

1. A driver circuit that outputs a drive signal to the display electrodes of an electro-optical panel, A driver control circuit that controls the aforementioned driver circuit, Test circuit and, Includes, The aforementioned test circuit is A comparison circuit that compares the voltage of the drive signal with a reference voltage, A determination circuit that determines an abnormality based on the expected value corresponding to the level of the drive signal and the comparison result of the comparison circuit, Includes, The aforementioned driver control circuit is A display driver characterized in that, in the determination mode, the gate of the drive transistor of the driver circuit is controlled so that the drive transistor outputs the drive signal with a constant current.

2. In the display driver described in claim 1, The aforementioned driver control circuit is A constant current setting circuit that generates the gate voltage of the drive transistor to output the drive signal with the constant current, In the normal operation mode, a switching circuit outputs a display signal to the gate of the drive transistor to cause the driver circuit to output the drive signal, and in the determination mode, a switching circuit outputs the gate voltage from the constant current setting circuit to the gate of the drive transistor. A display driver characterized by including the following.

3. In the display driver described in claim 2, The aforementioned driver circuit is The aforementioned drive transistors include a P-type drive transistor and an N-type drive transistor, which are connected in series between the high-potential power supply voltage node and the low-potential power supply voltage node. The aforementioned switching circuit is In the normal operating mode, a first switch circuit outputs the display signal to the gate of the P-type drive transistor, In the normal operating mode, a second switch circuit outputs the display signal to the gate of the N-type drive transistor, A display driver characterized by including the following.

4. In the display driver described in claim 3, The constant current setting circuit is, A first current setting circuit having a P-type transistor and a first current source provided in series between the high-potential power supply voltage node and the low-potential power supply voltage node, wherein the gate and drain of the P-type transistor are connected to the output node, A second current setting circuit having a second current source and an N-type transistor provided in series between the high-potential power supply voltage node and the low-potential power supply voltage node, wherein the gate and drain of the N-type transistor are connected to the output node, Includes, In the aforementioned determination mode, The first switch circuit connects the output node of the first current setting circuit to the gate of the P-type drive transistor, or A display driver characterized in that the second switch circuit connects the output node of the second current setting circuit to the gate of the N-type drive transistor.

5. In the display driver described in claim 4, The aforementioned driver control circuit is When the output node of the first current setting circuit and the gate of the P-type drive transistor are connected by the first switch circuit, the gate of the N-type drive transistor is pulled down. A display driver characterized in that, when the output node of the second current setting circuit and the gate of the N-type drive transistor are connected by the second switch circuit, the gate of the P-type drive transistor is pulled up.

6. In the display driver described in claim 1, A display driver characterized by having a variable constant current value.

7. In the display driver described in claim 1, The aforementioned determination circuit is A display driver characterized in that, when the comparison result of the comparison circuit does not correspond to the expected value, it is determined that a short circuit has occurred in the signal line of the drive signal.

8. A display driver as described in any one of claims 1 to 7, The aforementioned electro-optical panel, A display device characterized by including

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