Information processing device

Abstract

To provide an information processing device that makes the process of recovering a startup program easier than before when there is an abnormality in the startup program stored in the non-volatile memory of one of the two processors. [Solution] The information processing device comprises a first processor, a second processor, and a connecting line. The first processor has a first connection unit and a first storage unit that stores a first startup program. The first processor performs processing according to the first startup program. The second processor has a second connection unit and a second storage unit that stores a second startup program. The second processor performs processing according to the second startup program. The connecting line connects the first connection unit and the second connection unit. If there is an abnormality in the first startup program, the second processor retrieves the first startup program and performs a first write process (S17) to write the first startup program to the first storage unit via the connecting line.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus.

Background Art

[0002] A conventional electronic control device includes two microcontrollers and a circuit. The two microcontrollers usually execute control programs in their own flash memories. When a predetermined writing voltage is supplied and the external code matches their own code, the two microcontrollers update and write the external writing data into their own flash memories. One microcontroller monitors the control program execution state of the other microcontroller as the control program is executed. When one microcontroller determines an abnormality in the other microcontroller, it outputs a reset signal to the other microcontroller. The circuit prevents the reset signal from being input to the other microcontroller when a writing voltage is being supplied to the other microcontroller.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional electronic control device, when there is an abnormality in the startup program stored in the non-volatile memory unit connected to one of the two processors, it is necessary to prepare a special jig and rewrite it with a dedicated program by a technician, which is complicated. The startup program includes a boot program and an OS program.

[0005] An object of the present invention is to provide an information processing apparatus that contributes to making the work of restoring the startup program easier than before when there is an abnormality in the startup program stored in the non-volatile memory unit of one of the two processors.

Means for Solving the Problems

[0006] An information processing apparatus according to one aspect of the present invention includes a first processor having a first connection unit and a non-volatile first storage unit that stores a first startup program, and that processes according to the first startup program; a second processor having a second connection unit and a non-volatile second storage unit that stores a second startup program, and that processes according to the second startup program; and a connecting line connecting the first connection unit and the second connection unit. The second processor, in the event of an abnormality in the first startup program, retrieves the first startup program and executes a first write process that writes the first startup program to the first storage unit via the connecting line. The first write process executed by the second processor of the information processing apparatus according to this aspect contributes to automatic recovery in the event of an abnormality in the first startup program. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram showing the configuration of karaoke system 2. [Figure 2] This is an explanatory diagram showing the electrical connections of the first SoC40, the second SoC50, the microcontroller60, the effect mixing unit12, and the speaker24. [Figure 3] This is a flowchart of the first SoC processing performed by the first CPU 41 and the second SoC processing performed by the second CPU 51. [Figure 4] The following is a timing chart of the processes executed by the first SoC40, the second SoC50, and the microcontroller 60, as a specific example. [Figure 5] This is an explanatory diagram showing the electrical connections of the first SoC40, the second SoC50, the microcontroller60, the effect mixing unit12, and the speaker24. [Figure 6] This is a flowchart of the microcontroller processing performed by microcontroller 60. [Figure 7] This is an explanatory diagram showing the electrical connections of the modified first SoC40, second SoC50, microcontroller60, wireless LAN communication unit17, and LAN communication unit18. [Figure 8]This is an explanatory diagram showing the electrical connections of the modified SoC40, second SoC50, microcontroller 60, and fan 69. [Modes for carrying out the invention]

[0008] The karaoke system 2 shown in Figure 1 is a commercial karaoke system 2 installed, for example, in a karaoke establishment. The karaoke system 2 has the function of playing karaoke songs (hereinafter simply referred to as songs) selected by the user of the karaoke system 2, along with a video that includes lyrics. The karaoke system 2 comprises a karaoke device 1 and a remote control device 3. The karaoke device 1 and the remote control device 3 form a network and communicate with each other via an access point 5 and a LAN 8. The karaoke device 1 is connected to a network 9 via the LAN 8 and a router 6, and can send and receive data with an external device 7.

[0009] Karaoke device 1 is a device that plays songs in accordance with playback instructions received from remote control device 3, based on song data, in sync with video including lyrics. Karaoke device 1 comprises a first SoC 40, a second SoC 50, a microcontroller 60, a switch 21, a circuit 25, an effects / mixing unit 12, an infrared communication unit 16, a wireless LAN communication unit 17, a LAN communication unit 18, an operation unit 19, a temperature sensor 68, a fan 69, an LED 70, and a hard disk drive (HDD) 20.

[0010] The first SoC40, the second SoC50, and the microcontroller 60 are each SoCs (System on a Chip) having a CPU and memory as control units. The first SoC40, the second SoC50, and the microcontroller 60 are each chips that integrate the functions necessary to control the karaoke machine 1.

[0011] As shown in Figure 2, the first SoC 40 comprises a first CPU 41, a first memory unit 42, and a first RAM 43. The first memory unit 42 is a non-volatile memory device. In this embodiment, the first memory unit 42 is a ROM. The first memory unit 42 stores the first startup program. The first startup program is a program executed by the first CPU 41. The first startup program includes a boot program and a program for the first OS (Operating System). In this embodiment, the first OS is Linux (registered trademark). Linux is an OS that has been used in karaoke machines for many years. Linux is designed so that older application programs for karaoke machines (hereinafter referred to as "apps") run on the first OS.

[0012] The first storage unit 42 of this embodiment further stores a second startup program. The second startup program is a program executed by the second CPU 51. The second startup program includes a boot program and a second OS program. The second OS of this embodiment is Android®. Android is an OS for which numerous applications have been developed and are used with the spread of smartphones and the like.

[0013] The first SoC40 further includes MODE46, UART47, RESET48, and first connection section49. MODE46, UART47, and RESET48 are all connection sections for connecting the first SoC40 to the microcontroller 60. MODE46 is a connection section for receiving a signal output from the microcontroller 60 to switch the mode of the first memory unit 42. When MODE46 receives a High signal, it sets the mode of the first memory unit 42 to write mode. When MODE46 receives a Low signal, it sets the mode of the first memory unit 42 to normal mode. UART47 is a connection section for performing asynchronous serial communication with the microcontroller 60. RESET48 is a connection section for receiving an instruction from the microcontroller 60 to reset the first SoC40.

[0014] The first connection section 49 is a connection section for directly connecting the first SoC 40 and the second SoC 50. The first connection section 49 can switch between an input mode that accepts input signals and an output mode that outputs output signals. The first connection section 49 is set to input mode when the system is started up.

[0015] The second SoC 50 comprises a second CPU 51, a second memory unit 52, and a second RAM 53. The second memory unit 52 is a non-volatile memory device. In this embodiment, the second memory unit 52 is a ROM. The second memory unit 52 stores a second startup program. In this embodiment, the second memory unit 52 also stores a first startup program.

[0016] The second SoC50 further includes MODE56, UART57, RESET58, and a second connection section 59. MODE56, UART57, and RESET58 are all connection sections for connecting the second SoC50 to the microcontroller 60. MODE56 is a connection section for receiving a signal output from the microcontroller 60 to switch the mode of the second memory unit 52. UART57 is a connection section for performing asynchronous serial communication with the second SoC50. RESET58 is a connection section for receiving an instruction from the microcontroller 60 to reset the second SoC50.

[0017] The second connection section 59 is a connection section for directly connecting the first SoC 40 and the second SoC 50. The second connection section 59 can switch between an input mode that accepts input signals and an output mode that outputs output signals. The second connection section 59 is set to input mode when started up. The second SoC 50 and the first SoC 40 can communicate via the connection line 81 by switching either the first connection section 49 or the second connection section 59 from input mode to output mode.

[0018] The microcontroller 60 includes GPIO61, 63, 64, 66, and UART62, 65. GPIO61, 63, 64, 66 are connection parts for digital signals. UART62, 65 are connection parts for asynchronous serial communication. GPIO61 is connected to MODE46 via signal line 82. UART62 is connected to UART47 via the first communication line 83. GPIO63 is connected to RESET48 via signal line 84. GPIO64 is connected to MODE56 via signal line 85. UART65 is connected to UART57 via the second communication line 86. GPIO66 is connected to RESET58 via signal line 87. The microcontroller 60 can communicate with the first SoC40 via signal lines 82, 84, and communication line 83. The microcontroller 60 can communicate with the second SoC50 via signal lines 85, 87, and communication line 86.

[0019] As shown in FIG. 1, the first SoC40, the second SoC50, and the microcontroller 60 are each connected to the effect mixing unit 12, the infrared communication unit 16, the wireless LAN communication unit 17, the LAN communication unit 18, the operation unit 19, and the HDD20 via the bus 15.

[0020] The first SoC40 and the second SoC50 of the present embodiment each have a video output function. The switch 21 is connected to each of the first SoC40 and the second SoC50. The switch 21 outputs a video based on the video data output from the first SoC40 or the second SoC50 to the display device 22. The circuit 25 switches the SoC connected to the switch 21 between the first SoC40 and the second SoC50. At startup, the circuit 25 connects the first SoC40 and the switch 21.

[0021] The effect mixing unit 12 mixes the music reproduced by the first SoC40 or the second SoC50 and the voice input from the microphone 23 based on the music data and outputs it to the speaker 24. The effect mixing unit 12 may have a function of applying effects such as echo to the reproduced music and voice.

[0022] As shown in Figure 2, the effects mixing unit 12 includes an AudioMute control circuit 121, an audio output circuit 122, and a circuit 123. The AudioMute control circuit 121 switches whether or not to mute the audio. The audio output circuit 122 outputs music data output from the first SoC 40 or the second SoC 50 to the AudioMute control circuit 121. The circuit 123 switches whether the SoC connected to the AudioMute control circuit 121 is the first SoC 40 or the second SoC 50. At startup, the circuit 123 sets the SoC connected to the AudioMute control circuit 121 to the first SoC 40.

[0023] The infrared communication unit 16, the wireless LAN communication unit 17, and the LAN communication unit 18 function as communication units for the karaoke device 1 and can communicate with various external components of the karaoke device 1. In this embodiment, the karaoke device 1 uses the infrared communication unit 16 to communicate with the remote control device 3 and receives playback instructions from the remote control device 3.

[0024] The karaoke device 1 connects to the LAN 8 via a wired connection using the LAN communication unit 18, and then connects to the network 9. The LAN communication unit 18 is, for example, Ethernet®. The LAN communication unit 18 is controlled by the first SoC 41 when the first startup program stored in the first memory unit 42 is functioning correctly.

[0025] If LAN 8 is unavailable, the karaoke device 1 can connect to network 9 using the wireless LAN communication unit 17. The wireless LAN communication unit 17 is, for example, WiFi (registered trademark). The wireless LAN communication unit 17 is controlled by the second SoC 51 when the second startup program stored in the second memory unit 52 is functioning correctly.

[0026] The control unit 19 can accept various inputs from the user. Requests received from the control unit 19 are used for various processes of the first SoC 40 or the second SoC 50. The temperature sensor 68 outputs a detection result corresponding to the ambient temperature around the temperature sensor 68. The fan 69 is controlled to rotate at a rotation amount corresponding to the detection result output by the temperature sensor.

[0027] LED70 lights up when HDD20 fails, notifying the administrator of karaoke machine 1 that HDD20 has failed. HDD20 is a non-volatile storage device that stores information downloaded from external device 7, various other information, and multiple applications that can be executed on karaoke machine 1.

[0028] The remote control device 3 receives song selections from the user and transmits a playback command specifying the selected song to the karaoke device 1. The remote control device 3 can receive various information from the karaoke device 1 or external device 7 and perform various processes.

[0029] The remote control device 3 comprises a control unit 31, a storage unit 32, a wireless LAN communication unit 33, an infrared communication unit 34, an operation unit 35, an operation processing unit 36, a video RAM 37, a video control unit 38, and a touch panel 39. The control unit 31 is responsible for various processes of the remote control device 3. The storage unit 32 stores a database required for song selection processing, various programs, and various information generated in conjunction with program execution.

[0030] The wireless LAN communication unit 33 and the infrared communication unit 34 each function as communication units for the remote control device 3 and can communicate with various external components of the remote control device 3. The wireless LAN communication unit 33 connects wirelessly to the access point 5. The remote control device 3 is pre-associated with a specific karaoke machine 1. Various commands output from the remote control device 3 are received by the associated karaoke machine 1. The remote control device 3 can use the infrared communication unit 34 to send playback instructions, etc., when reserving songs to the karaoke machine 1.

[0031] The control unit 35 and the touch panel 39 are user interfaces that receive various instructions from the user. The touch panel 39 has a display unit and a touch screen. The touch panel 39 displays various interfaces on its display unit and can also receive touch input from the user.

[0032] The video control unit 38 forms the image to be displayed on the touch panel 39. The video RAM 37 temporarily stores the video information to be displayed on the touch panel 39. The operation processing unit 36 ​​outputs a signal to the control unit 31 in response to input from the touch panel 39 or the operation unit 35.

[0033] This section outlines the process of playing songs on the karaoke system 2. The remote control device 3 provides various information via the display on the touch panel 39. The remote control device 3 receives various inputs from the user via the touch panel 39 or the operation unit 35 and sends a song playback command to the karaoke device 1.

[0034] When karaoke device 1 receives a playback command from remote control device 3, it registers the song specified in the received playback command in the reservation table. Karaoke device 1 retrieves the song data of the song registered in the reservation table and plays the song. Karaoke device 1 mixes the played song based on the song data with the audio input from microphone 23 in the effects mixing unit 12 and outputs the audio from speaker 24. Based on the lyrics data and video data, karaoke device 1 displays the lyrics of the song and the video overlaid on the background video on the display device 22 in synchronization with the playback of the song.

[0035] Referring to Figures 2 to 6, the process executed by the karaoke machine 1 will be explained in the case where there is an abnormality in the first startup program stored in the first memory unit 42. In the karaoke machine 1, when the karaoke machine 1 is started, the first SoC process, the second SoC process, and the microcontroller process are executed in parallel. The first SoC process, the second SoC process, and the microcontroller process are processes to check whether there is an abnormality in the first startup program stored in the first memory unit 42.

[0036] The first SoC processing is performed by the first CPU 41 of the first SoC 40. If there are no abnormalities in the first startup program stored in the first memory unit 42 and the second startup program stored in the second memory unit 52, the first CPU 41 performs processing according to the first startup program. If there is an abnormality in the first startup program stored in the first memory unit 42, the first CPU 41 performs processing to cause the first startup program stored in the second memory unit 52 by the second CPU 51 to be stored in the first memory unit 42. After that, the first CPU 41 restarts the first SoC 40 and performs the first SoC processing again. If there is an abnormality in the second startup program stored in the second memory unit 52, the first CPU 41 performs processing to cause the second startup program stored in the first memory unit 42 to be stored in the second memory unit 52.

[0037] The second SoC processing is performed by the second CPU 51 of the second SoC 50. The second SoC processing is performed by the same program as the first SoC processing. If there are no abnormalities in the first startup program stored in the first memory unit 42 and the second startup program stored in the second memory unit 52, the second CPU 51 performs processing according to the second startup program. If there is an abnormality in the second startup program stored in the second memory unit 52, the second CPU 51 performs processing to cause the second startup program stored in the first memory unit 42 by the first CPU 41 to be stored in the second memory unit 52. After that, the second CPU 51 restarts the second SoC 50 and performs the second SoC processing again. If there is an abnormality in the first startup program stored in the first memory unit 42, the second CPU 51 performs processing to cause the first startup program stored in the second memory unit 52 to be stored in the first memory unit 42.

[0038] Microcontroller processing is performed by the microcontroller 60. If there are no abnormalities in the first startup program stored in the first memory unit 42 and the second startup program stored in the second memory unit 52, the microcontroller 60 performs processing according to the third startup program for the microcontroller 60. If there is an abnormality in at least one of the first startup program stored in the first memory unit 42 and the second startup program stored in the second memory unit 52, the microcontroller 60 performs processing to restart the SoC according to the startup program with the abnormality.

[0039] The following definitions are given for the self-control unit, other-control units, self-SoC, other-SoC, self-start program, other-start program, self-storage unit, and other-storage unit. The self-control unit is the control unit of the self-SoC, which executes processing, among the first CPU 41 and the second CPU 51. The other-control unit is the control unit of the other-SoC, which is different from the self-SoC, among the first CPU 41 and the second CPU 51, which executes processing. The self-start program is the startup program stored in the self-storage unit, which is the storage unit of the self-SoC, among the first-start program and the second-start program. The other-start program is the startup program stored in the other-storage unit, which is the storage unit of the other-SoC, among the first-start program and the second-start program.

[0040] Referring to Figures 3 to 5, the first SoC processing performed by the first CPU 41 will be described. When the karaoke machine 1 is started up, the first CPU 41 reads an information processing program for executing the first SoC processing from the first storage unit 42. The first CPU 41 executes the following steps according to the instructions contained in the program. The program includes instructions for the first CPU 41 to perform the following processing. Various data obtained during the first SoC processing are stored in the temporary area of ​​the first RAM 43.

[0041] As shown in Figures 3 and 4, the first CPU 41 checks the status of the self-start program stored in its own memory, that is, the first start program stored in the first memory unit 42, and outputs the check result to the microcontroller 60 (S1). Based on the check result in S1, the first CPU 41 determines whether or not there is an abnormality in the self-start program stored in its own memory (S2). The method for determining whether or not there is an abnormality in the self-start program can be set as appropriate. For example, the first CPU 41 may determine that there is an abnormality in the self-start program if the data capacity of the self-start program under normal conditions does not match the data capacity of the self-start program stored in the first memory unit 42. The first CPU 41 may also determine that there is an abnormality in the self-start program if the date and time when the self-start program was normally stored or updated does not match the date and time when the self-start program stored in the first memory unit 42 was stored or updated. As another example, when the first CPU 41 starts up, it is configured to perform predetermined communication with the microcontroller 60 via the connection line 81. The first CPU 41 may determine that there is an abnormality in the self-start program if the prescribed communication does not occur during startup. Furthermore, the first CPU 41 may also determine that there is an abnormality in the self-start program after receiving communication from the microcontroller 60.

[0042] In a specific example, the first CPU 41 determines that there is an abnormality in the self-start program stored in the self-storage unit (S2:YES), and increments the detection count of consecutive abnormalities by 1. The initial value of the detection count is 0. The first CPU 41 determines whether the detection count has reached a predetermined number (S3). The predetermined number can be set in advance. The administrator may set the predetermined number, or the manufacturer may set the predetermined number when the karaoke machine 1 is shipped from the factory. For example, the predetermined number is 3. If the detection count has reached the predetermined number (S3:YES), the first CPU 41 terminates the first SoC processing.

[0043] If the number of detections has not reached the specified number (S3:NO), the first CPU 41 determines whether or not it has received a mode switching completion notification from the microcontroller 60 (S4). If the first CPU 41 has not received a mode switching completion notification (S4:NO), it returns to processing S4.

[0044] When the first CPU 41 receives a notification that the mode switch is complete (S4: YES), the mode of the first SoC 40 is switched by the microcontroller 60 from normal mode to write mode (S5). Normal mode is a mode that prohibits writing to the first memory unit 42, and write mode is a mode that releases the prohibition on writing to the first memory unit 42. When the mode is write mode, the first CPU 41 can overwrite the first self-start program in the first memory unit 42. When the mode is normal mode, the first CPU 41 is prohibited from overwriting the self-start program in the first memory unit 42.

[0045] The first CPU 41 determines whether the self-start program writing process has been executed by the other control unit, i.e., the second CPU 51 (S6). If the self-start program writing process has not been executed (S6: NO), the first CPU 41 returns to process S6. If the self-start program writing process has been executed (S6: YES), the first CPU 41 determines whether it has received a reset instruction output from the microcontroller 60 (S7). If the first CPU 41 has not received a reset instruction (S7: NO), it returns to process S7.

[0046] If the first CPU 41 receives a reset command (S7:YES), it resets the first SoC 40 (S8). The first CPU 41 then terminates the first SoC processing. The reset restarts the first SoC processing.

[0047] In the first SoC processing after reboot, if there is no abnormality in the self-start program stored in the self-storage unit (S1, S2: NO), the first CPU 41 resets the detection count to 0. The first CPU 41 determines whether or not there is an abnormality in the other startup program stored in the other storage unit, that is, the second startup program stored in the second storage unit 52 (S11). As will be described later, if the microcontroller 60 obtains an abnormality in the status check result of the second startup program from the second CPU 51, it outputs the check result to the first CPU 41. Based on whether or not it has obtained the status check result of the second startup program transmitted from the microcontroller 60, the first CPU 41 determines whether or not there is an abnormality in the other startup program stored in the other storage unit.

[0048] If there are no abnormalities in the other startup programs stored in the other memory unit (S11: NO), the first CPU 41 executes the self-starting program normally (S21). S21 of the first SoC processing is a process executed according to the first startup program, and includes processing related to karaoke performance and processing for controlling peripheral devices. As processing related to karaoke performance, the first CPU 41 launches an application on the first OS and executes control processing for karaoke performance and karaoke scoring. As processing for controlling peripheral devices, the first CPU 41 executes the following processes: The first CPU 41 executes control of the AudioMute circuit 121. The first CPU 41 executes control of the switch 21. The first CPU 41 executes control of the LAN communication unit 18. The first CPU 41 controls the rotation speed of the fan 69 according to the detection result of the temperature sensor 68. The first CPU 41 then terminates the first SoC processing.

[0049] If there is an abnormality in another startup program stored in the other memory unit (S11:YES), the first CPU 41 executes the processes from S12 to S18 and then returns to S1. The processes from S12 to S18 will be explained in the second SoC processing executed by the second CPU 51.

[0050] Referring to Figures 3 to 5, the second SoC processing performed by the second CPU 51 will be explained. When the karaoke machine 1 is started up, the second CPU 51 reads an information processing program for executing the second SoC processing from the second storage unit 52. The second CPU 51 executes the following steps according to the instructions contained in the program. The program includes instructions for the second CPU 51 to perform the following processing. Various data obtained during the second SoC processing are stored in the temporary area of ​​the second RAM 53.

[0051] As shown in Figures 3 and 4, the second CPU 51 checks the status of the self-start program stored in the self-storage unit, that is, the second-start program stored in the second storage unit 52, and outputs the check result to the microcontroller 60 (S1). Based on the check result of S1, the second CPU 51 determines whether or not there is an abnormality in the self-start program stored in the self-storage unit (S2). If there is an abnormality in the self-start program (S2: YES), the second CPU 51 performs the processing of S3 to S8 with the second-start program as the self-start program, similar to the processing of S3 to S8 performed by the first CPU 41.

[0052] If there is no abnormality in the self-starting program (S2:NO), the second CPU 51 resets the detection count to 0. Based on the notification from the microcontroller 60, the second CPU 51 determines whether or not there is an abnormality in the other startup programs stored in the other memory unit (S11). As will be described later, if the microcontroller 60 obtains an abnormality in the status check result of the first startup program from the first CPU 41, it outputs the check result to the second CPU 51. Based on whether or not it has obtained the status check result of the first startup program transmitted from the microcontroller 60, the second CPU 51 determines whether or not there is an abnormality in the other startup programs.

[0053] If there are no abnormalities in other startup programs (S11: NO), the second CPU 51 executes the self-starting program normally (S21). S21 of the second SoC processing is a process executed according to the second startup program and includes processing related to karaoke effects and processing to control peripheral devices. As processing related to karaoke effects, the second CPU 51 launches an application on the second OS and executes lyric display, background video display, sound effects, and lighting control processing. As processing to control peripheral devices, the second CPU 51 executes control of the wireless LAN communication unit 17. On the other hand, the second CPU 51 does not execute control of the AudioMute circuit 121. The second CPU 51 does not execute control of the switch 21. The second CPU 51 then terminates the second SoC processing.

[0054] In this specific example, the second CPU 51 determines that there is an abnormality in the first startup program stored in the first memory unit 42 (S11: YES). The second CPU 51 controls circuit 123 to switch the SoC connected to the AudioMute control circuit 121 from the first SoC 40 to the second SoC 50 (S12). As shown in Figure 2, when the first startup program stored in the first memory unit 42 is normal, the first CPU 41 controls the AudioMute control circuit 121. As shown in Figure 5, the process in S12 enables the second CPU 51 to control the AudioMute control circuit 121. In other words, the process in S12 enables the second CPU 51 to output sound from the speaker 24.

[0055] In this embodiment, the second CPU 51 further controls the circuit 25 to switch the SoC connected to the switch 21 from the first SoC 40 to the second SoC 50 (S12). When the first startup program stored in the first memory unit 42 is normal, the first CPU 41 controls the switch 21. As a result of the process in S12, the second CPU 51 becomes capable of controlling the switch 21.

[0056] The second CPU 51 controls peripheral devices connected to circuit 123 via circuit 123 (S13). Specifically, the second CPU 51 controls the AudioMute control circuit 121 to set speaker 24 to output sound based on data output from the second CPU 51. The second CPU 51 controls speaker 24 to notify of an abnormality in another startup program (S13). For example, the second CPU 51 outputs the message "An abnormality has been detected. Please wait a while until recovery is complete." from speaker 24.

[0057] In this embodiment, the second CPU 51 further sets the display device 22 to a state where it can output video via the circuit 25. The second CPU 51 controls the display device 22 to notify of an abnormality in another startup program (S13). For example, the second CPU 51 displays the message "An abnormality has been detected. Please wait a while until recovery is complete." on the display device 22.

[0058] The second CPU 51 switches its own connection section, i.e., the second connection section 59, from input mode to output mode (S14). The second CPU 51 outputs a notification to the microcontroller 60 that the switch is complete (S15). The second CPU 51 determines whether or not it has received the mode switch completion notification from the microcontroller 60 (S16). If the second CPU 51 has not received the mode switch completion notification (S16: NO), the second CPU 51 returns to processing S16.

[0059] When the second CPU 51 receives a notification that the mode switching is complete (S16: YES), it retrieves the other startup program and executes a write operation to write it to the other memory unit (S17). The path for retrieving the other startup program can be set as appropriate. In this embodiment, the second CPU 51 retrieves the first startup program stored in the second memory unit 52 and overwrites the first memory unit 42 via the connection line 81. The second CPU 51 switches its own connection unit from output mode to input mode. The second CPU 51 outputs a notification that the write operation is complete to the microcontroller 60 (S18). The second CPU 51 returns the process to S1.

[0060] After the first SoC 40 restarts, the second CPU 51 determines that there are no abnormalities in the self-start program and other startup programs (S1, S2: NO, S11: NO). The second CPU 51 executes the self-start program, i.e., the second startup program, normally (S21). The second CPU 51 then terminates the second SoC processing.

[0061] The microcontroller processing will be explained with reference to Figures 4 to 6. When the karaoke machine 1 is started up, the microcontroller 60 reads an information processing program for executing the microcontroller processing. The microcontroller 60 executes the following steps according to the instructions contained in the program. The program contains instructions for the microcontroller 60 to execute the following processes. Various data obtained during the microcontroller processing are stored in the temporary area of ​​the memory unit of the microcontroller 60.

[0062] As shown in Figures 4 and 6, the microcontroller 60 checks the status of the first startup program and the second startup program based on the confirmation result of the first startup program output by the first CPU 41 and the confirmation result of the second startup program output by the second CPU 51 (S31). If the microcontroller 60 does not obtain a confirmation result from the first CPU 41 within a predetermined period after startup, it sets an abnormality in the confirmation result of the first startup program. If the microcontroller 60 does not obtain a confirmation result from the second CPU 51 within a predetermined period after startup, it sets an abnormality in the confirmation result of the second startup program.

[0063] The microcontroller 60 determines whether there is an abnormality in both the first startup program stored in the first memory unit 42 and the second startup program stored in the second memory unit 52 (S32). If there is an abnormality in both the first startup program and the second startup program (S32: YES), the microcontroller 60 notifies the microcontroller of the abnormality in both the first startup program and the second startup program (S35). The notification method in S35 may be set as appropriate. For example, the microcontroller 60 outputs the message "An abnormality has been detected. Please wait a while until it is restored." from the speaker 24. The microcontroller 60 may also notify the microcontroller of the abnormality by blinking or lighting up the LED 70. The microcontroller 60 then terminates its microcontroller processing.

[0064] If there are no abnormalities in either or both of the first and second startup programs (S32: NO), the microcontroller 60 determines whether there is an abnormality in either the first or second startup program (S33). If there are no abnormalities in either the first or second startup program (S33: NO), the microcontroller 60 executes the microcontroller startup program normally (S34). The microcontroller 60 then terminates its microcontroller processing.

[0065] If there is an abnormality in either the first startup program or the second startup program (S33:YES), the microcomputer 60 determines whether or not there is an abnormality in the first startup program stored in the first storage unit 42 (S41). If there is an abnormality in the first startup program stored in the first storage unit 42 (S41:YES), the microcomputer 60 increments the detection count of consecutive abnormalities detected in the first startup program stored in the first storage unit 42 by 1. The initial value of the detection count is 0.

[0066] The microcontroller 60 determines whether the number of times an abnormality has been detected in the first startup program stored in the first memory unit 42 has reached a predetermined number (S42). The predetermined number in S42 is the same as the predetermined number in S3. If the number of detections reaches the predetermined number (S42: YES), the microcontroller 60 notifies that an abnormality has been detected in the first startup program (S35). The microcontroller 60 outputs the message "An abnormality has been detected, so we will terminate." from the speaker 24, for example. The microcontroller 60 then terminates its processing.

[0067] If the number of detections has not reached the specified number (S42: NO), the microcontroller 60 notifies the second CPU 51 of the second SoC 50 of an abnormality in the first startup program via the second communication line 86 (S43). The microcontroller 60 determines whether or not it has received the switching completion notification output by the second CPU 51 of the second SoC 50 (S44). If the microcontroller 60 has not received the switching completion notification output by the second CPU 51 (S44: NO), it returns to processing S44.

[0068] When the microcontroller 60 receives a switching completion notification output by the second CPU 51 (S44: YES), the microcontroller 60 performs mode switching processing (S45). The microcontroller 60 switches the mode of the first memory unit 42 from normal mode to write mode by outputting a High signal to the first SoC 40 via the signal line 82. This allows the second CPU 51 to overwrite the first startup program in the first memory unit 42. The microcontroller 60 outputs a mode switching completion notification to the first CPU 41 of the first SoC 40 via the first communication line 83 (S46). The microcontroller 60 also outputs to the second CPU 51 of the second SoC 50 via the second communication line 86 (S46).

[0069] The microcontroller 60 prohibits the reset of the first SoC 40 (S47). The microcontroller 60 determines whether the first write process has been completed based on whether it has received a write process completion notification from the second CPU 51 (S48). The first write process is the process in S17 executed by the second CPU 51. Specifically, the first write process is the process of storing the first startup program stored in the second memory unit 52 in the first memory unit 42 based on instructions from the second CPU 51 output via the connection line 81. If the first write process has not been completed (S48: NO), the microcontroller 60 returns to process S48.

[0070] If the first write operation is completed (S48: YES), the microcontroller 60 releases the reset prohibition for the first SoC 40 (S49). The microcontroller 60 outputs an instruction to the first CPU 41 via signal line 84 to perform a reset of the first SoC 40 (S50). The first CPU 41 resets the first SoC 40 based on the instruction output from the microcontroller 60. The microcontroller 60 returns to processing S31.

[0071] If the second startup program stored in the second storage unit 52 is abnormal, rather than the first startup program stored in the first storage unit 42 (S41: NO), the microcontroller 60 increments the detection count of consecutive abnormalities detected in the second startup program stored in the second storage unit 52 by 1. The initial value of the detection count is 0. The microcontroller 60 determines whether the number of detections in which the second startup program has been judged to be abnormal has reached a predetermined number (S61). The predetermined number in S61 is the same as the predetermined number in S3. If the detection count reaches the predetermined number (S61: YES), the microcontroller 60 notifies the microcontroller 60 of the abnormality in the second startup program (S35). The microcontroller 60 outputs the message "An abnormality has been detected, so we will terminate." from the speaker 24, for example. The microcontroller 60 then terminates its microcontroller processing.

[0072] If the number of detections has not reached the specified number (S61: NO), the microcontroller 60 notifies the first CPU 41 of the first SoC 40 of an abnormality in the second startup program via the first communication line 83 (S62). The microcontroller 60 determines whether or not it has received the switching completion notification output by the first CPU 41 (S63). If the microcontroller 60 has not received the switching completion notification output by the first CPU 41 (S63: NO), it returns to processing S63.

[0073] When the microcontroller 60 receives a switching completion notification output by the first CPU 41 (S63: YES), it performs mode switching processing (S64). The microcontroller 60 switches the mode of the second memory unit 52 from normal mode to write mode by outputting a High signal to the first SoC 40 via signal line 85. This allows the first CPU 41 to overwrite the second startup program in the second memory unit 52. The microcontroller 60 outputs a mode switching completion notification to both the first CPU 41 and the second CPU 51, similar to the processing in S46 (S65).

[0074] The microcontroller 60 prohibits the reset of the second SoC 50 (S66). The microcontroller 60 determines whether the second write process has been completed based on whether it has received a write process completion notification from the first CPU 41 (S67). The second write process is the process in S17 executed by the first CPU 41. Specifically, the second write process is the process of storing the second startup program stored in the first memory unit 42 in the second memory unit 52 based on instructions from the first CPU 41 output via the connection line 81. If the second write process has not been completed (S67: NO), the microcontroller 60 returns to processing S67.

[0075] If the second write process is completed (S67: YES), the microcontroller 60 releases the reset prohibition for the second SoC 50 (S68). The microcontroller 60 outputs an instruction to the second CPU 51 via signal line 87 to perform a reset of the second SoC 50 (S69). The second CPU 51 resets the second SoC 50 based on the instruction output from the microcontroller 60. The microcontroller 60 returns to processing S31.

[0076] If, after processing S50 or S69, neither the first startup program stored in the first storage unit 42 nor the second startup program stored in the second storage unit 52 is abnormal (S31, S32: NO, S33: NO), the microcontroller 60 executes the microcontroller startup program normally (S34). The microcontroller 60 then terminates its microcontroller processing.

[0077] As described above, in the karaoke device 1, if there is an abnormality in the first startup program stored in the first memory unit 42, the second CPU 51 executes a process to overwrite the first startup program stored in the second memory unit 52 with the first startup program stored in the first memory unit 42. As a result, even if the first CPU 41 has accidentally modified the first startup program, the karaoke device 1 can overwrite it with a normal first startup program without using any special tools.

[0078] The karaoke device 1 executes the same process as when there is an abnormality in the first startup program stored in the first memory unit 42, in the case when there is an abnormality in the second startup program stored in the second memory unit 52. If there is an abnormality in the second startup program stored in the second memory unit 52, the karaoke device 1 executes the process of overwriting the second startup program stored in the first memory unit 42 with the second startup program stored in the second memory unit 52 using the first CPU 41. As a result, even if the second CPU 51 has erroneously modified the second startup program, the karaoke device 1 can overwrite it with a normal second startup program without using any special tools.

[0079] In the first SoC processing, the processes in S12 and S13 may be omitted if there is an abnormality in the second startup program stored in the second memory unit 52. In S12 and S13, the karaoke device 1 may perform a process to notify an external device of the abnormality in the second startup program via the wireless LAN communication unit 17 controlled by the second SoC 50, when the second startup program stored in the second memory unit 52 is normal.

[0080] In this case, as shown in Figure 7, for example, the karaoke device 1 may include circuits 26 and 27. Circuit 26 switches the SoC connected to the LAN communication unit 18 between the first SoC 40 and the second SoC 50. Circuit 26 sets the SoC connected to the LAN communication unit 18 to the first SoC 40 when the first startup program stored in the first memory unit 42 is normal. Circuit 27 switches the SoC connected to the wireless LAN communication unit 17 between the first SoC 40 and the second SoC 50. Circuit 27 sets the SoC connected to the wireless LAN communication unit 17 to the second SoC 50 when the second startup program stored in the second memory unit 52 is normal.

[0081] If there is an abnormality in the second startup program stored in the second memory unit 52 (S2: NO, S11: YES), the first CPU 41 may, in S12 of the first SoC processing, control the circuit 27 to switch the SoC connected to the LAN communication unit 18 from the second SoC 50 to the first SoC 40. In S13 of the first SoC processing, the first CPU 41 may notify external devices of the abnormality in the second startup program via the wireless LAN communication unit 17.

[0082] The processing in S12 and S13 when there is an abnormality in the other startup program stored in the other memory unit may be appropriately modified depending on the peripheral equipment provided by the karaoke device 1 or the peripheral equipment connected to the karaoke device 1. The peripheral equipment may be a fan 69. In this case, the karaoke device 1 may be equipped with a circuit 28 as shown in Figure 8. The circuit 28 switches the SoC connected to the fan 69 between the first SoC 40 and the second SoC. The circuit 28 sets the SoC connected to the fan 69 to the first SoC 40 when the first startup program stored in the first memory unit 42 is normal.

[0083] In the second SoC processing, if there is an abnormality in the first startup program stored in the first memory unit 42 (S2: NO, S11: YES), the second CPU 51 may, in S12 of the second SoC processing, control the circuit 28 to switch the SoC connected to the fan 69 from the first SoC 40 to the second SoC 50. In S13 of the second SoC processing, the second CPU 51 may execute a process to control the rotation amount of the fan 69 according to the output result of the temperature sensor 68. At this time, the second CPU 51 may or may not notify the system via the speaker 24 or display device 22 that there is an abnormality in the first startup program stored in the first memory unit 42.

[0084] In the above embodiment, the karaoke device 1 is an example of the information processing device of the present invention. The wireless LAN communication unit 17 and the LAN communication unit 18 are examples of network equipment of the present invention. The display device 22 is an example of video output equipment of the present invention. The speaker 24 is an example of audio output equipment of the present invention. The first SoC 40 is an example of the first processor of the present invention. The first storage unit 42 is an example of the first storage unit of the present invention. The first connection unit 49 is an example of the first connection unit of the present invention. The second SoC 50 is an example of the second processor of the present invention. The second storage unit 52 is an example of the second storage unit of the present invention. The second connection unit 59 is an example of the second connection unit of the present invention. The microcontroller 60 is an example of the third processor of the present invention. The fan 69 is an example of the fan of the present invention. The connection line 81 is an example of the connection line of the present invention. The signal line 82 is an example of the signal line of the present invention. The first communication line 83 is an example of the first communication line of the present invention. The second communication line 86 is an example of the second communication line of the present invention. The S17 process of the second SoC process is an example of the first write process of the present invention. The S17 process of the first SoC process is an example of the second write process of the present invention. The S14 process of the second SoC process is an example of the switching process of the present invention. The S45 process is an example of the setting process of the present invention. The S43 process is an example of the output process of the present invention. The S21 process of the first SoC process is an example of the first control process. The S13 process of the second SoC process is an example of the second control process.

[0085] The karaoke device 1 of the above embodiment comprises a first SoC 40, a second SoC 50, and a connecting line 81. The first SoC 40 has a first connection unit 49 and a non-volatile first storage unit 42 that stores a first startup program. The first SoC 40 performs processing according to the first startup program. The second SoC 50 has a second connection unit 59 and a non-volatile second storage unit 52 that stores a second startup program. The second SoC 50 performs processing according to the second startup program. The connecting line 81 connects the first connection unit 49 and the second connection unit 59. If there is an abnormality in the first startup program, the second SoC 50 retrieves the first startup program and performs a first write process (S17) to write the first startup program to the first storage unit 42 via the connecting line 81. The first write process performed by the second SoC 50 of the karaoke device 1 contributes to automatic recovery in the event of an abnormality in the first startup program.

[0086] The first SoC 40 performs a second write operation (S17) to retrieve the second startup program stored in the second memory unit 52 and write it to the second memory unit 52 if there is an abnormality in the second startup program stored in the second memory unit 52. The second write operation performed by the first SoC 40 of the karaoke device 1 contributes to the automatic recovery of the second startup program stored in the second memory unit 52 if there is an abnormality in it.

[0087] The second connection unit 59 can switch its operating mode between an input mode that accepts input signals and an output mode that outputs output signals. If there is an abnormality in the first startup program stored in the first memory unit 42, the second SoC 50 performs a switching process to switch the operating mode of the second connection unit 59 from input mode to output mode before the first write process (S14). If there is an abnormality in the first startup program stored in the first memory unit 42, the first SoC 40 may not be able to switch the mode of the first connection unit 49. For this reason, the karaoke device 1 keeps the first connection unit 49 and the second connection unit 59 in input mode as their normal settings. If there is an abnormality in the first startup program stored in the first memory unit 42, the second SoC 50 switches the setting of the second connection unit 59 from input mode to output mode. Therefore, the switching process performed by the second SoC 50 of the karaoke device 1 contributes to the smooth execution of the first write process compared to the case where the first SoC 40 switches the mode of the first connection unit 49 when there is an abnormality in the first startup program.

[0088] The karaoke device 1 includes a microcontroller 60 connected to the first SoC 40 by a signal line 82. If there is an abnormality in the first startup program stored in the first memory unit 42, the microcontroller 60 performs a setting process via the signal line 82 before the first write process, changing from the normal mode, which prohibits writing to the first memory unit 42 from the first SoC 40, to a write mode, which releases the prohibition on writing to the first memory unit 42 (S45). The setting process performed by the microcontroller 60 of the karaoke device 1 helps to prevent unintended writing to the first memory unit 42.

[0089] The karaoke device 1 further includes a microcontroller 60 connected to the first SoC 40 by a signal line 82. When there is an abnormality in the first startup program stored in the first memory unit 42, the microcontroller 60 performs a setting process via the signal line 82 to change from the normal mode, which prohibits writing to the first memory unit 42 of the first SoC 40, to a write mode, which releases the prohibition on writing to the first memory unit 42, after the second SoC 50 has performed a switching process (S12, S63: YES) and before the first write process (S45). From the viewpoint of reducing the possibility of unintended noise being written to the first memory unit 42, it is preferable that the time between the setting process and the first write process be short. The setting process performed by the microcontroller 60 of the karaoke device 1 in this embodiment contributes to avoiding unintended writing to the first memory unit 42 compared to when the setting process is performed before the switching process.

[0090] The microcontroller 60 is further connected to the first SoC 40 via a first communication line 83 for communication with the first SoC 40. The microcontroller 60 is connected to the second SoC 50 via a second communication line 86 for communication with the second SoC 50. The microcontroller 60 performs output processing (S43) to output to the second SoC 50 via the second communication line 86 the result of checking whether there is an abnormality in the first startup program of the first SoC 40, which was obtained via the first communication line 83 (S43). In the first write process, if there is an abnormality in the first startup program stored in the first memory unit 42 based on the check result (S11: YES), the second SoC 50 obtains the first startup program and writes the first startup program to the first memory unit 42 via the connection line 81 (S17). The output processing performed by the microcontroller 60 of the karaoke device 1 contributes to simplifying the processing performed by the second SoC 50 compared to when the second SoC 50 directly checks for an abnormality in the first startup program.

[0091] The karaoke device 1 includes a circuit 123 that switches the processor controlling the peripheral device, the speaker 24, from the first SoC 40 to the second SoC 50. The karaoke device 1 also includes a circuit 123 that switches the processor controlling the peripheral device, the display device 22, from the first SoC 40 to the second SoC 50. The first SoC 40 executes a first control process (S21) to control the peripheral devices according to the first startup program. The second SoC 50 does not control the peripheral devices if there is no abnormality in the first startup program stored in the first memory unit 42. If there is an abnormality in the first startup program stored in the first memory unit 42, the second SoC 50 controls the circuit to switch the processor connected to the peripheral devices from the first SoC 40 to the second SoC 50 (S12), and executes a second control process to control the peripheral devices (S13). The second SoC 50 of the karaoke device 1 also contributes to controlling the peripheral devices even if there is an abnormality in the first startup program stored in the first memory unit 42.

[0092] The peripheral devices are at least one of the following: LAN communication unit 18, wireless LAN communication unit 17, speaker 24, display device 22, and fan 69. The peripheral devices of the karaoke machine 1 contribute to controlling at least one of the peripheral devices, which are the network device, speaker 24, display device 22, and fan 69, in the event of an abnormality in the first startup program stored in the first storage unit 42.

[0093] The peripheral devices are at least one of the LAN communication unit 18, the wireless LAN communication unit 17, the speaker 24, and the display device 22. In the second control process, the second SoC 50 performs a notification process (S13) in which the peripheral devices notify that there is an abnormality in the first startup program stored in the first storage unit 42. The peripheral devices of the karaoke machine 1 contribute to notifying the abnormality of the first startup program stored in the first storage unit 42 by at least one of the network devices, the speaker 24, and the display device 22.

[0094] If the peripheral device is a fan 69, the second SoC 50 performs an air cooling process in the second control process to air cool the inside of the karaoke device 1 using the peripheral device (S13). The peripheral device of the karaoke device 1 also contributes to air cooling the inside of the karaoke device 1 even if there is an abnormality in the first startup program stored in the first memory unit 42.

[0095] The second memory unit 52 stores the first startup program. In the first write operation, if there is an abnormality in the first startup program stored in the first memory unit 42, the second SoC 50 retrieves the first startup program stored in the second memory unit 52 and writes the first startup program to the first memory unit 42 via the connection line 81. The second memory unit 52 of the karaoke device 1 contributes to facilitating the process of retrieving the first startup program.

[0096] The information processing apparatus of the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit of the invention. For example, the following modifications may be made as appropriate.

[0097] The information processing device is not limited to the karaoke machine 1, but may be implemented using various information processing devices such as the remote control device 3, a smartphone owned by the user, a personal computer and game console installed in the home, etc. The karaoke machine 1 may be equipped with two SoCs, or four or more SoCs. The first processor, second processor, and third processor may be any electronic device capable of performing various processes, and do not have to be an SoC.

[0098] The karaoke device 1 may include at least one of the following peripheral devices: a LAN communication unit 18, a wireless LAN communication unit 17, a remote control device 3, a fan 69, a display device 22, a microphone 23, and a speaker 24. The karaoke device 1 may be connected by wired or wireless means to an input unit such as a keyboard, mouse, and joystick instead of the remote control device 3. The karaoke device 1 may include only one of the wireless LAN communication unit 17 and the LAN communication unit 18 as network equipment. The first storage unit 42 may be eMMC and other types of non-volatile storage devices such as flash memory. The second storage unit 52 may be eMMC and other types of non-volatile storage devices such as flash memory. The fan 69 may be omitted, or two or more fans may be provided.

[0099] The program containing the instructions for executing the processes shown in Figures 3 and 6 only needs to be stored in the memory of each SoC before the processor of the karaoke machine 1 executes the corresponding program. Therefore, the method of acquiring the program, the acquisition path, and the device for storing the program can each be changed as appropriate. The program executed by the SoC may be received from other devices via cable or wireless communication and stored in a memory device such as a memory unit. Other devices include, for example, a PC and a server connected via a network.

[0100] Each step of the first SoC processing is not limited to being performed by the first CPU 41, and some or all of it may be performed by other electronic devices (e.g., ASICs). Each step of the first SoC processing may be distributed among multiple electronic devices (e.g., multiple CPUs) or performed by a single electronic device. Each step of the first SoC processing can be reordered, omitted, or added as needed.

[0101] Each step of the second SoC processing is not limited to being performed by the second CPU 51, and some or all of it may be performed by other electronic devices (e.g., ASICs). Each step of the second SoC processing may be distributed among multiple electronic devices (e.g., multiple CPUs) or performed by a single electronic device. The order of each step of the second SoC processing can be changed, steps omitted, and additions made as needed.

[0102] Each step of the microcontroller processing is not limited to being performed by the microcontroller 60, but may be partially or entirely performed by other electronic devices (e.g., ASICs). Each step of the microcontroller processing may be distributed among multiple electronic devices (e.g., multiple CPUs) or performed by a single electronic device. Each step of the microcontroller processing can be reordered, omitted, or added as needed.

[0103] The following modifications may be made to the first SoC processing, the second SoC processing, and the microcontroller processing as appropriate. The first SoC 40 may omit the second write processing. In this case, the first storage unit 42 does not need to store the second startup program. If the first SoC 40 omits the second write processing, the second connection unit 59 may not be able to switch between an input mode that accepts input signals and an output mode that outputs output signals. The second SoC 50 may omit the switching processing.

[0104] The karaoke device 1 may omit the microcontroller 60. The microcontroller 60 does not need to be connected to the first SoC 40 via the signal line 82. The microcontroller 60 may omit the setup process. The timing of the microcontroller 60's execution of the setup process may be changed, and it may be performed before the second SoC 50 performs the switching process. The first storage unit 42 may not be able to change its mode. From the viewpoint of reducing the possibility of unintended noise being written to the storage unit, the microcontroller 60 may, after receiving the notification of completion of the first write process (S48:YES) and before processing S49, execute a process via the signal line 82 to set the mode of the first storage unit 42 from write mode to normal mode. The microcontroller 60 may, after receiving the notification of completion of the second write process (S67:YES) and before processing S68, execute a process via the signal line 85 to set the mode of the second storage unit 52 from write mode to normal mode.

[0105] The karaoke device 1 may omit any of the first SoC40, the second SoC50, or the microcontroller 60. The karaoke device 1 may use the first SoC40 as the first processor and the microcontroller 60 as the second processor. The karaoke device 1 may use the second SoC50 as the first processor and either the first SoC40 or the microcontroller 60 as the second processor.

[0106] The microcontroller 60 does not need to be connected to the first SoC 40 via the first communication line 83. The microcontroller 60 does not need to be connected to the second SoC 50 via the second communication line 86. Output processing of the microcontroller 60 may be omitted. The second SoC 50 may obtain the verification result of the first startup program from the first SoC 40. The first SoC 40 may obtain the verification result of the second startup program from the second SoC 50.

[0107] The karaoke device 1 may omit circuits 26 to 28 and 123 as appropriate in accordance with S12 and S13. The first SoC 40 may omit the first control processing. The second SoC 50 may control peripheral devices if there is no abnormality in the first startup program. The second SoC 50 may omit the second control processing.

[0108] The peripheral devices of the karaoke machine 1 may be at least one of the LAN communication unit 18, wireless LAN communication unit 17, speaker 24, display device 22, and fan 69, or other devices. The peripheral devices may be controlled by any of the processors provided by the karaoke machine 1, including the first SoC 40, the second SoC 50, and the microcontroller 60. The karaoke machine 1 may appropriately modify the processing of S13 depending on the peripheral devices. For example, the karaoke machine 1 may omit the notification processing or air cooling processing of S13. The air cooling processing may be a process that controls the rotation of the fan 69 at a predetermined rotation speed, regardless of the detection result of the temperature sensor 68. The karaoke machine 1 may have the microcontroller 60 execute the processing of S13.

[0109] The first storage unit 42 does not need to store the second boot program. In this case, the first SoC 40 may obtain the second boot program from another storage unit, such as the HDD 20. The first SoC 40 may also obtain the second boot program from an external device via network equipment such as the LAN communication unit 18 and the wireless LAN communication unit 17. The first boot program stored in the first storage unit 42 may be modified as appropriate; for example, the first boot program may include an OS other than the first OS.

[0110] The second memory unit 52 does not need to store the first boot program. In this case, the second SoC 50 may obtain the first boot program from another memory unit, such as the HDD 20. The second SoC 50 may also obtain the first boot program from an external device via network equipment such as the LAN communication unit 18 and the wireless LAN communication unit 17. The second boot program stored in the second memory unit 52 may be modified as appropriate, and for example, the second boot program may include an OS other than the second OS.

[0111] The above modifications may be combined as appropriate, provided they are not contradictory. In addition to the combinations exemplified in the claims, the applicant intends to obtain patent rights for embodiments that combine each other in a manner that does not depart from the spirit of the present invention and is not contradictory. [Explanation of Symbols]

[0112] 1: Karaoke device, 17: Wireless LAN communication unit, 18: LAN communication unit, 22: Display device, 24: Speaker, 40: First SoC, 41: First CPU, 42: First memory unit, 49: First connection unit, 50: Second SoC, 51: Second CPU, 52: Second memory unit, 59: Second connection unit, 60: Microcontroller, 69: Fan, 81: Connection line, 82: Signal line, 83: First communication line, 86: Second communication line

Claims

1. A first processor having a first connection unit and a non-volatile first storage unit that stores a first startup program, and which performs processing according to the first startup program, A second processor having a second connection unit and a non-volatile second storage unit that stores a second startup program, and which performs processing according to the second startup program, A connecting wire connecting the first connection part and the second connection part. Equipped with, The information processing apparatus is characterized in that, when there is an abnormality in the first startup program, the second processor retrieves the first startup program and performs a first write operation to write the first startup program to the first storage unit via the connection line.

2. The information processing apparatus according to claim 1, characterized in that the first processor, when there is an abnormality in the second startup program, retrieves the second startup program and performs a second write operation to write it to the second storage unit.

3. The second connection unit is capable of switching between an input mode that accepts an input signal and an output mode that outputs an output signal. The aforementioned second processor is The information processing apparatus according to claim 2, characterized in that, if there is an abnormality in the first startup program, a switching process is further executed before the first writing process to switch the operating mode of the second connection unit from the input mode to the output mode.

4. The system further comprises a third processor connected to the first processor by a signal line, The aforementioned third processor is The information processing apparatus according to claim 1, characterized in that, if there is an abnormality in the first startup program, before the first write operation, a setting operation is performed via the signal line to change the first processor from a normal mode that prohibits writing to the first storage unit to a write mode that releases the prohibition on writing to the first storage unit.

5. The system further comprises a third processor connected to the first processor by a signal line, The aforementioned third processor is The information processing apparatus according to claim 3, characterized in that, if there is an abnormality in the first startup program, the second processor executes a setting process via the signal line to change from a normal mode in which writing to the first storage unit of the first processor is prohibited to a write mode in which the prohibition on writing to the first storage unit is lifted, after executing the switching process and before the first write process.

6. The aforementioned third processor is The first processor is further connected to the first processor via a first communication line that communicates with the first processor, The second processor is connected to the second processor via a second communication line that communicates with the second processor, Further output processing is performed to output the result of checking whether there is an abnormality in the first startup program of the first processor, which was obtained via the first communication line, to the second processor via the second communication line. The information processing apparatus according to claim 4 or 5, characterized in that, in the first write process, if there is an abnormality in the first start program based on the confirmation result, the second processor obtains the first start program and writes the first start program to the first storage unit via the connection line.

7. A circuit that switches the processor controlling peripheral devices from the first processor to the second processor, Furthermore, The first processor further executes a first control process to control the peripheral device in accordance with the first startup program. The information processing apparatus according to any one of claims 1 to 5, characterized in that the second processor does not control the peripheral device when there is no abnormality in the first startup program, and when there is an abnormality in the first startup program, it controls the circuit to switch the processor connected to the peripheral device from the first processor to the second processor and further executes a second control process to control the peripheral device.

8. The information processing apparatus according to claim 7, characterized in that the peripheral device is at least one of a network device, an audio output device, a video output device, and a fan.

9. The peripheral device is at least one of the network device, the audio output device, and the video output device. The information processing apparatus according to claim 8, characterized in that the second processor further performs a notification process in the second control process to notify the peripheral device that there is an abnormality in the first startup program.

10. The aforementioned peripheral device is the fan, The information processing apparatus according to claim 8, characterized in that the second processor further performs an air cooling process in which the peripheral equipment air cools the inside of the device.

11. The second memory unit stores the first startup program, The information processing apparatus according to any one of claims 1 to 5, characterized in that, in the first write operation, if there is an abnormality in the first startup program, the second processor retrieves the first startup program stored in the second storage unit and writes the first startup program to the first storage unit via the connection line.

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