Power supply unit and image forming apparatus

Abstract

This reduces inrush current in power supply devices that have multiple power supply units. [Solution] The first relay is connected between the AC power supply and the input of the first power supply unit, and has an ON state that supplies AC to the first power supply unit and an OFF state that does not supply AC to the first power supply unit. The second relay is connected between the AC power supply and the input of the second power supply unit, and has an ON state that supplies AC to the second power supply unit and an OFF state that does not supply AC to the second power supply unit. When the interlock switch transitions from the first state to the second state, the first relay switches from the OFF state to the ON state when a first delay time has elapsed from the time the transition to the second state occurred. The second relay switches from the OFF state to the ON state when a second delay time, which is longer than the first delay time, has elapsed from the time the transition to the second state occurred.

Description

Technical Field

[0004] , ,

[0001] The present invention relates to a power supply device and an image forming apparatus.

Background Art

[0002] An interlock switch is a switch that stops the supply of power from a power supply unit to a protected area when a member (e.g., a door, a drawer) provided at the entrance of the protected area is opened. When the interlock switch switches from off to on when the member is closed, an inrush current may flow into the power supply unit. According to Patent Document 1, it has been proposed to start up the power supply unit after a predetermined delay time has elapsed since the interlock switch is turned on. Thereby, it is said that the inrush current generated when the interlock switch is turned off / on is suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An image forming apparatus has a number of loads with different characteristics such as motors and heaters. In order to drive these loads, a plurality of power supply units (e.g., an AC / DC conversion circuit, a DC / DC conversion circuit) for generating a plurality of different DC voltages from an AC voltage supplied from a commercial power supply are required. According to Patent Document 1, the number of power supply units controlled by an interlock switch is limited to one. Therefore, when a plurality of power supply units are connected to an interlock switch, the invention described in Patent Document 1 cannot suppress an inrush current. Thus, an object of the present invention is to reduce an inrush current in a power supply device having a plurality of power supply units. [Means for solving the problem]

[0005] The present invention, for example, The first power supply unit is supplied with AC power from an AC power source, The aforementioned second power supply unit that is supplied with AC, A first relay is connected between the AC power supply and the input section of the first power supply unit, and has an ON state that supplies AC to the first power supply unit and an OFF state that does not supply AC to the first power supply unit. A second relay is connected between the AC power supply and the input section of the second power supply unit, and has an ON state that supplies AC to the second power supply unit and an OFF state that does not supply AC to the second power supply unit. A first interlock switch enters a first state when a predetermined first interlock condition is met, and enters a second state when the predetermined first interlock condition is no longer met, It has control means for controlling the first relay and the second relay, The control means is When the first interlock switch transitions from the second state to the first state, the first relay is switched from the ON state to the OFF state, and the second relay is switched from the ON state to the OFF state. The present invention provides a power supply device that, when the first interlock switch transitions from the first state to the second state, switches the first relay from the off state to the on state after a first delay time has elapsed from the time the transition to the second state occurred, and switches the second relay from the off state to the on state after a second delay time, which is longer than the first delay time, has elapsed from that time. [Effects of the Invention]

[0006] According to the present invention, inrush current is reduced in a power supply device having multiple power supply units. [Brief explanation of the drawing]

[0007] [Figure 1] Figure for explaining an image forming apparatus. [Figure 2] Figure for explaining a power supply device. [Figure 3] Figure for explaining an image forming apparatus. [Figure 4] Figure for explaining an image forming apparatus. [Figure 5] Figure for explaining a startup operation. [Figure 6] Figure for explaining an interlock operation. [Figure 7] Figure for explaining the functions of a CPU. [Figure 8] Flowchart showing a control method. [Figure 9] Figure for explaining a power supply device. [Figure 10] Figure for explaining a startup operation and an interlock operation. [Figure 11] Figure for explaining the functions of a CPU. [Figure 12] Flowchart showing a control method. [Figure 13] Figure for explaining relay-on control between a plurality of modules. [Figure 14] Figure for explaining a power supply device. [Figure 15] Figure for explaining a startup operation and an interlock operation. [Figure 16] Figure for explaining the functions of a CPU. [Figure 17] Flowchart showing a control method. [Figure 18] Figure for explaining a modification example. [[ID=�4]]

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] <Example 1> 1. Image forming apparatus (image forming system) FIG. 1 is a schematic diagram showing an example of the schematic configuration of the image forming apparatus 100. The Z direction is the height direction of the image forming apparatus 100. The Y direction is generally parallel to the sheet conveyance direction. The X direction is the width direction of the sheet S. Note that the width direction of the sheet S may be referred to as the main scanning direction. A direction parallel to the conveyance direction of the sheet S may be referred to as the sub-scanning direction.

[0010] The image forming apparatus 100 is a sheet-fed image forming apparatus that forms an ink image on a sheet S using two liquids, a reaction liquid and ink. The sheet S on which the ink image is formed may be referred to as a recording material, an output material, or a product. The ink contains, for example, a resin component, water, a water-soluble organic solvent, a colorant, a wax, and an additive. However, this is merely an example.

[0011] The image forming apparatus 100 includes a feeding module 1000, a printing module 2000, a drying module 3000, a fixing module 4000, a cooling module 5000, a reversing module 6000, and a discharge stacking module 7000, etc. The cut paper-like sheet S supplied from the feeding module 1000 is conveyed along a conveyance path, processed by each module, and discharged to the discharge stacking module 7000.

[0012] The feeding module 1000 has three storage bins 1100a to 1100c for storing the sheet S. The storage bins 1100a to 1100c can be pulled out to the front side of the image forming apparatus 100. The sheet S is fed one by one by a separation belt and a conveyance roller in the storage bins 1100a to 1100c and conveyed to the printing module 2000. Note that the number of the storage bins 1100a to 1100c may be one or more.

[0013] The print module 2000 includes a sheet correction unit 2100, a belt unit 2200, and a recording unit 2300. The sheet correction unit 2100 corrects the tilt and position of the sheet S conveyed from the feed module 1000 and conveys the sheet S to the belt unit 2200. The recording unit 2300 is positioned opposite the belt unit 2200 across the conveyance path. The recording unit 2300 performs a recording process (printing) on ​​the conveyed sheet S from above using a recording head to form an image. The sheet S is carried by the belt unit 2200 by suction. This ensures an appropriate clearance between the recording head and the sheet S. In addition, multiple recording heads may be arranged along the conveyance direction. In this embodiment, four line-type recording heads corresponding to four colors (Y: yellow, M: magenta, C: cyan, Bk: black) inks and one line-type recording head that ejects the reaction liquid C0 are provided. The number of colors and recording heads are not limited to five. For example, three additional line-type recording heads may be added for special colors C1, C2, and C3, which are different from Y, M, C, and Bk. Examples of inkjet recording methods include methods using heating elements, piezoelectric elements, electrostatic elements, or MEMS elements. MEMS is an abbreviation for micro-electromechanical system.

[0014] Each of the four inks is supplied to the recording head via an ink tube from an ink tank (not shown). The belt unit 2200 further transports the sheet S, on which the image has been printed by the recording unit 2300, downstream. An inline scanner 1 may be located downstream of the recording unit 2300. The inline scanner 1 detects the misalignment and color density of the image formed on the sheet S. The detection results are used to correct the subsequent printed image.

[0015] The drying module 3000 reduces the liquid content of the ink applied to the sheet S by the recording unit 2300, thereby improving the adhesion between the sheet S and the ink. The drying module 3000 includes a decoupling unit 3200, a drying belt unit 3300, and a hot air blowing unit 3400. The sheet S, on which an image has been printed by the recording unit 2300 of the print module 2000, is transported to the decoupling unit 3200 located within the drying module 3000. The decoupling unit 3200 holds the sheet S with upward air pressure and the frictional force of the belt, while transporting the sheet S further downstream. This suppresses displacement of the sheet S on the belt unit 2200. The sheet S is then transported from the decoupling unit 3200 to the drying belt unit 3300. The drying belt unit 3300 transports the sheet S while adsorbing it. The hot air blowing unit 3400 is located above the drying belt unit 3300. The hot air blowing unit 3400 applies hot air to the sheet S to dry the ink-applied surface of the sheet S. The drying belt unit 3300 transports the sheet S to the fixing module 4000.

[0016] The drying module 3000 heats and dries the liquid components of the reaction solution and ink applied to the sheet S. This promotes the evaporation of water from the reaction solution and ink, suppressing cockling of the sheet S.

[0017] The drying module 3000 can be any device capable of performing heat drying. For example, the drying module 3000 may have a hot air dryer or a heater. There are no particular restrictions on the type of heater. For example, an electric heating element heater or an infrared heater may be used as the heater.

[0018] The fixing module 4000 has a fixing belt unit 4100. The fixing belt unit 4100 has an upper belt unit and a lower belt unit. The upper belt unit and the lower belt unit are heated, and the sheet S passes between them. This allows the ink solvent to penetrate the sheet S sufficiently.

[0019] The cooling module 5000 has a plurality of cooling units 5100 that cool the high-temperature sheet S transported from the fixing module 4000. The cooling units 5100, for example, draw outside air into the cooling box with a fan to increase the pressure inside the cooling box and blow the air onto the sheet S through nozzles formed in the transport guide. This cools the sheet S. The cooling units 5100 are arranged on both sides of the transport path in the height direction. This cools both sides of the sheet S. A switching unit 5200 may be provided inside the cooling module 5000 to switch the transport path. The switching unit 5200 switches between transporting the sheet S to the inversion module 6000 and transporting the sheet S to the double-sided transport path used during double-sided printing. During double-sided printing, the sheet S is transported to the double-sided transport path 5300 located below the cooling module 5000. Furthermore, the sheet S is transported through the fixing module 4000, the drying module 3000, the printing module 2000, and the feeding module 1000. As a result, the sheet S is transported again to the sheet correction unit 2100, the belt unit 2200, and the recording unit 2300 of the printing module 2000. The recording unit 2300 then prints an image on the second surface of the sheet S.

[0020] The double-sided transport path of the fixing module 4000 may be provided with a reversal unit 4200 for reversing the front and back sides of the sheet S. The reversal module 6000 also has a reversal unit 6400. The reversal unit 6400 reverses the front and back sides of the transported sheet S. This allows for the free selection of the front and back sides (face down / face up) of the discharged sheet S.

[0021] The discharge and loading module 7000 has a top tray 7200 and a loading section 7500. The top tray 7200 and the loading section 7500 align and load the sheets S that have been transported from the inversion module 6000.

[0022] 2.Power supply Figure 2 shows a power supply unit 150 that can be mounted on each module of the image forming apparatus 100. The power supply unit 150 has a power supply 24 and a control unit 20. The power supply 24 has AC / DC conversion units 211, 221, 231, and 241 as multiple power supply units. AC is an abbreviation for alternating current, and DC is an abbreviation for direct current. The AC / DC conversion units 211, 221, 231, and 241 are conversion circuits that convert the alternating current input from the ACIN terminal connected to the AC power supply 10 into a predetermined direct current. The AC power supply 10 is, for example, a commercial AC power supply. The AC / DC conversion units 211, 221, 231, and 241 each generate a desired DC voltage DC1, DC2, DC3, and DC4. The power lines and wiring for supplying the DC voltages DC1, DC2, DC3, and DC4 to the loads (control unit 20, load 25) may be called power supply systems DC1, DC2, DC3, and DC4. Thus, DC1, DC2, DC3, and DC4 are symbols that indicate both DC voltages and power supply systems. Relay 210 is provided between the AC power supply 10 and the input of the AC / DC converter 211. Relay 220 is provided between the AC power supply 10 and the input of the AC / DC converter 221. Relay 230 is provided between the AC power supply 10 and the input of the AC / DC converter 231. Relay 240 is provided between the AC power supply 10 and the input of the AC / DC converter 241. The DC voltage DC1 generated by the AC / DC converter 211 is applied to the control unit 20. DC voltages DC2, DC3, and DC4 are supplied to the load 25. In Embodiment 1, four DC voltages are generated from one AC power supply 10, but this is just one example. As will be described later, AC may be input to the power supply 24 from multiple AC power supplies. A single power supply system may be branched into multiple power supply systems, such as the DC voltage DC4'. In this case, the DC voltages DC4 and DC4' may be equal or different. In the latter case, a DC-DC converter may be required to convert DC4 to DC4'.

[0023] Relays 210, 220, 230, and 240 are electromagnetic relays, triacs, or field-effect transistors controlled by control signals output from the control unit 20. Relays 210, 220, 230, and 240 each allow (supply or pass through) or prohibit (non-supply or block) AC input to the corresponding AC-DC converters 211, 221, 231, and 241, respectively.

[0024] The power supply system DC1 in Embodiment 1 is a +24V power supply. A +24V power supply means a DC voltage of +24V. The control unit 20 operates when supplied with a +24V power supply. The input terminal 21 is supplied with an Enable_IN signal from the controller 30 or another module. In Embodiment 1, the Enable_IN signal is the control signal for relay 210 (a module activation permission signal). When the Enable_IN signal is input to relay 210, relay 210 transitions from off to on, and AC is input to the AC / DC converter 211. The AC / DC converter 211 generates a DC voltage DC1 from the AC and supplies the DC voltage DC1 (+24V) to the control unit 20. The +24V power supply is used as the power supply to drive relays 210, 220, 230, and 240. The +24V power supply is also used as the power supply to generate the Enable_OUT signal. The output terminal 22 is connected to the input terminal 21 of another module and supplies the Enable_OUT signal to the other module.

[0025] The DC-DC converter 201 generates a +3V3 power supply from a +24V power supply and supplies this +3V3 power supply to the CPU 200. A +3V3 power supply means a DC voltage of +3.3V. In other words, the +3V3 power supply provides the operating voltage for the CPU 200. Note that these voltage values ​​are merely examples.

[0026] The CPU 200 controls relays 210, 220, 230, and 240 via a relay drive unit 203. The relay drive unit 203 may include a transistor or thyristor to supply current to the relay coils of relays 210, 220, 230, and 240. A relay coil is an electromagnetic coil that brings two contacts into contact or separates them. One terminal of the relay coil is called the high side and is connected to a +24V power supply. The other terminal of the relay coil is called the low side and is connected to ground (GND).

[0027] The door switch 23 is an interlock switch installed on the maintenance door of the image forming apparatus 100. When the interlock condition is met (e.g., maintenance door open, sheet cassette open), the door switch 23 is in the first state (open, off, low). When the interlock condition is not met (e.g., maintenance door closed, sheet cassette closed), the door switch 23 is in the second state (closed, on, high). The IL_st signal indicating the state of the door switch 23 is input to the relay drive unit 203 and the CPU 200. If the IL_st signal indicates that the door is open, the relay drive unit 203 shuts off relays 220, 230, and 240. The CPU 200 monitors the state of the door switch 23 based on the IL_st signal. The relay drive unit 203 conducts the corresponding relay if the logical AND of the state of the door switch 23 and the state of the relay control signal from the CPU 200 is true. In other words, the CPU 200 can forcibly turn off relays 220, 230, and 240, regardless of the state of the door switch 23.

[0028] The IL_st signal, which represents the state of the door switch 23, and its connection relationship are schematically represented. For example, a +24V power supply may be connected to the CPU 200 via the door switch 23 and a DC-DC converter. In this case, one end of the door switch 23 is connected to the +24V power supply, and the other end of the door switch 23 is connected to the input terminal of the DC-DC converter. When the door is closed and the door switch 23 is turned on, the DC-DC converter converts the +24V voltage input via the door switch 23 to a +3.3V voltage and applies the +3.3V voltage to the input port of the CPU 200. In other words, the CPU 200 may use the +3V3 power supply (+3.3V voltage) originating from the door switch 23 as the IL_st signal. The DC-DC converter may be a level converter that converts the +24V voltage to a +3.3V voltage using, for example, a photocoupler or a field-effect transistor. For example, a +24V voltage is applied as a control signal to the gate of an N-channel type field-effect transistor. The +24V voltage may be divided by multiple resistors and input to the gate. The drain is connected to a +3.3V power supply via a pull-up resistor. The connection point between the pull-up resistor and the drain is connected to the input port of the CPU200. The source is connected to ground (GND).

[0029] To suppress chattering of the IL_st signal associated with the opening and closing of the door, a chattering reduction circuit (not shown) may be provided in the door switch 23. The chattering reduction circuit operates in such a way that short-term changes in the input signal are not reflected in the output signal. The chattering reduction circuit may be, for example, a low-pass filter circuit formed by a resistor and a capacitor. The CPU 200 may reduce chattering through software processing. For example, the CPU 200 can reduce the effect of chattering by ignoring short-term changes in the input signal.

[0030] The relay drive unit 203 is similarly schematically represented. For example, the relay drive unit 203 may have a transistor that controls the high-side or low-side of relays 220, 230, and 240. This transistor switches between an ON state, where a +24V power supply is applied to the relay coil, and an OFF state, where a +24V power supply is not applied to the relay coil. This may control the opening and closing of relays 220, 230, and 240.

[0031] The CPU 200 outputs an Enable_OUT signal to the output terminal 22 at the timing specified in the control program. As shown in Figure 2, the load 25 is a DC load, but an AC load may also be present. The AC load is supplied with AC power from the AC power supply 10 via relays only, and without going through the AC / DC converter. In Example 1, the CPU 200 controls three relays 220, 230, and 240, but this is just one example. The number of relays can be one or more.

[0032] 3. Connections between multiple modules Figures 3 and 4 show the interconnection of power supplies between multiple modules. The feed module 1000 has a housing 1001 that houses the power supply unit 150. The print module 2000 has a housing 2001 that houses the power supply unit 150. The drying module 3000 has a housing 3001 that houses the power supply unit 150. The fuser module 4000 has a housing 4001 that houses the power supply unit 150. The cooling module 5000 has a housing 5001 that houses the power supply unit 150. The inversion module 6000 has a housing 6001 that houses the power supply unit 150. The discharge loading module 7000 has a housing 7001 that houses the power supply unit 150. Thus, each module has a power supply unit 150, a load 25, and a door switch 23, respectively. The controller 30 comprehensively controls the entire image forming apparatus 100. The controller 30 may be located outside the power supply unit 150.

[0033] The controller 30 generates an Enable signal 31 to start the image forming apparatus 100. The Enable signal 31 is input to the input terminal of the print module 2000. In Embodiment 1, Enable signals 31 to 36 are start-up permission signals, which are a type of control signal. The Enable signal 31 functions as an Enable_IN signal. This turns on the relay 210 in the print module 2000, starts the generation of a +24V power supply, and starts the control unit 20 of the print module 2000.

[0034] When the print module 2000 starts up, an Enable signal 32 is output as an Enable_OUT signal from the output terminal 22 of the print module 2000. The Enable signal 32 is input as an Enable_IN signal to the input terminal 21 of the feed module 1000 and the input terminal 21 of the drying module 3000. This turns on the relay 210 in the feed module 1000, and the control unit 20 of the feed module 1000 starts up. Similarly, the relay 210 in the drying module 3000 turns on, and the control unit 20 of the drying module 3000 starts up.

[0035] When the drying module 3000 is activated by the Enable signal 32, the control unit 20 of the drying module 3000 outputs an Enable signal 33 from the output terminal 22. The Enable signal 33 is input to the input terminal 21 of the fixing module 4000 as an Enable_IN signal. This turns on the relay 210 in the fixing module 4000, and the control unit 20 of the fixing module 4000 is activated.

[0036] When the fuser module 4000 is activated by the Enable signal 33, the control unit 20 of the fuser module 4000 outputs an Enable signal 34 from the output terminal 22. The Enable signal 34 is input to the input terminal 21 of the cooling module 5000 as an Enable_IN signal. This turns on the relay 210 in the cooling module 5000, and the control unit 20 of the cooling module 5000 is activated.

[0037] When the cooling module 5000 is activated by the Enable signal 34, the control unit 20 of the cooling module 5000 outputs the Enable signal 35 from the output terminal 22. The Enable signal 35 is input as the Enable_IN signal to the input terminal 21 of the inverting module 6000. This turns on the relay 210 in the inverting module 6000, and the control unit 20 of the inverting module 6000 is activated.

[0038] When the inverting module 6000 is activated by the Enable signal 35, the control unit 20 of the inverting module 6000 outputs an Enable signal 36 from the output terminal 22. The Enable signal 36 is input as an Enable_IN signal to the input terminal 21 of the discharge and loading module 7000. This turns on the relay 210 in the discharge and loading module 7000, and the control unit 20 of the discharge and loading module 7000 is activated.

[0039] In this way, each module is sequentially activated by Enable signals 31 to 36 originating from the controller 30. In Embodiment 1, the print module 2000 is the first to receive Enable signal 31, but the order in which Enable signals 31 to 36 are received is just one example. As shown in Figures 3 and 4, each module has an individual ACIN terminal, each connected to the AC power supply 10, but this is just one example. A single ACIN terminal may be shared among multiple modules.

[0040] 4. Timing Chart 4-1. Startup operation for each module Figure 5(A) is a timing chart showing the startup operation. Here, it is assumed that the door switch 23 is in the ON state (door closed state).

[0041] At time T1, the Enable_IN signal is input to input terminal 21. At time T2, the Enable_IN signal turns on relay 210, and the AC / DC converter 211 starts outputting the +24V power supply.

[0042] At time T3, the DC-DC converter 201 starts generating a +3V3 power supply. This starts up the CPU 200. With the +3V3 power supply enabled, the IL_st signal is recognized as a valid input signal by the CPU 200. The logic of the IL_st signal is either Hi or Lo. Hi represents the door switch ON (door closed) state. Lo represents the door switch OFF (door open) state.

[0043] Time T4 is the time after a delay of delay1 has elapsed from the start time (time T3). At time T4, the CPU 200 asserts the ON1 signal to turn on the relay 220. This starts the AC / DC converter 221 and begins generating the DC voltage DC2.

[0044] Time T5 is the time after a delay time of delay2 has elapsed from the start time (time T3). At time T5, the CPU 200 asserts the ON2 signal to turn on the relay 230. This starts the AC / DC converter 231 and begins generating the DC voltage DC3.

[0045] Time T6 is the time after a delay of delay3 has elapsed from the start time (time T3). At time T6, the CPU 200 asserts the ON3 signal to turn on the relay 240. This starts the AC / DC converter 241 and begins generating the DC voltage DC4.

[0046] At time T7, CPU200 determines that all relays 220, 230, and 240 have been switched on and asserts the Enable_OUT signal. This starts the generation of the +24V power supply for the subsequent modules, and the subsequent modules start up.

[0047] 4-2. Startup operation of the image forming apparatus Figure 5(B) shows the timing at which Enable signals 31-36 are asserted. Times T1 and T7 correspond to times T1 and T7 shown in Figure 5(A), respectively.

[0048] At time T1, the controller 30 sends an Enable signal 31 to the print module 2000. This causes the CPU 200 of the print module 2000 to sequentially turn on relays 220, 230, and 240 of the print module 2000.

[0049] At time T7, the CPU 200 of the print module 2000 asserts the Enable signal 32 for the subsequent drying module 3000 and feed module 1000. As a result, the drying module 3000 and the feed module 1000 start up. The print module 2000 may be called the upper module, and the drying module 3000 and feed module 1000 may be called the lower modules. The upper module starts up before the lower modules, and the lower modules start up after the upper module. Thus, "upper" and "lower" may indicate the priority of startup and the master-slave relationship of startup. The upper module may be called the preceding module, and the lower modules may be called the subsequent modules.

[0050] At time T8, the CPU 200 of the drying module 3000 asserts the Enable signal 33 to the subsequent fixing module 4000. This activates the fixing module 4000. In this case, the drying module 3000 is the upper module, and the fixing module 400 is the lower module.

[0051] At time T9, the CPU 200 of the fuser module 4000 asserts the Enable signal 34 to the subsequent cooling module 5000. This activates the cooling module 5000.

[0052] At time T10, the CPU 200 of cooling module 5000 asserts the Enable signal 35 to the subsequent inverting module 6000. This activates the inverting module 6000.

[0053] At time T11, the CPU 200 of the inversion module 6000 asserts the Enable signal 36 to the subsequent discharge and loading module 7000. This activates the discharge and loading module 7000.

[0054] As shown in Figure 5(A), the AC / DC converters 221, 231, and 241 start up in sequence, thus reducing the inrush current. As shown in Figure 5(A), the multiple modules start up in sequence, thus reducing the inrush current.

[0055] 4-3. Interlock Operation Figure 6 shows the interlock operation of the CPU 200 according to the state of the door switch 23. At time T51, the door is opened and the door switch 23 is turned off. As a result, the IL_st signal is negated.

[0056] At time T52, CPU200 detects that the IL_st signal has been negated. CPU200 then negates all of the ON1, ON2, and ON3 signals.

[0057] At time T53, the door is closed and door switch 23 is turned on. This causes the IL_st signal to be asserted.

[0058] Time T54 is the time when a predetermined delay time delay4 has elapsed from time T53. At time T54, CPU200 asserts the ON1 signal.

[0059] Time T55 is the time when a predetermined delay time delay5 has elapsed from time T53. At time T55, CPU200 asserts the ON2 signal. The delay time delay5 may be measured from time T54.

[0060] Time T56 is the time when a predetermined delay time delay6 has elapsed from time T53. At time T56, CPU200 asserts the ON3 signal. The delay time delay6 may be measured from time T55.

[0061] At time T53, even though the door switch 23 is ON, the CPU 200 negates the ON1 to ON3 signals. Therefore, the relay drive unit 203 does not turn on the relays 220, 230, and 240 under its control. In order for relays 220, 230, and 240 to actually turn on, the door switch 23 must be turned on and the ON1 to ON3 signals must be asserted. In other words, relays 220, 230, and 240 turn on at times T54, T55, and T56, respectively. Relays 220, 230, and 240 turn on with a delay from the timing when the door switch 23 is turned on.

[0062] delay1-3 may or may not match delay4-6. delay1-3 may or may not have the same value. delay4-6 may or may not have the same value.

[0063] 5. CPU Functions Figure 7 shows several functions that the CPU 200 implements by executing a control program. One or more of these functions may be implemented by logic circuits (e.g., transistors, discrete ICs). IC is an abbreviation for integrated circuit.

[0064] The setting unit 701 sets predetermined delay times for the determination units 711, 712, and 713. If the delay time is a fixed value, the setting unit 701 may be omitted. The timer 702 is used to measure time, such as a real-time clock or counter circuit. The monitoring unit 703 monitors the IL_st signal and obtains the state of the door switch 23. In other words, the monitoring unit 703 determines whether the interlock condition is met.

[0065] The determination unit 711 obtains the elapsed time from the timer 702 since the IL_st signal went high, and determines whether the elapsed time has reached the delay time delay4. The determination result is output to the determination unit 714 and the signal generation unit 721. Based on the determination signal indicating that the elapsed time has reached the delay time delay4, the signal generation unit 721 starts outputting an ON1 signal to the relay 220.

[0066] The determination unit 712 obtains the elapsed time from the timer 702 since the IL_st signal went high, and determines whether the elapsed time has reached the delay time delay5. The determination result is output to the determination unit 714 and the signal generation unit 722. Based on the determination signal indicating that the elapsed time has reached the delay time delay5, the signal generation unit 723 starts outputting an ON2 signal to the relay 230.

[0067] The determination unit 713 obtains the elapsed time from the timer 702 since the IL_st signal went high, and determines whether the elapsed time has reached the delay time delay6. The determination result is output to the determination unit 714 and the signal generation unit 723. Based on the determination signal indicating that the elapsed time has reached the delay time delay6, the signal generation unit 723 starts outputting an ON3 signal to the relay 220.

[0068] When the determination results from determination units 711 to 714 all indicate that a predetermined delay time has elapsed, the determination unit 714 commands the signal generation unit 724 to generate an Enable_OUT signal. As a result, the signal generation unit 724 asserts the Enable_OUT signal.

[0069] 6. Flowchart Figure 8 shows the control method executed by the CPU 200 according to the control program. When the +3V3 power supply is applied to the CPU 200, the CPU 200 performs the following processes.

[0070] In S801, the CPU200 (monitoring unit 703) determines whether the IL_st signal is asserted. If the IL_st signal is not asserted, the CPU200 proceeds from S801 to S812 and negates the ON1 signal. If the IL_st signal is asserted, the CPU200 proceeds from S801 to S802.

[0071] In S802, the CPU200 (determination unit 711) obtains the elapsed time from the timer 702 and determines whether the delay time delay4 has elapsed based on the elapsed time. If the delay time delay4 has elapsed, the CPU200 proceeds from S802 to S803. If the delay time delay4 has not elapsed, the CPU200 proceeds from S802 to S801.

[0072] In the S803, CPU200 (signal generation unit 721) asserts the ON1 signal.

[0073] In S804, the CPU200 (monitoring unit 703) determines whether the IL_st signal is asserted. If the IL_st signal is not asserted, the CPU200 proceeds from S804 to S812 and negates the ON2 signal. If the IL_st signal is asserted, the CPU200 proceeds from S804 to S805.

[0074] In S805, the CPU 200 (determination unit 712) obtains the elapsed time from the timer 702 and determines whether the delay time delay5 has elapsed based on the elapsed time. If the delay time delay5 has elapsed, the CPU 200 proceeds from S805 to S806. If the delay time delay5 has not elapsed, the CPU 200 proceeds from S805 to S804.

[0075] In the S806, CPU200 (signal generation unit 722) asserts the ON2 signal.

[0076] In S807, the CPU200 (monitoring unit 703) determines whether the IL_st signal is asserted. If the IL_st signal is not asserted, the CPU200 proceeds from S807 to S812 and negates the ON3 signal. If the IL_st signal is asserted, the CPU200 proceeds from S807 to S808.

[0077] In S808, the CPU200 (determination unit 713) obtains the elapsed time from the timer 702 and determines whether the delay time delay6 has elapsed based on the elapsed time. If the delay time delay6 has elapsed, the CPU200 proceeds from S808 to S809. If the delay time delay6 has not elapsed, the CPU200 proceeds from S808 to S807.

[0078] In the S809, CPU200 (signal generation unit 723) asserts the ON3 signal.

[0079] In S810, CPU200 (determination unit 714, signal generation unit 724) asserts the Enable_OUT signal.

[0080] At S811, the CPU200 (monitoring unit 703) determines whether the IL_st signal is asserted. If the IL_st signal is not asserted, the CPU200 proceeds from S811 to S812 and negates the ON1, ON2, and ON3 signals. If the IL_st signal is asserted, the CPU200 remains at S811.

[0081] According to Example 1, the CPU 200 monitors the state of the door switch 23 and negates the ON1, ON2, and ON3 signals to relays 220, 230, and 240 if the door switch 23 is in the off state (door open). When the door switch 23 is turned on (door closed), relays 220, 230, and 240 turn on at different times. In other words, the ON1, ON2, and ON3 signals are asserted sequentially according to different delay times.

[0082] This prevents relays 220, 230, and 240 from being turned on simultaneously when the door switch 23 returns from the off state to the on state. As a result, the inrush current from the AC power supply 10 to the AC / DC converters 221, 231, and 241 is reduced.

[0083] In Example 1, relays 220, 230, and 240 are examples of the first, second, and third relays, respectively. AC / DC converters 221, 231, and 241 are examples of the first, second, and third power supply units, respectively. In Example 1, when the door is closed, the first interlock switch (e.g., door switch 23) transitions from the first state to the second state. As a result, relay 220 switches from the off state to the on state when a first delay time (e.g., delay 4) has elapsed from the time the transition to the second state occurred. Relay 230 switches from the off state to the on state when a second delay time (e.g., delay 5) that is longer than the first delay time has elapsed from the time the transition to the second state occurred. Furthermore, relay 240 switches from the off state to the on state when a third delay time (e.g., delay 6) that is longer than the second delay time has elapsed from the time the transition to the second state occurred. In Example 1, the Enable signal output by the preceding module acts as the activation permission signal for the subsequent module. The start-up enable signal may be output after at least the first relay and the second relay have switched from off to on. Alternatively, the start-up enable signal may be output after at least the first relay, the second relay, and the third relay have switched from off to on. In Embodiment 1, the Enable signal (Enable_OUT, Enable_IN) is used as the start-up enable signal for the control unit 20. The startup of each module is controlled by the start-up enable signal.

[0084] As is clear from Figures 3 and 4, each module has a power supply unit 150 shown in Figure 2. By sequentially activating each module via the Enable signal, the inrush current is reduced throughout the entire image forming apparatus 100. In other words, in Embodiment 1, not only is the inrush current reduced in the power supply unit 150, but the inrush current is also reduced throughout the entire image forming apparatus 100.

[0085] <Example 2> In Example 1, each module of the image forming apparatus 100 was equipped with a single door switch 23, but this is merely one example. Example 2 describes the case where multiple door switches exist. A method for suppressing inrush current associated with door opening and closing across multiple modules is also mentioned.

[0086] In particular, in Example 2, each module turns on relays 220, 230, and 240 according to an internal control cycle at a fixed interval. Furthermore, in Example 2, by staggering the internal control cycles of each module, the timing of relay activation does not overlap among multiple modules.

[0087] 1.Power supply Figure 9 shows the power supply unit 150 that can be mounted on each module of Embodiment 2. The difference between Embodiment 1 and Embodiment 2 is that power supply systems DC2 and DC3 are interlocked by the door switch 23, while power supply system DC4 is interlocked by the door switch 26. The CPU 200 monitors the status of the door switches 23 and 26, respectively. For example, the door switch 23 may be provided on the first openable / closable member, and the door switch 26 may be provided on the second openable / closable member. Openable / closable members include, for example, maintenance doors and seat cassettes. Other aspects of Embodiment 2 are the same as those of Embodiment 1. Hereinafter, the status signal of the door switch 23 will be denoted as the IL_st1 signal. The status signal of the door switch 26 will be denoted as the IL_st2 signal.

[0088] 2. Timing Chart 2-1. Startup Operation Figure 10(A) shows the startup operation of the control unit 20. At time T71, the Enable_IN signal is input to input terminal 21. This turns on relay 210, and the generation of the +24V power supply and the +3V3 power supply begins.

[0089] CPU200 starts up at time T72. CPU200 starts generating a constant periodic signal, tick, using timer 702. Thus, the generation of the periodic signal tick begins with the input of the Enable_IN signal. Furthermore, CPU200 adds 1 to the count value each time the periodic signal tick rises. The periodic signal tick is used as the internal control period. The count value is used as the index for the periodic signal tick.

[0090] Time T73 corresponds to the timing synchronized with an even-numbered tick. CPU200 determines that the IL_st1 signal is asserted at time T73 and asserts the ON1 signal.

[0091] Time T74 corresponds to the timing synchronized with an even-numbered tick. CPU200 determines that the IL_st1 signal is asserted at time T74 and asserts the ON2 signal.

[0092] Time T75 is synchronized with an even-numbered tick. CPU200 determines that the IL_st2 signal was asserted at time T73 and asserts the ON3 signal.

[0093] Time T76 corresponds to the timing synchronized with the odd-numbered ticks. CPU200 determines that all ON1, ON2, and ON3 signals are asserted at time T76 and asserts the Enable_OUT signal.

[0094] According to Example 2, CPU 200 asserts an ON signal in synchronization with even-numbered ticks. CPU 200 asserts an Enable_OUT signal in synchronization with odd-numbered ticks. In other words, relays 220, 230, and 240 are turned on when the count value is even, and the Enable_OUT signal is asserted when the count value is odd. However, this is just one example. Relays 220, 230, and 240 may be turned on when the count value is odd, and the Enable_OUT signal may be asserted when the count value is even, because these are interchangeable.

[0095] 8-2. Interlock Operation Figure 10(B) shows the interlock operation. At time T77, CPU200 determines that the IL_st1 signal has been negated and negates the ON1 and ON2 signals. At time T78, CPU200 determines that the IL_st2 signal has been negated and negates the ON3 signal. In this way, multiple relays among relays 220, 230, and 240 may be turned off simultaneously.

[0096] At time T79, CPU200 detects that the IL_st1 signal has been asserted and waits for the next even-numbered tick. Time T80 corresponds to the 2n+2th tick. At time T80, CPU200 asserts the ON1 signal, where n is any positive integer. Time T81 corresponds to the 2n+4th tick. At time T81, CPU200 asserts the ON2 signal. Thus, the count value at which the ON2 signal is asserted (e.g., the second even-numbered value) is greater than the count value at which the ON1 signal is asserted (e.g., the first even-numbered value).

[0097] At time T82, CPU200 determines that the IL_st2 signal has been asserted and waits for the next even-numbered tick to arrive. Time T83 corresponds to the 2n+6th tick. At time T83, CPU200 asserts the ON3 signal. Thus, the count value at which the ON3 signal is asserted (e.g., the third even number) is greater than the count value at which the ON2 signal is asserted (e.g., the second even number).

[0098] In Embodiment 2, the CPU 200 is configured to turn on the relay when the count value of the internal control cycle is even, and to assert the Enable output signal when the count value is odd. The odd-numbered internal control cycles for which the Enable_OUT signal is output correspond to the start time of the internal control cycle in the subsequent module, i.e., the even-numbered internal control cycles. This distributes the timing of when the relays turn on across multiple adjacent modules, without depending on the on / off timing of the door switches 23 and 26 in each module. The staggered relay on timings between modules reduces the inrush current from the AC power supply 10 to the image forming apparatus 100.

[0099] 3. CPU Functions Figure 11 shows the function of the CPU 200 in Embodiment 2. Here, the differences from Embodiment 1 will be explained in detail. The counter 1101 refers to the timer 702 and counts the internal control cycle. That is, the counter 1101 adds 1 to the count value each time a time equivalent to a tick has elapsed. The counter 1101 may start counting ticks using the Enable_IN signal input to the input terminal 21 from the preceding module as a starting point or trigger. This allows the preceding module to control the starting point of the internal control cycle of the subsequent module.

[0100] The monitoring unit 703 monitors the state of the door switch 23 based on the IL_st1 signal. The monitoring results are supplied to the determination unit 711 and the determination unit 712. When the IL_st1 signal is asserted, the determination unit 711 obtains the count value from the counter 1101 and determines whether the count value is even. If the count value is even, the determination unit 711 instructs the signal generation unit 721 to assert the ON1 signal. When the IL_st1 signal is asserted, the determination unit 712 obtains the count value from the counter 1101 and determines whether the count value is even. If the count value is even, the determination unit 712 instructs the signal generation unit 721 to assert the ON2 signal. The determination unit 712 instructs the signal generation unit 721 to assert the ON2 signal after the determination unit 711.

[0101] The monitoring unit 1102 monitors the state of the door switch 26 based on the IL_st2 signal. When the IL_st2 signal is asserted, the determination unit 713 obtains the count value from the counter 1101 and determines whether the count value is even. If the count value is even, the determination unit 712 instructs the signal generation unit 721 to assert the ON3 signal as the determination result.

[0102] When all of the ON1 to ON3 signals are asserted, the determination unit 714 obtains a count value from the counter 1101 and determines whether the count value is odd. If the count value is odd, the determination unit 714 instructs the signal generation unit 724 to assert the Enable_OUT signal.

[0103] 4. Flowchart Figure 12 shows the control method executed by the CPU 200 according to the control program. When the +3V3 power supply is applied to the CPU 200, the CPU 200 executes the following processes. The CPU 200 (counter 1101) starts counting the internal control cycle starting from the Enable_IN signal input to input terminal 21.

[0104] In S1201, the CPU200 (monitoring unit 703) determines whether the IL_st1 signal is asserted. If the IL_st signal is not asserted, the CPU200 proceeds from S1201 to S1221 and negates the ON1 signal. If the IL_st signal is asserted, the CPU200 proceeds from S1201 to S1202.

[0105] In S1202, the CPU 200 (determination unit 711) obtains a count value from the counter 1101 and determines whether the count value is even. If the count value is even, the CPU 200 proceeds from S1202 to S1203. If the count value is odd, the CPU 200 proceeds from S1202 to S1201.

[0106] In S1203, CPU200 (signal generation unit 721) asserts the ON1 signal.

[0107] In S1204, the CPU200 (monitoring unit 703) determines whether the IL_st1 signal is asserted. If the IL_st1 signal is not asserted, the CPU200 proceeds from S1204 to S1221 and negates the ON2 signal. If the IL_st1 signal is asserted, the CPU200 proceeds from S1204 to S1205.

[0108] In S1205, the CPU 200 (determination unit 712) obtains a count value from the counter 1101 and determines whether the count value is even. If the count value is even, the CPU 200 proceeds from S1205 to S1206. If the count value is odd, the CPU 200 proceeds from S1205 to S1204.

[0109] In S1206, CPU200 (signal generation unit 722) asserts the ON2 signal. Note that the count value required to assert the ON2 signal is greater than the count value required to assert the ON1 signal.

[0110] In S1207, the CPU200 (monitoring unit 1102) determines whether the IL_st2 signal is asserted. If the IL_st2 signal is not asserted, the CPU200 proceeds from S1207 to S1231 and negates the ON3 signal. If the IL_st2 signal is asserted, the CPU200 proceeds from S1207 to S1208.

[0111] In S1208, the CPU 200 (determination unit 713) obtains a count value from the counter 1101 and determines whether the count value is even. If the count value is even, the CPU 200 proceeds from S1208 to S1209. If the count value is not even, the CPU 200 proceeds from S1208 to S1207.

[0112] In S1209, CPU200 (signal generation unit 723) asserts the ON3 signal. The count value required to assert the ON3 signal is greater than the count value required to assert the ON2 signal.

[0113] In S1210, the CPU 200 (determination unit 713) obtains a count value from the counter 1101 and determines whether the count value is odd. If the count value is odd, the CPU 200 proceeds from S1210 to S1211. If the count value is not odd, the CPU 200 remains in S1210.

[0114] In S1211, CPU200 (determination unit 714, signal generation unit 724) asserts the Enable_OUT signal. The count value required to assert the Enable_OUT signal is greater than the count value required to assert the ON3 signal.

[0115] In S1212, the CPU200 (monitoring unit 703) determines whether both the IL_st1 signal and the IL_st2 signal are negated. If both the IL_st1 signal and the IL_st2 signal are negated, the CPU200 proceeds from S1212 to S1213 and negates the ON1, ON2, and ON3 signals. If at least one of the IL_st1 signal and the IL_st2 signal is asserted, the CPU200 remains at S1212.

[0116] 5. Generalization In the above-described example, the ON1, ON2, and ON3 signals are asserted when the count value is even. The Enable_OUT signal is asserted when the count value is odd. However, these are just examples.

[0117] For example, if there are N modules, the CPU 200 performs a modulo operation on the count value to find the solution. The CPU 200 may turn on relays 220, 230, and 240 during the internal control cycle in which the solution is the first value (e.g., 0). Furthermore, the CPU 200 may assert the Enable_OUT signal during the internal control cycle in which the solution is the second value (e.g., 1). The first and second values ​​are different.

[0118] Figure 13 shows the internal control cycle when N is 3. Since N=3, it is assumed that there are three modules (denoted as module1, module2, and module3). The CPU 200 turns on relays 220, 230, and 240 in internal control cycles where the count values ​​are 3n+0, 3n+3, 3n+6... This indicates that the delay time between the timing when relay 220 turns on and the timing when relay 230 turns on is N times the internal control cycle. The delay time between the timing when relay 230 turns on and the timing when relay 240 turns on is also N times the internal control cycle. The CPU 200 asserts the Enable_OUT signal in one of the internal control cycles where the count values ​​are 3n+1, 3n+4, 3n+7... In Figure 13, the Enable_OUT signal is asserted in the 3n+7th internal control cycle, which is the first to occur after all of relays 220, 230, and 240 have turned on.

[0119] The internal control cycles 3n+1, 3n+4..., for which the Enable_OUT signal is output, correspond to the start timing of the internal control cycle in the subsequent module. In other words, the counter 1101 in the subsequent module starts counting the internal control cycle when the Enable_OUT signal is input as the Enable_IN signal.

[0120] As a result, the difference between the period during which the relay in the adjacent preceding module turns on and the period during which the relay in the adjacent succeeding module turns on becomes 1 / 3 of the internal control period. In other words, the timing of when the relay in the preceding module turns on and the timing of when the relay in the succeeding module turns on do not overlap. This should reduce inrush current.

[0121] The image forming apparatus 100 shown in Figure 1 has seven modules. In other words, the CPU 200 performs a modulo operation with N = 7, and based on the solution, it is possible to shift the timing of the relay on.

[0122] According to Embodiment 2, the CPU 200 controls the timing of relay activation and the timing of outputting the Enable_OUT signal based on the count value of the internal control cycle. This appropriately staggers the timing of power supply unit activation between multiple adjacent modules, thereby reducing inrush current.

[0123] In Embodiment 2, the timing of signal assertion is controlled so that it differs between multiple adjacent modules. However, this technical concept is also applicable to a power supply unit 150 having multiple door switches 23, 26 and corresponding power supply units within the same module. For example, relays 220 and 230 may be turned on when the count value is even, and relay 240 may be turned on when the count value is odd. More generally, relays 220 and 230 may be turned on in an internal control cycle where the solution to the modulo operation is the first value, and relay 240 may be turned on in an internal control cycle where the solution is the second value.

[0124] According to Embodiment 2, the door switch 26 is an example of a second interlock switch. Based on the count value of the internal control cycle, relays 220, 230, and 240 are each given different delay times and switch from off to on. For example, when the count value is the first even value, relay 220 switches from off to on. When the count value is the second even value, relay 230 switches from off to on. When the count value is the third even value, relay 240 switches from off to on. The second even value is greater than the first even value. The third even value is greater than the second even value. The first even value, second even value, and third even value are equal even when replaced with the first odd value, second odd value, and third odd value. In Embodiment 2, the starting point of the internal control cycle of the preceding module is offset from the starting point of the internal control cycle of the subsequent module. This may cause the startup timing between multiple modules to be staggered, and the inrush current in the image forming apparatus 100 may be reduced. An Enable signal may be used to shift the starting point of the internal control cycle of the preceding module from the starting point of the internal control cycle of the subsequent module. The Enable signal is output when the count value is an odd number. If relays 220, 230, and 240 are activated when the count value is an odd number, the Enable signal may be output when the count value is an even number. If there are N modules, the control cycle of the relays in each module may be N times the internal control cycle. If there are N relays, the control cycle of the relays in each module may be N times the internal control cycle. The control cycle of a relay may correspond to the delay time between relays.

[0125] <Example 3> In Example 2, the timing at which multiple relays 220, 230, and 240 are turned on is staggered based on the internal control cycle. In Example 3, the Enable_IN signal is used as a timing control signal to turn on relays 220, 230, and 240. For example, during the permission period when the preceding module asserts the Enable_OUT signal, the subsequent module can turn on relays 220, 230, and 240. The preceding module negates the Enable_OUT signal during the period when it should turn on relays 220, 230, and 240. The period during which the Enable_OUT signal is negated is a non-permission period (prohibition period). The preceding and subsequent modules each activate multiple relays in sequence.

[0126] 1.Power supply Figure 14 shows the power supply unit 150 of Example 2. Unlike Examples 1 and 2, in Example 3, the control unit 20 is always supplied with a +24V power supply from the AC / DC converter 211, regardless of the state of the input terminal 21. In Example 3, the Enable_IN signal input from the input terminal 21 is input to the CPU 200 and used as an enable signal for relay on control.

[0127] 2. Timing Chart 2-1. Startup Operation Figure 15(A) shows the startup operation. At time T101, a circuit breaker (not shown) is turned on, and AC power is input from the AC power supply 10 to the ACIN terminal. As a result, the AC / DC converter 211 starts generating a +24V power supply.

[0128] At time T102, the DC-DC converter 201 starts generating a +3V3 power supply. This starts up the CPU 200.

[0129] At time T103, the CPU 200 detects that the Enable_IN signal input to input terminal 21 has been asserted. As a result, the CPU 200 asserts the ON1 signal. Thus, the Enable_IN signal is a signal that enables relay ON control.

[0130] Time T104 is a predetermined delay time after time T103. At time T104, CPU200 asserts the ON2 signal.

[0131] Time T105 is a predetermined delay time after time T103. At time T105, CPU200 asserts the ON3 signal.

[0132] Time T106 is the time after all relays 220, 230, and 240 have been turned on. At time T106, CPU 200 asserts the Enable_OUT signal output from output terminal 22. This allows the subsequent module to control the relays.

[0133] 2-2. Interlock Operation Figure 15(B) shows the interlock operation. At time T108, the door is opened and the door switch 23 is turned off. As a result, the IL_st signal is negated.

[0134] At time T109, CPU200 detects that the IL_st signal has been negated. In response to the detection result indicating that the IL_st signal has been negated, CPU200 negates all of the ON1 to ON3 signals.

[0135] At time T110, the door is closed and door switch 23 is turned on. This asserts the IL_st signal. Furthermore, CPU 200 negates the Enable_OUT signal output from output terminal 22. The negated Enable_OUT signal functions as a prohibition signal (non-permission signal) that prevents the subsequent module from turning on the relay. This prevents the preceding and succeeding modules from turning on the relays simultaneously. The negated Enable_OUT signal may also be called a declaration signal that declares the preceding module will begin relay on control. CPU 200 starts turning on relays 220, 230, and 240, provided that the IL_st signal is asserted (door open) and the Enable_IN signal is asserted (relay control permitted). The Enable_IN signal is the Enable_OUT signal input from output terminal 22 of the preceding module to input terminal 21 of the subsequent module. The Enable_IN signal is used as a permission signal for relay on control. Therefore, the relay is not turned off because the Enable_IN signal is negated.

[0136] Time T111 is a predetermined delay time after time T110. CPU 200 asserts the ON1 signal in response to the detection result indicating that both signals are asserted. This turns on relay 220. Time T111 is a predetermined delay time after time T110, when both the Enable_IN signal and the IL_st signal are asserted.

[0137] Time T112 is a predetermined delay time after time T110. At time T112, CPU 200 asserts the ON2 signal in response to a detection result indicating that both signals are asserted. This turns on relay 230.

[0138] Time T113 is a predetermined delay time after time T110. At time T113, CPU 200 asserts the ON3 signal based on the detection result that both signals are asserted. This turns on relay 240.

[0139] At time T114, CPU200 determines whether all relays 220, 230, and 240 are ON. Based on the determination that all relays 220, 230, and 240 are ON, CPU200 asserts the Enable_OUT signal. This allows CPU200 to authorize relay ON control for subsequent modules.

[0140] 3. CPU Functions Figure 16 shows the functions realized by the CPU 200 of Embodiment 3. The monitoring unit 703 of Embodiment 1 has been replaced by the monitoring unit 1601. The monitoring unit 1601 monitors, detects, or determines whether the Enable_IN signal input to the input terminal 21 from the preceding module is asserted and the IL_st signal is asserted. The determination unit 711, when the Enable_IN signal and the IL_st signal are asserted, commands the signal generation unit 721 to generate an ON1 signal with a predetermined delay time delay4. The determination unit 712, when the Enable_IN signal and the IL_st signal are asserted, commands the signal generation unit 722 to generate an ON2 signal with a predetermined delay time delay4. When the Enable_IN signal is asserted and the IL_st signal is asserted, the determination unit 713 instructs the signal generation unit 723 to generate an ON3 signal with a predetermined delay time delay6.

[0141] The determination unit 1602 instructs the signal generation unit 724 to negate the Enable_OUT signal if the Enable_IN signal is asserted and the IL_st signal is asserted. The determination unit 1602 instructs the signal generation unit 724 to assert the Enable_OUT signal if all of the ON1 to ON3 signals are asserted.

[0142] 4. Flowchart Figure 17 is a flowchart showing the control method for Example 3. The differences from Example 1 will be explained in detail below.

[0143] S801 is replaced by S1700 and S1701. In S1700, the CPU200 determines whether the Enable_IN signal is asserted and the IL_st signal is asserted. If the Enable_IN signal is asserted and the IL_st signal is asserted, the CPU200 proceeds from S1700 to S1701. If at least one of the Enable_IN signal and the IL_st signal is negated, the CPU200 proceeds from S1700 to S810. In S810, the CPU200 asserts the Enable_OUT signal, allowing relay-on control for the subsequent module.

[0144] At S1701, CPU200 negates the Enable_OUT signal and proceeds from S1701 to S802. As a result, subsequent modules are prevented from controlling the relay.

[0145] S804 is replaced by S1704. In S1704, CPU200 determines whether the Enable_IN signal is asserted and the IL_st signal is asserted. If the Enable_IN signal is asserted and the IL_st signal is asserted, CPU200 proceeds from S1704 to S805. If at least one of the Enable_IN signal and the IL_st signal is negated, CPU200 proceeds from S1700 to S810.

[0146] S807 is replaced by S1707. In S1707, CPU200 determines whether the Enable_IN signal is asserted and the IL_st signal is asserted. If the Enable_IN signal is asserted and the IL_st signal is asserted, CPU200 proceeds from S1707 to S808. If at least one of the Enable_IN signal and the IL_st signal is negated, CPU200 proceeds from S1707 to S810.

[0147] According to Embodiment 3, the CPU 200 monitors both the door switch state and the Enable_IN signal, and turns on relays 220, 230, and 240 only when both are asserted. The CPU 200 negates the Enable_OUT signal to subsequent modules while its own module is performing relay-on control. This prevents subsequent modules from performing relay-on control while the preceding module is controlling relays 220, 230, and 240. This reduces inrush current.

[0148] In Example 3, the control unit 20 is constantly supplied with a +24V power supply. However, this is just one example. As in Examples 1 and 2, the supply of the +24V power supply may be initiated by the Enable_IN signal. In that case, a permission signal for relay-on control should be provided separately from the Enable_IN signal for activation permission.

[0149] According to Embodiment 3, the Enable signal functions as a permit or prohibit signal input from outside the power supply unit 150 (e.g., controller 30, preceding module). During the permit period, when a permit signal is input or no prohibit signal is input, relays 220, 230, and 240 switch from off to on in response to the state of the door switch 23. During the non-permit period, when no permit signal is input or a prohibit signal is input, relays 220, 230, and 240 remain in the off state, regardless of the state of the door switch 23.

[0150] <Example 4> In Examples 1 and 3, the ON1 to ON3 signals are delayed using Timer 702. However, this is just one example.

[0151] Figure 18 shows a modified example of Embodiment 1. Delay circuits 1801, 1802, and 1803 are used instead of the setting unit 701, timer 702, and determination units 711, 712, and 713. When the monitoring unit 703 negates the IL_st signal (door open), it commands the signal generation units 721, 722, and 723 to generate ON signals, respectively. The signal generation units 721, 722, and 723 generate ON1, ON2, and ON3 signals, respectively. Delay circuit 1801 is connected to the output terminal of signal generation unit 721 and delays the ON1 signal by a predetermined delay time of delay4. Delay circuit 1802 is connected to the output terminal of signal generation unit 722 and delays the ON2 signal by a predetermined delay time of delay5. Delay circuit 1803 is connected to the output terminal of signal generation unit 723 and delays the ON3 signal by a predetermined delay time of delay5. The determination unit 714 causes the signal generation unit 724 to assert the Enable_OUT signal when all of the delayed ON1, ON2, and ON3 signals are asserted. The delay circuits 1801 to 1803 may be implemented by a combination of analog elements such as resistors and capacitors (analog circuits) or by logic circuits (digital circuits). The delay circuits 1801, 1802, and 1803 may be placed between the CPU 200 and the relay drive unit 203.

[0152] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0153] 221, 231: AC / DC converter, 220, 230: relay, 20: control unit

Claims

1. The first power supply unit is supplied with AC power from an AC power source, The aforementioned second power supply unit that is supplied with AC, A first relay is connected between the AC power supply and the input section of the first power supply unit, and has an ON state that supplies AC to the first power supply unit and an OFF state that does not supply AC to the first power supply unit. A second relay is connected between the AC power supply and the input section of the second power supply unit, and has an ON state that supplies AC to the second power supply unit and an OFF state that does not supply AC to the second power supply unit. A first interlock switch enters a first state when a predetermined first interlock condition is met, and enters a second state when the predetermined first interlock condition is no longer met, It has control means for controlling the first relay and the second relay, The control means is When the first interlock switch transitions from the second state to the first state, the first relay is switched from the ON state to the OFF state, and the second relay is switched from the ON state to the OFF state. A power supply device that, when the first interlock switch transitions from the first state to the second state, switches the first relay from the off state to the on state after a first delay time has elapsed from the time the transition to the second state occurred, and switches the second relay from the off state to the on state after a second delay time, which is longer than the first delay time, has elapsed from that time.

2. The third power supply unit supplied with the aforementioned AC, The system further includes a third relay connected between the AC power supply and the input section of the third power supply unit, having an ON state for supplying AC to the third power supply unit and an OFF state for not supplying AC to the third power supply unit. The control means is When the first interlock switch transitions from the second state to the first state, the first relay is switched from the ON state to the OFF state, the second relay is switched from the ON state to the OFF state, and the third relay is switched from the ON state to the OFF state. The power supply device according to claim 1, wherein when the first interlock switch transitions from the first state to the second state, the first relay is switched from the off state to the on state after the first delay time has elapsed, the second relay is switched from the off state to the on state after the second delay time has elapsed, and the third relay is switched from the off state to the on state after a third delay time, which is longer than the second delay time, has elapsed from the time when the transition occurred.

3. The third power supply unit supplied with the aforementioned AC, A third relay is connected between the AC power supply and the input section of the third power supply unit, and has an ON state that supplies AC to the third power supply unit and an OFF state that does not supply AC to the third power supply unit. The system further includes a second interlock switch that enters the first state when a predetermined second interlock condition is met, and enters the second state when the predetermined second interlock condition is no longer met. The control means is When the second interlock switch transitions from the second state to the first state, the third relay is switched from the on state to the off state. The power supply device according to claim 1, wherein when the second interlock switch transitions from the first state to the second state, the third relay is switched from the off state to the on state when a third delay time, which is longer than the second delay time, has elapsed from the time the transition occurred to the time the transition occurred.

4. The control means is configured to output a start-up permission signal to other power supply devices. The power supply device according to claim 1, wherein the activation permission signal is output after the first relay and the second relay have each transitioned to the ON state.

5. The power supply device according to claim 3, wherein the control means is configured to output a start permission signal to other power supply devices after the first relay, the second relay, and the third relay have each transitioned to the ON state.

6. It further has a counter that counts control cycles at regular intervals, The power supply device according to claim 1, wherein the control means switches the first relay from the off state to the on state when the count value of the counter is a first even number, and switches the second relay from the off state to the on state when the count value of the counter is a second even number greater than the first even number.

7. It further has a counter that counts control cycles at regular intervals, The power supply device according to claim 3, wherein the control means switches the first relay from the off state to the on state when the count value of the counter is a first even number, switches the second relay from the off state to the on state when the count value of the counter is a second even number greater than the first even number, and switches the third relay from the off state to the on state when the count value of the counter is a third even number greater than the second even number.

8. The power supply device according to claim 7, wherein the control means is configured to output a signal to another power supply device that serves as the starting point for counting the control cycle in the other power supply device after the first relay, the second relay, and the third relay have each transitioned to the ON state and the count value of the counter is an odd number.

9. The control means is During the permission period when an permission signal is input from outside the power supply unit, or when no prohibition signal is input, if the first interlock switch transitions from the first state to the second state, the first relay is switched from the off state to the on state when the first delay time has elapsed from the time the transition to the second state occurred, and the second relay is switched from the off state to the on state after the second delay time has elapsed from that time. The power supply device according to claim 1, wherein, during a non-permit period in which the permit signal is not input or the prohibit signal is input, the first relay and the second relay are kept in the off state even if the first interlock switch transitions from the first state to the second state.

10. The first module comprising the first housing, An image forming apparatus having a second module having a second housing different from the first housing, The first module is, The first power supply unit is supplied with AC power from an AC power source, The aforementioned second power supply unit that is supplied with AC, A first relay is connected between the AC power supply and the input section of the first power supply unit, and has an ON state that supplies AC to the first power supply unit and an OFF state that does not supply AC to the first power supply unit. A second relay is connected between the AC power supply and the input section of the second power supply unit, and has an ON state that supplies AC to the second power supply unit and an OFF state that does not supply AC to the second power supply unit. A first interlock switch enters a first state when a predetermined first interlock condition is met, and enters a second state when the predetermined first interlock condition is no longer met, It comprises a first control means for controlling the first relay and the second relay, The second module is, A third power supply unit that receives AC power from an AC power source, The fourth power supply unit that is supplied with the aforementioned AC, A third relay is connected between the AC power supply and the input section of the third power supply unit, and has an ON state that supplies AC to the third power supply unit and an OFF state that does not supply AC to the third power supply unit. A fourth relay is connected between the AC power supply and the input section of the fourth power supply unit, and has an ON state that supplies AC to the fourth power supply unit and an OFF state that does not supply AC to the fourth power supply unit. A second interlock switch enters the first state when a predetermined second interlock condition is met, and enters the second state when the predetermined second interlock condition is no longer met, It includes a second control means for controlling the third relay and the fourth relay, The first control means is When the first interlock switch transitions from the second state to the first state, the first relay is switched from the ON state to the OFF state, and the second relay is switched from the ON state to the OFF state. When the first interlock switch transitions from the first state to the second state, the first relay is switched from the off state to the on state when a first delay time has elapsed from the first time when the transition to the second state occurred, and the second relay is switched from the off state to the on state when a second delay time longer than the first delay time has elapsed from the first time. The second control means is When the second interlock switch transitions from the second state to the first state, the third relay is switched from the on state to the off state, and the fourth relay is switched from the on state to the off state. Image forming apparatus, wherein when the second interlock switch transitions from the first state to the second state, the third relay is switched from the off state to the on state when a third delay time has elapsed from the second time when the transition to the second state occurred, and the fourth relay is switched from the off state to the on state when a fourth delay time, which is longer than the third delay time, has elapsed from the second time.

11. The first control means is After the first relay and the second relay switch from the off state to the on state, the first enable signal is output to the second module. The second control means is During the first permission period in which the first control means outputs the first permission signal, When the second interlock switch transitions from the second state to the first state, the third relay is switched from the on state to the off state, and the fourth relay is switched from the on state to the off state. The image forming apparatus according to claim 10, wherein when the second interlock switch transitions from the first state to the second state, the third relay is switched from the off state to the on state when the third delay time has elapsed from the second time, and the fourth relay is switched from the off state to the on state when the fourth delay time has elapsed from the second time.

12. The first control means has a first counter that counts a first control cycle at regular intervals, The second control means has a second counter that counts a second control cycle at regular intervals, The first control means switches the first relay from the off state to the on state when the count value of the first counter is a first even number, and switches the second relay from the off state to the on state when the count value of the first counter is a second even number greater than the first even number. The second control means switches the third relay from the off state to the on state when the count value of the second counter is a third even number, and switches the fourth relay from the off state to the on state when the count value of the second counter is a fourth even number greater than the third even number. The image forming apparatus according to claim 10.

13. The image forming apparatus according to claim 12, wherein the starting point of the first control cycle and the starting point of the second control cycle are offset.

14. The first control means outputs a predetermined control signal to the second control means after the first relay and the second relay are turned on. The image forming apparatus according to claim 13, wherein the second control means starts counting the second control cycle starting from the predetermined control signal.

15. When the first interlock switch switches from the first state to the second state, the first control means negates a predetermined control signal to the second control means, and asserts the predetermined control signal after the first relay and the second relay are turned on. The image forming apparatus according to claim 11, wherein the second control means does not turn on the third relay and the fourth relay during the period when the predetermined control signal is negated, and turns on the third relay and the fourth relay when the second interlock switch switches from the first state to the second state during the period when the predetermined control signal is asserted.

16. It further comprises a third module having a third housing, The third module is, A fifth power supply unit that receives AC power from an AC power source, The sixth power supply unit that is supplied with the aforementioned AC, A fifth relay is connected between the AC power supply and the input section of the fifth power supply unit, and has an ON state that supplies AC to the fifth power supply unit and an OFF state that does not supply AC to the fifth power supply unit. A sixth relay is connected between the AC power supply and the input section of the sixth power supply unit, and has an ON state that supplies AC to the sixth power supply unit and an OFF state that does not supply AC to the sixth power supply unit. A third interlock switch that enters the first state when a predetermined third interlock condition is met, and enters the second state when the predetermined third interlock condition is no longer met, It comprises a third control means for controlling the fifth relay and the sixth relay, The third control means is When the third interlock switch transitions from the second state to the first state, the fifth relay is switched from the on state to the off state, The image forming apparatus according to claim 10, wherein when the third interlock switch transitions from the first state to the second state, the fifth relay is switched from the off state to the on state when a fifth delay time has elapsed from the third time when the transition to the second state occurred, and the sixth relay is switched from the off state to the on state when a sixth delay time longer than the fifth delay time has elapsed from the third time.

17. An image forming apparatus having N modules, An image forming apparatus, wherein each of the N modules has a power supply device as described in any one of claims 1 to 9.

18. An image forming apparatus having N modules, Each of the N modules is The first power supply unit is supplied with AC power from an AC power source, The aforementioned second power supply unit that is supplied with AC, A first relay is connected between the AC power supply and the input section of the first power supply unit, and has an ON state that supplies AC to the first power supply unit and an OFF state that does not supply AC to the first power supply unit. A second relay is connected between the AC power supply and the input section of the second power supply unit, and has an ON state that supplies AC to the second power supply unit and an OFF state that does not supply AC to the second power supply unit. An interlock switch that turns off when a predetermined interlock condition is met, and turns on when the predetermined interlock condition is no longer met, It has control means for controlling the first relay and the second relay, The control means performs a remainder operation of N on the count value of the internal control period to obtain a solution, switches the first relay from the off state to the on state at a first timing when the solution is a first value, and switches the second relay from the off state to the on state at a second timing later than the first timing and when the solution is a first value.

19. The image forming apparatus according to claim 18, wherein the control means outputs a control signal to the other modules among the N modules, which serves as the starting point for the internal control cycle in the other modules, at the timing when the solution becomes a second value different from the first value.

20. The image forming apparatus according to claim 18, wherein the starting points of the internal control cycles in each of the N modules are offset from each other.

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