Power converter, air conditioner, parameter adjuster, parameter adjustment system, and method of using the parameter adjustment system

Abstract

Reduce the component costs of power conversion devices. [Solution] The power converter (10) is provided with a semiconductor switching element (110), a storage unit (43, 120) for storing parameters (PA) related to the gate voltage waveform, and a drive circuit (130) that refers to the gate drive signal (GS) and the parameters (PA) stored in the storage unit (43, 120) and applies a gate voltage waveform corresponding to the parameters (PA) to the semiconductor switching element (110).

Description

Technical Field

[0001] The present disclosure relates to a power conversion device, an air conditioner, a parameter adjuster, a parameter adjustment system, and a method of using the parameter adjustment system.

Background Art

[0002] The power conversion device disclosed in Patent Document 1 includes a plurality of semiconductor switching elements, an inverter that outputs current to a motor, and a basic signal generation unit that generates a pulse width modulation signal having a duty ratio according to state quantities such as the input current, output voltage, and output current of the inverter. It also includes an opening / closing characteristic setting unit that generates an opening / closing characteristic setting signal for controlling the magnitude and output timing of the drive signal for driving the semiconductor switching element based on state quantities such as the input current, output voltage, and output current of the inverter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above Patent Document 1, since an opening / closing characteristic setting unit having a high-level arithmetic processing function for generating an opening / closing characteristic setting signal is provided in the power conversion device, the component cost of the power conversion device becomes high.

[0005] An object of the present disclosure is to reduce the component cost of the power conversion device.

Means for Solving the Problems

[0006] A first aspect of the technology disclosed herein is a power converter comprising: a leg having a semiconductor switching element (110) having a first electrode (111), a second electrode (112), and a third electrode (113), wherein a main current corresponding to a control voltage applied to the first electrode (111) flows from the second electrode (112) to the third electrode (113); a rewritable storage unit (43, 120) for storing parameters (PA) relating to the waveform of the control voltage when the semiconductor switching element (110) is switched; and a drive circuit (130) that refers to a drive signal (GS) indicating whether or not to turn on the semiconductor switching element (110) and the parameters (PA) stored in the storage unit (43, 120) and applies the control voltage with a waveform corresponding to the parameters (PA) to the semiconductor switching element (110), wherein the semiconductor switching element The start timing (TG1) of the rising edge of the control voltage waveform when (110) is turned on is defined as the timing when the control voltage has risen to 10% of its peak voltage, the end timing (TG2) of the rising edge of the control voltage waveform when the semiconductor switching element (110) is turned on is defined as the timing when the control voltage has risen to 90% of its peak voltage, the number of semiconductor switching elements (110) is set to M, which is 2 or more, and the first period (tg) from the start timing (TG1) to the end timing (TG2) of the rising edge of the control voltage waveform when the x-th semiconductor switching element (110) among the M semiconductor switching elements (110) is turned on is divided equally into 20 divided periods (dt), and the rate of change of the control voltage in the y-th divided period (dt) of the 20 divided periods (dt) is defined as ΔV g Let [x] and [y] be the two periods from the timing (T2) when the main current of the x-th semiconductor switching element (110) rises to 10% of its peak current due to the rising edge of the control voltage waveform, to the timing (T3) when the main current of the x-th semiconductor switching element (110) rises to 90% of its peak current due to the rising edge of the control voltage waveform. r Let [x] be i, and let y be i. Substitute all integers between 1 and M for x to find ΔV. gThe maximum value of [x][y] is ΔV g_max [i], where y is i, and ΔV when all integers from 1 to M are substituted into x g The average value of [x][y] is ΔV g_ave [i], and ΔV when all integers from 1 to 20 are substituted into i g_max [i] / ΔV g_ave Let the maximum value of [i] be MAX, and t when all integers from 1 to M are substituted into x r The maximum value of [x] is t r_max , and t when all integers from 1 to M are substituted into x r The average value of [x] is t r_avg The power conversion device (10) is such that the following equation holds when

[0007] Max > t r_max / t r_avg In the first aspect, if the parameter (PA) regarding the gate voltage waveform is stored in the storage units (43, 120), the power conversion device (10) does not need to have a function of calculating the parameter (PA) based on the state quantity such as the output current of the power conversion device (10), and the gate voltage can be made into a waveform corresponding to the parameter (PA). Therefore, the component cost of the power conversion device (10) can be reduced.

[0008] Also, t r_max / t r_avg Compared with the case where it is larger than MAX, in the second period of the plurality of semiconductor switching elements (110), that is, t r [x] can be made uniform. That is, the individual variation of [x] in the second period of the semiconductor switching element (110), that is, t r can be suppressed.

[0009] The second aspect of the technology disclosed herein is that, in the first aspect, the power conversion device (10) includes a case (180), and the semiconductor switching element (11)0, the storage unit (120), and the drive circuit (130) are housed in the case (180).

[0010] A third aspect of the technology disclosed herein is, in the second aspect, the case (180) is provided with a terminal (183) for adjusting the parameter (PA) that allows the storage unit (120) to be connected to the outside of the case (180), and the adjustment terminal (183) is maintained at a predetermined voltage when it is not connected to the outside or when the storage unit (120) is powered on.

[0011] A fourth aspect of the technology disclosed herein is the power converter (10) in the first aspect, comprising a case (180) and a circuit board (41), wherein the semiconductor switching element (110) and the drive circuit (130) are housed in the case (180), and the storage unit (120) is mounted on the circuit board (41) outside the case (180).

[0012] A fifth aspect of the technology disclosed herein is, in the fourth aspect, the case (180) is indicated with an identifier (182) for identifying the parameter (PA).

[0013] In the fifth aspect, a user or device can store the parameter (PA) in the storage unit (43) by referring to the identifier (182).

[0014] A sixth aspect of the technology disclosed herein is that, in any one of the first to fifth aspects, the drive circuit (130) comprises a plurality of resistors (161) connected in parallel with each other between a voltage source (164) and the gate of a semiconductor switching element (110), at least one switch (162) connected in series with at least one of the plurality of resistors (161) between the voltage source (164) and the gate of the semiconductor switching element (110), and a switch control unit (163) that controls the on / off state of the switch (162) based on a parameter (PA) stored in the memory unit (43,120).

[0015] In the sixth embodiment, the gate voltage waveform can be controlled by controlling the on / off state of the switch (162).

[0016] A seventh aspect of the technology disclosed herein is that, in the first to sixth aspects, the storage unit (43,120) is a non-volatile memory.

[0017] In the seventh embodiment, even if the power supply to the power converter (10) is turned off after the parameters (PA) have been stored in the storage unit (43,120), the parameters (PA) are retained in the storage unit (43,120).

[0018] An eighth aspect of the technology disclosed herein is, in the second or third aspect, the case (180) is provided with a terminal (181) for reading the parameter (PA) that allows the storage unit (120) to be connected to the outside of the case (180).

[0019] In the eighth aspect, the parameters (PA) stored in the memory unit (120) can be read out from a device outside the case (180) via a reading terminal (181).

[0020] A ninth aspect of the technology disclosed herein relates to an air conditioner (1). The air conditioner (1) comprises a power converter (10) according to any one of the first to eighth aspects.

[0021] A tenth aspect of the technology disclosed herein is a parameter adjuster (20) which transmits the gate drive signal (GS) to one of the first to eighth power converters (10), acquires the current waveform of the drain current or collector current of the semiconductor switching element (110) when the gate voltage corresponding to the gate drive signal (GS) is applied and the parameter adjuster (20) calculates the parameter (PA) based on the current waveform and a predetermined reference relating to a target current waveform stored in the parameter adjuster (20), and performs a parameter adjustment operation which transmits the parameter (PA) to the storage unit (120) of the power converter (10).

[0022] In the tenth embodiment, an appropriate parameter (PA) can be calculated based on the current waveform of the drain current or collector current during switching of the semiconductor switching element (110), and this can be reflected in the gate voltage of the semiconductor switching element (110).

[0023] Furthermore, since the power converter (10) does not need to have a function to perform parameter adjustment operations, the component cost of the power converter (10) can be reduced.

[0024] An eleventh aspect of the technology disclosed herein is a parameter adjustment system (2) comprising a power converter (10) according to any one of the first to eighth aspects and a parameter adjuster (20) according to the tenth aspect.

[0025] A twelfth aspect of the technology disclosed herein, in the eleventh aspect, is that at least one of the storage unit (43,120) and the parameter adjuster (20) holds an initial value of the parameter (PA).

[0026] A thirteenth aspect of the technology disclosed herein is, in the eleventh or twelfth aspect, the parameter adjuster (20) repeats the parameter adjustment operation until the current waveform satisfies the predetermined criteria.

[0027] In the 13th embodiment, the current waveform of the drain current or collector current during switching of the semiconductor switching element (110) can be made to satisfy a predetermined standard.

[0028] A fourteenth aspect of the technology disclosed herein relates to a method of using a parameter adjustment system according to any one of the eleventh to thirteenth aspects, wherein the parameter adjuster (20) is made to perform the parameter adjustment operation during a manufacturing inspection process of the power converter (10). [Brief explanation of the drawing]

[0029] [Figure 1] Figure 1 is a block diagram showing the configuration of an air conditioner equipped with a power converter according to Embodiment 1. [Figure 2] Figure 2 is a circuit diagram showing the configuration of an inverter circuit. [Figure 3] Figure 3 is a circuit diagram showing the configuration of the time-series data generation unit and the gate voltage generation unit. [Figure 4] Figure 4 is an explanatory diagram illustrating the waveform of the gate voltage. [Figure 5] Figure 5 is a timing chart illustrating the waveforms of the drain-source voltage and drain current during the turn-on phase of a semiconductor switching element. [Figure 6] Figure 6 is a diagram equivalent to Figure 5 when the semiconductor switching element is turned off. [Figure 7] Figure 7 is a table showing the parameters corresponding to the gate voltage shown in Figure 4. [Figure 8] Figure 8 is a block diagram showing the configuration of a parameter adjustment system equipped with a power conversion device according to Embodiment 1. [Figure 9] Figure 9 is a flowchart illustrating the operation of the parameter adjustment system. [Figure 10] Figure 10 is a timing chart showing the gate voltage waveform when a semiconductor switching element is turned on. [Figure 11] Figure 11 is a timing chart showing the waveforms of the drain-source voltage, main current, and gate voltage during the rise time of the gate voltage of a semiconductor switching element. [Figure 12] Figure 12 is a block diagram showing the configuration of the power converter according to Embodiment 2. [Figure 13] Figure 13 is a diagram corresponding to Figure 8 of Embodiment 2. [Modes for carrying out the invention]

[0030] The embodiments of this disclosure will be described in detail below with reference to the drawings. However, this disclosure is not limited to the embodiments shown below, and various modifications are possible without departing from the technical idea of ​​this disclosure.

[0031] (Embodiment 1) Figure 1 shows an air conditioner (1). This air conditioner (1) performs, for example, indoor air conditioning. The air conditioner (1) comprises a power converter (10) according to Embodiment 1 of the present disclosure and a compressor (50). The power converter (10) converts and outputs power supplied from an AC power source. The compressor (50) compresses a gaseous refrigerant using the output power of the power converter (10).

[0032] The power converter (10) is a power module comprising a rectifier circuit (not shown) for rectifying power supplied from an AC power source, a plurality of semiconductor switching elements (110), a non-volatile memory (120) as a storage unit, a drive circuit (130), and a case (180).

[0033] As shown in Figure 2, six semiconductor switching elements (110) are provided to constitute a three-phase inverter circuit (11). The six semiconductor switching elements (110) constitute three legs (L1, L2, L3) each having an upper arm and a lower arm semiconductor switching element (110) connected in series with each other. The semiconductor switching elements (110) are N-channel MOS (metal-oxide-semiconductor) transistors. The inverter circuit (11) converts the DC output from the rectifier circuit into three-phase AC and supplies it to the motor (51) of the compressor (50). The semiconductor switching element (110) has a gate electrode (111) as the first electrode, a drain electrode (112) as the second electrode, and a source electrode (113) as the third electrode. A main current corresponding to the gate voltage, which is a control voltage applied to the gate electrode (111), flows from the drain electrode (112) to the source electrode (113).

[0034] The non-volatile memory (120) stores parameters (PA) related to the gate voltage waveform for each semiconductor switching element (110). In other words, the non-volatile memory (120) stores parameters (PA) for six semiconductor switching elements (110), i.e., six sets of parameters (PA). The non-volatile memory (120) is a flash memory. The parameters (PA) stored in the non-volatile memory (120) can be rewritten. Alternatively, a non-volatile memory (120) may be provided for each semiconductor switching element (110), and each non-volatile memory (120) may store the parameters (PA) of the corresponding semiconductor switching element (110).

[0035] The drive circuit (130) refers to the gate drive signals (GS) of the six semiconductor switching elements (110) and parameters (PA) stored in the non-volatile memory (120), and applies a gate voltage with a waveform corresponding to the parameters (PA) to each semiconductor switching element (110). The gate drive signal (GS) is a signal indicating whether or not to turn on the semiconductor switching element (110).

[0036] In terms of specific configuration, the drive circuit (130), as shown in Figure 3, is equipped with a time-series data generation unit (140) and a gate voltage generation unit (160) for each semiconductor switching element (110).

[0037] The time-series data generation unit (140) includes a data transmission / reception circuit (141), a controller (142), a volatile memory (143), an oscillator (144), a PLL (phase-locked loop) (145), an edge detection circuit (146), a counter (147), and an address selector (148).

[0038] The data transmission circuit (141) receives parameters from the parameter adjuster (20), which will be described later, and transmits them to the controller (142).

[0039] The controller (142) transmits the parameters received from the data transmission circuit (141) to the non-volatile memory (120). The controller (142) also receives parameters (PA) from the non-volatile memory (120) and transfers them to the volatile memory (143).

[0040] When the controller (142) transfers a parameter (PA) from the non-volatile memory (120) to the volatile memory (143), it sends the address indicating the write area of ​​the parameter (PA) in the volatile memory (143) to the address selector (148) as a selector signal (Sse).

[0041] Furthermore, the controller (142) outputs a switching signal (Ssw) to the address selector (148) that switches the output of the address selector (148) between the selector signal (Sse) and the output (count value) of the counter (147).

[0042] Furthermore, the controller (142) outputs a counter control signal (Sc) to the counter (147) that sets whether the counter (147) is enabled or disabled.

[0043] The volatile memory (143) stores the parameters (PA) received from the controller (142). Furthermore, when the semiconductor switching element (110) is driven, the volatile memory (143) outputs the data output by the address selector (148), i.e., the address data corresponding to the count value of the counter (147), as parameters (PA) to the gate voltage generation unit (160). At this time, the parameters output by the volatile memory (143) are updated with each cycle of the counter (147).

[0044] The oscillator (144) outputs an AC signal of a predetermined frequency.

[0045] The PLL (145) outputs a clock signal of a predetermined frequency based on the AC signal output by the oscillator (144).

[0046] The edge detection circuit (146) detects the rising and falling edges of the gate drive signal (GS) output from the parameter adjuster (20), which will be described later, and outputs a detection signal. The edge detection circuit (146) operates in synchronization with the clock signal output by the PLL (145).

[0047] The counter (147) is reset when the counter control signal (Sc) is disabled. On the other hand, when the counter control signal (Sc) is enabled, the counter (147) is triggered by the detection signal from the edge detection circuit (146), counts up in sync with the clock signal, and outputs the count value to the address selector (148).

[0048] The address selector (148) outputs either the selector signal (Sse) or the count value of the counter (147) as an address to the volatile memory (143) in response to the switching signal (Ssw).

[0049] In the time-series data generation unit (140) configured as described above, when the controller (142) transfers parameters (PA) from the non-volatile memory (120) to the volatile memory (143), it outputs a switching signal (Ssw) that selects the selector signal (Sse) as the output of the address selector (148). As a result, the selector signal (Sse), i.e., the address output by the controller (142), is output from the address selector (148). Then, the parameters (PA) read from the non-volatile memory (120) are written to the address output by the controller (142) in the volatile memory (143).

[0050] Once the transfer is complete, the controller (142) outputs a switching signal (Ssw) to the address selector (148) that switches the output of the address selector (148) to the output of the counter (147). The controller (142) also enables the counter (147) with a counter control signal (Sc). As a result, the count value of the counter (147) is output as an address from the address selector (148). The volatile memory (143) then outputs the address data corresponding to the address output by the address selector (148), i.e., the count value of the counter (147), as a parameter (PA) to the gate voltage generation unit (160).

[0051] Each gate voltage generating unit (160) includes a plurality of resistors (161), a plurality of switches (162), and a selector (163) which acts as a switch control unit.

[0052] Multiple resistors (161) are connected in parallel to each other between a voltage source (164) and the gate of a corresponding semiconductor switching element (110). Between the voltage source (164) and the gate of the corresponding semiconductor switching element (110), one of the multiple switches (162) is connected in series to each resistor (161). In this embodiment 1, one switch (162) is connected in series to each resistor (161), but it is also possible to have switches (162) connected in series to only some of the resistors (161). It is sufficient that at least one switch (162) is connected in series to one resistor (161).

[0053] The selector (163) turns on the switch (162) that is designated as on by the parameter (PA) output by the volatile memory (143) from among the multiple switches (162), and turns off the other switches (162). In other words, the selector (163) reads the parameter (PA) stored in the non-volatile memory (120) via the time-series data generation unit (140) and controls the on / off status of the switches (162) based on the parameter (PA).

[0054] In the gate voltage generation unit (160) configured as described above, the gate voltage waveform of the semiconductor switching element (110) can be controlled by controlling the on / off state of the switch (162).

[0055] The inverter circuit (11), non-volatile memory (120), and drive circuit (130) are housed in a common case (180).

[0056] The case (180) is provided with a parameter (PA) reading terminal (181) that allows connection between the non-volatile memory (120) and the outside of the case (180). The reading terminal (181) can be used to read the parameters (PA) stored in the memory unit (120) from a device outside the case (180). The reading terminal (181) can be used for purposes such as verifying what waveform voltage was applied when the semiconductor switching element (110) failed, and confirming whether the parameters (PA) to be written are reliably stored in the memory unit (120).

[0057] Furthermore, the case (180) is provided with a parameter (PA) adjustment terminal (183) that allows connection between the non-volatile memory (120) and the outside of the case (180). Before shipping the power converter (10), the parameter (PA) may be adjusted by connecting the adjustment terminal (183) to the outside, and after shipping the power converter (10), regardless of whether the adjustment terminal (183) is connected to the outside or not, the voltage applied to the adjustment terminal (183) may be maintained at a predetermined voltage during the period when the non-volatile memory (120) is powered on. Specifically, the voltage applied to the adjustment terminal (183) may be maintained at a predetermined voltage during the period when the non-volatile memory (120) is powered on by pulling up or pulling down the adjustment terminal (183). In other words, the voltage of the adjustment terminal (183) may be maintained at a predetermined voltage during the period when the non-volatile memory (120) is powered on. Additionally, after shipment, the adjustment terminal (183) may be left disconnected from the outside.

[0058] The parameters (PA) stored in the non-volatile memory (120) are information for generating gate voltage waveforms, for example, as shown in Figure 4. More specifically, the parameters (PA) are information for generating gate voltage waveforms at the rising edge of the gate voltage that yields the drain-source voltage and drain current during turn-on, as shown in Figure 5, and at the falling edge of the gate voltage that yields the drain-source voltage and drain current during turn-off, as shown in Figure 6. Figure 7 is a table illustrating some of the parameters (PA). Figure 7 illustrates parameters (PA) that show the switching patterns of multiple switches (162) from the start to the completion of the gate voltage rise. In this example, the parameters (PA) indicate the on / off states of multiple switches (162) connected in series with multiple resistors (161) at predetermined timings from the start to the completion of the gate voltage rise. The information in different columns in Figure 7 is stored at different addresses in the volatile memory (143). The timing difference between adjacent columns in Figure 7 corresponds to one period of the clock input to the counter (147).

[0059] Figure 8 shows a parameter adjustment system (2) comprising the power converter (10) and parameter adjuster (20) described above. Communication between the power converter (10) and the parameter adjuster (20) may be performed by wire or wireless means.

[0060] The parameter adjuster (20) performs a parameter adjustment operation during the inspection process when manufacturing the power converter (10), which involves sending new parameters (PA) to the non-volatile memory (120).

[0061] More specifically, the parameter adjuster (20) comprises an analog data measurement circuit (21), a CPU (Central Processing Unit) (22), a hard disk (23), a communication interface (24), and a signal generator (25).

[0062] The analog data measurement circuit (21) acquires the current waveform of the drain current of each semiconductor switching element (110).

[0063] The CPU (22) transmits a write flag (F1) and a transfer flag (F2) to the power converter (10) via a communication interface (24). The CPU (22) also acquires the current waveform of the drain current during switching of the semiconductor switching element (110) when a gate voltage corresponding to the gate drive signal (GS) transmitted by the signal generator (25) is applied, from the analog data measurement circuit (21). The CPU (22) then calculates parameters (PA) based on this current waveform and predetermined criteria for the target current waveform stored in the hard disk (23). Specifically, if the current waveform acquired by the analog data measurement circuit (21) does not meet the predetermined criteria for the target current waveform stored in the hard disk (23), the CPU (22) modifies the parameters (PA). Such modification is performed to bring the current waveform acquired by the analog data measurement circuit (21) closer to the target current waveform. Furthermore, at the start of the parameter adjustment operation described later, and when the parameter (PA) is modified, the CPU (22) transmits the parameter (PA) at that time to the power converter (10) via the communication I / F (24).

[0064] The hard disk (23) stores predetermined criteria for the target current waveform and initial values ​​for the parameters (PA).

[0065] The signal generator (25) transmits a gate drive signal (GS) to the power converter (10) at the same time that the CPU (22) transmits a parameter (PA) to the power converter (10).

[0066] Next, the operation of the parameter adjustment system (2) described above during the inspection process when manufacturing the power converter (10) will be explained with reference to the flowchart in Figure 9. At the start of the inspection process, the initial values ​​of the parameters (PA) are stored in the hard disk (23) of the parameter adjuster (20). By having the parameter adjuster (20) store the initial values ​​of the parameters (PA), the effort of storing the initial values ​​of the parameters (PA) for each power converter (10) being manufactured is eliminated. Alternatively, although this effort is required, the initial values ​​of the parameters (PA) may be stored in the non-volatile memory (120) of the power converter (10).

[0067] In step S101 of Figure 9, the CPU (22) of the parameter tuner (20) sets the write flag (F1).

[0068] Next, in step S102, the CPU (22) of the parameter adjuster (20) transmits the parameter (PA) to the time-series data generation unit (140) of the power converter (10). In response, the data transmission / reception circuit (141) of the time-series data generation unit (140) receives the parameter (PA) via the adjustment terminal (183). The controller (142) writes the parameter (PA) received by the data transmission / reception circuit (141) to the non-volatile memory (120). In this way, the CPU (22) of the parameter adjuster (20) transmits the parameter (PA) to the non-volatile memory (120) via the time-series data generation unit (140) of the power converter (10). When step S102 is executed for the first time, the CPU (22) transmits the initial value of the parameter (PA) held in the hard disk (23) to the power converter (10). On the other hand, when step S102 is executed for the second time or later, the CPU (22) sends the new parameter (PA) calculated in the most recent step S112 to the power converter (10). In this way, the parameter (PA) can be stored in the non-volatile memory (120) of the power converter (10) via the adjustment terminal (183) from a device outside the case (180).

[0069] Next, in step S103, the CPU (22) of the parameter tuner (20) determines whether or not the writing of the parameters (PA) to the non-volatile memory (120) is complete. If it is complete, the process proceeds to step S104; otherwise, the process returns to step S102.

[0070] In step S104, the CPU (22) of the parameter adjuster (20) sets the porting flag (F2).

[0071] In step S105, the controller (142) of the time-series data generation unit (140) reads the parameters (PA) stored in the non-volatile memory (120) and transfers them to the volatile memory (143).

[0072] In step S106, the CPU (22) of the parameter tuner (20) determines whether the transfer of parameters (PA) to the volatile memory (143) is complete. If the transfer is complete, the process proceeds to step S107; otherwise, the process in step S106 is repeated.

[0073] In step S107, the signal generator (25) transmits a gate drive signal (GS) to the power converter (10).

[0074] In step S108, the controller (142) enables the counter control signal (Sc). The address selector (148) outputs the count value of the counter (147) of the time-series data generation unit (140) as an address to the volatile memory (143). The volatile memory (143) outputs the parameter (PA) of the address corresponding to the count value. The parameter (PA) output by the volatile memory (143) is updated with each cycle of the counter (147).

[0075] In step S109, the gate voltage generation unit (160) outputs a gate voltage corresponding to the gate drive signal (GS) and the parameter (PA) output from the volatile memory (143). A switch (162), which is turned on when the gate drive signal (GS) becomes high level, is switched according to the parameter (PA) output from the volatile memory (143), thereby changing the gate voltage applied to the semiconductor switching element (110).

[0076] In step S110, the analog data measurement circuit (21) of the parameter adjuster (20) acquires the current waveform of the drain current of the semiconductor switching element (110) when a gate voltage corresponding to the gate drive signal (GS) is applied (step S109). In other words, the drain current of the semiconductor switching element (110) is fed back to the parameter adjuster (20).

[0077] In step S111, the CPU (22) of the parameter adjuster (20) determines whether the current waveform acquired in step S110 meets a predetermined criterion for the target current waveform stored in the hard disk (23). If the current waveform acquired in step S110 meets the predetermined criterion, the process ends. On the other hand, if the current waveform acquired in step S110 does not meet the predetermined criterion, the process proceeds to step S112.

[0078] In step S112, the CPU (22) of the parameter adjuster (20) modifies the parameters (PA) so that the current waveform acquired by the analog data measurement circuit (21) approaches the target current waveform stored in the hard disk (23). In other words, the CPU (22) calculates new parameters (PA) based on the current waveform acquired by the analog data measurement circuit (21) and a predetermined reference for the target current waveform stored in the hard disk (23).

[0079] In step S113, the CPU (22) of the parameter tuner (20) determines whether or not it has completed modifying the parameter (PA). If it has completed modifying the parameter (PA), the process returns to step S102. On the other hand, if it has not completed modifying the parameter (PA), the CPU (22) continues modifying the parameter (PA) in step S112.

[0080] The operations performed by the parameter adjuster (20) in steps S101 to S113 correspond to the parameter adjustment operation. The parameter adjustment operation is repeated until the current waveform acquired in step S110 meets a predetermined criterion for the target current waveform stored in the hard disk (23).

[0081] Through this parameter adjustment operation, an appropriate parameter (PA) can be calculated based on the current waveform of the drain current during switching of the semiconductor switching element (110), and this can be reflected in the gate voltage of the semiconductor switching element (110). Furthermore, the current waveform of the drain current during switching of the semiconductor switching element (110) can be made to meet a predetermined standard.

[0082] Here, Figure 10 shows the waveform of the gate voltage when the semiconductor switching element (110) is turned on. The waveform of the gate voltage is adjusted by a parameter (PA) according to the characteristics of the semiconductor switching element (110). As shown in Figure 10, the start timing (TG1) of the rising edge of the gate voltage waveform when the semiconductor switching element (110) is turned on is set to the timing when the gate voltage has risen to 10% of its peak voltage. The end timing (TG2) of the rising edge of the gate voltage waveform when the semiconductor switching element (110) is turned on is set to the timing when the gate voltage has risen to 90% of its peak voltage.

[0083] Hereinafter, the number of semiconductor switching elements (110) will be M. In this embodiment 1, M = 6. In Figure 10, the first period (tg) from the start timing (TG1) to the end timing (TG2) of the rising edge of the gate voltage waveform when the x-th semiconductor switching element (110) among the M (6) semiconductor switching elements (110) is turned on is divided equally into 20 divided periods (dt). Here, the rate of change of the gate voltage in the y-th divided period (dt) of the 20 divided periods (dt) is ΔV. g Let [x] and [y] be the two periods. As shown in Figure 11, the second period is defined as the time from when the main current of the x-th semiconductor switching element (110) rises to 10% of its peak current due to the rising edge of the gate voltage waveform (rising edge at T1) (T2) to when the main current of the x-th semiconductor switching element (110) rises to 90% of its peak current due to the rising edge of the gate voltage waveform (T3) (T2). r Let [x] be the value.

[0084] Then, let y be i, and substitute all integers between 1 and M(6) for x, and then consider ΔV. g The maximum value of [x][y] is ΔV g_max Let [i] be the case. That is, ΔV g_max [i] is ΔV g [1][i], ΔV g [2][i], ΔV g [3][i], ΔV g [4][i], ΔV g [5][i] and ΔV g [6] is the maximum value of i. Also, when y is i and x is all integers between 1 and 6, the ΔV is g The mean of [x][y] is ΔV g_ave Let [i] be the case. That is, ΔV g_ave [i] is ΔV g [1][i], ΔV g [2][i], ΔV g [3][i], ΔV g [4][i], ΔV g [5][i] and ΔV gThis is the average value of [6][i]. And, when all integers between 1 and 20 are substituted for i, ΔV g_max [i] / ΔV g_ave Let the maximum value of [i] be MAX. In other words, MAX is ΔV g_max [1] / ΔV g_ave [1], ΔV g_max [2] / ΔV g_ave [2], ΔV g_max [3] / ΔV g_ave [3], ...ΔV g_max

[18] / ΔV g_ave

[18] , ΔV g_max

[19] / ΔV g_ave

[19] , ΔV g_max

[20] / ΔV g_ave This is the maximum value of

[20] . The MAX tends to be larger when there are significant differences in the characteristics of the six semiconductor switching elements (110).

[0085] Also, when all integers between 1 and M(6) are substituted for x, the value of t is... r The maximum value of [x] is t r_max Let's assume that t r [1], t r [2], t r [3], t r [4], t r [5] and t r [6] The maximum value of t r_max Let's assume that when we substitute all integers between 1 and 6 for x, we get t r The mean value of [x] is t r_avg Let's assume that t r [1], t r [2], t r [3], t r [4], t r [5] and t r [6] The average value of t r_avg Let's assume that.

[0086] In this embodiment 1, the parameters (PA) are adjusted so that the following equation (1) holds true when the drain current values ​​of M (6) semiconductor switching elements (110) are equal to each other.

[0087] Max>t r_max / t r_avg ...(1) Therefore, according to this embodiment 1, by storing parameters (PA) related to the gate voltage waveform in a non-volatile memory (120), the gate voltage can be made to a waveform corresponding to the parameters (PA) without requiring the power converter (10) to have a function to perform parameter adjustment operations that calculate parameters (PA) based on state quantities such as the output current of the power converter (10). Consequently, the component cost of the power converter (10) can be reduced.

[0088] Furthermore, by making the non-volatile memory (120) rewritable, the initial parameter (PA) can be rewritten with the new parameter (PA) calculated in step S112.

[0089] Furthermore, since parameters (PA) related to the gate voltage waveform are stored in the non-volatile memory (120), even if the power supply to the power converter (10) is turned off after the parameters (PA) have been stored in the non-volatile memory (120), the parameters (PA) will remain in the non-volatile memory (120).

[0090] Furthermore, the parameter (PA) obtained in step S110 when the current waveform meets a predetermined criterion is maintained as the final parameter (PA) in the rewritable non-volatile memory (120), even if the power supply to the power converter (10) is turned off. Therefore, the gate voltage generation unit (160) can output the optimal gate waveform without providing the function of a parameter adjuster (20) in the power converter (power module) (10).

[0091] Main current rise time (second period, t r [x]) has individual variations due to the semiconductor switching element (110). This individual variation causes variations in the output voltage of the power converter (10). In this embodiment 1, t r_max / t r_avg The parameter (PA) is adjusted so that it becomes smaller than MAX, r_max / t r_avgCompared to the case where it is greater than MAX, the second period (t) of multiple semiconductor switching elements (110) r [x]) can be made equal. In other words, the rise time of the main current of the semiconductor switching element (110) (second period, t r [x]) individual variation can be suppressed. Main current rise time (second period, t r By suppressing individual variations in [x]), for example, variations in the output voltage of the power converter (10) can be suppressed, and the control performance of the inverter circuit (11) can be improved.

[0092] Here, consider the case where one of the switching elements (110) on the upper and lower arms of a common leg (L1, L2, L3) is turned off, and then the gate voltage of the other switching element (110) is turned on. In such a case, even if the other switching element (110) has the shortest rise time, it is necessary to set a dead time so that the other switching element (110) turns on after the first switching element (110) has completely turned off. In this embodiment 1, t r_max / t r_avg The parameter (PA) is adjusted so that it becomes smaller than MAX, r_max / t r_avg This allows for a shorter dead time compared to when the value is greater than the maximum.

[0093] (Embodiment 2) Figure 12 shows a power converter (10) according to Embodiment 2 of the present disclosure. In Embodiment 2, the case (180) of the power converter (10) does not house a non-volatile memory (120). Also, the case (180) is not provided with a read terminal (181) and an adjustment terminal (183). Furthermore, an identifier (182) for identifying parameters (PA) is printed on the case (180). The identifier (182) can be a character, a graphic, etc., for example, a QR code (registered trademark), a serial number, etc. The power converter (10) also further includes an inverter microcontroller (40). The inverter microcontroller (40) has a circuit board (41), a processing unit (42), and a non-volatile memory (43) as a storage unit. The processing unit (42) and the non-volatile memory (43) are mounted on the circuit board (41) outside the case (180). In this embodiment 2, the inverter circuit (11) and the drive circuit (130) are not mounted on the circuit board (41), but the inverter circuit (11) and the drive circuit (130) may be mounted on the same circuit board (41) as the processing unit (42) and the non-volatile memory (43).

[0094] Figure 13 is a diagram corresponding to Figure 8 of Embodiment 2. The parameter adjustment system (2) according to Embodiment 2 further includes a printing device (30).

[0095] In the parameter adjustment system (2) according to this second embodiment, steps S101 to S103 of the steps shown in Figure 9 are not executed. Also, in step S105, the controller (142) of the time-series data generation unit (140) reads the parameters (PA) stored in the hard disk (23) of the parameter adjuster (20) and transfers them to the volatile memory (143) of the time-series data generation unit (140). Then, in step S113, if the CPU (22) of the parameter adjuster (20) determines that the modification of the parameters (PA) is complete, it causes the printing equipment (30) to print an identifier (182) indicating the parameters (PA) onto the case (180).

[0096] As described above, after printing the identifier (182) on the case (180), the user can refer to the identifier (182) and store the parameter (PA) indicated by the identifier (182) in the non-volatile memory (43) of the inverter microcontroller (40). In this embodiment 2, the identifier (182) directly indicates the parameter (PA). However, the identifier (182) may also indicate information associated with the parameter (PA), such as a link to a web page that shows the parameter (PA). Alternatively, an external device may be equipped with a camera, and the external device may take a picture of the identifier (182) and store the parameter (PA) in the non-volatile memory (43) of the inverter microcontroller (40).

[0097] In the embodiments 1 and 2 described above, the semiconductor switching element (110) is an N-channel MOS transistor, but it may also be a P-channel MOS transistor. Alternatively, the semiconductor switching element (110) may be a bipolar transistor. In that case, during the parameter adjustment operation, the parameter (PA) may be calculated based on a predetermined reference relating the current waveform of the collector current (main current) during switching of the semiconductor switching element (110) when the base voltage as the control voltage is applied, and the target current waveform. Furthermore, the semiconductor switching element (110) may also be an IGBT (Insulated Gate Bipolar Transistor).

[0098] Furthermore, in embodiments 1 and 2 described above, the parameter adjustment operation shown in Figure 9 was performed during the inspection process when manufacturing the power converter (10). However, it may also be performed after the power converter (10) has been used for a certain period of time after being shipped.

[0099] Furthermore, in the above embodiment 2, the identifier (182) was printed on the case (180), but it is sufficient if it is indicated; for example, a sticker with the identifier (182) indicated could be attached to the case (180).

[0100] Furthermore, in embodiments 1 and 2 described above, the number of semiconductor switching elements (110) in the inverter circuit (11) was set to 6, but any other number of 2 or more may be used.

[0101] Furthermore, in embodiments 1 and 2 described above, the power converter (10) was a power module equipped with a rectifier circuit, an inverter circuit (11), a non-volatile memory (120), a drive circuit (130), and a case (180). However, the power converter (10) may also be a power module without a rectifier circuit. In other words, the power converter (10) may be equipped with only the inverter circuit (11), the non-volatile memory (120), the drive circuit (130), and the case (180) from the rectifier circuit, inverter circuit (11), non-volatile memory (120), drive circuit (130), and case (180).

[0102] While embodiments and modifications have been described above, it will be understood that a variety of changes in form and details are possible without departing from the spirit and scope of the claims. Furthermore, the embodiments, modifications, and other embodiments described above may be combined or substituted as appropriate, as long as they do not impair the functions covered by this disclosure. [Industrial applicability]

[0103] As described above, this disclosure is useful for power converters, air conditioners, parameter adjusters, parameter adjustment systems, and methods of using parameter adjustment systems. [Explanation of symbols]

[0104] 1. Air conditioner 2 Parameter Adjustment System 10 Power converter 20 Parameter Adjusters 43 Non-volatile memory (storage unit) 110 Semiconductor switching elements 111 Grid gate (first electrode) 112 Drain electrode (second electrode) 113 Source electrode (third electrode) 120 Non-volatile memory (storage unit) 130 Drive Circuit 161 Resistors 162 switches 163 Selector (Switch Control Unit) 164 Voltage source 180 cases 181 terminals 183 terminals 182 Identifier PA parameters GS gate drive signal dt division period tg 1st period TG1 Start Timing TG2 Ending Timing T2, T3 timing

Claims

1. A leg comprising a semiconductor switching element (110) having a first electrode (111), a second electrode (112), and a third electrode (113), wherein a main current corresponding to a control voltage applied to the first electrode (111) flows from the second electrode (112) to the third electrode (113), A rewritable storage unit (43, 120) for storing parameters (PA) relating to the waveform of the control voltage during switching of the semiconductor switching element (110), A power conversion device comprising a drive circuit (130) that refers to a drive signal (GS) indicating whether or not to turn on the semiconductor switching element (110) and a parameter (PA) stored in the memory unit (43,120), and applies the control voltage with a waveform corresponding to the parameter (PA) to the semiconductor switching element (110), The start timing (TG1) of the rising edge of the control voltage waveform when the semiconductor switching element (110) is turned on is defined as the timing when the control voltage has risen to 10% of its peak voltage, and the end timing (TG2) of the rising edge of the control voltage waveform when the semiconductor switching element (110) is turned on is defined as the timing when the control voltage has risen to 90% of its peak voltage. The number of semiconductor switching elements (110) is set to M, which is two or more. When the x-th semiconductor switching element (110) among the M semiconductor switching elements (110) is turned on, the first period (tg) from the start timing (TG1) to the end timing (TG2) of the rising edge of the control voltage waveform is divided equally into 20 divided periods (dt), and the rate of change of the control voltage in the y-th divided period (dt) of those 20 divided periods (dt) is ΔV. ｇ Let [x] and [y] be the second period from the timing (T2) when the main current of the x-th semiconductor switching element (110) rises to 10% of its peak current due to the rising edge of the control voltage waveform, to the timing (T3) when the main current of the x-th semiconductor switching element (110) rises to 90% of its peak current due to the rising edge of the control voltage waveform. ｒ Let [x] Let y be i, and substitute all integers between 1 and M for x to obtain ΔV. ｇ The maximum value of [x] [y] is ΔV ｇ＿ｍａｘ [i] Let y be i, and substitute all integers between 1 and M for x to obtain ΔV ｇ The mean of [x] and [y] is ΔV ｇ＿ａｖｅ Let [i] ΔV when i is replaced with all integers between 1 and 20 (inclusive) ｇ＿ｍａｘ [i] / ΔV ｇ＿ａｖｅ Let the maximum value of [i] be MAX. t when all integers from 1 to M are substituted for x ｒ Let t be the maximum value of [x] ｒ＿ｍａｘ t when all integers from 1 to M are substituted for x ｒ Let t be the average value of [x] ｒ＿ａｖｇ A power conversion device in which the following equation holds when Max>t ｒ＿ｍａｘ / t ｒ＿ａｖｇ

2. Equipped with a case (180), The semiconductor switching element (110), the memory unit (120), and the drive circuit (130) are housed in the case (180). The power conversion device according to claim 1.

3. The case (180) is provided with a terminal (183) for adjusting the parameter (PA), which allows the storage unit (120) to be connected to the outside of the case (180). The adjustment terminal (183) is either not connected to the outside or is maintained at a predetermined voltage during the period when the storage unit (120) is powered on. The power conversion device according to claim 2.

4. Case (180), It comprises a circuit board (41), The semiconductor switching element (110) and the drive circuit (130) are housed in the case (180). The memory unit (120) is mounted on the circuit board (41) outside the case (180). The power conversion device according to claim 1.

5. The case (180) includes an identifier (182) for identifying the parameter (PA). The power conversion device according to claim 4.

6. The aforementioned drive circuit (130) A plurality of resistors (161) are connected in parallel to each other between the voltage source (164) and the first electrode of the semiconductor switching element (110), Between the voltage source (164) and the first electrode of the semiconductor switching element (110), at least one switch (162) is connected in series with at least one of the plurality of resistors (161), The system includes a switch control unit (163) that controls the on / off state of the switch (162) based on parameters (PA) stored in the memory unit (43,120). The power conversion device according to claim 1.

7. The storage unit (43,120) is a non-volatile memory. The power conversion device according to claim 1.

8. The case (180) is provided with a terminal (181) for reading the parameter (PA), which allows the storage unit (120) to be connected to the outside of the case (180). The power conversion device according to claim 2.

9. An air conditioner equipped with the power conversion device (10) described in claim 1.

10. It is a parameter adjuster, A parameter adjuster that performs a parameter adjustment operation, which involves transmitting the drive signal (GS) to the power converter (10) described in claim 1, acquiring the current waveform of the main current when the semiconductor switching element (110) is switched when the control voltage corresponding to the drive signal (GS) is applied, calculating the parameter (PA) based on the current waveform and a predetermined standard relating to a target current waveform stored in the parameter adjuster (20), and transmitting the parameter (PA) to the storage unit (120) of the power converter (10).

11. A parameter adjustment system comprising a power converter (10) according to any one of claims 1 to 8 and a parameter adjuster (20) according to claim 10.

12. The parameter adjustment system according to claim 11, wherein at least one of the memory unit (43,120) and the parameter adjuster (20) holds the initial value of the parameter (PA).

13. The parameter adjustment system according to claim 11, wherein the parameter adjuster (20) repeats the parameter adjustment operation until the current waveform satisfies the predetermined standard.

14. In the method of using the parameter adjustment system described in claim 11, A method for using a parameter adjustment system to cause the parameter adjuster (20) to perform the parameter adjustment operation during the inspection process of the power converter (10) during manufacturing.

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