Methods for mitigating and characterizing logical errors in error-correcting quantum processors

Abstract

The present invention provides a method for mitigating errors in quantum circuits, including error-corrected quantum logic operations, and a storage medium. [Solution] The method includes providing a set of quantum error relaxation protocols, each comprising at least two quantum error relaxation protocols. At least one error-corrected quantum logic operation is performed, and at least one syndrome associated with this error-corrected quantum logic operation is measured to obtain a syndrome measurement. The execution follows at least one selected quantum error relaxation protocol from the set, based on the syndrome measurement.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 701,037, filed on 30 September 2024, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to the field of quantum computing, and more specifically to the sub-fields of quantum error characterization, quantum error relaxation, and quantum error correction.

[0003] Background technical literature The following is a list of publications that may provide technical background to better understand the subject matter of this disclosure. This list is in alphabetical order by publication title. - An introduction to matrix concentration inequalities,Tropp,2015 - A real-time, scalable, fast and highly resource efficient decoder for a quantum computer,Barber et.al.,2023 - Benchmarking logical three-qubit quantum Fourier transform encoded in the Steane code on a trapped-ion quantum computer,Mayer et.al.,2024 - Characterizing quantum gates via randomized benchmarking,Magesan et.al.,2012 - Constant-overhead fault-tolerant quantum computation with reconfigurable atom arrays,Xu et.al.,2024 - Distance-four quantum codes with combined postselection and error correction,Prabhu and Reichardt,2021 - Error mitigation and quantum-assisted simulation in the error corrected regime,Lostaglio and Ciani,2021 - Error mitigation for universal gates on encoded qubits,Piveteau et.al.,2021 - Fault-tolerant quantum error correction for Steane’s seven-qubit color code with few or no extra qubits,Reichardt,2018 - Gate set tomography,Nielsen et.el.,2021 - High-threshold and low-overhead fault-tolerant quantum memory,Bravyi et.al.,2024 - Logical quantum processor based on reconfigurable atom arrays,Bluvstein et.al.,2023 - Logical Randomized Benchmarking,Combes et.al.,2017 - Mitigating errors in logical qubits,Smith et.al.,2024 - Probabilistic error cancellation with sparse Pauli-Lindblad models on noisy quantum processors,van den Berg et.al.,2023 - Quantum error correction below the surface code threshold,Acharya et.al.,2024 - Quantum error mitigation,Cai et.al.,2023 - Quantum error mitigation as a universal error-minimization technique:applications from NISQ to FTQC eras,Suzuki et.al.,2020 - Quantum error mitigation as a universal error reduction technique:applications from the NISQ to the fault-tolerant quantum computing eras,Suzuki et.al.,2022 - Sampling overhead analysis of quantum error mitigation:uncoded vs.coded systems,Xiong et.al.,2020 - Scalability of quantum error mitigation techniques:from utility to advantage,Filippov et.al.,2024 - Symmetric Clifford twirling for cost-optimal quantum error mitigation in early FTQC regime,Tsubouchi et.al.,2024 - The error reconstruction and compiled calibration of quantum computing cycles,Carignan-Dugas et.al.,2023

[0004] The references to the above publications in this specification should not be construed as meaning that they are related in any way to the patentability of the subject matter of this disclosure. In particular, the recognition of the above references in this specification should not be construed as meaning that they are negating in any way the patentability of any of the claims of this patent. [Background technology]

[0005] Quantum computers are expected to significantly accelerate algorithms compared to classical computers for a wide range of applications (sometimes referred to as "quantum advantage" or QA). Important examples include Shor's factorization algorithm and efficient simulations of physical and chemical systems. Shor's factorization algorithm is already crucial for the global cryptography community, particularly in the context of e-commerce and digital identity. Efficient simulations of physical and chemical systems have significant implications in fields such as materials design and pharmaceuticals.

[0006] However, hardware errors, including noise and inaccuracies in quantum logic operations ("gates"), accumulate rapidly, rendering even small-scale quantum computations useless. The impact of these harmful errors on quantum algorithms is generally recognized as the most significant obstacle to achieving QA.

[0007] A long-term solution to errors in quantum processors is quantum error correction (EC), in which quantum information is encoded with a redundant number of qubits so that errors can be corrected non-destructively during computation.

[0008] Possible solutions in the short term (sometimes referred to as the "NISQ era," where "NISQ" stands for "Noisy Intermediate-Scale Quantum Computation") are generally called quantum error mitigation (EM). EM is standard practice when operating with a quantum processing unit (QPU). In EM, a single execution of an ideal (error-free) quantum circuit is replaced by multiple noisy circuit executions, and the measurement results are then post-processed to obtain an estimate of the result for a given ideal circuit. Current and near-state-of-the-art error rates (~10) -3 Using the ) and the number of qubits (tens to hundreds), the EM method is expected to soon provide the first QA that offers access to the first quantum circuits and computational problems that cannot be simulated or solved on classical supercomputers.

[0009] In contrast to EC, EM has little to no overhead in terms of the number of qubits, although it sacrifices QPU time overhead, and eliminates errors. The required QPU time for EM is known to be essentially an exponential function of the total error rate of the circuit; that is, the product of the error rate per operation ε and the total number of operations V. The exponential time requirement is given by the circuit volume V ~ (1-10) × ε -1 Limits the applicability of EM to the cutting edge ε~10 -3 Using this, this means that EM is set to circuit volume V~10 4 This is limited to the estimated minimum volume V~10 for known or suspected QA in industry-related issues. 5 -10 6 It falls below that.

[0010] Therefore, both EC and EM have severe limitations that strongly restrict the scope of industry-related QA. To address the challenges of EC and EM and overcome their respective limitations, a combination of the two methods has recently been proposed. This general approach can be called logical error mitigation (LEM). From a quantum resource perspective, LEM can efficiently utilize both available QPU time and the number of physical qubits to maximize accessible circuit volume and output accuracy. [Overview of the project]

[0011] Identifying technical problems The LEM method described in this art can be summarized as follows: apply EC to generate logic operations with reduced error rates for physical operations. Then, apply EM to these logic operations as if they were physical operations. This method may be called "external LEM" (ExtLEM) because it does not utilize the complex internal structure of logic operations, including "syndrome" data generated by the logic operations through in-circuit measurements. Specific EM methods previously proposed for ExtLEM are quasi-probability (QP) methods that are characterization-based and unbiased to the characterization error.

[0012] In this technical field, the characterization step is also "external," meaning that logical operations are characterized as if they were physical operations, while ignoring their internal structure and syndrome data. This method can be called external logical characterization (ExtLC).

[0013] A major drawback of ExtLC is the QPU time required by ExtLC.

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[0014] A significant drawback of ExtLEM is that it does not utilize the readily available syndrome data generated during error-corrected quantum computations. Known techniques for mitigating logical errors based on syndrome data are referred to as "post-selection" (PS) or "error detection", and these terms are often used synonymously in the literature. The PS technique can be based on a syndrome decoding algorithm ("decoder") that either applies a correction (or recovery) operation as a function of the measured syndrome or aborts the computation and starts the next circuit run (shot). The selection of "accepted" or "rejected" syndromes can be done in real-time and, contrary to the somewhat pejorative but now standard term "post-selection", does not need to be performed in post-processing.

[0015] Note that the combination of PS and EC requires an error-correcting code. This is in contrast to PS based only on an error-detecting code (i.e., a code that can detect errors but cannot provide any information about what recovery operations can be performed). The former is a form of LEM, while the latter is a physical or "non-logical" EM method.

[0016] Codes with distance d = 2t + 2 can correct errors up to weight t and additionally detect errors using weight t + 1, so the combination of PS and EC is generally considered for even - distance quantum codes. In comparison, codes with odd distance d = 2t + 1 can correct t errors without the ability to detect all errors with weight t + 1.

[0017] The main drawback of PS is generally that it only mitigates some of the logical errors remaining after EC. The mitigated errors are logical errors with rejected syndromes. Logical errors with accepted syndromes are not mitigated and can be considered "false negatives". Due to these residual logical errors, PS is generally a biased LEM method, which does not produce accurate results in large circuit volumes and thus has significantly lower performance compared to ExtLEM.

[0018] Additionally, the sampling overhead of PS is not optimal when the rejected syndrome leads to a non - zero probability of "false positives", i.e., when it does not indicate a logical error with probability 1. Furthermore, the false - negative probability needs to be small enough such that the QPU time overhead of PS (as a function of the fraction of logical errors in the rejected syndrome) is significantly lower than the QPU time overhead of the ExtLEM method that post - processes data including the shots in which the rejected syndrome was measured.

[0019] Solving Technical Problems The solutions disclosed herein generally include one or two components. The first component can be referred to as "syndrome - aware logical error mitigation", or SA - LEM for short. The second component can be referred to as "physical - to - logical characterization", or P2LC for short. These components are described in detail in the sections of the following detailed description.

[0020] Summary of Exemplary Embodiments According to a first aspect of the subject matter of this disclosure, a method implemented by a quantum computer for mitigating errors in a quantum circuit C is provided. The quantum circuit C includes at least one error-corrected quantum logic operation G. The method includes providing a set of quantum error mitigation protocols {EM}, which include at least two quantum error mitigation protocols configured to mitigate errors in the quantum circuit C. The method includes performing a plurality of shots to obtain a plurality of relaxed circuit results {o}. For at least one shot, the method provides a syndrome measurement result vector.

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[0021] In addition to the features described above, a quantum computer-implemented method for mitigating errors in a quantum circuit C according to this aspect of the subject matter of the present disclosure may optionally include one or more of the following features (i) to (xxxvii) in any technically possible combination or permutation. i. Performing a shot according to the quantum error mitigation protocol includes one of the following: (a) performing quantum circuit C with at least one additional quantum logic operation; (b) performing quantum circuit C with at least one removed quantum logic operation; (c) post-processing the measurement results of quantum circuit C; or (d) performing a quantum circuit having a different structure from quantum circuit C. ii. Performing a shot according to the quantum error mitigation protocol includes either intermediate processing of the syndrome measurement results of quantum circuit C or intermediate correction of quantum circuit C. iii. Syndrome measurement result vector

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[0022] A second aspect of the subject matter of this disclosure provides a computer-implemented method for computing a mitigable error of an error-corrected logic quantum operation. The method includes characterizing the physical error of at least one physical quantum gate included in the logic quantum operation in order to obtain physical characterization data. The method includes simulating the logic quantum operation according to the characterization data in order to obtain a simulated output error and syndrome in order to obtain a mitigable error.

[0023] In addition to the features described above, a computer-implemented method for computing a mitigate error in an error-corrected logical quantum operation, according to this aspect of the subject matter of the present disclosure, may optionally include one or more of the following features (i) to (viii) in any technically possible combination or permutation: i. Characterizing a physical error includes (a) applying at least one characterization sequence to a set of qubits contained in a quantum processor; (b) measuring the set of qubits using a measuring device for the quantum processor, thereby obtaining a set of measurements; and (c) computing physical characterization data by fitting a model to the set of measurements. ii. Simulating logical quantum operations involves calculating a distribution of either correctable or uncorrectable output errors according to the simulated output errors and syndromes. iii. Simulating output errors involves calculating logical output errors. iv. The calculation of logical output errors is performed according to the fault tolerance level t, which is the number of faults that can be corrected by an ideal error correction cycle. v. Includes the calculation of correctable errors, which include at least t+1 faults. vi. Simulating a logical quantum operation involves (a) providing an error-free input channel to the logical quantum operation in order to obtain an output error channel, and (b) a correctable portion of the output error channel Λ * And the logical error portion Λ of the output error channel lThis includes applying an ideal error correction cycle to the output error channel in order to obtain the desired result. vii. Characterizing physical errors improves the relative accuracy of physical errors.

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[0024] According to a third aspect of the subject matter of this disclosure, the sequence G of error-corrected logical quantum operations k··· A computer-implemented method is provided for characterizing the output error channel in G1. This method provides a partial sequence G of error-corrected logical quantum operations. n Each quantum operation G1,...,G h This includes carrying out a method according to a second aspect of the subject matter of this disclosure. This method involves each quantum operation G n Regarding quantum operation G n Output error channel Λ n To obtain quantum operation G n In contrast, the preceding quantum operation G n-1 Correctable portion of the output error channel

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[0025] According to a fourth aspect of the subject matter of this disclosure, error-corrected logic quantum operation subcircuit G D··· A computer-implemented method is provided for characterizing the output error channel in G1. This method is provided for each sequence G A··· G H This includes carrying out a method according to a third aspect of the subject matter of this disclosure, where H = max(1, Ah), and where h is the n history parameter.

[0026] According to some embodiments, h is equal to the fault tolerance level t or t+1.

[0027] According to a fifth aspect of the subject matter of this disclosure, a computer-implemented method for mitigating logic errors in error-corrected logic quantum operations is provided. The method includes characterizing a logic quantum operation by a method according to any one of the second to fourth aspects of the subject matter of this disclosure, thereby obtaining a characterization of the output error channel. The method also includes mitigating errors according to the characterization of the output error channel by a method according to the first aspect of the subject matter of this disclosure.

[0028] According to a sixth aspect of the subject matter of this disclosure, a non-temporary computer-readable storage medium is provided which tangibly embodies a program of instructions, and when executed by a computer, causes the computer to carry out a method according to any one of the first to fifth aspects of the subject matter of this disclosure.

[0029] According to a seventh aspect of the subject matter of this disclosure, a computer system is provided which includes at least one processing circuit. The computer system is configured to perform a method implemented by a computer according to any one of the first to fifth aspects of the subject matter of this disclosure.

[0030] According to some embodiments, the computer system includes a quantum processing unit.

[0031] According to the eighth aspect of the subject matter of this disclosure, a computer-implemented method is provided, which includes simulating a method according to any one of the first to fifth aspects of the subject matter of this disclosure.

[0032] According to the ninth aspect of the subject matter of this disclosure, a non-temporary computer-readable storage medium is provided which tangibly embodies a program of instructions, and when executed by a computer, causes the computer to carry out the method according to the eighth aspect of the subject matter of this disclosure. [Brief explanation of the drawing]

[0033] Embodiments are described herein, only as non-limiting examples, with reference to the accompanying drawings, in order to better understand the subject matter disclosed herein and to illustrate how it may actually be carried out. [Figure 1] This document provides a schematic example of an error correction cycle using the notation used in this disclosure. [Figure 2A] This paper provides a schematic example illustrating the encoding and decoding of a Shor 9 qubit error correction code. [Figure 2B] This provides a schematic example of an error-corrected logic gate. [Figure 3A] This represents ideal and unideal error correction. [Figure 3B] This represents ideal and unideal error correction. [Figure 3C] This paper provides a schematic illustration of different types of errors in syndrome measurement circuits for Steen error correction codes. [Figure 4] This disclosure provides a schematic illustration of a wide range of characteristics of the characterization method according to the embodiments of this disclosure. [Figure 5] This disclosure provides a schematic example of error calculation, including the simulation of logical errors. [Figure 6] This provides a schematic example of the computation in the characterization method described herein, which is applied to multilayer quantum circuits. [Figure 7A] This provides a general illustration of error propagation. [Figure 7B] This provides a general illustration of error propagation. [Figure 7C] This provides a general illustration of error propagation. [Figure 8] This disclosure provides a general example of the characterization method. [Figure 9] This disclosure provides a general example of how errors can be mitigated. [Figure 10A] A graph illustrating a comparison between the method described herein and methods known in the art is shown. [Figure 10B] A graph illustrating a comparison between the method described herein and methods known in the art is shown. [Figure 10C] A graph illustrating a comparison between the method described herein and methods known in the art is shown. [Figure 11] A computer implementing the method according to the embodiments of this disclosure is schematically illustrated. [Figure 12] This document provides a schematic example of a system that implements the method according to the embodiments of this disclosure. [Modes for carrying out the invention]

[0034] This specification describes several examples of systems and methods useful for mitigating and characterizing logic errors in error-corrected quantum processors.

[0035] The following detailed description includes numerous specific details to ensure a complete understanding of the subject matter. However, it will be understood by those skilled in the art that some examples of the subject matter can be carried out without these specific details. In other examples, well-known methods, procedures, components, and circuits are not described in detail so as not to obscure the subject matter of this disclosure.

[0036] As used herein, phrases such as “for example,” “etc.,” and “as an example,” and variations thereof, describe non-limiting embodiments of the subject matter of this disclosure.

[0037] In this specification, references to “one example,” “several examples,” “another example,” “other examples,” “one instance,” “several examples,” “another example,” “another example,” “one case,” “several cases,” “another case,” “other cases,” or variations thereof, mean that a particular feature, structure, or characteristic described is included in at least one example of the subject matter, but the appearance of the same term does not necessarily refer to the same example.

[0038] For clarity, certain features, structures, and / or properties disclosed herein, described in the context of separate examples, may be provided in combination in a single example. Conversely, various features, structures, and / or properties disclosed herein, described in the context of a single example for brevity, may be provided separately or in any appropriate partial combination.

[0039] Unless otherwise specified, as will be apparent from the following descriptions, any use of terms such as “calculate,” “determine,” “execute,” “implement,” “use,” and “carry out” throughout this specification may refer to actions and / or processes of any combination of software, hardware, and / or firmware. For example, these terms may, in some cases, refer to actions and / or processes of a programmable machine that manipulate and / or convert data, which is represented as a physical quantity such as an electronic quantity in the registers and / or memory of the programmable machine, into other data, which is similarly represented as a physical quantity in the memory, registers, and / or other such information storage, transmission, and / or display elements of the programmable machine.

[0040] Figure 2A schematically illustrates an example of error-correction coding 250 and decoding 260. The error-correction code is a Shor-9 qubit code that uses auxiliary qubits. The Shor-9 qubit code is one of the basic early examples of error-correction codes. The Shor-9 qubit code requires nine data qubits and eight auxiliary qubits. Coding 250 and decoding 260 each consist of two stages.

[0041] In the first stage of coding 250, all auxiliary qubits are initialized to zero. Each of the three subsets of the three data qubits is entangled (via four CNOT gates) with the corresponding set of two auxiliary qubits, as represented, for example, for the first stage coding 253 of the first subset.

[0042] In the second stage 256 of encoding 250, the nine data qubits are entangled with the last two auxiliary qubits (via 12 CNOT gates), and Hadamard gates are applied to these two auxiliary qubits before and after the entanglement.

[0043] In the first stage of decoding 260, for each of the three subsets of data qubits, the corresponding auxiliary qubit is measured, and the results are provided to a classical circuit that can control the application of a quantum operation. If both auxiliary qubits are measured to zero, no operation is performed. If any auxiliary qubit is measured to be non-zero, the Pauli X operation is applied to the corresponding qubit. That is, if only the first auxiliary qubit is measured to be non-zero, the Pauli X operation is applied to the third data qubit. If only the second auxiliary qubit is measured to be non-zero, the Pauli X operation is applied to the first data qubit. If both auxiliary qubits are measured to be non-zero, the Pauli X operation is applied to the second data qubit. For example, this is expressed for the first stage of decoding 263 of the first subset.

[0044] In the second stage 266 of decoding 260, the last two auxiliary qubits (i.e., the auxiliary qubits entangled with the data qubits in the second stage 256 of encoding 250) are measured, and the results are provided to a classical circuit that can control the application of the quantum operation. If both auxiliary qubits are measured to zero, no operation is performed. If any auxiliary qubit is measured to be non-zero, the Pauli Z operation is applied to the first qubit of the corresponding subset of qubits. That is, if only the first auxiliary qubit is measured to be non-zero, the Pauli Z operation is applied to the first qubit of the first subset of qubits. If only the second auxiliary qubit is measured to be non-zero, the Pauli Z operation is applied to the first qubit of the third subset of qubits. If both auxiliary qubits are measured to be non-zero, the Pauli Z operation is applied to the first qubit of the second subset of qubits.

[0045] Figure 2B schematically illustrates an example of an error-corrected logic gate. The logic gate is a transversal CNOT gate. A first logic qubit may be encoded on a first set of data qubits 221. A second logic qubit may be encoded on a second set of data qubits 222. Multiple physical CNOT gates may be applied such that each data qubit in the first set of data qubits 221 can be a control qubit for the corresponding data qubit in the second set of data qubits 222. After the application of the physical CNOT gates, error correction may be performed on any of the logic qubits; for example, an auxiliary qubit (not illustrated) may be measured and a recovery operation may be applied. Error correction may be performed independently on each logic qubit (as illustrated) or on both logic qubits together. The encoding of the logic qubits is not limited and may be, for example, by Steen coding (illustrated in Figure 3C).

[0046] General settings, mathematical definitions, notation, and terminology A vertical bar, when not part of a parenthetical notation, can indicate a condition on the left-hand quantity / object by the quantity / object on the right. In other words, the notation a|b can indicate a given b. This notation may also be expressed via a subscript. For example, an error channel Λ can be conditioned by syndrome s, Λ|s or Λ |s This can be expressed as follows. In other words, the error channel mentioned may be part of an error channel Λ that can result in a given syndrome s.

[0047] The term "quantum code" (or "code space") refers to a quantum state on n qubits. k dimensional subspace

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[0048] The term "quantum encoder" refers to a system that maps a subset of k qubits into a code space.

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[0049] (The term "logical equivalence" can be defined as follows: Two operators σ, σ' (for example, Kraus operators in the context of errors) can be said to be logically equivalent if their actions on the code space are identical. Logical equivalence can be denoted by a tilde, i.e., all

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[0050] Π s This can represent the orthogonal projection operator corresponding to the syndrome measurement result s. s This can represent the recovery operation corresponding to the syndrome measurement result s. Specifically, Π0 can be a projection operator on the code space such that R0=I. The following equivalences can hold for each syndrome measurement result s:

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[0051] Additional "measurement qubits" and "flag qubits" may be added to the sign qubit. The measurement qubit and flag qubit are,

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[0052] The ideal error correction cycle is EC 理想的な =Σ s R s Π s Here, the summation is performed over all possible syndrome measurement results s. An ideal EC cycle always outputs a sign state.

[0053] Syndrome measurement and recovery operations can generally be implemented by noisy quantum circuits. Each physical operation in these circuits may propagate a physical error channel (i.e., an error channel defined across multiple physical qubits). The physical error channel may be assumed to operate before the operation, after the operation, or both before and after the operation. As an example, a noisy model with a Pauli channel after each physical gate may be assumed. Such a model may be, for example, one employing Pauli twirling or by considering the Clifford EC cycle (see Nielsen & Chuang, p. 443). In such an example, each physical error channel may be considered a probability distribution across multiple Pauli superoperators. Locality may also be assumed such that each physical Pauli error may have a low weight (see definition below) and may only involve neighboring qubits according to a certain graph or hypergraph.

[0054] A fault f can correspond to a set of physical errors that may occur during a noisy EC cycle. A fault f can be specified by the spatiotemporal location in the circuit where each error occurs, and the type of error that occurs at each location (for example, specified by a Pauli operator).

[0055] The weight of a fault can be defined contextually. Possible definitions include the number of physical errors contained in fault f and the number of qubits affected by fault f.

[0056] The term "error-fault combination" (abbreviated as EFC) refers to a pair of errors e and faults f, and an EFC can be written as (e,f). The weight of an EFC is w e,f =w e + w f It can be defined as, in the formula, w e This could be the weight of the input error e.

[0057] Figure 1B schematically illustrates an exemplary error correction cycle using the notation introduced above. A simple EC cycle (i.e., a calculation involving one round of syndrome measurement) is illustrated. The data qubit 1115 is encoded, i.e., a quantum state.

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[0058] Given a distribution of possible faults p(f), a non-ideal EC cycle is:

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[0059] To achieve "fault tolerance" (see definition below), it is common to use repeated EC cycles, for example, a cycle with two faults may be performed.

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[0060]

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[0061]

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[0062]

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[0063] The input channel can be defined in code space, that is, it can describe an error on an ideal code state. Under this assumption, the output channel can be a normal Pauli channel. This convention can be used for any EC cycle or error-corrected logic operation, regardless of its location in the circuit. Thus, Λ in Aside from that, all previous errors can be assumed to have been corrected, or at least to the extent of minor corrections, to have generated logical errors (that preserve the code space).

[0064] Λ out This can be expressed in several alternative ways.

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[0065] A "classical decoder" or "classical decoding algorithm" is a mapping.

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[0066] In addition to, or as part of, a classical decoding algorithm, a subset of syndromes can be rejected, i.e., if a rejected syndrome is measured, the final measurement result of the shot can be discarded. A rejected shot can be terminated after the rejected syndrome is measured and before the final measurement. In other words, the rejection of a shot can occur in the middle of the shot, for example, after the syndrome measurement of a partially error-corrected circuit. The set of syndromes can be divided into two non-overlapping subsets,

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[0067] Λ out =Σ σ p(σ)σ and the output error σ in Λ out|s can be divided into three different types. The first type can be a corrected (or trivial) output error. The output error σ can be classified as corrected (or trivial) if the output error is the identity mapping, σ~I, or for all code states c

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[0068] The second type can be a correctable error. The output error σ is such that an additional ideal code cycle corrects the output error,

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[0069] A third type can be a logical error. The output error σ is the k-qubit operation in which the output error is encoded.

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[0070] Figures 3A and 3B illustrate ideal and non-ideal error correction, along with several types of errors. Figure 3A represents ideal error correction, while Figure 3B represents non-ideal error correction. A logical qubit can be composed of multiple physical qubits. The multiple quantum states of a physical qubit are represented as points inside polygons 370a and 370b. Ideally, a logical qubit is,

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[0071] Each polygon defines a set of quantum states of physical qubits that can be corrected to the same logical quantum state by an ideal EC cycle. That is, a quantum state represented as a point within polygon 370a (such as quantum state 380a) can be corrected by an ideal EC cycle.

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[0072] Quantum state

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[0073] When non-ideal error correction is applied, some errors may not be corrected, and / or new errors may be introduced. For example, correctable errors (due to ideal EC cycles) can affect the quantum state.

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[0074] Figure 3C schematically illustrates corrected and correctable errors in a syndrome measurement circuit for a Steen error-corrected code. Figure 3C schematically illustrates a syndrome measurement circuit U for three of the six stabilizers of the Steen code. A complementary syndrome measurement circuit U' may be used to measure the remaining three stabilizers of the Steen code. See [Reichardt, 2018] listed above, on which Figure 3C is based.

[0075] The EC cycle can start from syndrome measurement using these two circuits (i.e., U, U'). If non-trivial syndrome bits are observed, the syndrome measurement can be stopped and restarted (here, without the CNOT gates marked by arrows in this specification). It can be assumed that U' is implemented first and then U is implemented. x4 marks a Pauli X error, affects the fourth qubit, and its effect can be measured and corrected. x5 marks a Pauli X error, acts on the fifth qubit, and its effect is too late to be measured by U in the syndrome measurement circuit (i.e., no further gates between the affected qubit and the ancillary qubit are applied after the error). However, x5 is correctable because it can be corrected by the next EC cycle (if this is an EC cycle without faults). A simple example of a fault that can lead to a logical error is a pair of Pauli Z errors (Z1Z3 ~ Z2Z l ) that can affect the first and third qubits located at the positions marked by z1, z3. This fault leads to a trivial syndrome and thus a trivial recovery. x (without a subscript) marks a Pauli X that can invert the measurement result (measurement error) and lead to an incorrect syndrome.

[0076] In general, an error can be decomposed into a product of (other) errors. In other words, an error can be equivalent to a sequence of two or more (other) errors. Therefore, any output error σ can be a product (and equivalent) of a logical error σ l σ c and a correctable error σ l , i.e., σ ~ σ c . The proof is as follows. Given an output error σ, the following equivalence can hold (refer to the above in the definition of logical equivalence):

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[0077] The natural result is an ideal e-commerce cycle.

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[0078] The aforementioned decomposition (into correctable errors and logical errors) is shown in Figure 3A. As shown above, an error affects the quantum state.

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[0079] Up to logical equivalence, the output error channel is,

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[0080] Correctable error channel Λ c and uncorrectable error channel Λ nc It can be defined as follows:

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[0081] The logical error rate / probability / non-fidelity is defined by the logical error channel Λ described above. l The non-fidelity can be ε l =ε nc It can be given by [this]. The error channel can be defined for each syndrome.

[0082]

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[0083] The set of logical operations (or code cycles) is weighted w e,f Any EFC with ≤t that can be corrected or correctable (regardless of what the next logical operation is) can be defined as fault tolerance up to weight t, or simply t-FT. That is, the lowest weight EFC that leads to an uncorrectable error may have a weight of t+1.

[0084] The sign with distance d is equivalently (d-1) / 2 for odd d and (d-2) / 2 for even d.

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[0085] The EC threshold is ε l It can be defined as a physical non-fidelity ε such that =ε. According to the above rule of thumb, the threshold is

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[0086] A "naive" rejection strategy might reject any syndrome that does not correspond to a unique lowest-weighted output error (the weight of the output error is the weight of the corresponding EFC, and the output error is considered up to logical equivalence). This applies to the syndrome subset S. rej It can be used as a specification. In t-FT settings, S rej This can correspond to a syndrome that can only be generated by EFCs with w≧t+1. This may include a substantial portion of EFCs with w=t+1. A code with distance d=2t+2 can correct input errors up to weight t and additionally detect input errors with weight t+1, so S rej The above naive definition may be particularly useful in even-distance codes. In comparison, codes with odd distances d=2t+1 can correct input errors up to weight t without any additional guarantee of detection. In the context of SA-LEM, as described below, syndrome rejection may be very useful in odd-distance codes in some embodiments. In some embodiments of SA-LEM,

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[0087] In this subsection, the EC cycles and definitions presented and detailed above can be considered error-corrected logical idle (or identity) operations. The above formal theory is directly extended to non-identity operations. An n-qubit operation g is defined as this operation being performed

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[0088] Fault in the subcircuit G = Σ s G s (EC F =Σ s EC s By analogy, this subcircuit may be called an “error-corrected logic operation” if it includes syndrome measurement and recovery operations and is intended to implement logic operation g (see Figure 2B as an example). Error-corrected ideal version G 理想的な This is the case where the same subcircuit can be given, but the assumption that there are no faults holds. That is, any sign state

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[0089] Logical operations

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[0090] Each annotation provided within the pseudocode of an algorithm ("inline comment") can be given using a prefix hash symbol (i.e., the # symbol).

[0091] Description of P2LC components As shown above, SA-LEM, in some embodiments, is a syndrome-conditional error channel.

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[0092] An additional difficulty with ExtLC is that it characterizes logic operations outside the context of the logic operations in a given circuit, which are given by prior and subsequent quantum operations. Therefore, ExtLC ignores the "logic context dependence" phenomenon, which will be explained later.

[0093] As an alternative to ExtLC, a physical-to-logic characterization method (hence abbreviated as P2LC) is presented in this disclosure. To outline P2LC, error-corrected logic operations,

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[0094] Referring to Figure 4, a method 400 implemented on a computer according to an embodiment of the present disclosure for computing the mitigable error of an error-corrected logical quantum operation is schematically illustrated. Method 400 may be one embodiment of a P2LC component. In other words, a P2LC component can be schematically illustrated in Figure 4.

[0095] Method 400 may include a step 410 of characterizing a physical error. To obtain physical characterization data, an error in at least one physical quantum gate involved in a logical quantum operation may be characterized.

[0096] Method 400 may include step 420 of simulating a logical quantum operation. The logical quantum operation may be simulated according to characterized data. In other words, a computation may be performed, the input to which the computation may include the characterized data and a representation of a quantum state which is the input to the logical quantum operation. The output of the computation may be a representation of a quantum state which is the output to the logical quantum operation, given the representation of a quantum state which is the input to the logical quantum operation.

[0097] Logical quantum operations can be simulated to obtain simulated output errors and syndromes. These simulated output errors and syndromes can be obtained to obtain mitigable errors. For example, mitigable errors can be computed (i.e., post-processed) according to the inputs of the simulated output errors and syndromes.

[0098] Generally, step 410 of characterizing a physical error may include applying a characterization protocol. Examples include, but are not limited to, gate set tomography, state tomography, and process tomography. Step 410 of characterizing a physical error may include step 413 of applying at least one characterization sequence to the set of qubits contained in the quantum processor. Step 410 of characterizing a physical error may include step 415 of measuring the set of qubits using a measuring device for the quantum processor, thereby obtaining a set of measurements. Step 417 of characterizing a physical error may include calculating physical characterization data by fitting a model to the set of measurements.

[0099] Step 420, which simulates a logical quantum operation, may include step 423, which calculates the distribution of correctable output errors. Step 420, which simulates a logical quantum operation, may include step 425, which calculates the distribution of uncorrectable output errors according to the simulated output errors and syndromes. Step 420, which simulates a logical quantum operation, may include step 427, which simulates output errors and includes the calculation of logical output errors.

[0100] The physical characterization step in P2LC (i.e., step 410) may correspond to the characterization of individual physical gates, layers of such gates acting in parallel, subcircuits containing several such layers, and / or entire subcircuits implementing syndrome measurement and logic operations. The difference from ExtLC is that the characterized operations may not include any (or at least as much as possible) recovery operations or syndrome rejection.

[0101] Referring to Figure 5, an exemplary simulation of a logical error 500 (i.e., an exemplary implementation of step 427 in Figure 4) is schematically illustrated. A logical operation may be denoted as G. The version of logical operation G for which error correction is ideal is G EC 理想的な It can be written as follows.

[0102] In some embodiments, simulating a logical quantum operation may involve performing the simulation using either a Clifford simulator (e.g., a stabilizer simulator) or a state vector simulator.

[0103] In some embodiments (for example, P2LC of method 400), simulating a logic quantum operation 500 may include the step 510 of providing a logic quantum operation with an error-free input channel in order to obtain an output error channel, namely Λ out To obtain Λ in =I can be provided to G. Simulating the logical quantum operation 500 is correctable part Λ of the output error channel.c And the logical error portion Λ of the output error channel l To obtain Λ, step 520 may include applying an ideal error correction cycle (in simulation) to the output error channel. l and Λ c To obtain Λ out G EC 理想的な It can be provided to.

[0104] In some embodiments, the classical algorithm included in P2LC may take a “history parameter” h≧1 as input. The classical algorithm included in P2LC has iterations across multiple logic layers.

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[0105] channel

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[0106] Figure 8 shows a flowchart illustrating a schematic characteristicization method 800 according to this disclosure. Method 800 may be an iterative embodiment of P2LC as described above and further detailed below. The error-corrected quantum circuit 805 may consist of a sequence of error-corrected quantum gates. The first error-corrected quantum gate in the sequence may be G1. The last error-corrected quantum gate in the sequence is G DThis is possible. Method 800 can fully characterize the error in the error-corrected quantum circuit 805.

[0107] Method 800 may include step 810 of selecting desired history parameters. Method 800 may include step 815 of setting the first loop index j to j=1. Method 800 may include step 820 of setting the first layer to include a layer pointer (layer indexer) n in the characterization. Thus, the layer pointer n is set to n=max(1,jh). Method 800 may include a first input error channel

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[0108] Method 800 computes the output error channel for the mth quantum gate (i.e., G m Associated

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[0109] Method 800 may include step 840 of computing the input error channel for the m+1th quantum gate. The specific calculation method is not limited. The calculation is generally expressed as an expression.

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[0110] This is to simulate the next (m+1) quantum gate. Method 800 may include step 850, which checks a condition on m. If m ≠ n+1, then the next quantum gate can be simulated (the execution of Method 800 returns to step 835).

[0111] If m=n+1, step 855 (sometimes known in algorithm theory as the "yield output") is performed to provide / record a partial output. The yield output is the output of the last simulated (error-corrected) quantum gate (in the loop indexed by m). Mathematically, the yield output is

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[0112] After step 855, method 800 may include step 860, which advances the first loop index j by one (i.e., j ← j+1). Method 800 may include step 865, which checks a condition on j. If j ≠ D+1, the next output logic error channel may be characterized (the execution of method 800 returns to step 820). If j = D+1, method 800 terminates.

[0113] The iterative embodiment can be summarized as follows, with some modification of notation: Error-corrected logical quantum operation G k··· A computer-implemented method for characterizing the output error channel in a sequence of G1 (e.g., Method 800). The method involves error-corrected logical quantum operations G1,...,G h Each quantum operation G included in the subsequence n This may include performing P2LC on each quantum operation G (e.g., Method 400). n Regarding quantum operation G n To obtain the output error channel, quantum operation G n In contrast, the preceding quantum operation G n-1 Correctable portion of the output error channel

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[0114] The importance of the history parameter h can arise from the fact that, in all known EC schemes, errors generated within a given logical operation can be partially corrected by subsequent logical operations. The fundamental reason is that physical errors may generally occur "too late" in a logical operation to be corrected by it. Examples include physical measurement errors and errors in recovery operations. See Figure 3C for the aforementioned example and its associated explanation.

[0115] The output error channel after each logic operation may depend on both the input error received from the preceding logic operation (an uncorrected but correctable error) and the error passed as input to the subsequent operation. An inherent "logic context dependency" or "logic non-Markov property" can result in an error-corrected quantum circuit. That is, a logic error that may appear after a given logic operation can generally depend on both past and future operations. This effect is clear and occurs independently of any non-Markov property or context dependency that may occur at the physical level.

[0116] Larger h values ​​can lead to longer classical execution times for P2LC (e.g., Method 800). However, making h too small can result in highly inaccurate execution times.

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[0117] In some embodiments, the calculation of logic output errors may be performed according to a fault tolerance level t, which is the number of faults correctable by an ideal error correction cycle. In some embodiments, the calculation may include the calculation of correctable errors that may include at least t+1 faults. Later, for a t-fault-tolerant circuit (t-FT, where each fault-tolerant with weight ≤ t can be corrected by some logic operation), setting h=t means that

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[0118] In some embodiments, the above iterative procedure of classical simulation and elimination of uncorrectable errors may be based on sampling of fault paths. Each fault path is a subset circuit L j··· L i_0 This can be a set of physical errors in which the system can be sampled from a physical error model (or a model of a model of physical errors) of physical operations in the subcircuit. The iterative procedure can then be applied separately to each sampled fault path. Working with fault paths can make it possible to condition the syndrome data in the P2LC by recording the syndrome data acquired in each simulated fault path. This can be done as follows: a) Partial circuit

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[0119] In the case of syndrome-related conditions

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[0120] The classical resources required for P2LC may be proportional to the number n fault paths that may need to be sampled to meet the required characterization accuracy. Later, it will be demonstrated that simple ("naive") sampling of fault paths, where a physical error is sampled from each physical error channel, has advantages when the error rate of m can be characterized.

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[0121] More sophisticated sampling can be implemented. The “priority sampling” strategy, described later, can be used in P2LC. Sampling can be based on a set of constraints that can be satisfied by the fault path in order to generate a logical error. (Factors in the expression for n)

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[0122] In some embodiments, characterizing physical errors is the relative accuracy of physical errors.

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[0123] The output error described above was written as a function of input errors and faults. Input errors may result from previous operations that were not corrected. Input errors may include multiple faults or fault paths occurring in multiple previous operations. As a result, the output error channel in an error-corrected circuit may have its own memory, in other words, non-Markov property. Thus, the error channel may depend not only on the operation to which the error channel corresponds, but also on previous operations. As will be shown later, this memory can be extended further back in time for error-corrected circuits with higher fault tolerance levels. Additionally, the distinction of output errors between correctable and uncorrectable errors may depend on subsequent logic operations, meaning that uncorrectable error channels and logic error channels may depend not only on previous operations, but also on subsequent operations. This dependency may be called "logic context dependency" and may pose a challenge to the "External Logic Characterization" (ExtLC) protocol proposed in the prior art. The ExtLC protocol involves a logic characterization circuit different from a given logic circuit, and therefore characterizes operations outside the appropriate context in a given circuit. This is specific to ExtLC because, despite this dependency between output errors occurring in different error-corrected logic operations, it is desirable to specify a separate error model associated with each operation in the circuit for some applications, including specific logic error mitigation (LEM) protocols.

[0124] Error-corrected circuit C=G D··· Given G1 (each G j This can be a layer of error-corrected logical operations, and is a "strict" error channel.

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[0125] therefore,

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[0126]

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[0127]

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[0128] Later, error channels that occur after each logical layer will be discussed.

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[0129] t-FT error-corrected circuit C=G D··· G1 and each logic gate G j Given a physical error model for faults occurring in and , the pseudocode for a P2LC characterization protocol based on classical simulation may be as follows:

[0130] Algorithm 1: P2LC Channel Version 1. Input: 1.1. t-FT error-corrected circuit C=G D··· G1. 1.2. Each Logical Layer G j A physical error model for faults occurring in [location]. 1.3. The integer "history parameter" h has a default value of t. 2. For j=1,...,D, 2.1. Set i0=max(1,jh) to the ideal input channel.

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[0131]

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[0132] Algorithm 1 is schematically illustrated in Figure 6. Each error-corrected gate (equivalently, a layer), e.g., gate 605, is represented as a striped segment. Gates are separated (i.e., isolated) from preceding / successor gates (in the circuit) by dashed lines. An error-free input (Λ=I) can be provided to the first gate. Three examples are shown. In the first shown example, the first gate may be assigned an index following jh. The execution of the circuit can be simulated. The result may be an output error channel. The simulation may reach an indexed gate j and continue. Thus, an input error channel for the (i.e.,) the (j+1)th layer is obtained (i.e.,

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[0133] The second represented example may be similar to the first represented example, except that the first gate may be assigned the index jh, and the simulation will stop at the gate indexed j. Thus, it is the input error channel for the jth layer.

[0134] The third represented example may be similar to the second represented example, except that the simulation terminates at the gate indexed with j. Thus, the output error channel is obtained (i.e.,

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[0135] Several theorems concerning P2LC can be given here.

[0136] Theorem 1 (Λ at h=t) a P2LC guarantee regarding (h=t): If h=t,

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[0137] Proof: First Λ in,i+1 =Λ c,i =Λ out,i +O(ε t+1 Keep this in mind, and then,

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[0138] G j-h Even if it does not contain a fault (i.e.,

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[0139] Here, O(ε) = Σa σ If (σ-I), then notation O c (ε)=Σ σεc a σ (σ-I) is O(ε t+1 This means that the uncorrectable part is removed at the expense of correcting the ). Therefore, for h≧t, the equation

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[0140] Proof: Theorem 1 is that for h=t,

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[0141] Increasing h=t to h=t+1 is scaling ε a =O(ε t+1 ) does not change, but generally eliminates the dominant "accidental" correctable errors that are not guaranteed by t-FT, ε a This reduces the number of steps. If the step size is h=t+1 (as opposed to h=t), it can be called a "greedy P2LC".

[0142] System 2 is such that P2LC captures the leading term logic error and is a strict equality

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[0143] Theorem 2 (Λ at h=t) l P2LC warranty regarding:

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[0144] Proof:

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[0145] Under the subsequent logical layer, G j+1,理想的な [Λ nc,j -Λ l,j ]=0, and therefore,

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[0146] Following the results above, in some embodiments in which SA-LEM is combined with P2LC, the exact error channel Λ e This corresponds to channel Λ, which handles mitigated logical errors. L It can play the role of, Λ e Strictly speaking, this is not a logical error channel. In other embodiments of SA-LEM, the actual logical error channel Λ l is, Λ L It can serve that role. The lowercase and uppercase subscripts l and L emphasize this degree of flexibility.

[0147] P2LC using fault path sampling, and syndrome-recognition P2LC Assuming that the physical error channel in each error-corrected logic layer can be described by a probability distribution of errors (e.g., Pauli errors), a classical simulation in P2LC can be performed by sampling fault paths from the h-history of each logic layer and separately performing classical simulations for each fault path (for input errors, output errors, and logic errors, as well as measured syndromes). In this fault path formulation, it may be easy to condition with respect to measured syndromes and to characterize error channels conditional on syndrome data, as required for SA-LEM. An example for a single layer is given as pseudocode in Algorithm 2. Algorithm 2 can be repeated for multiple layers.

[0148] G j Each logical layer G in the h-hi history i Syndrome classification in (i=i0,...,j, i0=max(1,jh))

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[0149] Algorithm 2: P2LC (Fault Path Version, Syndrome Recognition) 1. Input: 1.1. t-FT error-corrected circuit C=G D··· G1. 1.2. Target Layer G j . 1.3. The integer "history parameter" h has a default value of t. 1.4. Each Logical Layer G i A physical error model for faults occurring at i=i0,...,j, i0=max(1,jh). 1.5. Fault path to samples of amber n, a non-negative integer. 1.6.

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[0150] G j+1 After the algorithm is executed,

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[0151] The execution time of Algorithm 2 may be proportional to the number of fault paths n that need to be sampled to satisfy the required characterization accuracy. For simplicity of proof, the logic error channel averaged across multiple accepted syndromes,

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[0152] In P2LC, fault paths can be sampled. However, the resulting logical error σ forms a sample from p, and therefore,

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[0153] Lemma 1 (Complexity of P2LC classical samples, naive sampling): Let m = |Supp(p)| be the number of non-zero entries in p (this does not need to be known beforehand). Then,

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[0154] Proof: The probability vector with the entry σ=I removed is q=(q σ ) σ≠I =(p σ ) σ≠I If written as follows, the following holds true:

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[0155]

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[0156] The boundary value for variance can satisfy the following:

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[0157] The following will happen.

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[0158] Support m can be the number of non-negligible terms in the characterized logic error channel. In a simple implementation, m is 4 for a logic layer acting on N logic qubits. N It can be about the same size as [this]. Later, it is shown that m=O(N) can be sufficient for local EC schemes and local physical error models.

[0159] Lemma 2 (Linear support of logic error channels in local EC schemes): Assuming that EC is performed independently in t-FT blocks with a small number of logic qubits and a fixed number ≤ k (regardless of the number of physical qubits in each block), and that there are no individual physical errors connecting physical qubits in different blocks (no inter-block crosstalk errors), then each weighted -(t+1) fault path can result in a logic error in at most one block in a single layer. From this, the leading term ~ε t+1 In this case, the total number of non-zero logic error probabilities m is at most (N / k)4 k This means the time complexity is O(N).

[0160] Proof: A logical error in two blocks at the same layer requires that each of these blocks contains a fault with a weight ≥ 1; otherwise, one of the blocks is ideal and corrects the input error in that block. However, a fault of weight 1 in each block is insufficient for a logical error; the leading logical error requires that the fault is part of a fault path of weight t+1 that extends back to t layers. Thus, the total weight of the fault required for a logical error in a different block is ≥ (t+1)+1 = t+2. Figure 7A schematically illustrates the fault path and logical error in an example at t=1, i.e., a local EC scheme of 1-FT (see Lemma 2). Each rectangle represents a fault-corrected logical operation, and the × marks indicate physical errors involved in the fault path. In examples (a) and (c), logical errors can only be generated in the lower block. In example (b), a logical error may not be generated. Example (d) shows the lowest weight assignment (w=t+2=3) to physical errors that could lead to logical errors in two distinct blocks.

[0161] In a local EC scheme, each simulation step in P2LC mapping input errors to output errors may involve a separate simulation of each fault block. A similar statement can be made when EC is performed on a single block where all N logical qubits are encoded with quantum low-density parity check (LDPC) codes. In this case, each stabilizer measurement may involve only a few physical qubits, and each physical qubit may be involved in a few stabilizer measurements. Leading term ~ε t+1 Generating logical errors in this system may require that all t+1 physical errors be sufficiently close spatially (more precisely, on the graph corresponding to the LDPC code).

[0162] Number of samples

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[0163] Theorem 3 (Complexity of P2LC classical samples, importance sampling): Let F be a subset of the set of fault paths with weights ≥ t+1, this subset contains all fault paths that lead to logical errors.

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[0164] The coefficient c can be reduced toward 1 by including as many constraints as possible that the fault path can satisfy in the definition F of the sampled set. Several exemplary constraints are described below and shown in Figure 7B. Many additional constraints can be incorporated.

[0165] Time continuity constraint: Layer G jLogical error ~ε after t+1 ends in G j and may require a fault path with weight t+1 that ends in G and may be time - continuous. A time - continuous fault path can be defined as follows: If a time - continuous fault path contains a fault in layer G i (i < j), the time - continuous fault path also contains a fault in each subsequent layer i ≤ j. Time - continuity is important because if there is no fault in layer k between i and j, this layer can correct the output error from layer k - 1 (since this output error has weight w<t, this output error can be corrected). The remaining part of the fault path has weight t - w<t, and thus the remaining part may not generate a logical error.

[0166] Spatial - continuity constraint: For a local EC scheme, as defined above, faults in two consecutive layers in a time - continuous fault path with weight t+1 may need to occur in blocks with overlapping support. Spatial - continuity can be important because if it is not spatial - continuous, the output of a previous layer can be corrected by blocks without faults in a later layer.

[0167] Causal - connectivity constraint: The time - continuity constraint and the spatial - continuity constraint described above can be combined. In other words, the constraint may require both time - continuity and spatial - continuity. This constraint can be referred to as the causal - connectivity constraint. The causal - connectivity constraint means that a fault path with weight t+1 that leads to a logical error in a given block may end in that block, may be continuous (with no blocks without faults along the path), and may be included in the reverse - causal cone of the block.

[0168] In Figure 7B, example (a) represents an error that adheres to the time continuity constraint, while example (b) represents an error that does not adhere to the time continuity constraint. Example (c) represents an error that adheres to the spatial continuity constraint, while example (d) represents an error that does not adhere to the spatial continuity constraint.

[0169] Priority sampling (as described above) can be achieved, for example, via a "fault path tree". A fault path tree can be defined as a binary tree T, where each branch is:

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[0170] An exemplary fault path tree 750 is shown in Figure 7C. The error-corrected circuit 700 may contain two error-corrected logic operations. The first error-corrected logic operation 703 may be affected by two error channels (X1, Y2). The second error-corrected logic operation 707 may be affected by a single error channel (Z3). Error channels X1, Y2, and Z3 may result in errors with probabilities ε1, ε2, and ε3, respectively. Errors in the error-corrected circuit 700 may be associated with the fault path tree 750.

[0171] The procedure described below can correspond to sampling branching from tree T based on the sampling level. Level l1 (of the first fault) can be sampled. Then, level l2 (of the second fault) can be sampled. Level l (of the (t+1)th fault) t+1 The next level can be sampled until the previous level has been sampled. This ensures that only fault paths with weights ≥ t+1 can be sampled. To obtain an unbiased estimator of the logical error channel, all levels l > l t+1 Naive sampling can be performed. Alternatively, the final step of naive sampling may be omitted. Omitting the naive sampling step results in O(ε) t+2 This can result in a bias in Λ. e Instead of Λ l When used, the same order of bias may exist, so these biases may not be significant. Level l1, ··· ,l t+1 Constraints such as causal connectivity, which can be expressed from this perspective, can be easily incorporated. An exemplary pseudocode for emphasis sampling is provided in Algorithm 3.

[0172] Fault path algorithm in P2LC (3): 1. l0 = 0. 2. For a=1,...,t+1, 2.1. Probability

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[0173] When using algorithm 3, the output of P2LC

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[0174] P2LC errors caused by physical characterization errors The threshold for statistical error s (resulting from fault path sampling in P2LC) was provided above. The threshold for systematic error in P2LC (resulting from inaccurate characterization of physical errors) may be provided below.

[0175] A potential concern is that small logical errors estimated by P2LC might require unduly high precision in physical characterization. This concern is shown to be unfounded later. The basic intuition is:

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[0176] Theorem 4 (Required physical characterization precision for P2LC): Let ε be the average nonfiscality of the physical operation in the error-corrected logic layer. Assume that the physical operation is characterized to an average 1-norm inaccuracy δε. Then the average relative 1-norm inaccuracy in the physical characterization δε / ε≦δ rel / [C(t+1)] represents the relative 1-norm (systematic) inaccuracy δ in the output of P2LC. rel This may be sufficient to secure it. Here,

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[0177] Proof: O(ε t+2 Until the correction of )

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[0178]

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[0179] Here,

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[0180] P2LC QPU Time Requirements The QPU time required for the physical characterization step in P2LC can be compared to the QPU time required in ExtLC. The logic error channel averaged across accepted syndromes.

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[0181] First, we assume that all syndromes are acceptable, and then we consider cases where certain syndromes may be rejected. A given characterization protocol can be assumed that can be applied to either physical or logical operations (or layers). An operation with non-fidelity ε is given relative 1-norm precision δ. rel The QPU time required by this protocol to characterize it is

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[0182] The proportionality constant may include a time scale (e.g., gate time) and an extensional constant (similar to m in Lemma 1). This extensional constant may relate, for example, to the number of characterized parameters, the number of required characterized circuits, and the Jacobian involved in the mapping from the circuit results to the model parameters. Both the physical and logical layers can be assumed to be characterized as tensor products of small-quantity qubit (physical or logical) operations. Therefore, the extensional constant is not important.

[0183] Some embodiments of P2LC have slightly better accuracy.

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[0184] For ε which is significantly lower than the threshold, T P2LC ≪T ExtLC This is acceptable. The proportionality constant in the above equation can depend on many details, such as the number of physical operations per logical operation and the time of a single logical operation relative to a physical operation. However, these factors are polynomial with respect to t, while the factor (ε / ε) th ) t It is exponential and dominant below the threshold.

[0185] As mentioned earlier, the only case in which ExtLC may be able to provide the required characterization (part of it) for SA-LEM is when there are only two syndrome subsets, one of which is rejected. In this case, ExtLC can be used to implement the rejection in the logic characterization circuit (which runs on the QPU as part of ExtLC), thereby accepting the error channel Λ. L|acc This can be characterized. This means that the non-zero rejection probability p rej = 1-p acc This can result in shot sampling overhead in the characterization step. Furthermore, significantly smaller logical errors ε may be more difficult to characterize. L|acc <ε L This may exist. Quantitatively, the QPU time required for ExtLC.

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[0186] The P2LC method may be applicable outside the context of SA-LEM components (described later). In general, the P2LC method may be applicable outside the context of LEM. For example, the P2LC method may be applicable to the design and improvement of decoding algorithms for EC. P2LC may have three main advantages over ExtLC: 1. P2LC can characterize logic errors conditioned on the measured syndrome. 2. P2LC is the inverse ε of the physical error rate. -1 This may require QPU time that can be scaled. This is far worse scaling than is known in the art.

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[0187] SA-LEM Component Description For a given error-corrected quantum logic circuit C, i.e., a quantum circuit compiled to run on a QPU using a given EC scheme (where the EC scheme includes a quantum EC code and a set of error-corrected logic operations including syndrome measurement, decoding, and recovery), it may be desirable to mitigate logic errors, i.e., errors that cannot be corrected by the given EC scheme. Mitigating logic errors may come at the expense of the number of shots overhead corresponding to the QPU time overhead. The basic idea of ​​SA-LEM is to leverage the rich syndrome data generated during the execution of the error-corrected circuit to significantly reduce the QPU time overhead required to satisfy a given output precision, including both statistical and systematic errors, and thus improve upon the currently available solutions of ExtLEM and PS.

[0188] While syndromes are highly useful for correctable errors, they are also blind to logical errors that remain after correction and need to be mitigated. That is, a given syndrome does not indicate with high probability which logical errors occurred (assuming reasonable decoding). The applicant, however, found that syndrome data can be highly useful for understanding the distribution of possible logical errors. This is the information utilized in SA-LEM.

[0189] As an example of SA-LEM, a single occurrence of a single error-corrected logic operation G in a given error-corrected circuit C can be considered. The set of syndromes of this logic operation can be represented by S = {s}, where each syndrome s can be a possible result vector containing the results of all circuit intermediate measurements in G. The syndromes are,

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[0190] EM Protocol EM k Some of these, ideally each of them, S k Error channel Λ under the condition L|k It can be designed to mitigate the mean error channel Λ. L =Σ k p k Λ L|k This is in contrast to ExtLEM, where the restrictions are eased.

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[0191] Tracing back to the decryption algorithm that can be implemented as part of a given EC scheme, ε L|kThe differences can be tracked. Decoding would ideally be performed using a maximum likelihood algorithm. A maximum likelihood algorithm can map each syndrome to a recovery operation that inverts the most probable output error, given the syndrome and the error model of the physical gates. A practical decoder may rely on approximating the ideal decoder. Approximating the ideal decoder may be limited by the limitations arising from limited knowledge of the error model of the physical gates and / or by the classical computational complexity of the decoding problem for large code blocks, where a lookup table may not be feasible. L|k A subset S having k This may include syndromes that, with a high probability, indicate a uniquely required recovery operation. High ε L|k A subset containing this may include syndromes in which multiple recovery operations have a high probability of success.

[0192] EM Protocol EM k To design a conditional non-fidelity ε L|k An example of how it can be used can be given. ε L|k This can be ignored (for example,

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[0193] Any EM protocol designed to mitigate errors in physical operations can, in principle, be adapted and used for error-corrected logical operations within SA-LEM. The EM protocol may include mitigation based on QP decomposition. QP decomposition may be configured to directly invert errors (as in PEC). QP decomposition may be configured to add errors and then perform zero-noise extrapolation (as in ZNE). Additional examples may include the application of a classical inverse description of a universal noise channel in post-processing (as in TEM). In some embodiments, SA-LEM may involve adaptations of two or more physical EM protocols, such that the selection of the adapted protocol may be syndrome-dependent. For example, in some embodiments, PEC may be syndrome-dependent

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[0194] The above example of an EM protocol could be characterization-based and may require a detailed error model to be provided as input. Such a characterization-based protocol is a function that can map a given error channel Λ to the resulting EM protocol EM(Λ).

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[0195] For simplicity, the SA-LEM description given so far can be associated with a single occurrence of a single logic operation G in a given circuit C, and with a single conditional error channel Λ. L|k A subset of syndromes S that can be associated with k This referred to [something]. However, this method allows any number of error-corrected logic operations {G} in a given error-corrected quantum circuit. α} α∈A This can be applied to any number of occurrences of the set {G α} α∈A This may or may not cover all occurrences of all operations in a given circuit. α Some of the (preferably G α For each of the syndromes, K α non-overlapping subsets

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[0196] The rejected subsets and the accepted subsets, as well as their weights w i Optimization of the shot or QPU time overhead can be performed for this. For example, for an acceptable subset S k ≠S rej Supported protocol EM k If the mapping to is fixed, for example,

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[0197] Using these conditions, the shot sampling overhead of SA-LEM is the harmonic expectation of the "conditional variance," as shown below.

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[0198] Minimizing QPU time (as opposed to the number of shots) is achieved by a non-empty set S of rejected elements. rej This could lead to minimizing QPU time, which is an acceptable syndrome s∈S acc This can lead to a partitioning of the accepted syndromes into a single set {s} with inverse variance weights. acc |A division with +1 subsets) is a distinct logical error channel Λ that may need to be characterized and mitigated. L|k This may be useful in reducing the number of subsets. Such coarsening can generally increase the overhead of shots and QPU time. k Conditional logic errors of individual syndromes within

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[0199] In some embodiments, S rej Acceptable subset S as a function of k ≠S rej The selection of can be fixed, and set S rej This can be selected by minimizing either the total QPU time or the total number of shots N, which may be required to satisfy the maximum allowable statistical error and / or the maximum allowable systematic error. In some embodiments, given S rej The selection of acceptable syndromes is for all acceptable syndromes.

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[0200] EM protocols applied to physical operations generally involve three steps: (i) A classical preprocessing step in which an ideal input circuit, an observable expectation estimated with a specified precision, and optionally a physical error model can be mapped (e.g., via modification of the input circuit) to a set of quantum circuits that can be run on a noisy QPU in a certain number of shots (which may be per circuit). (ii) A QPU step in which the acquired circuit is executed on the QPU and the resulting noise can be collected. (iii) A classical post-processing step in which noisy results can be mapped to an estimate of the required expected value.

[0201] In general, the logic involved in both the pre-processing and post-processing steps of the EM protocol can be adapted to utilize syndrome data. That is, the EM protocol can be k-dependent. Circuit modifications that can be adapted to be k-dependent may not be performed during pre-processing as part of SA-LEM, but may be performed in real time, i.e., during circuit execution and / or after syndrome measurement. In particular, the characterization-based protocol EM... k =EM(Λ L|k ) is a subset S of at least two k With respect to embodiments that may be used, the above statement refers to the conditional logic error channel Λ L|kThis can hold for any characteristic-dependent circuit modification that can become k-dependent through (e.g., sampling of circuit modifications from QP decomposition). Assuming that only acceptable syndromes can be measured during circuit execution, and since circuit modifications can be performed in preprocessing, the rejected subset S rej And, characteristic-based mitigation that combines all acceptable syndromes, EM acc =EM(Λ L|acc In the simple case where K=2, accompanied by ), the above implementation issues may not arise.

[0202] Both EC and PS can generally be performed in real time. PS can also be performed in post-processing (for example, by completing the calculation of rejected shots and discarding the corresponding final measurement results). As mentioned earlier, aborting a shot when a rejected syndrome is measured can lead to a reduction in QPU time. In EC, the decoding and recovery steps in each logical operation can be completed before the next logical operation may be performed.

[0203] The Pauli frame method can offer advantages. It can allow subsequent logic operations to be performed in parallel with the decoding process (of preceding logic operations). In known techniques, Pauli frames can also be used in the QPU step of ExtLEM. The same is true for SA-LEM; that is, Pauli frames can be used in the QPU step of SA-LEM, for example, as part of IntLEM. When using SA-LEM, the Pauli frame method can be advantageous because, as mentioned above, several circuit modifications can be performed in real time.

[0204] In known techniques, to avoid unnecessary time delays between subsequent logic operations, it is generally accepted that the decoding algorithm in EC should be loaded as software onto dedicated classical hardware (such as an FPGA or ASIC) that is part of the classical control system of the associated QPU. Similarly, the classical real-time logic involved in SA-LEM may be loaded onto control hardware and, more generally, may be considered part of a generalized syndrome decoding algorithm from both a software and hardware perspective.

[0205] SA-LEM and P2LC may be combined. In some embodiments of SA-LEM, a conditional error channel Λ L|k However, the mitigation protocol EM k This may be required as an input to the following. This input may be provided by P2LC. For example, as follows:

[0206] A subset of layers in a given circuit C

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[0207] In some embodiments, SA-LEM uses the quasi-probability distribution QP k This may involve sampling from the EM protocol. k However, by directly sampling fault paths from the physical error model, QP k This can be combined with fault path sampling in P2LC so that elements can be sampled from it.

[0208] SA-LEM is schematically illustrated in Figure 9. Figure 9 shows a flowchart illustrating an error mitigation method 900 according to an embodiment of the present disclosure. Method 900 may be implemented on a quantum computer. Method 900 may be for mitigating errors in a quantum circuit C. The quantum circuit C may include at least one error-corrected quantum logic operation G.

[0209] The method may include step 915, which may include providing a set of quantum error relaxation protocols {EM}. The set of quantum error relaxation protocols {EM} may include at least two quantum error relaxation protocols. A quantum error relaxation protocol may be configured to relax an error in a quantum circuit C.

[0210] Method 900 may include step 920 which may include performing multiple shots. Performing multiple shots may be done in order to obtain (i.e., to obtain) multiple relaxed circuit results {o}.

[0211] For at least one shot, method 900 may include performing at least one error-corrected quantum logic operation G. For at least one shot, method 900 may include a syndrome measurement result vector.

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[0212] At least one shot may be performed according to at least one quantum error relaxation protocol EM. At least one quantum error relaxation protocol EM may be selected from the set of quantum error relaxation protocols {EM}. The selection of at least one quantum error relaxation protocol EM is the vector of syndrome measurement results.

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[0213] Method 900 is an estimate of the result of the ideal version C0 of the quantum circuit C.

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[0214] It should be noted that a one-to-one correspondence between shots and relaxed circuit results {o} may not always be necessary. For example, in some embodiments, at least one syndrome measurement result vector may be associated with at least two relaxed circuit results. Alternatively, or in combination, at least one relaxed circuit result may be associated with at least two syndrome measurement result vectors.

[0215] In some embodiments, performing a shot according to a quantum error relaxation protocol includes one (or more) of the following: a) Perform the quantum circuit C using at least one additional quantum logic operation. b) Perform the quantum circuit C using at least one removed quantum logic operation. c) Post-process the measurement results of quantum circuit C.

[0216] In some embodiments, executing a shot according to a quantum error relaxation protocol may include either intermediate shot processing of the syndrome measurement results of quantum circuit C, or intermediate shot modification of quantum circuit C. In some embodiments, intermediate shot modification of quantum circuit C may include step 940 of gate selection (e.g., which gates to remove and / or which gates to add).

[0217] In some embodiments, method 900 may include step 930 of applying error suppression (e.g., dynamic separation) for at least one shot.

[0218] In some embodiments, the syndrome measurement result vector

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[0219] In some embodiments, each EM of the quantum error relaxation protocol i This is the syndrome measurement result vector.

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[0220] In some embodiments, a set of quantum error relaxation protocols {EM} may include at least two quantum error relaxation protocols EM 1,2 Each can be configured to mitigate an error in at least one error-corrected quantum logic operation G. As mentioned above, at least two quantum error mitigation protocols EM 1,2 However, it should be noted that while a more general case is described in which errors in quantum circuit C are mitigated, this is not necessarily in at least one error-correcting quantum logic operation G.

[0221] In some embodiments, method 900 applies at least two quantum error relaxation protocols EM to at least one error-corrected quantum logic operation G. 1,2 This may include applying at least one quantum error relaxation protocol selected from the set of quantum error relaxation protocols {EM}. Applying at least one quantum error relaxation protocol may follow at least one associated syndrome of the quantum error relaxation protocol. In some embodiments, method 900 may include performing at least two quantum error relaxation protocols that are included in the set of quantum error relaxation protocols {EM}.

[0222] In some embodiments, the combination is a vector of syndrome measurement results.

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[0223] It should be noted that the combinations are not limited to calculating linear combinations. In some embodiments, combining the measurement results may include calculating a nonlinear function of the result {o} of the relaxed circuit.

[0224] In some embodiments, at least two quantum error relaxation protocols are used to determine the syndrome measurement result vector.

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[0225] In some embodiments, the set of quantum error relaxation protocols {EM} may include any one of quasi-stochastic decomposition, zero-noise extrapolation, and tensor network error relaxation. In some embodiments, the set of quantum error relaxation protocols {EM} may include any two of quasi-stochastic decomposition, zero-noise extrapolation, and tensor network error relaxation. Note that the phrase "any two of" also includes cases where the set of quantum error relaxation protocols {EM} may include multiple error relaxation protocols from only a single type, and different parameterizations may provide differences. For example, the set of quantum error relaxation protocols {EM} may include only error relaxation protocols of the quasi-stochastic decomposition type, and different decompositions may define different weights and / or different circuits. In another example, the set of quantum error relaxation protocols {EM} may include only error relaxation protocols of the zero-noise extrapolation type, and different extrapolations may define different regression analyses (e.g., linear and exponential) and / or different thresholds.

[0226] In some embodiments, the set of quantum error relaxation protocols {EM} may include quasi-probability decompositions, and method 900 is an error channel

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[0227] In some embodiments, the set of quantum error relaxation protocols {EM} may include quasi-stochastic decompositions that can approximate an ideal version C0 of a quantum circuit C. In general, quasi-stochastic decompositions are not limited to approximating ideal circuits. For example, in some embodiments, quasi-stochastic decompositions may approximate an amplified error channel

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[0228] In some embodiments, the set of quantum error relaxation protocols {EM} may include a quasi-probability decomposition, and the square of the quasi-probability norm of the quasi-probability decomposition W 2 This is an error channel

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[0229] In some embodiments, sampling the quantum circuit can be performed concurrently with the execution of at least one shot.

[0230] In some embodiments, method 900 may include a post-selection step 960, namely, rejection syndrome.

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[0231] In some embodiments, a collection of rejection syndromes

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[0232] It should be noted that a one-to-one correspondence between selected / rejected shots and measured syndromes may not always be necessary. For example, in some embodiments, at least one shot may be selected (or rejected) based on multiple vectors of syndrome measurement results.

[0233] It should be noted that a one-to-one correspondence between the gate and the measured syndrome may not always be necessary. For example, in some embodiments, the quantum circuit C is a set of multiple error-corrected quantum logic operations G (α) This may include at least one syndrome measurement result vector, and at least two error-corrected quantum logic operations G (1,2) It can be associated with.

[0234] In some embodiments, at least one error-corrected quantum logic operation G is encoded according to an odd-distance error-corrected code.

[0235] In some embodiments, the quantum circuit C performs at least two quantum logic operations G that can act on overlapping sets of qubits. 1,2 It may include. In some embodiments, the quantum circuit C has at least two quantum logic operations G 1,2 This includes and can act sequentially. In some embodiments, at least two error-corrected quantum logic operations G (1,2) This could be a different quantum logic operation.

[0236] In some embodiments, at least one quantum error relaxation protocol EM may be selected from a set of quantum error relaxation protocols {EM} based on multiple vectors of syndrome measurement results.

[0237] The derivation of an example of SA-LEM, as well as the simulation and proof of the advantages of SA-LEM, are provided below.

[0238] In some embodiments, method 900 may include step 970 of updating any one of the error mitigation protocols and / or any subset of the syndrome (for example, the association of the syndrome with the error mitigation protocol may be updated). Step 970 may be performed concurrently with the execution of the shot (i.e., step 920).

[0239] Method 900 may include step 980 in which the number of shots N performed can be compared to the target number of shots. Step 980 may control the loop processing of Method 900.

[0240] Single-shot SA-LEM using QP distribution The single-shot SA-LEM based on a quasi-probability (QP) distribution is described below, and its unbiased nature (at least approximately) is proven. The all-N-shot protocol is then described, and its sampling overhead is calculated. The channel Λ generated by P2LC is then explained. l|k and Λ e|k An example of a QP distribution based on this will be explained further later.

[0241] An error correction circuit with faults,

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[0242] From the first syndrome measurement, each syndrome s1 is a probability

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[0243] Sample QP operation after G1

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[0244] Algorithm 4 (Single-shot SA-LEM using QP distribution): 1. Input: 1.1. Error correction circuit C=G D··· G1. In the formula, G1 is the sign state.

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[0245] Lemma 3 (Expected value of SA-LEM using the QP distribution): The estimator o defined by Algorithm 3 is

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[0246] Proof: The conditional expectation of o is,

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[0247] Theorem 5 (SA-LEM using a QP distribution that inverts the exact error channel is unbiased): The QP decomposition used in Algorithm 3 is

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[0248] Proof: Using Lemma 3 above,

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[0249] For your information, the last two multi-line expressions include ( * ) and ( ** ) is attached.

[0250] Some comments can be made regarding Theorem 5. This notation is the input channel to the jth layer.

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[0251] Within P2LC, even with a fixed historical parameter h, it is possible to select (i.e., choose) which portion of the “recent” syndrome data to condition on. A simple example of selection is when P2LC uses the syndrome supervisor input channel.

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[0252] Therefore, SA-LEM can be unbiased regardless of the syndrome data used for conditioning.

[0253] Lemma 3 and Theorem 5 revealed the distributions of two distinct but closely related syndromes.

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[0254] N-Shot SA-LEM and its sampling overhead Previously, we described the construction of SA-LEM (using the QP distribution) in which relaxed single-shot results o can be obtained. Achieving high statistical accuracy generally requires performing N≫1 shots. Multiple shots result in a syndrome data vector s i It can generate a relaxed result of a single shot. i , can generate i=1,...,N. Each o i This can be understood as the syndrome vector s being generated by a two-step sampling procedure, from which the relaxed single-shot result o|s can then be sampled, as explained above. Each o|s is an independent estimator for the same ideal circuit result.

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[0255] weight w i as a function of

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[0256] Multiple weights w i over

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[0257] This provides an incentive to use inverse variance weights within SA-LEM. When using SA-LEM with a QP distribution, the boundary values ​​can be simplified:

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[0258] Algorithm 5 (N-shot SA-LEM): 1. Input: 1.1. Number of shots N. 1.2. Estimates of Syndrome-Conditional Variance

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[0259] Algorithm 5' (N-shot SA-LEM using QP distribution): 1. Input: 1.1. Number of shots N. 1.2. All inputs required for Algorithm 4. 2. Syndrome data vectors s i and the mitigated result of single shot o i To obtain i=1,...,N, algorithm 4 is executed N times. 3. Output:

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[0260] To estimate the accuracy of algorithm 5 (or algorithm 5') as a function of the number of shots N, please note the following (assuming each o|s is unbiased):

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[0261]

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[0262]

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[0263]

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[0264] As mentioned above, each o|s is,

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[0265]

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[0266] System 3: Incorporating syndrome rejection into SA-LEM may only increase shot overhead, but it may reduce QPU time overhead.

[0267] Proof: In terms of shot overhead, syndrome rejection puts weight on a particular shot. i This may correspond to assigning =0. These weights may differ from the optimal inverse variance weights (i.e., these weights are

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[0268] The rejection syndrome does not need to be decrypted or mitigated, meaning that syndrome rejection can simplify software and hardware implementations.

[0269] The rejected subset S rej To obtain an expression for the shot overhead of SA-LEM with , syndrome rejection can be considered a limited case of inverse variance weighting, where s∈S rej Regarding

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[0270] The sampling overhead of SA-LEM can be compared to the sampling overhead of ExtLEM (i.e., "naive" syndrome forgetting type relaxation of logical errors). To make a comparison, the non-fidelity ε to be relaxed is L And the corresponding boundary values ​​for single-shot dispersion of the EM protocol method

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[0271] Theorem 7 (SA-LEM's advantage over ExtLEM in terms of shot overhead):

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[0272] Proof: The syndrome-conditional variance boundary in SA-LEM is,

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[0273] Applying f to both sides of the inequality,

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[0274] Example: A simplified but representative expression for shot overhead in the EM protocol is:

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[0275]

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[0276] In the proof of Theorem 7, SA-LEM uses a different relaxation protocol EM for each syndrome vector. s =EM(Λ L|sWe assumed that we could assign ) to any partition of a subset of the syndrome. The extension to any partition of a subset of the syndrome is straightforward. Any syndrome vector, the entry of the syndrome vector, s=(s α ) α∈A It can be written from the perspective of, and in the formula, each s α This can be a syndrome of different logic operations in a circuit. (Each

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[0277] A general division {S} that includes a subset that is rejected. k The following equality can be held for}:

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[0278] Blow-up rate of SA-LEM using QP distribution To demonstrate that reducing shot overhead caused by SA-LEM is generally important, SA-LEM using the QP distribution (Algorithm 5') can be used as a representative example. In this case,

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[0279]

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[0280]

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[0281]

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[0282] Therefore, Theorem 7 is confirmed again. Furthermore, what has been explicitly demonstrated is:

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[0283] Case Study: Binary SA-LEM using the QP distribution Exemplary blow-up rate λ SA-LEM To perform the analysis and calculation, the binary division of the syndrome at each layer can be considered. That is, the syndrome can be divided into only two syndrome subsets S0 and S1. Each subset corresponds to the EM protocol EM0 = EM(Λ L|0 ), EM1=EM(Λ L|1 ) may have. The corresponding EM protocol is QP distribution

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[0284]

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[0285] λ SA-LEM ε could be the proportion of logical errors included in S1. L|1 and

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[0286] ε L|1 Since λ is generally not small, SA-LEM The blow-up rate is such that set S1 has a significant proportion of logical errors p 1|L As long as it can bear the responsibility, λ ExtLEM =4+O(ε L ), can be significantly reduced.

[0287] large ε L|1 Regarding this, it may be reasonable to reject set S1 instead of relaxing this set with EM1. In this case, the blow-up rate may be as follows:

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[0288] ε L As long as it is >1 / 4, this simpler version of SA-LEM may also improve the blow-up rate compared to ExtLEM, but as expected, the improvement can always be greater when using EM1, as opposed to rejecting S1.

[0289] In this example, these two cases are ε L|1 =1 / 2 can be given the same blow-up rate, where we ignore (O(ε)L (Ignoring the correction)

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[0290] Squared QP norm W 2 (ε L|1 )=(1-2ε L|1 ) -2 is, ε L|1 Any channel Λ < 1 / 2 L|1 It can be obtained from a series expansion that can be used to invert ε. L|1 Regarding >1 / 2, the expansion may not converge. However, expression W 2 (ε L|1 )=(1-2ε L|1 ) -2 is, Λ L|1 =(1-ε L|1 )I+ε L|1 If σ can be a Pauli channel with a single Pauli error σ, then all ε L|1 This may be valid for ≠1 / 2, because:

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[0291] ε L|1 Regarding >1 / 2, in this example, assuming maximum likelihood decoding, the identity operator is the logical error channel Λ L|1 Since it may be necessary to have the highest probability in this range, it can address "decoding errors". Therefore, the QP norm is in the range 1 / 2 < ε L|1 It can decrease for ≤ 1, and using ε with W1=1 L|1 Deterministic decoding correction at =1

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[0292] Generally, a large ε L|1 This may not accommodate decoding errors, and the QP norm can generally be large in this regime. Figure 10A illustrates a common example of this based on the "Hadamard QP distribution" (described later) for a depolarized channel.

[0293] More specifically, Figure 10A shows a line graph illustrating the blow-up rates of several versions of binary SA-LEM compared to the blow-up rate of ExtLEM.

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[0294] In the first embodiment of SA-LEM, the subset S0 is the norm

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[0295] In a second embodiment of SA-LEM, the subset S1 is, here, the norm

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[0296] The third embodiment of SA-LEM is a large ε L|1 A more general example of the behavior in is provided to illustrate this. Such behavior can be obtained by considering the "Hadamard QP distribution" of a depolarized channel on a single logical qubit. ε L|1 =3 / 4,

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[0297] Lower fault tolerance threshold When using ExtLEM, logical non-fiction ε L Aside from the replacement of physical fidelity ε by the sampling overhead

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[0298] Therefore, the physical error ε(where,

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[0299] Figure 10B illustrates an example of this effect. More specifically, Figure 10B illustrates a comparison of circuit volume (CV) boost due to EC and EM for exemplary embodiments of ExtLEM and SA-LEM. This is a numerical simulation of repeated EC cycles (logic memory circuit) using a well-known Steen code (7-qubit color code, see Figure 3C and the related description above).

[0300] The dataset is denoted as follows: Datasets associated with error correction only are marked with a circular marker. • Datasets associated with implementing only unbiased error mitigation are marked with a triangular marker. • Datasets associated with performing ExtLEM are marked with an x ​​marker. • Datasets associated with performing SA-LEM are marked with a diamond-shaped marker.

[0301] SA-LEM is performed using two syndrome subsets. The first subset is the rejected subset S. rej This includes all syndromes that do not allow a unique lowest weight recovery operation. The second subset is (i.e., complementary to the first subset). The EM protocol is applied based on the QP distribution. Each physical two-qubit gate bears a physical fidelity ε, resulting from the tensor product of the two single-qubit depolarized channels after the gate.

[0302] Both SA-LEM and ExtLEM are based on error models generated by P2LC. The dataset labeled EC+PS is the same rejected subset S rej This corresponds to conducting post-selection based on [the criteria].

[0303] Panel (a) shows the following: The maximum circuit volume possible with each method is calculated as a function of the required output accuracy relative to the volume possible with bare execution (while maintaining the same accuracy). Each method is

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[0304] ExtLEM, which applies EM to logic qubits, benefits from both EC and EM and provides a greater CV boost than EM. SA-LEM leverages syndrome data to implement more efficient mitigation of logic errors and significantly boosts the available CV compared to EM alone, EC alone, and ExtLEM. In particular, the CV is boosted orders of magnitude more than EC.

[0305] EC+PS offers significant advantages over EC, and can even outperform ExtLEM at low precision, but consistently underperforms SA-LEM, especially at high precision. This is due to the unmitigated residual logic error ε. l|acc It is caused by this.

[0306] Panel (b) shows the following: SA-LEM has a fidelity of ε=10 -3Even above the Steen code threshold, it offers a significant advantage over all competing strategies, which has already been experimentally demonstrated herein. Above the threshold, logical errors become greater than physical errors, and EC only reduces the available CV for the bare QPU. Therefore, ExtLEM appears to underperform EM, and EC seems useless. However, SA-LEM still offers a significant advantage over EM (and over ExtLEM and EC), making EC useful even above the EC threshold. The non-fidelity of EM underperforming SA-LEM becomes a characteristic of a significantly higher, new kind of EC threshold. {This much has already been sent to cl.}

[0307] Optimal rejection As mentioned above,

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[0308] The above strategy is rejected by the subset S. rej In contrast, a shot overhead

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[0309] Λ l QP distribution for (In embodiments in which SA-LEM can be combined with P2LC) P2LC is,

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[0310] The following definition applies when σ≠I, a I =Σ σ≠I p σ and a σ =p σ .

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[0311] The above QP norm is W = 1 + 2ε + O(ε 2 In this sense, it is suboptimal for small ε, and it can be shown that this coincides with an exact lower bound on the QP norm in the leading term. At ε = 1 / 2, the QP norm explodes, signaling the radius of convergence of the above series expansion, which may be valid for ε < 1 / 2.

[0312] In the context of SA-LEM,

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[0313] Λ e QP distribution for

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[0314]

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[0315] Here, nc is Λ out It can be included in Λ in This could be a set of Pauli errors that may not be included, and this could correspond to uncorrectable errors for h≧t+1. Finally,

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[0316] Λ l Approximate QP distribution and integrated sampling for Λ l When working with O(ε t+2 ) An approximation may already be used,

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[0317] This representation may be useful because it could allow for easy sampling of relaxation circuits directly from the physical error model. In other words, it could enable the integration of relaxation circuit sampling in SA-LEM with fault path sampling in P2LC. The following may hold:

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[0318] Inserting such a QP distribution into a given error correction circuit can give the following:

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[0319] LEM bias caused by characterization errors Proposition 2 (LEM bias is bounded by relative characterization precision): Λ j =Σp j,σ σ and

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[0320]

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[0321] Proof: The diamond norm is a Pauli channel.

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[0322] Figure 10C shows a graph illustrating the fidelity of the simulated logic output state as a function of the logic circuit depth. The error-corrected logic circuit is (CX) depth Given by the formula, where CX is based on Steen coding (see Figure 3C and the related explanation above). For the record, "correlated decoding" of the syndrome was used in both syndrome measurement blocks. Physical nonfiction is given by ε = 10 -3 The physical error channel is set to the example illustrated in Figure 10B. All error reduction methods are given a shot "budget" N=5000 for each circuit depth. SA-LEM and ExtLEM are implemented as described in the example illustrated in Figure 10B. EC alone (dashed line, dataset 1005) is significantly biased and results in large inaccuracies at very small circuit depths. ExtLEM (dashed line, dataset 1010) eliminates this bias but comes with statistical error bars that grow exponentially with depth. The error bars for SA-LEM (solid line, dataset 1015) also increase exponentially, but the blow-up rate is significantly reduced.

[0323] Figure 11 and the following discussion are intended to provide a brief and general description of exemplary computing environments in which the disclosed technology may be implemented. While not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, executed by a personal computer (PC). Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Furthermore, the disclosed technology may be implemented in other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, and mainframe computers. The disclosed technology may also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0324] Referring to Figure 11, an exemplary system for implementing the disclosed technology includes a general-purpose (typical) computing device in the form of an exemplary conventional PC 1100, comprising one or more processing units 1110, a system memory 1120, and a system bus 1130 that connects various system components, including the system memory 1120, to one or more processing units 1110. The system bus 1130 may be one of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, and / or a local bus using any of various bus architectures. The exemplary system memory 1120 includes read-only memory (ROM) 1122 and random-access memory (RAM) 1127. A basic input / output system (BIOS) 1125, which contains basic routines useful for transferring information between elements within the PC 1100, is stored in the ROM 1122. As shown in Figure 11, the system memory 1120 may store computer-executable instructions for performing any of the disclosed techniques (e.g., sending instructions to a quantum computer to apply a characterization gate sequence and an adjacent gate sequence to a subset of qubits, measuring the results, collecting frequencies, and calculating model parameters) in their respective memory portions (generally indicated as executable software 1129 for performing any embodiment of the disclosed synthesis technique).

[0325] An exemplary PC1100 further includes one or more storage devices 1140, such as a hard disk drive for reading and writing to a hard disk, a magnetic disk drive for reading and writing to a removable magnetic disk, and / or an optical disk drive for reading and writing to a removable optical disk (such as a CD-ROM or other optical medium). Such storage devices can each be connected to the system bus 1130 by a hard disk drive interface, a magnetic disk drive interface, and / or an optical drive interface. The drives and their associated computer-readable media provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data for the PC1100. In the exemplary operating environment, other types of computer-readable media that can store data accessible by the PC may also be used, such as magnetic cassettes, flash memory, digital video discs, CDs, DVDs, RAM, NVRAM, and ROM. As used herein, the terms storage, memory, and computer-readable media may not include or encompass the propagating carrier or signal itself.

[0326] The operating system, one or more application programs, other program modules, and several program modules including program data may be stored in the storage device 1140. The storage of quantum measurement results and instructions for obtaining such measurements (and / or instructions for carrying out any embodiment of the disclosed technology) may also be stored in the storage device 1140. The user may input commands and information to the PC 1100 via one or more input devices 1150, such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, gamepad, satellite receiver antenna, scanner, etc. These and other input devices are often connected to one or more processing units 1110 via a serial port interface coupled to the system bus 1130, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 1180 or other type of display device is also connected to the system bus 1130 via an interface such as a video adapter. Other peripheral output devices 1160 may include speakers and a printer (not shown). In some cases, a user interface is displayed so that the user can input the circuit for synthesis and verify the success of the synthesis.

[0327] The PC1100 may operate in a networked environment using logical connections to one or more remote computers, such as remote computers 1190. In some examples, this may include one or more network or communication connections 1170. The remote computer 1190 may be another PC, server, router, network PC, or peer device or other common network node, and typically includes many or all of the elements described above with respect to the PC1100, although only the memory storage device 1195 is illustrated in Figure 11. The personal computer 1100 and / or remote computer 1190 may be connected to a local area network (LAN) and a wide area network (WAN). Such networking environments are common in offices, enterprise-wide computer networks, intranets, and the internet.

[0328] When used in a LAN networking environment, the PC1100 connects to the LAN via a network interface. When used in a WAN networking environment, the PC1100 typically includes a modem or other means for establishing communication over a WAN such as the Internet. In a networked environment, program modules or parts thereof described in relation to the personal computer 1100 may be stored in a remote memory storage device or other location on the LAN or WAN. The illustrated network connection is illustrative, and other means may be used to establish communication links between computers.

[0329] Referring to Figure 12, an exemplary system for implementing the disclosed technology includes a computing environment 1200, the environment including one or more quantum processing units 1210, each including one or more monitoring / measurement devices. The quantum processing units execute quantum circuits provided by a typical processing unit 1220. The quantum circuits are downloaded to the quantum processing units 1210 or used (e.g., via control lines (quantum buses) 1270) to program or configure the quantum processing units. Procedures according to any of the disclosed embodiments (e.g., high-level descriptions of qubit patches and sets of quantum circuits applied to neighboring qubits) may be stored in memory 1230.

[0330] Referring to Figure 12, a high-level description of quantum software can be translated into a quantum circuit (e.g., a sequence of quantum gates, or a layer of gates acting in parallel on different qubits). Such a high-level description may optionally be stored on one or more external computers 1260 outside the computing environment 1200 using one or more memory and / or storage devices 1265, and then, if necessary, can be downloaded to the computing environment 1200 via one or more communication connections 1240. The quantum circuit (according to any of the disclosed embodiments) is coupled to a quantum processor 1210.

[0331] The quantum processing unit may be, but is not limited to, one or more of the following: (a) a superconducting quantum computer, (b) an ion-trap quantum computer, (c) a topological quantum computer using, for example, a Majorana zero-mode, (d) a photon quantum computer, or (e) a neutral-atom quantum computer. A set of gates (e.g., using any of the disclosed embodiments) may be transmitted to the quantum processing unit via control lines 1270 in the controller 1250 (or may be otherwise applied). In the illustrated example, the desired quantum computing process is carried out using one or more controllers 1250, each specifically adapted to control one of the corresponding quantum processors 1210. The classical processor 1220 can further interact with a measurement / monitoring device (e.g., a readout device) 1280 to help control and implement the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit when available).

[0332] The foregoing description of embodiments of the present invention is presented for illustrative and explanatory purposes only and is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Numerous modifications and adaptations thereof will be apparent to those skilled in the art without departing from the spirit and scope of the invention. For example, techniques from any example can be combined with techniques described in any one or more of the other examples.

[0333] The foregoing description of embodiments of the present invention is presented for illustrative and explanatory purposes only and is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Numerous modifications and adaptations thereof will be apparent to those skilled in the art without departing from the spirit and scope of the invention. For example, techniques from any example can be combined with techniques described in any one or more of the other examples.

[0334] Therefore, applying the wording of the clause, this disclosure provides methods, systems, and circuits subject to the following clauses, but is not limited to these: Clause 1: A computer-implemented method for mitigating errors in a quantum circuit C that includes at least one error-corrected quantum logic operation G, wherein the method is (a) To provide a set of quantum error relaxation protocols {EM} including at least two quantum error relaxation protocols configured to mitigate errors in the quantum circuit C, (b) Performing multiple shots to obtain the result {o} of multiple relaxed circuits, i) For at least one shot, the method is used to determine the syndrome measurement result vector.

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[0335] Clause 2: The shot must be executed in accordance with the quantum error mitigation protocol. (a) The quantum circuit C is performed by at least one additional quantum logic operation, (b) The quantum circuit C is performed using at least one removed quantum logic operation, (c) Post-processing the measurement results of the quantum circuit C, (d) Executing a quantum circuit having a different structure from the quantum circuit C, (e) Executing a quantum circuit having a different structure from the said quantum circuit C, The method according to Clause 1, comprising any one of the following: (f) post-processing the measurement result of at least one shot of the quantum circuit C.

[0336] Clause 3: The method according to Clause 2, wherein executing a shot in accordance with a quantum error mitigation protocol includes either intermediate processing of the syndrome measurement result of the quantum circuit C or intermediate modification of the quantum circuit C.

[0337] Clause 4: Syndrome measurement result vector

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[0338] Clause 5: Syndrome measurement result vector

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[0339] Clause 6: Each EM of the said quantum error mitigation protocol i However, the syndrome measurement result vector

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[0340] Clause 7: The set of quantum error relaxation protocols {EM} is configured to relax errors in at least one error-corrected quantum logic operation G, with at least two quantum error relaxation protocols EM 1,2 The method described in any one of the clauses 1 to 6, including the method described in any one of the clauses 1 to 6.

[0341] Clause 8: The at least one error-corrected quantum logic operation G is associated with the at least one associated quantum error mitigation protocol EM 1,2 The method according to Clause 7, comprising applying at least one quantum error mitigation protocol selected from the following.

[0342] Clause 9: The method described in any one of Clauses 1 to 8, comprising performing at least two quantum error relaxation protocols included in the set of quantum error relaxation protocols {EM}.

[0343] Clause 10: The combination of the vector of the syndrome measurement results

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[0344] Clause 11: Combining the results of the relaxed circuit shall result in a weighted average of the results of the relaxed circuit {o}.

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[0345] Article 12: Each of the weights

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[0346] Clause 13: Estimate of the variance

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[0347] Clause 14: The at least two quantum error relaxation protocols are used to determine the syndrome measurement result vector

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[0348] Clause 15: The error channel

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[0349] Clause 16: The error channel

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[0350] Clause 17: The method according to any one of Clauses 1 to 16, wherein combining the measurement results includes calculating a nonlinear function of the result {o} of the relaxed circuit.

[0351] Clause 18: The method according to any one of Clauses 1 to 17, wherein the set of quantum error relaxation protocols {EM} includes any two of the following: quasi-stochastic decomposition, zero-noise extrapolation, and tensor network error relaxation.

[0352] Clause 19: The set of quantum error relaxation protocols {EM} includes a quasi-stochastic decomposition method, and the method includes the error channel

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[0353] Clause 20: The method according to Clause 19, wherein the quasi-stochastic decomposition approximates an ideal version C0 of the quantum circuit C.

[0354] Clause 21: If the quasi-probability decomposition is the error channel

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[0355] Clause 22: The square of the quasi-probability norm of the quasi-probability decomposition W 2 However, the error channel

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[0356] Clause 23: The method according to any one of Clauses 19-22, wherein sampling of the quantum circuit is performed concurrently with the execution of at least one shot.

[0357] Clause 24: Refusal Syndrome

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[0358] Article 25: The collection of such rejection syndromes

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[0359] Article 26: The collection of such rejection syndromes

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[0360] Clause 27: The method of Clauses 24-26, which are subordinate to Clause 6 or 7, including the denial of at least one shot based on the at least one associated syndrome of at least one shot.

[0361] Clause 28: The method described in any one of Clauses 24-27, wherein the refusal includes the cancellation of at least one shot.

[0362] Clause 29: The method according to any one of Clauses 24 to 28, wherein the at least one error-corrected quantum logic operation G is encoded according to an error-correcting code of odd distance.

[0363] Clause 30: The vector of the syndrome measurement result corresponding to the rejected shot.

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[0364] Clause 31: The quantum circuit C acts on at least two quantum logic operations G on an overlapping set of qubits. 1,2 The method described in any one of the clauses 1 to 30, including the method described in any one of the clauses 1 to 30.

[0365] Clause 32: The quantum circuit C acts sequentially on at least two quantum logic operations G 1,2 The method described in any one of the clauses 1 to 31, including the method described in any one of the clauses 1 to 31.

[0366] Clause 33: The method according to any one of Clauses 1 to 32, wherein the result of at least one relaxed circuit is associated with at least two syndrome measurement result vectors.

[0367] Clause 34: The method according to any one of Clauses 1 to 33, wherein at least one syndrome measurement result vector is associated with at least two relaxed circuit results.

[0368] Clause 35: The method according to any one of Clauses 1 to 34, wherein the at least one quantum error relaxation protocol EM is selected from a set of quantum error relaxation protocols {EM} based on a plurality of vectors of syndrome measurement results.

[0369] Clause 36: The method according to any one of Clauses 1 to 34, wherein multiple shots are performed in accordance with the at least one quantum error mitigation protocol EM.

[0370] Clause 37: The method according to any one of Clauses 1 to 36, wherein the at least one shot is selected based on multiple vectors of syndrome measurement results.

[0371] Article 38: The quantum circuit C performs multiple error-corrected quantum logic operations G (α) The at least one syndrome measurement result vector includes at least two error-corrected quantum logic operations G (1,2) The method described in any one of clauses 1 to 37, relating thereto. Article 39: The at least two error-corrected quantum logic operations G (1,2) However, the method described in Article 38 is a different quantum logic operation.

[0372] Clause 40: A computer-implemented method for simulating quantum computing, the method comprising simulating on a classical computer a method implemented by a quantum computer according to any one of Clauses 1 to 39.

[0373] Clause 41: A non-temporary computer-readable storage medium that tangibly embodies a program of instructions that, when executed by a computer, cause a computer to carry out the method described in any one of Clauses 1 to 40.

[0374] Clause 42: A computer-implemented method for computing a mitigate error in an error-corrected logical quantum operation, wherein the method is (a) Characterizing the physical error of at least one physical quantum gate included in the logical quantum operation in order to obtain physical characterization data, (b) A method comprising simulating the logical quantum operation according to the characterized data to obtain simulated output errors and syndromes in order to obtain such mitigable errors.

[0375] Clause 43: Characterizing physical errors, (a) Applying at least one characterization sequence to the set of qubits contained in the quantum processor, (b) Using a measuring device for the quantum processor to measure the set of qubits and thereby obtain a set of measurements, (c) The method of Clause 42, which includes calculating the physical characterization data by fitting a model to the set of measurements.

[0376] Clause 44: The method according to Clause 42 or 43, wherein simulating the logical quantum operation includes calculating a distribution of correctable and uncorrectable output errors according to the simulated output errors and syndromes.

[0377] Clause 45: The method described in Clause 44, which includes simulating output errors, including the calculation of logical output errors.

[0378] Clause 46: The method according to Clause 45, wherein the calculation of logical output errors is performed according to a fault tolerance level t, which is the number of faults correctable by an ideal error correction cycle.

[0379] Clause 47: The method according to Clause 46, which includes calculating at least t+1 faults.

[0380] Article 48: Simulating the said logical quantum operation, (a) In order to obtain the output error channel, provide an error-free input channel to the logic quantum operation, (b) Correctable portion Λ of the output error channel * And the logical error portion Λ of the output error channel in question. l The method according to any one of the clauses 45 to 47, which includes applying an ideal error correction cycle to the output error channel in order to obtain the following.

[0381] Clause 49: Error-corrected sequence of logical quantum operations G k··· A computer-implemented method for characterizing the output error channel in G1, wherein the method is a partial sequence of error-corrected logical quantum operations G1,...,G h Each quantum operation G n This includes performing the method described in any one of the clauses 45 to 47, wherein each quantum operation G n Regarding (a) the quantum operation G n Output error channel Λ n In order to obtain the quantum operation, the preceding quantum operation G n-1 Correctable portion of the output error channel

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[0382] Clause 50: Error-corrected subcircuit G of logic quantum operations D··· Computer-implemented method G for characterizing the output error channel in G1 D··· G1, and the method is each sequence G A··· G H The method includes carrying out the method described in Article 49, wherein H = max(1, Ah) and where h is a historical parameter n.

[0383] Clause 51: The method according to Clause 50, wherein h is equal to the fault tolerance level t or t+1.

[0384] Clause 52: Characterizing physical errors is important for the relative accuracy of physical errors.

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[0385] Clause 53: The method described in any one of Clauses 42 to 52, wherein simulating the logical quantum operation includes performing the simulation using either a Clifford simulator or a state vector simulator.

[0386] Clause 54: A computer-implemented method for mitigating logical errors in error-corrected logical quantum operations, wherein the method is (a) Characterizing a logical quantum operation by any one of the methods described in any one of clauses 42 to 53, thereby obtaining a characterization of the output error channel. (b) A method comprising mitigating errors in accordance with the characterization of an output error channel by the method described in any one of clauses 1 to 39.

[0387] Clause 55: A non-temporary computer-readable storage medium that tangibly embodies a program of instructions that, when executed by a computer, cause a computer to carry out the method described in any one of Clauses 42 to 54.

[0388] Clause 56: A computer system comprising at least one processing circuit configured to perform a computer-implemented method for computing a mitigate error in an error-corrected logic quantum operation as described in any one of Clauses 42 to 54.

[0389] Clause 57: A computer system comprising at least one processing circuit configured to perform a computer-implemented method for mitigating logic errors in a quantum circuit including an error-corrected logic quantum operation, as described in any one of Clauses 1 to 39 and 54.

[0390] Clause 58: A computer system as described in any one of Clauses 56 to 57, comprising a quantum processing unit.

[0391] Clause 59: A method implemented by a computer, the method comprising simulating a method described in any one of Clauses 42 to 54.

[0392] Clause 60: A non-temporary computer-readable storage medium that tangibly embodies a program of instructions that, when executed by a computer, cause a computer to carry out the methods described in Clause 59.

[0393] Further embodiments may include the following: 1. Error-corrected logic operations implemented on a quantum processor {G α} α∈A A method for mitigating a logic error in a given error-corrected quantum circuit ("syndrome recognition logic error mitigation"), the method including, a) Each error-corrected logical operation G α Regarding the set of corresponding syndromes, K αnon-overlapping subsets

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[0394] 2. Each error mitigation protocol EM k but, a) Modification of a quantum circuit, wherein k-independent circuit modification may be performed in preprocessing, k α Dependent circuit modification occurs during circuit execution and operation G α After it is executed, and the corrections that will be made, b) The method according to Example 1, which may involve post-processing of the modified circuit results to obtain the results of a relaxed single-shot circuit.

[0395] 3. Combining the results of a relaxed single-shot circuit with the syndrome subset index to obtain the results of a relaxed N-shot circuit is a weighted average.

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[0396] 4. Some of the weights in the weighted average are inverse variance weights.

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[0397] 5. For a certain α,

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[0398] 6.

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[0399] 7.

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[0400] 8. k-dependent error mitigation protocol EM k However, S k Conditional error channel Λ corresponding to a logical error that is conditional L|k The method according to any one of Examples 1 to 7, configured to mitigate the effects of the following:

[0401] 9. k-dependent error mitigation protocol EM k However, Λ L|kThe k-dependent quasi-probability distribution QP of circuit modifications constructed based on this k The method according to Example 8, with sampling from [source].

[0402] 10. Quasi-probability distribution QP k However, given the circuit C=C(Λ L|k The method according to Example 9, wherein a logic error-free version C(I) of ) is approximated, and the quantum channel C(·) expresses a given circuit as a function of the conditional error channel.

[0403] 11. The variance estimate used for inverse variance weighting is QP k Quasi-probability norm W k Squaring it, that is

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[0404] 12. Error Mitigation Protocol EM k However, Λ L|k Amplification or reduction of and subsequent zero logic error (Λ) of the given circuit L|k The method according to Example 8, which involves extrapolation to the value =I).

[0405] 13.Λ L|k Amplification or reduction of the exponent λ≠±1

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[0406] 14. Error Mitigation Protocol EM k However, the final measurement of a given circuit in one or more measurement bases and the global conditional error channel

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[0407] 15. A system implementing the method of any one of Examples 1 to 14, comprising a classical processor, a quantum processor, and a classical control system for the quantum processor, wherein the classical processor uses an error mitigation protocol EM k The pre-processing and post-processing included in the classical control system can be implemented, and syndrome decoding as part of error correction, and EM k A system in which any k-dependent circuit modification included can be implemented, and the quantum processor implements the corresponding modified quantum circuit.

[0408] 16. Conditional error channel Λ L|k However, the method according to any one of Examples 8 to 16, obtained by applying an error characterization protocol to a quantum processor.

[0409] 17. The method according to Example 17, wherein the characterization protocol is applied to a physical operation involving an error-corrected quantum circuit C.

[0410] 18. Error-corrected quantum circuit C=L constructed from the physical operations of a quantum processor. D··· Layer L of error-corrected logic operations included in L1 j A method for characterizing input errors, output errors, and logic errors in a system, wherein the method is a) Obtaining a model of physical errors in physical operations by applying a characterization protocol to physical operations on a quantum processor, b) Mapping the physical error model to a model of input errors, output errors, and logical errors for the error-corrected logic operation layer, wherein the mapping is L j And the preceding circuit layer where h≧1

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[0411] 19. Characterization protocols applied to physical operations, a) Application of quantum circuits and final measurements sensitive to parameters of a physical error model to quantum processors. b) The method according to Example 18, further comprising fitting the model parameters to the results of the final measurement of the model parameters in order to obtain the values ​​of the model parameters.

[0412] 20. The iterative procedure is a)

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[0413] 21.L j and L j+1 Applies to both, ratio

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[0414] 22. The method according to any one of Examples 18 to 21, wherein circuit C has a fault tolerance level t and h = t.

[0415] 23. Each fault path is a partial circuit

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[0416] twenty four. a) Partial circuit

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[0417] 25. Operation G α However, the final simulated layer L j The method described in Example 24, which is included only in [the specified example].

[0418] 26. The method according to any one of Examples 23-25, wherein fault path sampling from a physical error model is performed via emphasis sampling based on a set of constraints that must be satisfied by the fault path in order to generate a logical error.

[0419] 27. Conditional error channel Λ L|k However, this is estimated using the characterization method described in any one of Examples 19 to 27. a) A subset of layers in a given circuit C

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[0420] 28. EM Protocol EM k However, by directly sampling fault paths from the physical error model, QP k Quasi-probability distribution QP k The method according to any one of Examples 17 and 23-26, wherein sampling from is combined with sampling of fault paths.

Claims

1. A computer-implemented method for mitigating errors in a quantum circuit C that includes at least one error-corrected quantum logic operation G, wherein the method is - To provide a set of quantum error mitigation protocols {EM} including at least two quantum error mitigation protocols configured to mitigate errors in the quantum circuit C, - Performing multiple shots to obtain the result {o} of multiple relaxed circuits, i) For at least one shot, the method determines the syndrome measurement result vector [Math 1] To obtain the at least one error-corrected quantum logic operation G, the process includes performing the at least one error-corrected quantum logic operation G and measuring the at least one syndrome associated with the at least one error-corrected quantum logic operation. ii) At least one shot is the vector of the syndrome measurement result [Math 2] Based on this, the following is performed according to at least one quantum error relaxation protocol EM selected from the set of quantum error relaxation protocols {EM}: • An ideal version C of the aforementioned quantum circuit C ０ Estimated result [Math 3] A method comprising combining the results of the relaxed circuit {o} to obtain.

2. Performing a shot according to the quantum error mitigation protocol, - The quantum circuit C is executed by at least one additional quantum logic operation, - The quantum circuit C is executed using at least one removed quantum logic operation, - Implementing a quantum circuit having a structure different from the aforementioned quantum circuit C, - Post-processing the measurement result of at least one shot of the quantum circuit C, The method according to claim 1, wherein executing a shot according to a quantum error mitigation protocol includes either intermediate processing of the syndrome measurement result of the quantum circuit C or intermediate correction of the quantum circuit C.

3. • Syndrome measurement result vector [Math 4] A non-overlapping set of quantum error relaxation protocols {EM} is a set of different quantum error relaxation protocols EM included in the set of quantum error relaxation protocols {EM}. ｉ Associated with, • Syndrome measurement result vector [Math 5] The union of the non-overlapping sets of includes all possible syndromes of the at least one quantum logic operation G, Each of the EMs of the aforementioned quantum error mitigation protocols ｉ However, the syndrome measurement result vector [Math 6] The method according to claim 1, configured to mitigate errors associated with a set of values.

4. The set of quantum error relaxation protocols {EM} consists of at least two quantum error relaxation protocols EM configured to mitigate errors in at least one error-corrected quantum logic operation G. １，２ The method includes, wherein the method applies to the at least one error-corrected quantum logic operation G according to the at least one associated syndrome of the at least one error-corrected quantum logic operation, the at least two quantum error mitigation protocols EM １，２ The method according to claim 1, comprising applying at least one quantum error mitigation protocol selected from the following.

5. The method according to claim 1, comprising performing at least two quantum error relaxation protocols included in the set of quantum error relaxation protocols {EM}.

6. The aforementioned combination is the vector of the syndrome measurement results. [Number 7] The method according to claim 1, as carried out in accordance with the present invention.

7. - Combining the results of the relaxed circuit results in a weighted average of the results of the relaxed circuit {o}. [Number 8] This includes calculating each weight w in the formula. ｋ However, the syndrome measurement result vector [Number 9] It is associated with a set, where N is the number of shots, Each of the above weights [Number 10] but, [Math 11] It is proportional to, and in the formula, [Math 12] However, this is an estimate of the variance of the probability distribution of the result o of the relaxed circuit, and the said distribution is the syndrome measurement result vector. [Number 13] It is conditioned according to the set of, - The above method is the estimated value of the variance [Number 14] The method according to claim 6, which includes calculating

8. The at least two quantum error relaxation protocols described above affect the syndrome measurement result vector. [Number 15] Error channels associated with [Number 16] and the error channel [Number 17] However, logical error channels [Number 18] And in the formula, [Number 19] The method is configured to mitigate the error channel, and the method is configured to mitigate the error channel [Number 20] The method according to claim 1, comprising estimating the following.

9. The method according to claim 1, wherein combining the measurement results includes calculating a nonlinear function of the result {o} of the relaxed circuit.

10. The method according to claim 1, wherein the set of quantum error relaxation protocols {EM} includes any two of the following: quasi-stochastic decomposition, zero-noise extrapolation, and tensor network error relaxation.

11. The set of quantum error relaxation protocols {EM} includes a quasi-probability decomposition, and the method includes the error channel [Math 21] The method according to claim 10, dependent on claim 8, comprising sampling a quantum circuit according to a distribution based on .

12. - The quasi-probability decomposition is the ideal version C of the quantum circuit C. ０ And the execution of the quantum circuit C is the error channel [Number 22] The amplified error channel has an exponent λ ≠ ±1. [Number 23] It is approximated by either being affected by or - The square of the quasi-probability norm of the quasi-probability decomposition W ２ However, the error channel [Number 24] The aforementioned estimate of the variance associated with [Number 25] The method according to claim 11, which is equivalent to claim 6.

13. The method according to claim 11, wherein sampling of the quantum circuit is performed concurrently with the execution of at least one shot.

14. Rejection Syndrome [Number 26] Includes rejecting at least one shot based on the set, - The aforementioned rejection syndrome [Number 27] The set is the syndrome measurement result vector associated with the quantum error relaxation protocol EM ｉ ​ [Number 28] It does not overlap with any set of, - The collection of the aforementioned rejection syndromes [Number 29] However, it is selected to minimize at least one of the total execution time and the number of shots N. - The method includes a rejection of at least one shot based on the associated at least one syndrome of at least one shot, wherein the rejection includes a halt to the at least one shot. - The method provides the vector of the syndrome measurement result corresponding to the rejected shot. [Number 30] The method according to claim 3, which includes processing.

15. The quantum circuit C performs at least two quantum logic operations G sequentially on a set of overlapping qubits. １，２ The method according to claim 1, including the method described in claim 1.

16. - At least one relaxed circuit result is associated with at least two syndrome measurement result vectors. The method according to claim 1, wherein at least one syndrome measurement result vector is associated with at least two relaxed circuit results.

17. - The at least one quantum error mitigation protocol EM and - At least one of the above shots is The method according to claim 1, wherein a selection is made from a set of quantum error relaxation protocols {EM} based on a plurality of vectors of syndrome measurement results.

18. The method according to claim 1, wherein multiple shots are performed according to the at least one quantum error mitigation protocol EM.

19. The quantum circuit C performs multiple error-corrected quantum logic operations G （α） The at least one syndrome measurement result vector includes at least two error-corrected quantum logic operations G （１，２） Associated with the at least two error-corrected quantum logic operations G （１，２） However, the method according to claim 1 is a different quantum logic operation.

20. A non-temporary computer-readable storage medium that tangibly embodies a program of instructions that, when executed by a computer, causes the computer to carry out the method described in claim 1.

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