Decoder for analog neural memory in deep learning artificial neural networks

Abstract

This invention provides a bit line decoder circuit, system, word line driver, and current voltage circuit for use with vector matrix multiplication (VMM) arrays in artificial neural networks. [Solution] The decoder includes a bit line decoder, a word line decoder, a control gate decoder, a source line decoder, and an erase gate decoder. In certain embodiments, high-voltage and low-voltage versions of the decoder are used. The system comprises a vector matrix multiplication (VMM) array and a source line decoder circuit coupled to the word line terminals of a non-volatile memory cell, to which a low voltage or high voltage can be applied to the coupled source line terminals, and comprising a drive transistor and a monitor transistor.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Provisional Patent Application No. 62 / 642,884, filed March 14, 2018, entitled "Decoders for Analog Neuromorphic Memory in Artificial Neural Network," and U.S. Patent Application No. 15 / 991,890, filed May 29, 2018, entitled "Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network."

[0002] (Field of invention) Numerous embodiments of decoders for use with vector-matrix multiplication (VMM) arrays in artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks can rely on a large number of inputs and are used to estimate or approximate functions that are largely unknown, mimicking biological neural networks (the central nervous system of animals, particularly the brain). Artificial neural networks generally consist of layers of interconnected "neurons" that exchange messages.

[0004] Figure 1 illustrates an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple layers of inputs. Typically, there are hidden layers of one or more neurons and output layers of neurons that provide the output of the neural network. At each level, neurons make decisions individually or collectively based on the data received from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., very high levels of computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of specialized graphics processing units. However, in addition to the high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses have been too bulky considering the large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application No. 15 / 594,439, incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neuromorphic memories. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced source and drain regions formed in a semiconductor substrate with a channel region extending between them, a floating gate disposed above a first portion of the channel region and isolated from the first portion of the channel region, and a non-floating gate disposed above a second portion of the channel region and isolated from the second portion of the channel region. Each of the plurality of memory cells is configured to store weight values ​​corresponding to many electrons of the floating gate. Multiple memory cells are configured to generate a first set of outputs by multiplying a first set of inputs by stored weight values.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory system must be erased and programmed to hold a highly specific and precise amount of charge within its floating gate. For example, each floating gate must hold one of N distinct values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, and 64.

[0008] Conventional decoding circuits (such as bit-line decoders, word-line decoders, control-gate decoders, source-line decoders, and erase-gate decoders) are not suitable for use with VMMs in analog neuromorphic memory systems. One reason for this is that in VMM systems, the verification portion of the program and verification operation (which is the read operation) operates on a single selected memory cell, while the read operation operates on all memory cells in the array.

[0009] What is needed is an improved decoding circuit suitable for use with VMM in analog neuromorphic memory systems. [Overview of the Initiative]

[0010] Numerous embodiments for use with vector-matrix multiplication (VMM) arrays in artificial neural networks are disclosed.

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[0054] [Brief explanation of the drawing]

[0055] [Figure 1] This is a diagram of an artificial neural network. [Figure 2] This is a cross-sectional view of a conventional 2-gate non-volatile memory cell. [Figure 3] This is a cross-sectional view of a conventional 4-gate non-volatile memory cell. [Figure 4] This is a cross-sectional view of a conventional 3-gate non-volatile memory cell. [Figure 5] This is a cross-sectional view of another conventional 2-gate non-volatile memory cell. [Figure 6] This figure shows exemplary artificial neural networks at different levels that utilize non-volatile memory arrays. [Figure 7] This is a block diagram of a vector multiplier matrix. [Figure 8] This is a block diagram showing vector multiplier matrices of various levels. [Figure 9] One embodiment of a vector multiplier matrix is ​​shown. [Figure 10] Another embodiment of the vector multiplier matrix is ​​shown. [Figure 11] Another embodiment of the vector multiplier matrix is ​​shown. [Figure 12] Another embodiment of the vector multiplier matrix is ​​shown. [Figure 13] Another embodiment of the vector multiplier matrix is ​​shown. [Figure 14] One embodiment of a bit line decoder for a vector multiplier matrix is ​​shown. [Figure 15] Another embodiment of a bit line decoder for a vector multiplier matrix is ​​shown. [Figure 16] Another embodiment of a bit line decoder for a vector multiplier matrix is ​​shown. [Figure 17] This document describes a system for operating a vector multiplier matrix. [Figure 18] Here is another system for operating a vector multiplier matrix. [Figure 19] Here is another system for operating a vector multiplier matrix. [Figure 20] This document presents one embodiment of a word line driver for use with a vector multiplier matrix. [Figure 21] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 22] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 23] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 24] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 25] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 26] Another embodiment of the word line driver for use with a vector multiplier matrix is ​​shown. [Figure 27]This shows a source line decoder circuit for use with a vector multiplier matrix. [Figure 28] This document shows word-line decoder circuits, source-line decoder circuits, and high-voltage level shifters for use with a vector multiplier matrix. [Figure 29] This document shows an erase gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high-voltage level shifter for use with a vector multiplier matrix. [Figure 30] This shows a word line decoder circuit for use with a vector multiplier matrix. [Figure 31] This shows a control gate decoder circuit for use with a vector multiplier matrix. [Figure 32] Another control gate decoder circuit for use with a vector multiplier matrix is ​​shown. [Figure 33] Another control gate decoder circuit for use with a vector multiplier matrix is ​​shown. [Figure 34] This shows a current-voltage circuit for controlling word lines in a vector multiplier matrix. [Figure 35] Another current-voltage circuit for controlling word lines in a vector multiplier matrix is ​​shown. [Figure 36] This diagram shows a current-voltage circuit for controlling the control gate lines in a vector multiplier matrix. [Figure 37] Another current-voltage circuit for controlling the control gate lines in a vector multiplier matrix is ​​shown. [Figure 38] Another current-voltage circuit for controlling the control gate lines in a vector multiplier matrix is ​​shown. [Figure 39] Another current-voltage circuit for controlling word lines in a vector multiplier matrix is ​​shown. [Figure 40] Another current-voltage circuit for controlling word lines in a vector multiplier matrix is ​​shown. [Figure 41]Another current-voltage circuit for controlling word lines in a vector multiplier matrix is ​​shown. [Figure 42] Figure 9 shows the operating voltage of the vector multiplier matrix. [Figure 43] Figure 10 shows the operating voltage of the vector multiplier matrix. [Figure 44] Figure 11 shows the operating voltage of the vector multiplier matrix. [Figure 45] Figure 12 shows the operating voltage of the vector multiplier matrix. [Modes for carrying out the invention]

[0056] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. Non-volatile memory cell

[0057] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("Patent No. 130") discloses an array of split-gate non-volatile memory cells, which are incorporated herein by reference for all purposes. Such memory cells are shown in Figure 2. Each memory cell 210 is formed in a semiconductor substrate 12 and includes a source region 14 and a drain region 16, with a channel region 18 between them. A floating gate 20 is formed above a first portion of the channel region 18, insulated from the first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18), and also formed above a portion of the source region 16. A word line terminal 22 (typically coupled to a word line) is disposed above a second portion of the channel region 18 and has a first portion that is insulated from the second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18), and a second portion that is above and extends upward of the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0058] The memory cell 210 is erased by applying a high-voltage positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), thereby tunneling the electrons from the floating gate 20 through the intermediate insulator to the word line terminal 22 via Fowler-Nordheim tunneling.

[0059] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source 16 (where electrons are applied to the floating gate). The electron current flows from the source 16 towards the drain 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, they are accelerated and heated. Some of the heated electrons are injected into the floating gate 20 through the gate oxide 26 due to the electrostatic attraction from the floating gate 20.

[0060] The memory cell 210 is read by applying a positive read voltage to the drain 14 and the word line terminal 22 (turning on the channel region below the word line terminal). If the floating gate 20 is positively charged (i.e., erases electrons and positively couples to the drain 16), the portion of the channel region below the floating gate 20 is then similarly turned on, and current flows through the channel region 18, which is perceived as the erased state, or the "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is then almost or completely turned off, and no current flows (or only a small current flows) through the channel region 18, which is perceived as the programmed state, or the "0" state.

[0061] Table 1 shows typical voltage ranges that can be applied to the terminals of the memory cell 210 for performing read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 2 [Table 1]

[0062] Other split-gate memory cell configurations are known. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a selection gate 28 (typically coupled to a word line) above a second portion of the channel region 18, a control gate 22 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except the floating gate 20, are non-floating gates, meaning they are electrically connected to or connectable to a voltage source. Programming is indicated by heated electrons from the channel region 18 injecting themselves into the floating gate 20. Erasing is indicated by electrons tunneling from the floating gate 20 to the erase gate 30.

[0063] Table 2 shows typical voltage ranges that can be applied to the terminals of the memory cell 310 for performing read, erase, and program operations. Table 2: Operation of the flash memory cell 310 in Figure 3 [Table 2]

[0064] Figure 4 shows a split-gate 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (erasure through the erase gate) and read operation are the same as those in Figure 3, except that there is no control gate bias. The programming operation is also performed without a control gate bias, so the program voltage on the source line is higher to compensate for the lack of control gate bias.

[0065] Table 3 shows typical voltage ranges that can be applied to the terminals of the memory cell 410 for performing read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0066] Figure 5 shows a stacked gate memory cell 510. The memory cell 510 is similar to the memory cell 210 in Figure 2, except that the floating gate 20 extends above the channel region 18, and the control gate 22 extends above the floating gate 20 separated by an insulating layer. Erase, programming, and read operations are performed in the same manner as described above for the memory cell 210.

[0067] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 for read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0068] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured so that each memory cell can be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0069] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously with minimal disturbance to other memory cells, from a completely erased state to a completely programmed state. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously with minimal disturbance to other memory cells, from a completely programmed state to a completely erased state, and vice versa. This means that cell memory can be analog or store at least one of a number of distinct values ​​(such as 16 or 64 different values), which allows for very precise and individual tuning of all cells in the memory array, making the memory array ideal for storage and allowing for fine-tuning of the synaptic weights of a neural network. Neural networks using non-volatile memory cell arrays

[0070] Figure 6 conceptually illustrates an unrestricted embodiment of a neural network utilizing a non-volatile memory array. While this example uses a non-volatile memory array neural network for a facial recognition application, any other suitable application can be implemented using a non-volatile memory array-based neural network.

[0071] S0 is the input, and in this example, it is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1 going from S0 to C1 has both different sets of weights and shared weights, scans the input image with a 3x3 pixel overlapping filter (kernel), and shifts the filter by one pixel (or two or more pixels as determined by the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, by which these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of that multiplication, a single output value is determined and given by the first neuron of CB1 to generate one pixel of a layer in the feature map C1. The 3x3 filter is then shifted one pixel to the right (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), so the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, which are then multiplied by the same weights to determine a second single output value by the associated neuron. This process continues until the 3x3 filter has scanned all three colors and all bits across the entire 32x32 pixel image (precision value). The process is then repeated with different sets of weights to generate different feature maps of layer C1 until all feature maps of C1 have been computed.

[0072] In C1, in this example, there are 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array, and thus in this example, synapse CB1 constitutes 16 layers of two-dimensional arrays (note that the neuron layers and arrays referred to herein are logical relationships rather than physical relationships, i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps is generated by one of 16 different sets of synaptic weights applied to the filtered scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, the first map (generated using a first set of weights shared across all scans used to generate this first map) can identify circular edges, and the second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0073] The activation function P1 (pooling) is applied before moving from C1 to S1, pooling values ​​from consecutive, non-overlapping 2x2 regions within each feature map. The purpose of the pooling stage is to average to neighborhood locations (or the max function may also be used), reduce dependence on edge locations, for example, and reduce the data size before moving to the next stage. In S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapses and associated neurons in CB2 moving from S1 to C2 scan the maps in S1 with a 4x4 filter using a 1-pixel filter shift. In C2, there are 22 12x12 feature maps. The activation function P2 (pooling) is applied before moving from C2 to S2, pooling values ​​from consecutive, non-overlapping 2x2 regions within each feature map. In S2, there are 22 6x6 feature maps. The activation function is applied at synapse CB3, which goes from S2 to C3, where all neurons in C3 connect to all maps in S2. There are 64 neurons in C3. Synapse CB4, which goes from C3 to output S3, completely connects S3 to C3. The output in S3 contains 10 neurons, where the highest output neuron determines the class. This output can, for example, indicate the identification or classification of the content of the original image.

[0074] Each level of the synapse is performed using an array or part of an array of non-volatile memory cells. Figure 7 is a block diagram of a vector matrix multiplication (VMM) array that includes non-volatile memory cells and is used as a synapse between the input layer and the next layer. Specifically, the VMM 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, control gate decoder 35, bit line decoder 36, and source line decoder 37, which decoders decode the input to the memory array 33. In this example, the source line decoder 37 also decodes the output of the memory cell array. Alternatively, the bit line decoder 36 can decode the output of the memory array. The memory array serves two purposes. First, it stores the weights used by the VMM. Second, the memory array effectively multiplies the input by the weights stored in the memory array and adds them up for each output line (source line or bit line) to produce an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also power-efficient for on-the-spot memory calculations.

[0075] The output of the memory array is fed to a differential adder (such as an adder operational amplifier) ​​38, which sums the outputs of the memory cell array to produce a single value for its convolution. The differential adder is such that a positive input results in the sum of positive and negative weights. The summed output value is then fed to an activation function circuit 39, which rectifies the output. The activation function may include a sigmoid, tanh, or ReLU function. The rectified output value becomes an element of the feature map as the next layer (e.g., C1 in the above description), and is then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the memory array constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the adder operational amplifier 38 and activation function circuit 39 constitute multiple neurons.

[0076] Figure 8 is a block diagram of VMMs at various levels. As shown in Figure 14, the input is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM 32a. The output generated by the input VMM 32a is provided as input to the next VMM (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM (hidden level 2) 32b, and so on. The 32 different layers of the VMM function as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM can be a standalone non-volatile memory array, or multiple VMMs can utilize different parts of the same non-volatile memory array, or multiple VMMs can utilize overlapping parts of the same non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that the system may instead have more than two hidden layers and more than two fully connected layers. Vector Matrix Multiplication (VMM) Array

[0077] Figure 9 shows a neuron VMM900 particularly suited to the type of memory cell shown in Figure 2, which is used as part of the synapses and neurons between the input layer and the next layer. The VMM900 comprises a memory array 903 of non-volatile memory cells, a reference array 901, and a reference array 902. The reference arrays 901 and 902 are responsible for converting the current inputs flowing into terminals BLR0~3 into voltage inputs WL0~3. The reference arrays 901 and 902 shown are oriented in the column direction. Generally, the reference array direction is perpendicular to the input lines. In practice, the reference memory cells are diodes connected via multiplexers (multiplexer 914, which includes one multiplexer and one cascode transistor VBLR for biasing the reference bit lines), and the current inputs flow into them. The reference cells are tuned to a target reference level.

[0078] The memory array 903 serves two purposes. First, it stores the weights used by the VMM900. Second, the memory array 903 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0~3, which reference arrays 901 and 902 convert into input voltages and supply to word lines WL0~3) to generate an output, which becomes the input to the next layer or the final layer. By performing the multiplication function, the memory array eliminates the need for a separate multiplication logic circuit and is also power efficient. Here, the voltage input is provided to the word line, and the output appears on the bit line during read (inference) operation. The current on the bit line performs a function of the sum of all currents from memory cells connected to the bit line.

[0079] Figure 42 shows the operating voltages of the VMM900. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations.

[0080] Figure 10 shows a neuron VMM1000 particularly suited to the type of memory cell shown in Figure 2, which is used as part of the synapse and neuron between the input layer and the next layer. The VMM1000 comprises a memory array 1003 of nonvolatile memory cells, a reference array 1001, and a reference array 1002. The VMM1000 is similar to the VMM900 except that the word lines in the VMM1000 extend vertically. There are two reference arrays 1001 (at the top, providing reference conversion input current to the voltages of even rows) and 1002 (at the bottom, providing reference conversion input current to the voltages of odd rows). Here, the input is provided to the word line, and the output appears on the source line during read operations. The current on the source line performs a function of the sum of all currents from the memory cells connected to the source line.

[0081] Figure 43 shows the operating voltages of the VMM1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations.

[0082] Figure 11 shows a neuron VMM1100 particularly suitable for the type of memory cell shown in Figure 3, and is used as part of the synapses and neurons between the input layer and the next layer. The VMM1100 comprises a memory array 1101 of nonvolatile memory cells, a reference array 1102 (providing reference conversion input current to the input voltage of even rows), and a reference array 1103 (providing reference conversion input current to the input voltage of odd rows). The VMM1100 is similar to the VMM900 except for the VMM1100. The VMM1100 further comprises control lines 1106 coupled to the control gates of the memory cell rows, and control lines 1107 coupled to the erase gates of adjacent rows of memory cells. Here, the word lines, control gate lines, and erase gate lines are in the same direction. The VMM further comprises a reference bit line selection transistor 1104 (part of mux 1114) which selectively couples to the bit line contacts of a selected reference memory cell and switch 1105 (part of mux 1114), and this bit line selection transistor 1104 selectively couples the reference bit line to the control line 1106 for a particular selected reference memory cell. Here, the input is provided to the word line (of the memory array 1101) and the output appears on the bit line, such as the bit line 1109, during read operations. The current on the bit line performs a function of the sum of all currents from the memory cells connected to the bit line.

[0083] Figure 44 shows the operating voltages of the VMM1100. The columns in the table show the voltages of the word line of the selected cell, the word line of the unselected cell, the bit line of the selected cell, the bit line of the unselected cell, the control gate of the selected cell, the control gate of an unselected cell in the same sector as the selected cell, the control gate of an unselected cell in a different sector than the selected cell, the erase gate of the selected cell, the erase gate of an unselected cell, the source line of the selected cell, and the source line of an unselected cell. The rows show the read, erase, and program operations.

[0084] Figure 12 shows a neuron VMM1200 particularly suitable for the type of memory cell shown in Figure 3, and is used as part of the synapse and neuron between the input layer and the next layer. The VMM1200 is similar to the VMM1100 except that the erase gate lines, such as the erase gate line 1201, extend vertically. Here, the input is supplied to the word line and the output appears on the source line. The current on the bit line performs a function of the sum of all currents from the memory cells connected to the bit line.

[0085] Figure 45 shows the operating voltages of the VMM1200. The columns in the table show the voltages of the word line of the selected cell, the word line of the unselected cell, the bit line of the selected cell, the bit line of the unselected cell, the control gate of the selected cell, the control gate of an unselected cell in the same sector as the selected cell, the control gate of an unselected cell in a different sector than the selected cell, the erase gate of the selected cell, the erase gate of an unselected cell, the source line of the selected cell, and the source line of an unselected cell. The rows show the read, erase, and program operations.

[0086] Figure 13 shows a neuron VMM1300 particularly suited to the type of memory cell shown in Figure 3, which is used as part of the synapses and neurons between the input layer and the next layer. The VMM1300 comprises a memory array 1301 of nonvolatile memory cells and a reference array 1302 (at the top of the array). Alternatively, another reference array may be located at the bottom, as in Figure 10. In other respects, the VMM1300 is similar to the VMM1200, except that in the VMM1300, control gate lines such as control gate lines 1303 extend vertically (thus the row-direction reference array 1302 is perpendicular to the input control gate lines), and erase gate lines such as erase gate lines 1304 extend horizontally. Here, inputs are provided to the control gate lines and outputs appear on the source lines. In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current on the source line performs a function of the sum of all currents from the memory cells connected to the source line.

[0087] As described herein for the neural network, the flash cell is preferably configured to operate in the subthreshold region.

[0088] The memory cells described herein are biased in weak inversion. Ids = Io * e (Vg-Vth) / kVt = w * Io * e (Vg) / kVt w = e (-Vth) / kVt

[0089] Regarding the I-V log converter that uses the memory cell to convert the input current into an input voltage: Vg = k * Vt * log[Ids / wp * Io]

[0090] Regarding the memory array used as the vector matrix multiplier VMM, the output current is as follows: Iout = wa * Io * e (Vg) / kVt That is Iout = (wa / wp) * Iin = W * Iin W = e (Vthp-Vtha) / kVt

[0091] The word line or control gate can be used as the input to the memory cell for the input voltage.

[0092] Alternatively, the flash memory cell can be configured to operate in the linear region. Ids = β * (Vgs - Vth) * Vds; β = u * Cox * W / L W α (Vgs - Vth)

[0093] IV linear converters use memory cells that operate in the linear domain to linearly convert input / output currents to input / output voltages.

[0094] Other embodiments of the ESF vector matrix multiplier are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. The source line or bit line can be used as the neuron output (current sum output).

[0095] Figure 14 shows one embodiment of the bit-line decoder circuit 1400. The bit-line decoder circuit 1400 comprises a column decoder 1402 and an analog neuromorphic neuron ("ANN") column decoder 1403, each of which is coupled to a VMM array 1401. The VMM array can be based on any of the VMM designs discussed earlier (such as VMM900, 1000, 1100, 1200, and 1300) or any other VMM design.

[0096] One challenge with analog neuromorphic systems is that the system must be programmable and verifiable (including read operations), and capable of performing ANN readouts in which all cells in the array are selected and read. In other words, the bit-line decoder may, in some cases, select only one bit line, and in other cases, select all bit lines.

[0097] The bit line decoder circuit 1400 achieves this objective. The column decoder 1402 is a conventional column decoder (program and erase, or PE, decode path) that can be used to select individual bit lines such as program and program verification (sensing operation). The output of the column decoder 1402 is coupled to a program / erase (PE) column driver circuit for controlling program, PE verification, and erase (not shown in Figure 14). The ANN column decoder 1403 is a column decoder specifically designed to allow read operations on all bit lines at once. The ANN column decoder 1403 comprises an exemplary selection transistor 1405 and output circuit (e.g., current adder and activation function such as tanh, sigmoid, ReLU) 1406 coupled to a bit line (here BL0). The same set of devices is attached to each of the other bit lines. All of the selection transistors, such as selection transistor 1405, are coupled to selection line 1404. During ANN readout operation, selection line 1404 is enabled, each of the selection transistors such as selection transistor 1405 is turned on, and then the current from each bit line is received by the output circuit such as circuit 1406 and output.

[0098] Figure 15 shows one embodiment of the bit line decoder circuit 1500. The bit line decoder circuit 1500 is coupled to a VMM array 1501. The VMM array can be based on any of the VMM designs discussed earlier (such as VMM900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0099] Select transistors 1502 and 1503 are controlled by a pair of complementary control signals (V0 and VB_0) and coupled to a bit line (BL0). Select transistors 1504 and 1505 are controlled by another pair of complementary control signals (V1 and VB_1) and coupled to another bit line (BL1). Select transistors 1502 and 1504 are coupled to the same output to enable programming, and select transistors 1503 and 1505 are coupled to the same output for disabling programming, etc. The output lines of transistors 1502 / 1503 / 1504 / 1505 (program and erase PE decode paths) are such that they are coupled to PE column driver circuits for controlling program, PE verification, and erase (not shown).

[0100] The selection transistor 1506 is coupled to the bit line (BL0) and to the output and activation function circuit 1507 (e.g., current summing and activation functions such as tanh, sigmoid, ReLU). The selection transistor 1506 is controlled by the control line 1508.

[0101] When only BL0 is activated, control line 1508 is deasserted, signal V0 is asserted, and therefore only BL0 is read. During ANN readout operation, control line 1508 is asserted, selection transistor 1506 and similar transistors are turned on, and all bit lines are read out for all neuron processing.

[0102] Figure 16 shows one embodiment of the bit line decoder circuit 1600. The bit line decoder circuit 1600 is coupled to a VMM array 1601. The VMM array can be based on any of the VMM designs discussed earlier (such as VMM900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0103] The selection transistor 1601 is coupled to the bit line (BL0) and to the output and activation function circuit 1603. The selection transistor 1602 is coupled to the bit line (BL0) and the common output (PE decode path).

[0104] When only BL0 is activated, the selection transistor 1602 is activated, and BL0 is connected to the common output. During ANN readout operation, the selection transistor 1601 and similar transistors are turned on, and all bit lines are read out.

[0105] Regarding decoding in Figures 14, 15, and 16, non-selected transistors can be negatively biased to reduce the impact of transistor leakage on memory cell performance. Alternatively, the PE decoding path can be negatively biased while the array is operating in ANN mode. The negative bias may be -0.1V to -0.5V or higher.

[0106] Figure 17 shows the VMN1700. The VMM system 1700 comprises a VMM array 1701 and a reference array 1720 (which can be based on any of the aforementioned VMM designs, such as VMM900, 1000, 1100, 1200, and 1300, or other VMM designs), a low-voltage row decoder 1702, a high-voltage row decoder 1703, a reference cell low-voltage column decoder 1704 (shown for the column-direction reference array, meaning it provides inputs for outputting conversions in the row direction), a bit-line PE driver 1712, a bit-line multiplexer 1706, an activation function circuit and adder 1707, control logic 1705, and an analog bias circuit 1708.

[0107] As shown in the figure, the reference cell low-voltage column decoder 1704 is located for the column-oriented reference array 1720 and provides inputs for outputting conversions in the row direction. If the reference array is row-oriented, the reference decoder must be located at the top and / or bottom of the array and provide inputs for outputting conversions in the column direction.

[0108] The low-voltage row decoder 1702 provides bias voltages for read and program operations and provides the decode signal for the high-voltage row decoder 1703. The high-voltage row decoder 1703 provides high-voltage bias signals for program and erase operations. The reference cell low-voltage row decoder 1704 provides the decode function for the reference cell. The bit line PE driver 1712 provides the bit line control function for program, verification, and erase. The bias circuit 1705 is a shared bias block that provides multiple voltages required for various program, erase, program verification, and read operations.

[0109] Figure 18 shows the VMM system 1800. The VMM system 1800 is similar to the VMM system 1700, except that the VMM system 1800 further comprises a red array 1801, a bit line PE driver BLDRV 1802, a high-voltage column decoder 1803, an NVR sector 1804, and a reference array 1820. The high-voltage column decoder 1803 provides a high-voltage bias for the vertical decode line. The red array 1802 provides array redundancy for replacing defective array portions. The NVR (Non-Volatile Register, also known as Information Sector) sector 1804 is an array sector used to store user information, device ID, password, security key, trim bits, configuration bits, manufacturing information, etc.

[0110] Figure 19 shows VMM system 1900. VMM system 1900 is similar to VMM system 1800, except that VMM system 1900 further comprises a reference system 1999. The reference system 1999 comprises a reference array 1901, a reference array low-voltage row decoder 1902, a reference array high-voltage row decoder 1903, and a reference array low-voltage column decoder 1904. The reference system can be shared across multiple VMM systems. The VMM system further comprises an NVR sector 1905.

[0111] The reference array low-voltage row decoder 1902 provides a bias voltage for readout and programming operations with the reference array 1901, and also provides the decode signal for the reference array high-voltage row decoder 1903. The reference array high-voltage row decoder 1903 provides a high-voltage bias for programming and operation with the reference array 1901. The reference array low-voltage column decoder 1904 provides the decode function for the reference array 1901. The reference array 1901 provides a reference target or cell margin for program verification (such as searching for edge cells).

[0112] Figure 20 shows a word line driver 2000. The word line driver 2000 selects word lines (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown herein) and provides a bias voltage to those word lines. Each word line is connected to a selection transistor, such as a selection iso (isolation) transistor 2002, which is controlled by a control line 2001. The iso transistor 2002 is used to isolate high voltages, such as erase (e.g., 8-12V), from the word line decode transistor, which can be implemented with an IO transistor (e.g., 1.8V, 3.3V). Here, during any operation, the control line 2001 is activated, and all selection transistors similar to the iso transistor 2002 are turned on. Exemplary bias transistor 2003 (part of the word line decoding circuit) selectively couples word lines to a first bias voltage (e.g., 3V), and exemplary bias transistor 2004 (part of the word line decoding circuit) selectively couples word lines to a second bias voltage (lower than the first bias voltage, including ground, an intermediate bias, and a negative voltage bias to reduce leakage from unused memory rows). During ANN readout operation, all used word lines are selected and coupled to the first bias voltage. All unused word lines are coupled to the second bias voltage. During other operations, such as program operation, only one word line is selected until the other word line is coupled to the second bias voltage, which may be a negative bias (e.g., -0.3 to -0.5V or higher) to reduce array leakage.

[0113] Figure 21 shows the word line driver 2100. The word line driver 2100 is similar to the word line driver 2000, except that top transistors such as bias transistor 2103 can be individually coupled to the bias voltage, and all such transistors are not coupled together as in the word line driver 2000. This makes it possible for all word lines to have different independent voltages simultaneously.

[0114] Figure 22 shows the word line driver 2200. The word line driver 2200 is similar to the word line driver 2100, except that the bias transistors 2103 and 2104 are coupled to the decoder circuit 2201 and inverter 2202. Therefore, Figure 22 shows the decode subcircuit 2203 within the word line driver 2200.

[0115] Figure 23 shows the word line driver 2300. The word line driver 2300 is similar to the word line driver 2100, except that bias transistors 2103 and 2104 are coupled to the output of stage 2302 of the shift register 2301. The shift register 1301 allows for independent control of each column, such as enabling one or more rows to be enabled simultaneously in response to shifts in the data pattern by serial shifting of data (serial timing of the register).

[0116] Figure 24 shows the word line driver 2400. The word line driver 2400 is similar to the word line driver 2000, except that each select transistor is further coupled to a capacitor such as capacitor 2403. Capacitor 2403 can provide a precharge or bias to the word lines at the start of operation, enabled by transistor 2401 to sample the voltage of line 2440 by transistor 2401. Capacitor 2403 acts to sample and hold the input voltage for each word line (S / H). Transistor 2401 is off during the ANN operation (array current adder and activation function) of the VMM array, meaning that the voltage of the S / H capacitor acts as a (stray) voltage source for the word lines. Alternatively, capacitor 2403 may be provided by the word line capacitance from the memory array.

[0117] Figure 25 shows the word line driver 2500. The word line driver 2500 is similar to the previously described word line driver, except that bias transistors 2501 and 2502 are connected to switches 2503 and 2504, respectively. Switch 2503 receives the outputs of the operational amplifier (OPA) 2505 and switch 2504, and switch 2504 provides a reference input to the negative input of the OPA 2505, thereby essentially providing the voltage stored by capacitor 2403 through the action of the closed loop provided by the OPA 2505, transistor 2501, and switches 2503 and 2504. In this way, when switches 2503 and 2504 are closed, the voltage of input 2506 is superimposed on capacitor 2403 by transistor 2501. Alternatively, capacitor 2403 may be provided by word line capacitance from a memory array.

[0118] Figure 26 shows a word line driver. The word line driver 2600 is similar to the word line driver described above, except for the addition of an amplifier 2601 that acts as a voltage buffer for the voltage of capacitor 2604 to drive a voltage to the word line WL0, meaning that the voltage of the S / H capacitor acts as a (stray) voltage source for the word line. This is to avoid, for example, word line coupling affecting the capacitor voltage.

[0119] Figure 27 shows a high-voltage source-line decoder circuit 2700. The high-voltage source-line decoder circuit comprises transistors 2701, 2702, and 2703 configured as shown. Transistor 2703 is used to deselect the source line to a low voltage. Transistor 2702 is used to drive a high voltage to the source line of the array, and transistor 2701 is used to monitor the voltage of the source line. Transistors 2702, 2701 and the driver circuit (e.g., opa) are configured in a closed-loop scheme (force / sensing) to maintain PVT (process, voltage, temperature) and fluctuating current load conditions. The SLE (driven source line node) and SLB (monitored source line node) may be at one end of the source line. Alternatively, the SLE may be at one end of the source line and the SLB at the other end.

[0120] Figure 28 shows a VMM high-voltage decoding circuit comprising a word-line decoder circuit 2801, a source-line decoder circuit 2804, and a high-voltage level shifter 2808, which is suitable for use with the type of memory cell shown in Figure 2.

[0121] The word line decoder circuit 2801 comprises a PMOS selection transistor 2802 (controlled by signal HVO_B) and an NMOS selection transistor 2803 (controlled by signal HVO_B), configured as shown in the figure.

[0122] The source line decoder circuit 2804 includes an NMOS monitoring transistor 2805 (controlled by signal HVO), a drive transistor 2806 (controlled by signal HVO), and a transistor 2807 configured as shown in the figure (controlled by signal HVO_B).

[0123] The high-voltage level shifter 2808 receives a valid signal EN and outputs a high-voltage signal HV and its complement HVO_B.

[0124] Figure 29 shows a VMM high-voltage decoding circuit comprising an erase gate decoder circuit 2901, a control gate decoder circuit 2904, a source line decoder circuit 2907, and a high-voltage level shifter 2911, which is suitable for use with the type of memory cell shown in Figure 3.

[0125] The erase gate decoder circuit 2901 and the control gate decoder circuit 2904 use the same design as the word line decoder circuit 2801 in Figure 28.

[0126] Source line decoder circuit 2907 uses the same design as source line decoder circuit 2804 in Figure 28.

[0127] The high-voltage level shifter 2911 uses the same design as the high-voltage level shifter 2808 shown in Figure 28.

[0128] Figure 30 shows a word line decoder 300 with exemplary word lines WL0, WL1, WL2, and WL3. The exemplary word line WL0 is coupled to a pull-up transistor 3001 and a pull-down transistor 3002. When the pull-up transistor 3001 is activated, WL0 is enabled. When the pull-down transistor 3002 is activated, WL0 is disabled. The function in Figure 30 is similar to that in Figure 21, which does not have an isolation transistor.

[0129] Figure 31 shows an exemplary control gate decoder 3100 with control gate lines CG0, CG1, CG2, and CG3. The exemplary control gate line CG0 is coupled to a pull-up transistor 3101 and a pull-down transistor 3102. When the pull-up transistor 3101 is activated, CG0 is enabled. When the pull-down transistor 3102 is activated, CG0 is disabled. The selection and deselection functions in Figure 31 are similar to the selection and selection functions for the control gates in Figure 30.

[0130] Figure 32 shows an exemplary control gate decoder 3200 for control gate lines CG0, CG1, CG2, and CG3. The control gate decoder 3200 is similar to the control gate decoder 3100, except that the control gate decoder 3200 includes capacitors such as capacitor 3203 coupled to each control gate line. These sample-and-hold (S / H) capacitors can provide a precharge bias to each control gate line before operation, meaning that the voltage across the S / H capacitors acts as a (stray) voltage source for the control gate lines. The S / H capacitors may be provided by the control gate capacitance from the memory cell.

[0131] Figure 33 shows exemplary control gate decoders 3300 for control gate lines CG0, CG1, CG2, and CG3. Control gate decoder 3300 is similar to control gate decoder 3200, except that control gate decoder 3300 further comprises a buffer 3301 (such as an opa).

[0132] Figure 34 shows a current-voltage circuit 3400. The circuit comprises a configured diode-connected reference cell circuit 3450 and a sample-and-hold circuit 3460. Circuit 3450 comprises an input current source 3401, an NMOS transistor 3402, a cascoding bias transistor 3403, and a reference memory cell 3404. The sample-and-hold circuit consists of a switch 3405 and an S / H capacitor 3406. Memory 3404 is biased in a diode-connected configuration with a bit line bias to convert the input current into a voltage, such as supplying a word line.

[0133] Figure 35 shows the current-voltage circuit 3500, which is similar to the current-voltage circuit 3400 but with the addition of an amplifier 3501 after the S / H capacitor. The current-voltage circuit 3500 comprises a configured diode-connected reference cell circuit 3550, a sample-and-hold circuit 3470, and an amplifier stage 3562.

[0134] Figure 36 shows a current-voltage circuit 3600, which has the same design as the control gate current-voltage circuit 3400 in a diode-connected configuration. The current-voltage circuit 3600 comprises a configured diode-connected reference cell circuit 3650 and a sample-and-hold circuit 3660.

[0135] Figure 37 shows a current-voltage circuit 3700 in which a buffer 3790 is placed between a reference circuit 3750 and an S / H circuit 3760.

[0136] Figure 38 shows a current-voltage circuit 3800 similar to Figure 35, having a control gate connected in a diode-connected configuration. The current-voltage circuit 3800 comprises a configured diode-connected reference cell circuit 3550, a sample-and-hold circuit 3870, and an amplifier stage 3862.

[0137] Figure 39 shows a current-voltage circuit 3900 similar to that in Figure 34, applied to the memory cell in Figure 2. The current-voltage circuit 3900 comprises a configured diode-connected reference cell circuit 3950 and a sample-and-hold circuit 3960.

[0138] Figure 40 shows a current-voltage circuit 4000 similar to that in Figure 37 applied to the memory cell in Figure 2, with the buffer 4090 positioned between the reference circuit 4050 and the S / H circuit 4060.

[0139] Figure 41 shows a current-voltage circuit 4100 similar to that in Figure 38, applied to the memory cell in Figure 2. The current-voltage circuit 4100 comprises a configured diode-connected reference cell circuit 4150, a sample-and-hold circuit 4170, and an amplifier stage 4162.

[0140] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (no intermediate material, element, or space is placed between them) and “indirectly on” (intermediate material, element, or space is placed between them). Similarly, the term “adjacent” includes “directly adjacent” (no intermediate material, element, or space is placed between them) and “indirectly adjacent” (intermediate material, element, or space is placed between them); “attached” includes “directly attached” (no intermediate material, element, or space is placed between them) and “indirectly attached to” (intermediate material, element, or space is placed between them); and “electrically coupled” includes “directly electrically coupled” (there is no intermediate material or element between them that electrically connects the elements together) and “indirectly electrically coupled to” (there is an intermediate material or element between them that electrically connects the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate with no intermediate material / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A bit line decoder circuit coupled to a vector matrix multiplication array, wherein the vector matrix multiplication array comprises an array of non-volatile memory cells arranged in rows and columns, each column connected to a bit line, and the bit line decoder circuit is A first circuit for enabling individual bit lines during programming and verification operations, A bit line decoder circuit comprising a second circuit for enabling all bit lines during a read operation.

2. The bit line decoder circuit according to claim 1, wherein the second circuit comprises a selection transistor and an activation function circuit coupled to each bit line.

3. The bit line decoder circuit according to claim 2, wherein the gates of each selection transistor are coupled to the same control line.

4. The bit line decoder circuit according to claim 1, wherein a negative bias is applied to the word line of each unselected memory cell during programming and verification operations or during read operations.

5. The bit line decoder circuit according to claim 1, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

6. The bit line decoder circuit according to claim 1, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

7. The bit line decoder circuit according to claim 1, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

8. The bit line decoder circuit according to claim 1, wherein each of the non-volatile memory cells is configured to operate in the linear region.

9. The bit line decoder circuit according to claim 1, wherein a negative bias is applied to the gate of each unselected bit line decoder during programming and verification operations or during readout operations.

10. A bit line decoder circuit coupled to a vector matrix multiplication array, wherein the vector matrix multiplication array comprises an array of non-volatile memory cells arranged in rows and columns, each column connected to a bit line, and the bit line decoder circuit is A bit line decoder circuit comprising a multiplexing circuit, wherein in a first mode, the multiplexing circuit enables individual bit lines during program and verification operations, and in a second mode, the multiplexing circuit enables all bit lines during read operations.

11. The bit line decoder circuit according to claim 10, wherein the multiplexing circuit comprises a selection transistor and an activation function circuit coupled to each bit line.

12. The bit line decoder circuit according to claim 10, wherein a negative bias is applied to the word line of each unselected memory cell during programming and verification operations or during read operations.

13. The bit line decoder circuit according to claim 10, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

14. The bit line decoder circuit according to claim 10, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

15. The bit line decoder circuit according to claim 10, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

16. The bit line decoder circuit according to claim 10, wherein each of the non-volatile memory cells is configured to operate in the linear region.

17. The bit line decoder circuit according to claim 10, wherein a negative bias is applied to the gate of each unselected bit line decoder during programming and verification operations or during read operations.

18. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each column is connected to a bit line, and each memory cell has a word line terminal and a source line terminal, A word line decoder circuit coupled to the word line terminal of the non-volatile memory cell, wherein a low voltage or a high voltage can be applied to the coupled word line terminal, A system comprising a source line decoder circuit coupled to the source line terminal of the non-volatile memory cell, the source line decoder circuit capable of applying a low voltage or a high voltage to the coupled source line terminal.

19. Each memory cell further comprises an erase gate terminal, and the system is The system according to claim 18, further comprising an erase gate decoder circuit coupled to the erase gate terminal of the nonvolatile memory cell, the erase gate decoder circuit being capable of applying a low voltage or a high voltage to the coupled erase gate terminal.

20. A word line driver coupled to a vector matrix multiplication array, wherein the vector matrix multiplication array comprises an array of non-volatile memory cells organized into rows and columns, each row being coupled to a word line, each word line being coupled to the word line driver, and the word line driver is A plurality of selection transistors, each of which comprises a first terminal, a second terminal, and a gate, the gate of each of which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises which comprises a plurality of selection transistors, each of which comprises which comprises which comprises a plurality of selection transistors, each of which comprises which comprises a plurality of selection transistors, A word line driver in which the bias transistor coupled to each of the plurality of selection transistors can provide a bias voltage to a single selection transistor or all of the selection transistors.

21. The word line driver according to claim 20, wherein at least one bias transistor coupled to each of the plurality of selection transistors is coupled to a common control line.

22. The word line driver according to claim 20, wherein each bias transistor coupled to each of the plurality of selection transistors is coupled to a different control line.

23. The word line driver according to claim 20, wherein each of the bias transistors is coupled to a circuit for decoding word line addresses.

24. The word line driver according to claim 20, wherein the bias transistor is coupled to a shift register.

25. The word line driver according to claim 20, wherein each selection transistor is coupled to a capacitor.

26. The word line driver according to claim 20, wherein each bias transistor is coupled to a comparator.

27. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each column is connected to a bit line, and each memory cell comprises a word line terminal and a source line terminal, A system comprising a word line decoder circuit coupled to the word line terminal of the non-volatile memory cell, the word line decoder circuit being capable of applying a low voltage via a low voltage transistor or a high voltage via a high voltage transistor to the coupled word line terminal, and comprising an isolation transistor coupled to each word line to isolate the high voltage transistor from the low voltage transistor.

28. The system according to claim 27, wherein a negative bias is applied to the word line of each unselected memory cell during programming and verification operations or during read operations.

29. The system according to claim 27, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

30. The system according to claim 27, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

31. The system according to claim 27, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

32. The system according to claim 27, wherein each of the nonvolatile memory cells is configured to operate in the linear region.

33. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each column is connected to a bit line, and each memory cell comprises a word line terminal and a source line terminal, A word line decoder circuit coupled to the word line terminal of the non-volatile memory cell, wherein a low voltage or a high voltage can be applied to the coupled word line terminal, A system comprising a sample-and-hold capacitor coupled to each word line.

34. The system according to claim 33, wherein a negative bias is applied to the word line of each unselected memory cell during programming and verification operations or during read operations.

35. The system according to claim 33, wherein the capacitor in the sample-and-hold capacitor is provided by the intrinsic capacitance of the word line.

36. The system according to claim 33, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

37. The system according to claim 33, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

38. The system according to claim 33, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

39. The system according to claim 33, wherein each of the nonvolatile memory cells is configured to operate in the linear region.

40. The system according to claim 33, wherein the S / H capacitor provides a voltage source for the word line.

41. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each column is connected to a bit line, and each memory cell comprises a word line terminal and a source line terminal, A system comprising a source line decoder circuit coupled to the word line terminal of the non-volatile memory cell, the source line decoder circuit being capable of applying a low voltage or a high voltage to the coupled source line terminal, and comprising a drive transistor and a monitoring transistor.

42. The system according to claim 41, further comprising a force sensing circuit operating in a closed loop.

43. The system according to claim 41, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

44. The system according to claim 41, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

45. The system according to claim 41, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

46. The system according to claim 41, wherein each of the nonvolatile memory cells is configured to operate in the linear region.

47. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, wherein each column is connected to a bit line, and each memory cell comprises a word line terminal and a source line terminal, A control gate decoder circuit coupled to the control gate line terminal of the non-volatile memory cell, wherein a low voltage or a high voltage can be applied to the coupled control gate terminal, A system comprising a sample-and-hold capacitor coupled to each word line.

48. The system according to claim 47, wherein a negative bias is applied to the word line of each unselected memory cell during programming and verification operations or during read operations.

49. The system according to claim 47, wherein the sample-and-hold capacitor has a control gate capacitance.

50. The system according to claim 47, wherein each of the non-volatile memory cells is a split-gate flash memory cell.

51. The system according to claim 47, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

52. The system according to claim 47, wherein each of the non-volatile memory cells is configured to operate in a subthreshold region.

53. The system according to claim 47, wherein each of the nonvolatile memory cells is configured to operate in the linear region.

54. The system according to claim 47, wherein the S / H capacitor provides a voltage source for the control gate line.

55. A current-voltage circuit, A reference circuit for receiving an input current and outputting a first voltage according to the input current, comprising an input current source, an NMOS transistor, a cascoding bias transistor, and a reference memory cell, A current-voltage circuit comprising: a sample-and-hold circuit for receiving a first voltage and outputting a second voltage, wherein the second voltage constitutes a sampled value of the first voltage, and the sample-and-hold circuit includes a switch and a capacitor.

56. The current-voltage circuit according to claim 55, further comprising an amplifier for receiving the second voltage and outputting a third voltage.

57. The current-voltage circuit according to claim 55, wherein the second voltage is supplied to the word line in the flash memory system.

58. The current-voltage circuit according to claim 56, wherein the second voltage is supplied to the word line in the flash memory system.

59. The current-voltage circuit according to claim 55, wherein the second voltage is supplied to a control gate line in a flash memory system.

60. The current-voltage circuit according to claim 56, wherein the second voltage is supplied to a control gate line in a flash memory system.

61. A current-voltage circuit, A reference circuit for receiving an input current and outputting a first voltage according to the input current, comprising an input current source, an NMOS transistor, a cascoding bias transistor, and a reference memory cell, An amplifier for receiving the first voltage and outputting a second voltage, A current-voltage circuit comprising: a sample-and-hold circuit for receiving the second voltage and outputting a third voltage, wherein the third voltage constitutes a sampled value of the second voltage.

62. The current-voltage circuit according to claim 61, wherein the third voltage is supplied to the word line in the flash memory system.

63. The current-voltage circuit according to claim 61, wherein the third voltage is supplied to a control gate line in a flash memory system.

64. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, A system equipped with redundant sectors.

65. The system according to claim 64, further comprising a non-volatile register for storing system information.

66. It is an analog neuromorphic memory system, A vector matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns, A system equipped with a non-volatile register for storing system information.

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