Semiconductor equipment

Abstract

To provide a semiconductor device that can reduce power consumption and has a small number of transistors. [Solution] One of the source and drain is electrically connected to the first wiring, and the source and drain The other end of the rain is electrically connected to the second wiring, and the first transistor is connected to the source and drain. One end of the input is electrically connected to the first wiring, and the gate is electrically connected to the gate of the first transistor. A second transistor is electrically connected, and one of its electrodes is electrically connected to a third wire. The other electrode is a capacitance electrically connected to the other source and drain of the second transistor. It has an element and

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a display device. [Background technology]

[0002] With the increasing size of display devices such as liquid crystal displays and EL displays, more value-added display devices are being developed. Development is underway. In particular, the driving circuit of the display device uses only single-conductivity transistors. Technological development to construct these components is actively underway (see Patent Document 1 and Non-Patent Document 1).

[0003] Figure 17(A) shows the drive circuit disclosed in Patent Document 1. (Driving circuit of Patent Document 1) This is due to transistors M1, M2, M3 and M4 It is configured as follows. When the signal IN is at a high level, transistor M1 is turned off. As a result, transistors M2, M3, and M4 turn on. The signal OUT becomes high level. On the other hand, when the signal IN is low level, the transistor When transistor M1 is turned on, transistors M2 and M4 are turned off, The Zista M3 turns on briefly, then turns off. The signal output then becomes low. .

[0004] Figure 17(B) shows the drive circuit disclosed in Non-Patent Document 1. The circuit is composed of transistors M11 to M19, and capacitive elements C11, etc. This is done. When the signal IN is at a high level, transistor M12 and transistor M 14. Transistors M16 and M17 are turned on, and transistor M11, Transistors M13 and M15 turn off, and transistors M18 and The M19 inverter turns on and then off. Then the signal OUT goes to a low level. Yes. On the other hand, when the signal IN is low level, transistor M12, transistor Transistors M14, M16, M17, and M18 are turned off. , transistors M11, M15 and M19 turn on, and transistor M1 3 turns on briefly, then turns off. Then, the signal OUT becomes high level. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2002-328643 [Non-patent literature]

[0006] [Non-Patent Document 1] Eri Fukumoto, Toshiaki Arai, Narihiro Morosawa, Kazuhiko Tokunaga, Yasuhiro Terai, Takashige Fujimori, and Tatsuya Sasaoka, "High Mobility Oxide Semiconductor TFT for Circuit Integration of AM-OLED," IDW'10, pp.631-634. [Overview of the project] [Problems that the invention aims to solve]

[0007] In the drive circuit of Patent Document 1, when the signal IN becomes high level, transistor M3 and Both the Zista M4 and the other device were turned on. Therefore, the period during which the signal IN was at a high level... In this case, since current continues to flow from the wiring to which the potential VDD is supplied, through the transistors M3 and M4 in sequence, to the wiring to which the potential VSS is supplied, the power consumption increases.

[0008] Also, in the drive circuit of Patent Document 1, during the period when the signal IN is at the high level, it is necessary to lower the potential of the gate of the transistor M1 to such an extent that the transistor M1 turns off. Therefore, it is necessary to make the W (W: channel width) / L (L: channel length) of the transistor M4 sufficiently larger than that of the transistor M3. However, this is not always easy. This is because when the W / L of the transistor M3 is increased, the W / L of the transistor M4 also needs to be increased, resulting in an increase in the layout area. Therefore, when the transistor M3 is turned on during the period when the signal IN is at the high level and the potential VDD is supplied to the gate of the transistor M1, the time until the potential of the gate of the transistor M1 reaches a predetermined potential has been long. As a result, the timing for the transistor M1 to turn on has been delayed, and the Vgs of the transistor M1 has become small, so that the rise time of the signal OUT has been long. Thus, delay or sag has occurred in the signal OUT.

[0009] Also, in the drive circuit of Non-Patent Document 1, as is clear even in comparison with the drive circuit of Patent Document 1, a large number of elements such as transistors and capacitor elements are required.

[0010] Therefore, in one aspect of the present invention, one of the problems is to suppress the current flowing between the wirings of the circuit through the transistor and reduce the power consumption of the circuit. Also, the rise of the output signal from the circuit ​​​​​​​​​​One of the problems is to shorten the delay time and suppress the delay or sag of the output signal. Another problem is to reduce the number of elements such as transistors and capacitive elements in the circuit. Another problem is to provide a new circuit configuration. Note that the problem and the effect are two sides of the same coin. When the effect is described in this specification or the like, it is obvious that there is a problem corresponding to the effect. Conversely, when the problem is described in this specification or the like, it is obvious that the effect corresponding to the problem is achieved. One of the problems is to reduce the number of elements such as transistors and capacitive elements in the circuit. Another problem is to provide a new circuit configuration. Note that the problem and the effect are two sides of the same coin. When the effect is described in this specification or the like, it is obvious that there is a problem corresponding to the effect. Conversely, when the problem is described in this specification or the like, it is obvious that the effect corresponding to the problem is achieved.

Means for Solving the Problem

Effect of the Invention

[0011] One aspect of the present invention suppresses the current flowing between the wirings of the circuit via the transistor, reducing the power consumption of the circuit. One aspect of the present invention includes a first transistor in which one of the source and the drain is electrically connected to the first wiring and the other of the source and the drain is electrically connected to the second wiring, and a second transistor in which one of the source and the drain is electrically connected to the first wiring and the gate is electrically connected to the gate of the first transistor, and a capacitive element in which one electrode is electrically connected to the third wiring and the other electrode is electrically connected to the other of the source and the drain of the second transistor. The semiconductor device is characterized by having these components. In one aspect of the present invention described above, the W / L (W is the channel width and L is the channel length) of the first transistor may be larger than the W / L of the second transistor. In one aspect of the present invention described above, the first transistor and the second transistor may have the same conductivity type. One aspect of the present invention suppresses the current flowing between the wirings of the circuit via the transistor, reducing the power consumption of the circuit. One aspect of the present invention includes a first transistor in which one of the source and the drain is electrically connected to the first wiring and the other of the source and the drain is electrically connected to the second wiring, and a second transistor in which one of the source and the drain is electrically connected to the first wiring and the gate is electrically connected to the gate of the first transistor, and a capacitive element in which one electrode is electrically connected to the third wiring and the other electrode is electrically connected to the other of the source and the drain of the second transistor. The semiconductor device is characterized by having these components.

[0012] In one aspect of the present invention described above, the W / L (W is the channel width and L is the channel length) of the first transistor may be larger than the W / L of the second transistor. In one aspect of the present invention described above, the first transistor and the second transistor may have the same conductivity type.

[0013] In one aspect of the present invention described above, the first transistor and the second transistor may have the same conductivity type. In one aspect of the present invention described above, the first transistor and the second transistor may have the same conductivity type.

Effect of the Invention

[0014] One aspect of the present invention suppresses the current flowing between the wirings of the circuit via the transistor, reducing the power consumption of the circuit. It can reduce power consumption. It can also shorten the rise time of the output signal from the circuit. This allows for the suppression of delay or distortion in the output signal. Furthermore, the transistors in the circuit... The number of elements such as transistors and capacitive elements can be reduced. [Brief explanation of the drawing]

[0015] [Figure 1] A diagram illustrating an inverter circuit according to one aspect of the present invention. [Figure 2] A diagram illustrating an inverter circuit according to one aspect of the present invention. [Figure 3] A diagram illustrating an inverter circuit according to one aspect of the present invention. [Figure 4] A diagram illustrating a circuit used in an inverter circuit according to one aspect of the present invention. [Figure 5] A diagram illustrating an inverter circuit according to one aspect of the present invention. [Figure 6] A diagram illustrating an inverter circuit according to one aspect of the present invention. [Figure 7] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 8] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 9] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 10] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 11] A diagram illustrating a shift register circuit according to one aspect of the present invention. [Figure 12] A diagram illustrating a display device according to one aspect of the present invention. [Figure 13] A diagram illustrating a transistor according to one aspect of the present invention. [Figure 14] A diagram illustrating a display device according to one aspect of the present invention. [Figure 15] A diagram illustrating an electronic device according to one aspect of the present invention. [Figure 16] A diagram illustrating a semiconductor device according to one aspect of the present invention. [Figure 17] A diagram illustrating a conventional drive circuit. [Modes for carrying out the invention]

[0016] An example of an embodiment illustrating the present invention will be described below with reference to the drawings. The contents of the embodiments may be modified without departing from the spirit and scope of the present invention. This will be easy for those skilled in the art. Therefore, the present invention is not limited to the embodiments described below. It will not be done.

[0017] (Embodiment 1) In this embodiment, an inverter circuit (semiconductor device or drive circuit) according to one aspect of the present invention is used. To explain (what is said).

[0018] The configuration of the inverter circuit in this embodiment will be described with reference to Figure 1(A).

[0019] The inverter circuit in Figure 1(A) has circuit 100 and circuit 200. Circuit 100 is It is connected to wiring 11, wiring 12, wiring 13, wiring 14, and circuit 200. 200 is connected to wiring 11, wiring 13, wiring 14, and circuit 100.

[0020] Circuit 100 has transistor 101 and transistor 102. The first terminal of 101 (also known as the source or drain) is connected to wiring 11, The second terminal of the converter 101 (also known as the source and drain) is connected to the wiring 12. The first terminal of transistor 102 is connected to wiring 13, and the second terminal of transistor 102 Terminal 2 is connected to wire 12, and the gate of transistor 102 is connected to wire 14.

[0021] Circuit 200 consists of transistor 201, transistor 202, transistor 203, It has a capacitive element 204 and the first terminal of transistor 201 is connected to the wiring 11. The gate of transistor 201 is connected to the gate of transistor 101. The first terminal of 202 is connected to wire 13, and the second terminal of transistor 202 is connected to The second terminal of transistor 201 is connected, and the gate of transistor 202 is connected to wire 14. The first terminal of transistor 203 is connected to wiring 13, and the second terminal of transistor 203 is connected to wiring 13. The terminal is connected to the gate of transistor 201, and the gate of transistor 203 is connected to wire 1. It is connected to 4. The first electrode (also called one electrode) of the capacitive element 204 is connected to the wiring 14. The second electrode (also called the other electrode) of the capacitive element 204 is connected to the second electrode of the transistor 201. It is connected to the terminal.

[0022] Furthermore, the gate of transistor 101, the gate of transistor 201, and transistor 203 The connection point with the second terminal of transistor 201 is indicated as node N1. The connection point between the second terminal of transistor 202 and the second electrode of capacitive element 204 is defined as a node. This is denoted as N2.

[0023] Furthermore, the transistors in the inverter circuit of this embodiment must have the same conductivity type. Preferred. For example, in the inverter circuit of Figure 1(A), transistor 101, transistor Transistors 102, 201, 202, and 203 are the same type. It is preferable that it be an electric type. In this embodiment, transistor 101, transistor 10 2. Transistors 201, 202, and 203 are of the N-channel type. Let me explain a particular situation.

[0024] In this specification, "connection" refers to an electrical connection, including current, voltage, potential, and signal. This corresponds to a state in which a signal or electric charge can be supplied or transmitted. Therefore, "connected" means In addition to being directly connected, for example, wiring, conductive films, resistors, diodes, and transistors This category also includes situations where connections are made indirectly through elements such as switching elements. .

[0025] The wiring 11 (also called the power line) is supplied with a potential VDD, and the wiring 11 transmits the potential VDD. It has the function of [doing something]. The potential VDD is a constant potential.

[0026] The wiring 13 (also called the power line) is supplied with the potential VSS, and the wiring 13 transmits the potential VSS. It has the function of [doing something]. The potential VSS is a constant potential, and is less than the potential VDD.

[0027] A signal IN is input to wiring 14 (also called a signal line), and wiring 14 is a device that transmits the signal IN. It has the ability. Signal IN is the input signal of the inverter circuit in Figure 1(A). Also, signal IN This refers to the conduction or non-conductivity of transistors 102, 202, and 203. It is a signal used for control.

[0028] A signal OUT is output from wiring 12 (also called the signal line), and wiring 12 transmits the signal OUT. It has the function of doing so. Signal OUT is the output signal of the inverter circuit in Figure 1(A).

[0029] Furthermore, wiring 11, wiring 13, and wiring 14 are not limited to the signals or potentials described above, but also include other Various signals or electrical potentials can also be input.

[0030] Circuit 100 (also called a buffer circuit) controls the power of wiring 11 according to the output signal of circuit 200. It has the function of supplying a VDD to wiring 12. In addition, circuit 100 distributes according to the signal IN It has the function of supplying the potential VSS of line 13 to wiring 12. Also, circuit 100 has the function of supplying the potential VSS of line 13 to wiring 12. In response to the output signal 0 and the signal IN, the potential VDD of wiring 11 and the potential VSS of wiring 13 One side has the function of supplying power to wiring 12.

[0031] Circuit 200 (also called a control circuit) responds to the signal IN by adjusting the potential V of the wiring 11 in circuit 100. A device that generates a signal (potential at node N1) that controls the timing of supplying DD to wiring 12. To have the ability.

[0032] Transistor 101 has the function of controlling the conduction or non-conductivity between wiring 11 and wiring 12. Furthermore, transistor 101 has the function of supplying the potential VDD of wiring 11 to wiring 12. Furthermore, transistor 101 has the function of maintaining the potential difference between wiring 12 and node N1.

[0033] Transistor 102 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 12. Furthermore, transistor 102 has the function of supplying the potential VSS of wiring 13 to wiring 12.

[0034] Transistor 201 has the function of controlling the conduction or non-conductivity between wiring 11 and node N2. Furthermore, transistor 201 has the function of supplying the potential VDD of wiring 11 to node N2. Furthermore, transistor 201 has the function of maintaining the potential difference between node N1 and node N2. do.

[0035] Transistor 202 has the function of controlling the conduction or non-conductivity between wiring 13 and node N2. Furthermore, transistor 202 has the function of supplying the potential VSS of wiring 13 to node N2. ru.

[0036] Transistor 203 has the function of controlling the conduction or non-conductivity between wiring 13 and node N1. Furthermore, transistor 203 has the function of supplying the potential VSS of wiring 13 to node N1. ru.

[0037] The capacitive element 204 has the function of maintaining the potential difference between the wiring 14 and node N2.

[0038] Next, an example of a method for driving the inverter circuit in Figure 1(A) will be explained with reference to Figure 1(B). To clarify, Figure 1(B) is a timeline for explaining the driving method of the inverter circuit in Figure 1(A). An example of a chart is shown.

[0039] Note that when the signal IN is at a high level, the potential is equal to potential VDD, and when it is at a low level, the potential is equal to potential VS. We will explain this assuming that it is a digital signal equal to S. Also, the signal IN is at a high level. I will explain this by dividing it into two cases: one where the signal IN is at a low level, and another where the signal IN is at a low level.

[0040] First, when the signal IN becomes high level, transistors 102 and 202... And transistor 203 turns on.

[0041] When transistor 203 is turned on, the potential VSS of wiring 13 is supplied to node N1. Therefore, the potential of node N1 drops to potential VSS. When the voltage drops, transistors 101 and 201 turn off.

[0042] Furthermore, when transistor 202 is turned on, the potential VSS of wiring 13 is supplied to node N2. Therefore, the potential of node N2 drops to potential VSS.

[0043] Furthermore, when transistor 102 is turned on, the potential VSS of wiring 13 is supplied to wiring 12. Therefore, the potential of wiring 12 drops to potential VSS. In other words, signal OUT is at a low level. It will become.

[0044] Next, when the signal IN becomes low level, transistors 102 and 202... And transistor 203 turns off.

[0045] When transistor 203 is turned off, node N1 becomes floating. Therefore, node N1 Because the potential remains at potential VSS, transistors 101 and 201 are It will remain as "Fu".

[0046] Furthermore, when transistor 202 is turned off, node N2 becomes floating. At this time, The quantitative element 204 has wiring 14 and node N2 during the period when the signal IN is at a high level. The potential difference is maintained. Therefore, as the signal IN becomes low level, the node The potential of N2 also decreases. The potential of node N2 is lower than the potential of node N1 (for example, potential VSS). When the potential drops below the threshold voltage of transistor 201, transistor 201 turns on. It will become.

[0047] When transistor 201 is turned on, the potential VDD of wiring 11 is supplied to node N2. Therefore, the potential at node N2 rises. At this time, the gate of transistor 201 and the second The power between node N1 and node N2 when transistor 202 is turned off is shown between the terminals. The potential difference is maintained. Therefore, as the potential of node N2 rises, the potential of node N1 also rises. It rises. The potential of node N2 rises to potential VDD, and the potential of node N1 rises to potential VDD. The potential becomes even higher. This is what is known as bootstrap operation. And the power of node N1 As the position rises, transistor 101 turns on.

[0048] When transistor 101 is turned on, the potential VDD of wiring 11 is supplied to wiring 12. Also, as mentioned above, the potential of node N1 will be higher than the potential VDD. Therefore, wiring 12 The potential rises to potential VDD. In other words, the signal OUT becomes high level.

[0049] As described above, the inverter circuit in Figure 1(A) consists of transistor 101 and transistor 1 There is no period when both 02 are turned on simultaneously. Also, transistor 201 and transistor There is no period when both 202 are turned on at the same time. Therefore, there is no current between wire 11 and wire 13. This eliminates the path through which the current continues to flow. Furthermore, it uses fewer transistors than conventional drive circuits. With this method, the high-level potential of the signal OUT can be raised to the potential VDD of wiring 11. Cut.

[0050] Furthermore, when the signal IN is at a low level, the power of the second terminal of transistor 201 As the position rises, the potential of the second terminal of transistor 101 also rises. Consequently, the potential of node N1 rises. Therefore, the potential of node N1 reaches a predetermined potential. Because the time it takes to reach the target can be shortened, the timing at which transistor 101 turns on This allows for faster aging. Also, it allows for a higher potential at node N1. This allows the Vgs of transistor 101 to be increased. (Inverter shown in Figure 1(A)) In this circuit, the timing at which transistor 101 turns on can be made earlier, The ability to increase the Vgs of transistor 101 has a synergistic effect, and the signal OU The rise time of T can be significantly reduced.

[0051] Next, an inverter circuit different from that in Figure 1(A) will be explained with reference to Figures 2 to 6. .

[0052] First, the inverter circuit in Figure 2(A) is the inverter circuit in Figure 1(A) with a 300A circuit added. It has a digit configuration.

[0053] The first terminal of circuit 300A (also called the input terminal) is connected to wiring 14, and the first terminal of circuit 300A is connected to wiring 14. The second terminal (also called the output terminal) is connected to the gate of transistor 203.

[0054] Circuit 300A outputs a signal corresponding to the signal input to the first terminal (e.g., signal IN) to the second terminal. It has the function of outputting from the child. Also, circuit 300A is more than the signal input to the first terminal. It has the function of outputting delayed and / or distorted signals from a second terminal.

[0055] For example, if the second signal is delayed compared to the first signal, then the first signal is delayed. The timing of the rise or fall of the second signal is more important than the timing of the rise or fall of the second signal. This refers to a delay in the timing of the rise or fall of a signal. It can also refer to, for example, a delay in the timing of the first signal. The second signal being "loosened" refers to the rise time or fall time of the first signal. This refers to a situation where the rise or fall time of the second signal is longer than that of the first signal.

[0056] In the inverter circuit shown in Figure 2(A), even when the signal IN changes from a high level to a low level, For a specified period, the signal output from the second terminal of circuit 300A will remain at a high level. When you switch, even if the signal IN changes from a high level to a low level, the transistor will remain active for a predetermined period of time. Terminal 203 remains on, and the potential VSS continues to be supplied to node N1.

[0057] Therefore, in the inverter circuit of Figure 2(A), the potential of node N2 is equal to the capacitance of the capacitive element 204. When the potential decreases due to quantitative coupling, the potential VSS of wiring 13 can be supplied to node N1. Therefore, the decrease in the potential of node N1 as the potential of node N2 decreases is suppressed. This is possible. In other words, it is possible to increase the potential difference between node N1 and node N2. It is possible. If the potential difference between node N1 and node N2 can be increased, the power of node N2 The potential of node N1 can be made higher when the position becomes potential VDD, and the transient The Vgs of TA101 can be made larger. Therefore, the rising edge time of signal OUT It can be shortened.

[0058] In the inverter circuit shown in Figure 2(A), the first electrode of the capacitive element 204 is connected to the circuit 300. It may also be connected to the second terminal of A.

[0059] Next, the inverter circuit in Figure 2(B) is created by adding circuit 300B to the inverter circuit in Figure 2(A). It has a digit configuration.

[0060] The first terminal of circuit 300B is connected to wiring 14, and the second terminal of circuit 300B is connected to a capacitive element It is connected to the first electrode of 204.

[0061] Circuit 300B has the same function as circuit 300A. However, the second terminal of circuit 300B The signal output from is delayed compared to the signal output from the second terminal of circuit 300A. It is preferable that it is not and / or not slurred.

[0062] In the inverter circuit in Figure 2(B), even when the signal IN changes from a high level to a low level, For a set period of time, the signals output from the second terminal of circuit 300A and the second terminal of circuit 300B The signal remains at a high level. In other words, the signal IN changes from a high level to a low level. However, transistor 203 remains on for a predetermined period, and the potential VSS at node N1 The supply will remain as is. Also, the signal input to the first electrode of the capacitive element 204 for a predetermined period of time The issue number will remain at a high level.

[0063] Subsequently, the signal output from the second terminal of circuit 300B changes from a high level to a low level. However, for a specified period, the signal output from circuit 300A will remain at a high level. When you change it, the signal output from the second terminal of circuit 300B changes from high level to low level. Even if this happens, transistor 203 remains on for a predetermined period, and potential VS is applied to node N1. S will remain supplied.

[0064] Therefore, in the inverter circuit of Figure 2(B), after transistor 202 is turned off... This allows the potential of the first electrode of the capacitive element 204 to be lowered. That is, node N2 can be confirmed After actually creating a floating state, the potential of node N2 is lowered by the capacitive coupling of the capacitive element 204. This is possible. Therefore, the potential of node N2 can be made lower. Also, Figure 2(A) Similar to the inverter circuit, the potential of node N2 is lowered by the capacitive coupling of the capacitive element 204. When this happens, the potential VSS of the wiring 13 can be supplied to node N1. Therefore, node N This method can suppress the decrease in the potential of node N1 that occurs when the potential of node 2 decreases.

[0065] Furthermore, in the inverter circuit shown in Figure 2(B), the potential of node N2 can be made even lower. The synergistic effect of this, and the ability to suppress the decrease in the potential of node N1, This allows the potential difference between node N1 and node N2 to be made larger. If the potential difference with node N2 can be increased, the potential of node N2 will become potential VDD. When this is done, the potential of node N1 can be made higher, and the Vgs of transistor 101 can be increased. It can be made larger. Therefore, the rise time of the signal OUT can be shortened. It is possible.

[0066] Next, the inverter circuit in Figure 3(A) is the inverter circuit in Figure 2(A) with circuit 300C added. It has a digit configuration.

[0067] The first terminal of circuit 300C is connected to wire 14, and the second terminal of circuit 300C is connected to circuit 30 It is connected to the first terminal of 0A and the first electrode of the capacitive element 204.

[0068] Circuit 300C has the same function as circuit 300A.

[0069] In the inverter circuit shown in Figure 3(A), even when the signal IN changes from a high level to a low level, For a set period of time, the signals output from the second terminal of circuit 300A and the second terminal of circuit 300C The signal remains at a high level. In other words, the signal IN changes from a high level to a low level. However, transistor 203 remains on for a predetermined period, and the potential VSS at node N1 The supply will remain as is. Also, the signal input to the first electrode of the capacitive element 204 for a predetermined period of time The issue number will remain at a high level.

[0070] Subsequently, the signal output from the second terminal of circuit 300C changes from a high level to a low level. However, for a specified period, the signal output from circuit 300A will remain at a high level. When you change it, the signal output from the second terminal of circuit 300C changes from high level to low level. Even if this happens, transistor 203 remains on for a predetermined period, and potential VS is applied to node N1. S will remain supplied.

[0071] Therefore, the inverter circuit in Figure 3(A) exhibits the same behavior as the inverter circuit in Figure 2(B). This allows for the operation to be performed. Therefore, it produces the same effect as the inverter circuit in Figure 2(B). It can perform.

[0072] Furthermore, in the inverter circuit shown in Figure 3(A), circuits 300A and 300C are connected in series. As a result, the signal output from the second terminal of circuit 300A is connected to circuit 300C. The signal output from the second terminal is delayed and / or distorted. This allows for a reduction in the circuit size of circuit 300A or a reduction in the size of the components.

[0073] Next, the inverter circuit in Figure 3(B) is the same as the inverter circuit in Figure 2(A) with transistor 10 The configuration is such that the gate of transistor 2 is connected to the gate of transistor 203.

[0074] In the inverter circuit shown in Figure 3(B), the gate of transistor 102 bypasses circuit 300A. Compared to when it is connected to wiring 14, the timing at which transistor 102 turns on is delayed. Therefore, both transistor 101 and transistor 102 can be done simultaneously. The time it is on can be shortened. In other words, the through flow between wire 11 and wire 13 This allows for the suppression of current flow, thereby reducing power consumption.

[0075] Furthermore, similar to the inverter circuit in Figure 3(B), the above-mentioned (i) in Figure 2(B) or Figure 3(A) is also relevant. In the converter circuit as well, the gate of transistor 102 is connected to the gate of transistor 203. You may connect.

[0076] Here, specific configuration examples of circuits 300A, 300B, and 300C are shown in Figure 4. (A) to Figure 4(F) will be explained with reference. Figures 4(A) to 4(F) show a circuit of 300A, rotation Circuit 300 that can be used in path 300B and circuit 300C is shown.

[0077] The circuit 300 in Figure 4(A) has a resistive element 301.

[0078] One terminal of the resistor element 301 is connected to the first terminal of the circuit 300, and the other terminal of the resistor element 301 is connected to the first terminal of the circuit 300. The other terminal is connected to the second terminal of circuit 300.

[0079] The circuit 300 in Figure 4(B) is a configuration in which a capacitive element 302 is added to the circuit 300 in Figure 4(A). ru.

[0080] The first electrode of the capacitive element 302 is connected to the wiring 13, and the second electrode of the capacitive element 302 is connected to the circuit It connects to the second terminal of the 300.

[0081] The first electrode of the capacitive element 302 may be connected to the wiring 11 or wiring 14, etc.

[0082] Alternatively, the second electrode of the capacitive element 302 may be connected to the first terminal of the circuit 300.

[0083] The circuit 300 in Figure 4(C) has a transistor 303.

[0084] The first terminal of transistor 303 is connected to the first terminal of circuit 300, and transistor 3 The second terminal of 03 is connected to the second terminal of circuit 300, and the gate of transistor 303 is It is connected to wiring 11.

[0085] The circuit 300 in Figure 4(D) is the same as the circuit 300 in Figure 4(C) but with a transistor 304 added. That is the case.

[0086] The first terminal of transistor 304 is connected to the first terminal of circuit 300, and transistor 3 The second terminal of 04 is connected to the second terminal of circuit 300, and the gate of transistor 304 is It is connected to the first terminal of circuit 300.

[0087] In the circuit 300 of Figure 4(D), when the signal input to the first terminal is low level Transistor 303 turns on, and transistor 304 turns off. Meanwhile, the first terminal If the signal input to the child is high level, transistor 303 and transistor Both 304s will be turned on.

[0088] Therefore, in the circuit 300 of Figure 4(D), the signal input to the first terminal is at a low level. In some cases, the signal can be delayed and output from the second terminal. On the other hand, the first If the signal input to the terminal is high level, the second signal should be processed with as little delay as possible. It can output from the terminal.

[0089] Furthermore, in the circuit 300 described above, such as in Figures 4(A) and 4(B), the transistor 30 You may also include option 4.

[0090] The circuit 300 in Figure 4(E) is the same as the circuit 300 in Figure 4(C) but with the addition of a transistor 305. That is the case.

[0091] The first terminal of transistor 305 is connected to the wiring 11, and the second terminal of transistor 305 The child is connected to the second terminal of circuit 300, and the gate of transistor 305 is connected to the second terminal of circuit 300. It is connected to terminal 1.

[0092] In the circuit 300 shown in Figure 4(E), when the signal input to the first terminal is at a low level... Transistor 303 turns on, and transistor 305 turns off. Meanwhile, the first terminal If the signal input to the child is high level, transistor 303 and transistor Both 305s will be turned on.

[0093] Therefore, it is possible to achieve the same effect as circuit 300 in Figure 4(D).

[0094] Furthermore, in the circuit 300 described above, such as in Figures 4(A) and 4(B), the transistor 30 You may also include option 5.

[0095] The circuit 300 in Figure 4(F) is the same as the circuit 300 in Figure 4(C), but with transistor 306 and transistor This configuration includes a 307-series component.

[0096] The first terminal of transistor 306 is connected to the wiring 11, and the second terminal of transistor 306 The child is connected to the second terminal of circuit 300. The first terminal of transistor 307 is connected to circuit 30 The first terminal of transistor 0 is connected to the second terminal of transistor 307, and the second terminal of transistor 307 is connected to the gateway of transistor 306. The gate of transistor 307 is connected to the wire 11.

[0097] In the circuit 300 of Figure 4(F), when the signal input to the first terminal is low level Transistor 303 turns on, and transistor 306 turns off. Meanwhile, the first end If the signal input to the child is high level, transistor 303 and transistor Both 306s turn on, especially when the signal input to the first terminal is high level. Due to the bootstrap operation, the gate potential of transistor 306 is lowered to potential VDD. The potential becomes even higher.

[0098] Therefore, in addition to the same effect as circuit 300 in Figure 4(D), the output from the second terminal is also The high-level potential of the signal can be defined as potential VDD. Furthermore, circuit 3 in Figure 4(D) The signal delay is reduced when the signal input to the first terminal is at a higher level than 00. It is possible.

[0099] Note that when circuit 300 in Figure 4(F) is used in the inverter circuit in Figure 2(A), the capacitive element 2 The first electrode of 04 may be connected to the gate of transistor 306. Transistor 306 The difference between the minimum and maximum potential of the gate is greater than the amplitude voltage of the signal IN, therefore, the node This allows us to further lower the potential of N2.

[0100] Furthermore, in the circuit 300 described above, such as in Figures 4(A) and 4(B), the transistor 30 6 and transistor 307 may also be provided.

[0101] Note that the transistors in circuit 300 (for example, transistor 304, transistor 30 5. Transistors 306 and 307) have the same conductivity type as transistor 101. It is preferable that this be the case.

[0102] Note that circuits 300A, 300B, and 300C do not need to have the same configuration. You can apply any of Figures 4(A) to 4(F) as appropriate.

[0103] Note that the inverter circuit in Figure 5(A) is the same as the inverter circuit in Figure 2(A), but with circuit 30 This is an example configuration when circuit 300 in Figure 4(D) is applied to 0A.

[0104] Note that the inverter circuit in Figure 5(B) is the same as the inverter circuit in Figure 2(A), but with circuit 30 This is an example configuration when circuit 300 in Figure 4(F) is applied to 0A.

[0105] Next, the inverter circuit in Figure 6(A) is the same as the inverter circuit in Figure 1(A) but with transistor 20 The configuration includes a 5-point section.

[0106] The first terminal of transistor 205 is connected to the second terminal of transistor 203, The second terminal of transistor 205 is connected to the gate of transistor 101 and the gate of transistor 201. The gate of transistor 205 is connected to wiring 11.

[0107] Transistor 205 is connected to the gate of transistor 101 and the gate of transistor 201. It has the function of controlling the conduction or non-conductivity between the second terminal of transistor 203 and the other terminal.

[0108] In the inverter circuit shown in Figure 6(A), during the period when the signal IN is at a low level, the transient The potential of the second terminal of transistor 203 is equal to the potential of the gate of transistor 205 (potential VDD). When the potential rises to the level obtained by subtracting the threshold voltage of transistor 205, transistor 205 This turns it off. Therefore, the potential of the second terminal of transistor 203 can be lowered. Therefore, the degradation and / or destruction of transistor 203 can be suppressed.

[0109] Note that, similar to the inverter circuit in Figure 6(A), Figures 2(A), 2(B), 3(A), and 3(A) are also shown. In the inverter circuits described above, such as 3(B), Figure 5(A), and Figure 5(B), the transient You may also provide a st205.

[0110] Next, the inverter circuit in Figure 6(B) is the same as the inverter circuit in Figure 1(A), with wiring 11 The configuration also involves dividing the wiring 13 into multiple wires.

[0111] Wiring 11 is divided into wiring 11A and wiring 11B, and the first terminal of transistor 101 is connected It is connected to wire 11A, and the first terminal of transistor 201 is connected to wire 11B. The wiring 13 is divided into wiring 13A, wiring 13B and wiring 13C, and the transistor 102 The first terminal is connected to wiring 13A, and the first terminal of transistor 202 is connected to wiring 13B. The first terminal of transistor 203 is connected to wire 13C.

[0112] In the inverter circuit in Figure 6(B), the potential VDD is supplied to wiring 11A and wiring 11B. If the potential VSS is supplied to wiring 13A, wiring 13B, and wiring 13C, the result will be the same as in Figure 1(A). This operation can be performed by supplying different potentials to wiring 11A and wiring 11B. Alternatively, different potentials may be supplied to wiring 13A, wiring 13B, and wiring 13C.

[0113] Alternatively, only one of the wires, wire 11 or wire 13, may be divided into multiple wires.

[0114] Furthermore, when dividing wiring 13 into multiple wirings, wiring 13C may be omitted, and the transistor The first terminal of TA203 may be connected to wiring 13A or wiring 13B. Alternatively, wiring 13 Even if A is omitted and the first terminal of transistor 102 is connected to wire 13B or wire 13C, good.

[0115] Note that, similar to the inverter circuit in Figure 6(B), Figures 2(A), 2(B), 3(A), and 3(A) are also shown. In the inverter circuits described above, such as 3(B), Figure 5(A), Figure 5(B), and Figure 6(A) Alternatively, wiring 11 and / or wiring 13 may be divided into multiple wirings.

[0116] Although not shown in the diagrams, see Figures 1(A), 2(A), 2(B), 3(A), and 3(B). In the inverter circuits described above, such as in Figures 5(A), 5(B), 6(A), and 6(B), The first electrode is connected to the second terminal of transistor 101, and the second electrode is connected to the transistor A capacitive element connected to the gate of sta 101 may be provided.

[0117] Although not shown in the diagrams, see Figures 1(A), 2(A), 2(B), 3(A), and 3(B). In the inverter circuits described above, such as in Figures 5(A), 5(B), 6(A), and 6(B), The first electrode is connected to the second terminal of transistor 201, and the second electrode is connected to the transistor A capacitive element connected to the gate of sta201 may be provided.

[0118] Note that the load driven by transistor 101 (for example, the load connected to wiring 12) is The load (for example, a load) driven by transistors 201, 202, and 203 It is greater than the load connected to node N1 or node N2. Also, transistor 101 The larger the W / L ratio, the shorter the rise time of the signal OUT. Therefore, The W / L of transistor 101 is the W / L of transistor 201, and the W / L of transistor 202. It is preferable that L is greater than the W / L of transistor 203.

[0119] Similarly, the load driven by transistor 102 (for example, the load connected to wiring 12) is Larger than the load that drives transistors 201, 202 and 203 Also, the larger the W / L of transistor 102, the longer the fall time of the signal OUT. It can be shortened. Therefore, the W / L of transistor 102 is the same as that of transistor 201. The W / L must be greater than the W / L of transistor 202 and the W / L of transistor 203. It is preferable.

[0120] Also, when transistor 101 is turned on, Vgs is when transistor 102 is turned on. It is often smaller than Vgs at that time. Therefore, the W / L of transistor 101 is It is preferable that the W / L of transistor 102 is larger. In other words, transistor 101 is In the inverter circuit of this embodiment, it is preferable that the transistor with the largest W / L ratio is the one that is most suitable. It's nice.

[0121] Note that the low-level potential of signal IN is determined by transistors 102, 202 and If the potential is such that the transistor 203 turns off, the inverter circuit of this embodiment is positive. It is always in operation. Therefore, the low-level potential of signal IN is set to a potential lower than the potential VSS. This is also fine. In this way, transistors 201, 202 and 203 When it turns off, Vgs can be a negative voltage. Therefore, transistor 201 , when transistors 202 and 203 are normally on, or The electrical current between the gate and source of transistor 201, transistor 202, and transistor 203 Even when the drain current is large when the voltage difference is 0[V], it will operate normally. It is possible.

[0122] Furthermore, the high-level potential of signal IN is determined by transistors 102, 202 and transistor If the potential is such that inverter 203 turns on, the inverter circuit of this embodiment is functioning normally. It operates in this way. Therefore, even if the high-level potential of signal IN is lower than the potential VDD Good. This way, the drive voltage of the circuit that outputs a signal to wiring 14 can be reduced. Furthermore, in the inverter circuit of this embodiment, the high-level potential of signal IN is potential VDD. Even at lower potentials, the high-level potential of the signal OUT can be used as the potential VDD. ru.

[0123] The signal IN is transmitted by transistors 102, 202, and 203. The potential at which it turns off, and transistors 102, 202 and 203 As long as it has an ON potential, it is not limited to digital signals. For example, signal IN is It may have three or more potentials, and it may also be an analog signal.

[0124] If a signal such as a clock signal is input to wiring 11, then if the signal IN is at a low level... The signal from wiring 11 can be output to wiring 12. In particular, the inverter circuit in Figure 6(B) When dividing wiring 11 into wiring 11A and wiring 11B, as in the case of a road, wiring 11A is It is preferable to input a signal such as a lock signal and supply a potential VDD to the wiring 11B. This allows the potential of node N1 to be raised, making it easier for transistor 101 to turn on. The signal from wiring 11A can be stably output to wiring 12.

[0125] Furthermore, transistors 102, 202, and 203 are connected to wiring 13. During the ON period (for example, the period when the signal IN is at a high level), the signal becomes low. If you input the number, the inverter circuit of this embodiment will operate normally. Also, in wiring 13, The period during which transistors 102, 202, and 203 are turned off (example) For example, a signal that is at a high level for all or part of the period during which the signal IN is at a low level. If input is given, transistors 102, 202, and 203 will be negatively affected. As can be applied. Therefore, transistor 102, transistor 202 and This can mitigate the deterioration of the Rangista 203.

[0126] Herein, one aspect of the present invention includes the following configuration.

[0127] One aspect of the present invention comprises a transistor 101, a transistor 201, a capacitive element 204, This is a semiconductor device having the following: The first terminal of transistor 101 is connected to wiring 11, The second terminal of transistor 101 is connected to wire 12. The first terminal of transistor 201 The child is connected to wiring 11, and the gate of transistor 201 is connected to the gate of transistor 101. The first electrode of the capacitive element 204 is connected to the wiring 14, and the second electrode of the capacitive element 204 is connected to the wiring 14. The electrode is connected to the second terminal of transistor 201 (see Figure 16(A)).

[0128] In addition, in the above embodiment of the present invention, as the potential of the wiring 14 decreases, the transistor 20 The potential at the second terminal of transistor 1 decreases. Also, the potential at the second terminal of transistor 201 decreases. As a result, transistor 201 turns on, and the potential of wiring 11 changes. It is supplied to the second terminal of transistor 201, and the potential of the second terminal of transistor 201 rises. See Figure 16(B). Also, as the potential of the second terminal of transistor 201 increases, The gate potential of transistor 201 rises. As the voltage rises, transistor 101 turns on, and the potential of wiring 11 increases The current is supplied to wiring 12, causing the potential of wiring 12 to rise (see Figure 16(C)).

[0129] This embodiment can be implemented in appropriate combination with other embodiments.

[0130] (Embodiment 2) In this embodiment, a shift register circuit (semiconductor device or drive circuit) according to one aspect of the present invention is used. This explains (also known as).

[0131] The shift register circuit of this embodiment consists of multiple flip-flop circuits (semiconductor devices or drive circuits). It has (also called a circuit). So, first I will explain the flip-flop circuit, and then the This section describes a shift register circuit that includes a lip-flop circuit.

[0132] Figure 7(A) shows the flip-flop circuit in the shift register circuit of this embodiment. See the explanation below.

[0133] The flip-flop circuit in Figure 7(A) consists of transistor 401, transistor 402, and It has transistor 403, transistor 404, transistor 405, and circuit 500. The first terminal of transistor 401 is connected to the wiring 21, and the second terminal of transistor 401 is connected to the wiring 21. The child is connected to wiring 22. The first terminal of transistor 402 is connected to wiring 13, The second terminal of transistor 402 is connected to wiring 22. The first terminal of transistor 403 The child is connected to wire 13, and the second terminal of transistor 403 is connected to the gateway of transistor 401. The first terminal of transistor 404 is connected to wiring 23, and the transistor The second terminal of 404 is connected to the gate of transistor 401, and the gate of transistor 404 The terminal is connected to wire 23. The first terminal of transistor 405 is connected to wire 13. The second terminal of transistor 405 is connected to the gate of transistor 401, and the transistor The gate of terminal 405 is connected to wiring 24. The first terminal of circuit 500 (also called the input terminal) ) is connected to the gate of transistor 401, and the second terminal of circuit 500 (also known as the output terminal) (u) is connected to the gate of transistor 402 and the gate of transistor 403.

[0134] Furthermore, the inverter circuit of Embodiment 1 can be used as circuit 500. The first terminal of 500 corresponds to the wiring 14 of the inverter circuit of Embodiment 1, and the circuit 500 The second terminal corresponds to the wiring 12 of the inverter circuit in Embodiment 1.

[0135] Note that the gate of transistor 401, the second terminal of transistor 403, and transistor 4 Connection between the second terminal of 04, the second terminal of transistor 405, and the first terminal of circuit 500. The location is indicated as node N3. Also, the gate of transistor 402 and the gate of transistor 403 The connection point between the terminal and the second terminal of circuit 500 is indicated as node N4.

[0136] Furthermore, the transistors in the flip-flop circuit of this embodiment have the same conductivity type. This is preferable. For example, in the flip-flop circuit of Figure 7(A), transistor 401 , transistor 402, transistor 403, transistor 404 and transistor 40 It is preferable that the transistors in 5 and circuit 500 have the same conductivity type.

[0137] The signal CK is input to wiring 21 (also called the signal line), and wiring 21 is a device that transmits the signal CK. It has the ability. The signal CK is a clock signal that alternates between high and low levels.

[0138] The signal SOUT is output from wiring 22 (also called the signal line), and wiring 22 is connected to signal SOUT. It has the function of transmitting signals. The signal SOUT is the output signal of the flip-flop circuit in Figure 7(A). That is the case.

[0139] A signal SP is input to wiring 23 (also called a signal line), and wiring 23 is a device that transmits the signal SP. It has the capability. Signal SP is the input signal to the flip-flop circuit in Figure 7(A).

[0140] The signal RE is input to wiring 24 (also called the signal line), and wiring 24 is a device that transmits the signal RE. It has the ability. Signal RE is the input signal to the flip-flop circuit in Figure 7(A).

[0141] Note that wiring 21, wiring 23, and wiring 24 are not limited to the signals or potentials mentioned above, but also include other Various signals or electrical potentials can also be input.

[0142] Transistor 401 has the function of controlling the conduction or non-conductivity between wiring 21 and wiring 22. Furthermore, transistor 401 has the function of supplying the signal CK from wiring 21 to wiring 22. Furthermore, transistor 401 has the function of maintaining the potential difference between wiring 22 and node N3.

[0143] Transistor 402 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 22. Furthermore, transistor 402 has the function of supplying the potential VSS of wiring 13 to wiring 22.

[0144] Transistor 403 has the function of controlling the conduction or non-conductivity between wiring 13 and node N3. Furthermore, transistor 403 has the function of supplying the potential VSS of wiring 13 to node N3. ru.

[0145] Transistor 404 has the function of controlling the conduction or non-conductivity between wiring 23 and node N3. Furthermore, transistor 404 has the function of supplying the signal SP from wiring 23 to node N3. .

[0146] Transistor 405 has the function of controlling the conduction or non-conductivity between wiring 13 and node N3. Furthermore, transistor 405 has the function of supplying the potential VSS to node N3.

[0147] Next, refer to Figure 7(B) for an example of how to drive the flip-flop circuit shown in Figure 7(A). Let's explain. Figure 7(B) illustrates the method of driving the flip-flop circuit in Figure 7(A). Here is an example of a timing chart for this purpose.

[0148] Furthermore, when signals CK, SP, and RE are at a high level, their potential is equal to potential VDD, and low It will be described as a digital signal whose level potential is equal to the potential VSS. Also, it will be described by dividing it into a period Ta, period Tb, period Tc, and period Td.

[0149] During period Ta, the signal SP becomes high level, the signal RE becomes low level, and the signal C K becomes low level. Therefore, the transistor 404 turns on and the transistor 405 turns off.

[0150] When the transistor 404 turns on, the signal SP on the wiring 23 is supplied to the node N3. Since the signal SP is at high level, the potential of the node N3 rises. When the potential of the node N3 rises the output signal of the circuit 500 becomes low level. Therefore, the transistors 402 and t ransistor 403 turn off. Also, when the potential of the node N3 rises, the transistor 4 01 turns on.

[0151] When the transistor 401 turns on, the signal CK on the wiring 21 is supplied to the wiring 22. Since the signal CK is at low level, the potential of the wiring 22 becomes the potential VSS. That is, the signal SO UT becomes low level.

[0152] Note that when the potential of the node N3 rises to the potential obtained by subtracting the threshold voltage of the transistor 404 from the potential (potential VDD) of the gate of the transistor 404, the transistor 404 turns off . Therefore, the node N3 becomes a floating state.

[0153] Next, during period Tb, the signal SP becomes low level, the signal RE remains low level, and the signal CK becomes high level. Therefore, the transistors 404 and transistor 40 5 remain off. Also, the output signal of the circuit 500 remains at low level. Therefore Transistors 402 and 403 remain off.

[0154] Transistors 403, 404, and 405 remain off. Therefore, node N3 remains in a floating state. Consequently, the potential of node N3 remains high. Therefore, transistor 401 remains on.

[0155] Since transistor 401 remains ON, the signal CK from wiring 21 is supplied to wiring 22. It remains as is. Because the signal CK is at a high level, the potential of wiring 22 begins to rise. At that time, between the gate and the second terminal of transistor 401, node N3 in period Ta The potential difference between and wiring 22 is maintained. Therefore, as the potential of wiring 22 rises, The potential of N3 also rises. As a result, the potential of wiring 22 is equal to the potential of signal CK. It rises to level VDD. In other words, the signal SOUT becomes high level.

[0156] Next, during period Tc, signal SP remains at a low level, and signal RE is at a high level. As a result, the signal CK becomes low level. Therefore, transistor 404 remains off. Transistor 405 turns on.

[0157] When transistor 405 is turned on, the potential VSS of wiring 13 is supplied to node N3. Therefore, the potential of node N3 drops to potential VSS. Consequently, transistor 401 turns off. This results in the output signal of circuit 500 becoming high level, and transistor 402 and the transistor... The 403 generator is turned on.

[0158] When transistor 402 is turned on, the potential VSS of wire 13 is supplied to wire 22. Then, the potential of the wiring 22 drops to the potential VSS. That is, the signal SOUT becomes a low level.

[0159] Next, in the period Td, the signal SP remains at the low level, the signal RE becomes the low level, and the signal CK repeats between the low level and the high level. Therefore, the transistor 404 remains off, and the transistor 405 turns off. Also, the output signal of the circuit 500 remains at the high level. Therefore, the transistors 402 and 403 remain on.

[0160] When the transistor 403 remains on, the potential VSS of the wiring 13 is continuously supplied to the node N3. Therefore, since the potential of the node N3 is maintained at the potential VSS, the transistor 401 remains off.

[0161] Also, when the transistor 402 remains on, the potential VSS of the wiring 13 is continuously supplied to the wiring 22. Therefore, the potential of the wiring 22 remains at the potential VSS. That is, the signal SOUT remains at the low level.

[0162] As described above, the flip - flop circuit in Fig. 7(A) has the inverter circuit of Embodiment 1, and thus can achieve the same effects as the inverter circuit of Embodiment 1.

[0163] Next, a flip - flop circuit different from Fig. 7(A) will be described with reference to Figs. 8 and 9. Note that the parts different from Fig. 7(A) will be described.

[0164] First, the flip - flop circuit in Fig. 8(A) is obtained by adding a tra ​​​​This configuration includes a 406 inverter.

[0165] The first terminal of transistor 406 is connected to wire 13, and the second terminal of transistor 406 is connected to wire 13. The child is connected to wire 22, and the gate of transistor 406 is connected to wire 25.

[0166] The signal CKB is input to wiring 25 (also called the signal line), and wiring 25 transmits the signal CKB. It has the function of being an inverted signal of signal CK or a signal that is out of phase with signal CK. be.

[0167] Transistor 406 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 22. Furthermore, transistor 406 has the function of supplying the potential VSS of wiring 13 to wiring 22. ru.

[0168] In the flip-flop circuit shown in Figure 8(A), during period Td, the signal CKB is at a high level. Each time this happens, transistor 406 turns on. Therefore, during period Td, the signal CKB is Each time the level increases, the potential VSS of wiring 13 is supplied to wiring 22.

[0169] In particular, when signal CKB is the inverted signal of signal CK, in periods Ta and Tc The signal CKB becomes high level, and transistor 406 turns on. Therefore, the period Tc In this configuration, the potential VSS of the wiring 13 is transmitted through both transistor 402 and transistor 406. Since it is supplied to wiring 22, the falling edge time of signal SOUT can be shortened. .

[0170] Furthermore, if the flip-flop circuit has transistor 406, then in period Td, The potential of wiring 22 can be maintained at potential VSS. Therefore, transistor 402 can be omitted. It may be omitted. Omitting transistor 402 reduces the number of transistors and the layout. This allows for a reduction in area, etc.

[0171] Next, the flip-flop circuit in Figure 8(B) is connected to the flip-flop circuit in Figure 7(A). This configuration includes a 407 radiator.

[0172] The first terminal of transistor 407 is connected to wire 13, and the second terminal of transistor 407 is connected to wire 13. The child is connected to wire 22, and the gate of transistor 407 is connected to wire 24.

[0173] Transistor 407 has the function of controlling the conduction or non-conductivity between wiring 13 and wiring 22. Furthermore, transistor 407 has the function of supplying the potential VSS of wiring 13 to wiring 22. .

[0174] In the flip-flop circuit shown in Figure 8(B), during periods Ta, Tb, and Td, Transistor 407 turns off. Also, during period Tc, transistor 407 turns on. Yes. During period Tc, when transistor 407 is turned on, the potential VSS of wiring 13 is It is supplied to wiring 22.

[0175] Therefore, during period Tc, the potential VSS of wiring 13 is such that transistor 402 and transistor Since it is supplied to wiring 22 via both sides of the zista 407, the falling edge time of the signal SOUT It can be shortened.

[0176] Furthermore, similar to the flip-flop circuit in Figure 8(B), the flip-flops described above in Figure 8(A), etc. In the lop circuit, transistor 407 may also be provided.

[0177] Next, the flip-flop circuit in Figure 9(A) is connected to the flip-flop circuit in Figure 7(A). This configuration includes a 408 radiator.

[0178] The first terminal of transistor 408 is connected to wire 11, and the second terminal of transistor 408 is connected to wire 11. The child is connected to node N4, and the gate of transistor 408 is connected to wire 24.

[0179] Transistor 408 has the function of controlling the conduction or non-conductivity between wiring 11 and node N4. Furthermore, transistor 408 has the function of supplying the potential VDD of wiring 11 to node N4. To possess.

[0180] In the flip-flop circuit shown in Figure 9(A), during periods Ta, Tb, and Td, Transistor 408 turns off. Also, during period Tc, transistor 408 turns on. During period Tc, when transistor 408 turns on, the potential VDD of wiring 11 becomes It is supplied to node N4.

[0181] Therefore, the time it takes for the potential of node N4 to reach a predetermined value can be shortened. Therefore, the timing at which transistors 402 and 403 turn on is made earlier. This is possible. As a result, the timing at which the potential VSS of wiring 13 is supplied to wiring 22 is also accelerated. Therefore, the falling edge time of the SOUT signal can be shortened.

[0182] Furthermore, similar to the flip-flop circuit in Figure 9(A), the aforementioned components are shown in Figures 8(A) and 8(B), etc. In the flip-flop circuit described above, transistor 408 may also be provided.

[0183] Furthermore, if the flip-flop circuit has transistor 408, then in period Tc, Transistors 402 and 403 turn on. Therefore, transistor 405 It may be omitted. Omitting transistor 405 reduces the number of transistors, and also reduces the number of rays. This allows for a reduction in the area of ​​play outside the court.

[0184] Note that transistor 408 is used in the flip-flop circuit in Figure 8(A), and the transistor The first terminal of transistor 408 may be connected to wiring 25. Even when connected to wiring 25, during period Tc, the signal CKB of wiring 25 will be at a high level. Therefore, transistor 408 turns on and can operate as described above.

[0185] Next, the flip-flop circuit in Figure 9(B) is connected to the flip-flop circuit in Figure 7(A). This configuration includes a 409 inverter.

[0186] The first terminal of transistor 409 is connected to the wiring 21, and the second terminal of transistor 409 is connected to the wiring 21. The child is connected to wiring 26, and the gate of transistor 409 is connected to node N3.

[0187] In the flip-flop circuit shown in Figure 9(B), the signal output from wiring 22 is the signal SO UTa is indicated, and the signal output from wiring 26 is indicated as signal SOUTb. Signal SOUTb is This is the output signal of the flip-flop circuit. Also, wiring 26 (also called the signal line) is signal SO It has the function of transmitting UTb.

[0188] Transistor 409 has the same function as transistor 401, for example, transistor 40 9 has the function of controlling the continuity or non-continuity between wiring 21 and wiring 26.

[0189] In the flip-flop circuit shown in Figure 9(B), the signal SOU is a signal similar to the signal SOUTa. Tb can be generated. Therefore, for example, the signal SOUTa is connected to wiring 22. The signal SOUTb is used as a signal to drive the load and is connected to another stage with wiring 26. It can be used as a signal to drive the flip-flop circuit.

[0190] Note that, similar to the flip-flop circuit in Figure 9(B), Figures 8(A), 8(B), and 9( In the flip-flop circuits described above, such as A), transistor 409 may also be provided. .

[0191] Although not shown in the illustrations, see Figures 7(A), 8(A), 8(B), 9(A), and 9(B) In the above-mentioned flip-flop circuits, such as the one described above, the first terminal of transistor 404 is wired 11 or wiring 25 may be connected. In this case, during period Ta, node N3 is connected to wiring Because the potential or signal etc. of 11 or wiring 25 is supplied, the signal SP is supplied to wiring 23. This can reduce the load on the road.

[0192] Although not shown in the illustrations, see Figures 7(A), 8(A), 8(B), 9(A), and 9(B) In the flip-flop circuits described above, such as the one shown above, one electrode is connected to the wiring 22, and the other electrode is connected to the wiring 22. A capacitive element may be provided in which the electrodes are connected to node N3. The capacitive element is flip-flop If installed in the circuit, it increases the capacitance value between the gate and the second terminal of transistor 401. This makes it easier to perform bootstrapping.

[0193] Although not shown in the illustrations, see Figures 7(A), 8(A), 8(B), 9(A), and 9(B) In the flip-flop circuits described above, such as the one shown above, the first terminal is connected to the wiring 22, and the second terminal is connected to the wiring 22. Even if a transistor is provided in which the terminal is connected to node N3 and the gate is connected to wiring 21 Good. This way, during the period Td when the signal CK is at a high level, node N The potential VSS of 3 is supplied to the wiring 22, or the potential of the wiring 22 is supplied to node N3. Yes, it is possible. Therefore, either transistor 402 or transistor 403 may be omitted. If either transistor 402 or transistor 403 is omitted, the negative of circuit 500 Because the load is reduced, the W / L ratio of the transistor in circuit 500 can be reduced. ru.

[0194] Although not shown in the illustrations, see Figures 7(A), 8(A), 8(B), 9(A), and 9(B) In the flip-flop circuits described above, such as the one shown above, the first terminal is connected to the wiring 23, and the second terminal is connected to the wiring 23. Even if a transistor is provided in which the terminal is connected to node N3 and the gate is connected to wiring 25 Good. In this case, the potential of node N3 can be raised quickly during period Ta.

[0195] Although not shown in the illustrations, see Figures 7(A), 8(A), 8(B), 9(A), and 9(B) In the flip-flop circuits described above, such as the one shown above, the second terminal of transistor 404 and the transistor Without connecting the gate of transistor 401, the first terminal is connected to the second terminal of transistor 404. The second terminal is connected to the gate of transistor 401, and the gate is connected to wiring 11 A transistor may be newly provided that is connected to wiring 25. In this way, the transistor The electric current applied to transistor 404 and the transistor connected to the second terminal of transistor 404 Because the pressure can be reduced, it is possible to prevent transistor degradation or destruction. The first terminal of circuit 500 is the second terminal of transistor 404 or the transistor It should be connected to the gate of transistor 401. Also, the second terminal of transistor 405 is connected to the terminal It should be connected to the second terminal of transistor 404 or the gate of transistor 401.

[0196] Although not shown in the diagram, in the flip-flop circuit described above, such as Figure 9(B), the first The terminal is connected to wiring 13, the second terminal is connected to wiring 26, and the gate is node N4, A transistor connected to wire 24 or wiring 25 may be provided. In this way, wiring 13 Since the potential VSS can be supplied to the wiring 26, the potential of the wiring 26 can be maintained at the potential VSS. It becomes easier.

[0197] Next, a specific example using the inverter circuit of Embodiment 1 as circuit 500 will be described. .

[0198] The flip-flop circuit in Figure 10(A) is the same as the flip-flop circuit in Figure 7(A), Circuit 500 is configured using the inverter circuit shown in Figure 1(A).

[0199] The flip-flop circuit in Figure 10(B) is similar to the flip-flop circuit in Figure 10(A). The first terminal of transistor 101 and the first terminal of transistor 201 are connected to the wiring 21. It is a continuous structure.

[0200] In the flip-flop circuit shown in Figure 10(B), during periods Ta and Tb, the wiring 13 The potential VSS is supplied to node N4, and during periods Tc and Td, the signal C of wiring 21 K is supplied to node N4. During period Td, the signal CK from wiring 21 is supplied to node N4. If supplied, the potential of node N4 will alternate between potential VDD and potential VSS, and the trap will Transistors 402 and 403 repeatedly switch on and off. That is, during the period Td In this configuration, the potential VSS of wiring 13 is periodically supplied to wiring 22, and transistor 402 And the time that transistor 403 is on becomes shorter. Therefore, the potential of wiring 22 is set to potential V. To maintain SS and suppress the degradation of transistors 402 and 403. It is possible.

[0201] Note that, similar to the flip-flop circuit in Figure 10(B), Figures 8(A), 8(B), and 9( In the flip-flop circuit described above, as shown in A) and Figure 9(B), it is implemented as circuit 500. Even when using any of the inverter circuits in form 1, the first terminal of transistor 101 The child and the first terminal of transistor 201 may be connected to the wiring 21.

[0202] Next, the shift register circuit of this embodiment will be described with reference to Figure 11.

[0203] The shift register circuit in Figure 11 has N (where N is a natural number) flip-flop circuits 600. However, Figure 11 shows the first to third stage flip-flop circuits 600 (flip Flop circuit 600_1, flip-flop circuit 600_2, flip-flop circuit 60 Only 0_3) is shown.

[0204] In the shift register circuit of Figure 11, the flip-flop circuit 600 is the same as the flip-flop circuit in Figure 7(A). A lip-flop circuit is used. However, the flip-flop circuit 600 is... The flip-flop circuit is not limited to the one shown in Figure 7(A).

[0205] The shift register circuit in Figure 11 is connected to N wires 31, 32, 33 and 34. The i-th (where i is any one from 2 to N-1) stage flip-flop circuit 600 continues. Wiring 31 in the i-th row, Wiring 31 in the i-1th row, Wiring 31 in the i+1th row, Wiring 33 and Wiring 34 It is connected to one of the other. Also, wiring 22 is connected to the i-th stage wiring 31, and wiring 23 is i- Wiring 24 is connected to the first stage wiring 31, and wiring 21 is connected to the i+1 stage wiring 31. It is connected to wiring 33 or wiring 34.

[0206] In addition, in the i-th stage flip-flop circuit 600, when wiring 21 is connected to wiring 33 In addition, in the i-1 and i+1 stage flip-flop circuits 600, wiring 21 is connected to wiring 34. Connected.

[0207] Note that the first stage flip-flop circuit 600 is the same as the i-th stage flip-flop circuit 600. Although the connection is as described, the i-1 stage corresponds to the 600 flip-flop circuit in the first stage. Wire 31 does not exist. Therefore, in the first stage flip-flop circuit, wire 23 becomes wire 3 It connects to 2.

[0208] Furthermore, the Nth stage flip-flop circuit 600 is the same as the i-th stage flip-flop circuit 600. Although the connection is as shown, the Nth stage flip-flop circuit 600 has wiring 3 for the i+1 stage. 1 does not exist. Therefore, in the Nth stage flip-flop circuit 600, wire 24 becomes wire 3 It is connected to 2. However, in the Nth stage flip-flop circuit 600, wiring 24 is connected It may be connected to line 33 or wiring 34. Alternatively, a wiring to which a signal corresponding to signal RE is input may be connected. It may be connected to a wire.

[0209] From each of the N wires 31 (also called signal lines), signal SOUT_1 to signal SOUT_ N is output, and the N wires 31 have the function of transmitting signals SOUT_1 to SOUT_N. It has. For example, the signal SOUT_i is output from the i-th stage wiring 31, and the i-th stage wiring 31 has the function of transmitting the signal SOUT_i.

[0210] The signal SSP is input to wiring 32 (also called the signal line), and wiring 32 transmits the signal SSP. It has the function of [doing something]. Signal SSP is the start pulse of the shift register circuit in Figure 11.

[0211] The signal CK is input to wiring 33 (also called the signal line), and wiring 33 is a device that transmits the signal CK. To have the ability.

[0212] The signal CKB is input to wiring 34 (also called the signal line), and wiring 34 transmits the signal CKB. It has the function of [doing something].

[0213] Note that wiring 32, wiring 33, and wiring 34 are not limited to the signals or potentials mentioned above, but may also carry other signals. Various signals or potentials may also be input to it.

[0214] This embodiment can be implemented in appropriate combination with other embodiments.

[0215] (Embodiment 3) Taking an EL display device as an example, the cross-sectional structure of the pixels and driving circuit of a display device according to one aspect of the present invention The construction will be explained using Figure 12. Figure 12 shows a cross-sectional view of the pixel 840 and the drive circuit 841. This is given as an example.

[0216] Pixel 840 comprises a light-emitting element 832 and a transistor that has the function of supplying current to the light-emitting element 832. It has a zista 831. The pixel 840 has a light-emitting element 832 and a transistor 831. In addition, transistors that control the input of the image signal to pixel 840, and the potential of the image signal It may have various semiconductor elements, such as capacitive elements for holding data.

[0217] The drive circuit 841 includes transistor 830 and holds the gate voltage of transistor 830. It has a capacitive element 833 for this purpose. The drive circuit 841 is the inverter circuit of Embodiment 1. This corresponds to the flip-flop circuit or shift register circuit, etc. of Embodiment 2. Specifically, Transistor 830 is either transistor 101 of Embodiment 1 or transistor 2 of Embodiment 2. This corresponds to transistor 401, etc. The drive circuit 841 consists of transistor 830 and a capacitive element. In addition to child 833, it may also have various semiconductor elements such as transistors and capacitive elements. .

[0218] Transistor 831 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and at a position overlapping with the conductive film 816 A semiconductor film 817 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 815 and 818 located on the semiconductor film 817. The film 816 also functions as a scan line.

[0219] The transistor 830 has a conductive film that functions as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and at a position overlapping with the conductive film 812 A semiconductor film 813 located on the gate insulating film 802, and a source terminal or drain terminal It functions and has conductive films 814 and 819 located on the semiconductor film 813.

[0220] Capacitive element 833 is provided on a substrate 800 having an insulating surface, with a conductive film 812 and on the conductive film 812 The gate insulating film 802 and the conductive film 812 overlap at a position on the gate insulating film 802 It has a conductive film 819 placed on top.

[0221] Furthermore, insulating film 820 is applied to conductive film 814, conductive film 815, conductive film 818, and conductive film 819. The insulating film 821 is arranged to be stacked in order. A conductive film 822 that functions as an anode is provided. The conductive film 822 is an insulating film 820 and connected to the conductive film 818 via contact holes 823 formed in the insulating film 821. It is being done.

[0222] Furthermore, an insulating film 824 having an opening that exposes a portion of the conductive film 822, 1 is provided on. On a part of the conductive film 822 and on the insulating film 824, there is an EL layer 825, A conductive film 826, which functions as a cathode, is arranged in a stacked manner. The region where 2, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. ru.

[0223] In one aspect of the present invention, transistors 830 and 831 are amorphous, micro Semiconductors such as silicon or germanium, which are crystalline, polycrystalline, or single crystals, are used in semiconductor films. It is fine if they are included, and wide-bandgap semiconductors such as oxide semiconductors are used in semiconductor films. It's okay to be there.

[0224] The semiconductor film of transistors 830 and 831 is amorphous, microcrystalline, polycrystalline or When a single crystal semiconductor such as silicon or germanium is used, a single conductive material is added. The impurity elements are added to the semiconductor film to function as source or drain terminals. This forms an impurity region. For example, by adding phosphorus or arsenic to the semiconductor film, An impurity region having n-type conductivity can be formed. Also, for example, boron can be used as described above. By adding it to a semiconductor film, it is possible to form an impurity region with p-type conductivity.

[0225] In cases where oxide semiconductors are used in the semiconductor films of transistors 830 and 831 In addition, a dopant is added to the above semiconductor film to function as a source terminal or drain terminal. An impurity region may be formed. Dopant addition can be performed using ion implantation. Dopants are, for example, noble gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, Group 15 elements such as arsenic and antimony can be used. For example, nitrogen can be used as dopan. When used as a toner, the concentration of nitrogen atoms in the impurity region is 5 × 10⁻⁶. 19 / cm 3 The above 1× 10 22 / cm 3 The following is preferable:

[0226] Furthermore, silicon semiconductors are produced using vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon produced by the annealing method, amorphous silicon subjected to treatments such as laser annealing After injecting hydrogen ions, etc., into polycrystalline silicon or single-crystal silicon wafers that have been crystallized Single-crystal silicon with the surface layer removed can be used.

[0227] The oxide semiconductor film must be at least one or more selected from In, Ga, Sn, and Zn. It contains elements. For example, the In-Sn-Ga-Zn-O system oxide, which is an oxide of a quaternary metal. Monocrystalline semiconductors, and oxide semiconductors such as In-Ga-Zn-O, which are oxides of ternary metals, and In-S n-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors, Sn-Ga-Zn -O-based oxide semiconductors, Al-Ga-Zn-O-based oxide semiconductors, Sn-Al-Zn-O-based acids Iridescent semiconductors, and binary metal oxides such as In-Zn-O oxide semiconductors, Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, and In-Ga-O-based oxide semiconductors. Monocrystalline semiconductors, in-O oxide semiconductors and Sn-O oxide semiconductors, which are oxides of monocrystalline metals. Zn-O-based oxide semiconductors can be used. In addition, In can be added to the above oxide semiconductor. Other elements besides Ga, Sn, and Zn, such as SiO2, may also be included.

[0228] For example, an In-Ga-Zn-O oxide semiconductor is made up of indium (In) and gallium (G a) This means an oxide semiconductor containing zinc (Zn), and its composition is not specified.

[0229] Furthermore, oxide semiconductor films have the chemical formula InMO3(ZnO) m Thin films denoted as (m>0) It can be used. Here, M is one selected from Zn, Ga, Al, Mn and Co. or indicates multiple metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, or Examples include Ga and Co.

[0230] Furthermore, when using an In-Zn-O based material as an oxide semiconductor, the target used The atomic ratio of metal elements is In:Zn = 50:1 to 1:2 (which translates to In2O in mole ratios). 3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (molar ratio) Converted to this ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15:1 to 1.5:1 (Converted to a mole ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming In-Zn-O oxide semiconductors is the atomic ratio. When the ratio of In:Zn:O = X:Y:Z, assume Z > 1.5X + Y. The ratio of Zn is within the above range. By fitting it into this configuration, mobility can be improved.

[0231] Furthermore, impurities such as water or hydrogen, which act as electron donors, are reduced, and acid Purified oxide semiconductors (purified Oxi) are achieved by reducing elemental defects. A de Semiconductor is an i-type (intrinsic semiconductor) or very close to an i-type. Therefore, transistors using the above-mentioned oxide semiconductor have the characteristic of having a remarkably low off-current. It has the following characteristics. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV. More preferably, the voltage is 3 eV or higher. The concentration of impurities such as water or hydrogen is sufficiently reduced. Furthermore, by reducing oxygen deficiency, a highly purified oxide semiconductor film is used. This allows the transistor's off-current to be reduced.

[0232] Specifically, transistors using highly purified oxide semiconductors as semiconductor films have a low off-current. This can be proven through various experiments. For example, if the channel width is 1 × 10⁻⁶ 6 micrometers Even with an element with a channel length of 10 μm, the voltage between the source terminal and the drain terminal (drain voltage) When the voltage is in the range of 1V to 10V, the off-current is measured by a semiconductor parameter analyzer. Below the limit, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, The off-current density, which corresponds to the value obtained by dividing the f-current by the transistor's channel width, is 100 Hz. It can be seen that it is less than / μm. Also, by connecting the capacitive element and the transistor, the capacitive element Using a circuit that controls the charge flowing into or out of a capacitive element with the transistor, The current density can be measured. In this measurement, the transistor is purified to high purity. Using an oxide semiconductor film as the channel formation region, the change in the amount of charge per unit time of a capacitive device is observed. The off-current density of the transistor is measured from the source. When the voltage between the terminal and the drain terminal is 3V, the off-current is extremely low, at several tens of yA / μm. It is known that a high fluidity can be obtained. Therefore, a highly purified oxide semiconductor film can be channeled. The transistor used in the transistor formation region has an off-current, and the transistor uses crystalline silicon. It is clear that this is significantly lower compared to the 'njista'.

[0233] Unless otherwise specified, in this specification, off-current refers to the off-current of an n-channel transistor. Therefore, with the drain terminal at a higher potential than the source terminal and gate, the source terminal When the gate potential is 0 or less relative to the potential of the child, the source terminal and drain This refers to the current flowing between terminals. Alternatively, in this specification, off-current refers to p-channel current. In a transistor of this type, the drain terminal is at a lower potential than the source terminal and the gate. In this state, when the gate potential is 0 or greater with respect to the potential of the source terminal, This refers to the current flowing between the source terminal and the drain terminal.

[0234] Oxide semiconductor films are made of, for example, In (indium), Ga (gallium), and Zn (zinc). It can be formed by sputtering using a target containing In-Ga-Zn acid. When depositing a semiconductor film by sputtering, preferably the atomic ratio is In:Ga: Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1: A target of the In-Ga-Zn oxide system shown in 4 is used. It has the aforementioned atomic ratio. By depositing oxide semiconductor films using an In-Ga-Zn-based oxide target, multiple connections can be formed. Crystals or CAACs (described later) are more likely to form.

[0235] Furthermore, the packing density of the target containing In, Ga, and Zn is preferably 90% to 100%. Or it is between 95% and 100%. By using a target with a high filling rate, The oxide semiconductor film that is formed becomes a dense film.

[0236] Specifically, the oxide semiconductor film is processed by holding the substrate in a processing chamber that is kept under reduced pressure, and then processing... While removing residual moisture in the laboratory, sputtered gas from which hydrogen and moisture have been removed is introduced, and the above-mentioned It can be formed using a film-forming agent. During film formation, the substrate temperature should be between 100°C and 600°C. Alternatively, the temperature can be between 200°C and 400°C. By depositing the film while heating the substrate... This allows for a reduction in the impurity concentration contained in the deposited oxide semiconductor film. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, ion pump, or titanium pump. It is preferable to use a breech pump. Furthermore, a turbopump is preferred as the exhaust means. A cold trap may be added to the system. The deposition chamber is evacuated using a cryopump. Then, for example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (more preferably carbon Because compounds containing elementary atoms are also exhausted, the oxide semiconductor film deposited in the processing chamber contains The concentration of impurities can be reduced.

[0237] Furthermore, in oxide semiconductor films formed by sputtering, etc., there may be water or hydrogen as an impurity. It may contain a large amount of (hydroxyl groups). Water or hydrogen forms donor levels. Because it is easily oxidized, it is an impurity for oxide semiconductors. Therefore, in one aspect of the present invention, To reduce impurities such as water or hydrogen in a semiconductor film (dehydration or dehydrogenation) For oxide semiconductor films, under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas, acid Under a gas atmosphere or in ultra-dry air (CRDS (cavity ring-down laser spectroscopy) The moisture content measured using a dew point meter of the ) type is 20 ppm or less (equivalent to a dew point of -55°C). The heat treatment is performed in an atmosphere (preferably 1 ppm or less, preferably 10 ppb or less of air) To administer.

[0238] By applying heat treatment to the oxide semiconductor film, water or hydrogen is removed from the oxide semiconductor film. This is possible. Specifically, a substrate at 250°C to 750°C, preferably 400°C or higher. The heat treatment should be performed at a temperature below the strain point. For example, 500°C for 3 to 6 minutes. It should be done to a certain extent. If the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time. Therefore, processing can be performed even at temperatures exceeding the strain point of the glass substrate.

[0239] Furthermore, the above heat treatment causes oxygen to be removed from the oxide semiconductor film, and oxygen remains in the oxide semiconductor film. Defects may be formed. Therefore, in one aspect of the present invention, the g An insulating film containing oxygen is used as the insulating film, such as a galvanic insulating film. After forming the film, heat treatment is applied to supply oxygen from the insulating film to the oxide semiconductor film. This configuration reduces the oxygen vacancies that serve as donors and is contained in the oxide semiconductor film. The oxide semiconductor can satisfy the stoichiometric composition. The oxide semiconductor film has a chemical composition. It is preferable that the oxygen content exceeds the stoichiometric composition. As a result, oxide semiconductor film This makes it possible to bring it closer to type i, reducing variations in the electrical characteristics of transistors due to oxygen deficiency. This can reduce the noise and improve electrical characteristics.

[0240] Furthermore, the heat treatment to supply oxygen to the oxide semiconductor film is performed using nitrogen, ultra-dry air, or dilute air. In a gaseous atmosphere (such as argon or helium), preferably at a temperature of 200°C to 400°C. The following steps should be performed at a temperature between 250°C and 350°C. The gas mentioned above must contain less than 20 ppm of water. Preferably, the concentration is 1 ppm or less, and more preferably 10 ppb or less.

[0241] Oxide semiconductor films can be single crystals, polycrystalline (also called polycrystals), or amorphous. To act in a certain manner.

[0242] Preferably, the oxide semiconductor film is CAAC-OS(C Axis Aligned Cr The film is a ystalline oxide semiconductor film.

[0243] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. This is an oxide semiconductor film having a crystalline-amorphous multiphase structure with crystalline and amorphous parts in the amorphous phase. Yes, it exists. Furthermore, the crystalline portion must be small enough to fit within a cube with sides less than 100 nm long. There are many. Also, transmission electron microscopes (TEM) In the image observed using a microscope, the amorphous region contained in the CAAC-OS film and The boundary with the crystalline portion is not clear. Also, TEM revealed grain boundaries in the CAAC-OS film. Also called inboundary. ) cannot be confirmed. Therefore, the CAAC-OS film has grain boundaries. The resulting decrease in electron mobility is suppressed.

[0244] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0245] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0246] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. The crystalline portion is formed during film formation or by performing crystallization treatments such as heat treatment after film formation. It will be done.

[0247] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. It is possible to reduce this. Therefore, the transistor in question is highly reliable.

[0248] Furthermore, some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0249] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. This is a possibility. In this case, the flat sputtered particles maintain their crystalline state. It is believed that the CAAC-OS film is formed when it reaches the substrate.

[0250] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0251] By reducing the inclusion of impurities during film formation, it is possible to suppress the breakdown of crystals due to impurities. For example, you can reduce the concentration of impurities (hydrogen, water, carbon dioxide, etc.) present in the film deposition chamber. . Further, the impurity concentration in the film-forming gas may be reduced. Specifically, a film-forming gas having a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0252] Also, by increasing the substrate heating temperature during film formation, it is considered that the migration of sputtering particles is promoted after reaching the substrate. Therefore, it is preferable to form a film with the substrate heating temperature being 100°C or higher and 740 °C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate heating temperature during film formation, the flat sputtering particles that reach the substrate migrate on the substrate, and it is considered that an oxide semiconductor film is formed such that the flat surface of the sputtering particles is parallel to the substrate.

[0253] Also, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30 vol% or higher, preferably 100 vol %.

[0254] As an example of the sputtering target, an In-Ga-Zn-O compound target is shown below.

[0255] InO X powder, GaO Y powder, and ZnO Z powder are mixed at a predetermined molar ratio, and after pressure treatment , a polycrystalline In-G a-Zn-O compound target is obtained by heat treatment at a temperature of 1000°C or higher and 1500°C or lower. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO powder, GaO X powder, and ZnO Y powder such that Z The ratios are 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The type of powder and the molar ratio in which they are mixed will be determined for the sputtering process. You can change it as needed by getting it.

[0256] Next, an example of a specific configuration of the transistor in the semiconductor device of the present invention will be described. do.

[0257] The transistor shown in Figure 13(A) is a bottom-gate type with a channel etch structure.

[0258] The transistor shown in Figure 13(A) has a gate electrode formed on an insulating surface. (T) 1602, gate insulating film 1603 on gate electrode 1602, and gate insulating film 160 3 The semiconductor film 1604 overlaps with the gate electrode 1602, and the semiconductor film 1604 It has conductive films 1605 and 1606 formed on top. Furthermore, the transistor The insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606 It may be included as one of its components.

[0259] Furthermore, the transistor shown in Figure 13(A) is in an insulating position where it overlaps with the semiconductor film 1604. The device may further have a back gate electrode formed on the border film 1607.

[0260] The transistor shown in Figure 13(B) is a bottom-gate type with a channel protection structure.

[0261] The transistor shown in Figure 13(B) has a gate electrode 161 formed on an insulating surface. 2, the gate insulating film 1613 on the gate electrode 1612, and on the gate insulating film 1613 The semiconductor film 1614 overlaps with the gate electrode 1612, and is formed on the semiconductor film 1614. A channel protective film 1618 and a conductive film 1615 formed on the semiconductor film 1614, conductive The transistor also has a channel protection film 1618 and a conductive film 16 The insulating film 1617 formed on the conductive film 1616 may also be included as a component. .

[0262] Furthermore, the transistor shown in Figure 13(B) is in an insulating position where it overlaps with the semiconductor film 1614. The device may further have a back gate electrode formed on the edge film 1617.

[0263] By providing the channel protection film 1618, the channel formation region of the semiconductor film 1614 and In subsequent processes, the film formed by plasma or etching agent during etching of certain parts This prevents damage such as wear and tear. Therefore, it improves the reliability of transistors. It is possible.

[0264] The transistor shown in Figure 13(C) is a bottom-gate type with a bottom-contact structure.

[0265] The transistor shown in Figure 13(C) has a gate electrode 162 formed on an insulating surface. 2, the gate insulating film 1623 on the gate electrode 1622, and the conductive film on the gate insulating film 1623 Film 1625, conductive film 1626, and gate electrode 1622 on gate insulating film 1623 The semiconductor film 162 is formed on the conductive film 1625 and conductive film 1626, which are overlapping. It has 4. Furthermore, the transistor has conductive film 1625, conductive film 1626, and semiconductor An insulating film 1627 formed on the film 1624 may also be included as a component.

[0266] Furthermore, the transistor shown in Figure 13(C) is in an insulating position where it overlaps with the semiconductor film 1624. The device may further have a back gate electrode formed on the border film 1627.

[0267] The transistor shown in Figure 13(D) is a top-gate type with a bottom-contact structure.

[0268] Furthermore, the transistor shown in Figure 13(D) has a conductive film 1645 formed on the insulating surface. A conductive film 1646 and a semiconductor formed on the insulating surface and conductive film 1645 and conductive film 1646. Film 1644, conductive film 1645, conductive film 1646, and semiconductor film 1644 formed on film 1644 The gate insulating film 1643 overlaps with the semiconductor film 1644 on the gate insulating film 1643. The transistor has a gate electrode 1642 on the gate electrode 1642. The formed insulating film 1647 may also be included as a component.

[0269] This embodiment can be implemented in appropriate combination with other embodiments.

[0270] (Embodiment 4) Figure 14 illustrates an example of a panel, which corresponds to one form of display device. The panel consists of a substrate 700, a pixel section 701 on the substrate 700, a signal line driving circuit 702, and a scanning line It has a drive circuit 703 and a terminal 704.

[0271] The pixel unit 701 has multiple pixels, and each pixel has a display element and a control for the operation of the display element. One or more transistors are provided to perform the scan line drive. The scan line drive circuit 703 controls each image By controlling the supply of potential to the scan lines connected to the base, the pixels of the pixel unit 701 are selected. Select. The signal line drive circuit 702 controls the image of the pixel selected by the scan line drive circuit 703. Controls the supply of signals.

[0272] One or both of the signal line drive circuit 702 and the scan line drive circuit 703 are the same as in Embodiment 1. Barta circuit, flip-flop circuit of Embodiment 2, or shift register circuit of Embodiment 2 This includes the road. In this way, the effects described in Embodiment 1 and Embodiment 2 can be achieved. This also allows for a larger pixel area 701. It is possible to set up an element.

[0273] This embodiment can be implemented in appropriate combination with other embodiments.

[0274] (Embodiment 5) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) Electronic devices such as (devices that play back recording media and have a display capable of displaying the images) It can be used in a device. In addition, a semiconductor device according to one aspect of the present invention can be used. Electronic devices that can be used include mobile phones, game consoles including portable models, personal digital assistants, e-books, and videotapes. Cameras such as camera and digital still camera, goggle-type display (head mount) (display), navigation system, sound playback device (car audio, digital) Audio players, etc.), photocopiers, fax machines, printers, multifunction printers, current Examples include automated teller machines (ATMs) and vending machines. The specifics of these electronic devices... An example is shown in Figure 15.

[0275] Figure 15(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It includes illustration 5008, etc. A semiconductor according to one aspect of the present invention is used in the drive circuit of a portable game console. By using this device, it is possible to provide a portable game console with low power consumption and stable operation. Yes, it is possible. By using a semiconductor device according to one aspect of the present invention in the display unit 5003 or the display unit 5004. This makes it possible to provide a high-definition portable game console. Note that as shown in Figure 15(A) The portable game console has two display units 5003 and 5004, but the portable The number of display units a game console has is not limited to this.

[0276] Figure 15(B) shows a display device, which includes a housing 5201, a display unit 5202, a support base 5203, etc. To do so, by using a semiconductor device according to one aspect of the present invention in the drive circuit of a display device, the power consumption is reduced. This invention provides a display device that is low in power and operates stably. By using a semiconductor device according to one embodiment, a high-resolution display device can be provided. Oh, the display devices include all kinds, such as those for personal computers, TV broadcast reception, and advertising displays. This includes display devices for information display.

[0277] Figure 15(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It has a keyboard 5403, a pointing device 5404, etc. Notebook personal By using a semiconductor device according to one aspect of the present invention in the drive circuit of a computer, the power consumption is reduced. We can provide a notebook personal computer with low power consumption and stable operation. By using a semiconductor device according to one aspect of the present invention in the display unit 5402, a high-resolution notebook-type paper We can provide a computer.

[0278] Figure 15(D) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 The connection is made by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It is made movable by 5605. The video in the first display unit 5603 is displayed on the first housing 560 The configuration may also be such that the switching occurs according to the angle between the first and the second housing 5602. At least one of the display unit 5603 and the second display unit 5604 has a function as a position input device. A semiconductor display device with the added feature may also be used. This functionality can be added by providing a touch panel to the semiconductor display device. Alternatively, Its function as an input device involves using a photoelectric conversion element, also known as a photosensor, in a semiconductor display device. It can also be added by providing it in the pixel section. By using a semiconductor device according to one embodiment, a portable information terminal with low power consumption and stable operation is obtained. This can provide the first display unit 5603 or the second display unit 5604 of the present invention. By using the semiconductor device according to this embodiment, a high-resolution portable information terminal can be provided.

[0279] Figure 15(E) is a mobile phone, consisting of a housing 5801, a display unit 5802, an audio input unit 5803, It has an audio output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the received light into an electrical signal, external images can be captured. By using a semiconductor device according to one aspect of the present invention in the drive circuit of a mobile phone, power consumption is reduced. This enables the provision of a mobile phone with stable operation. In one aspect of the present invention, the display unit 5802 is provided. By using such a semiconductor device, it is possible to provide a mobile phone with high image quality.

[0280] This embodiment can be implemented in appropriate combination with other embodiments. [Explanation of symbols]

[0281] 11 Wiring 11A wiring 11B Wiring 12 Wiring 13 Wiring 13A wiring 13B Wiring 13C wiring 14 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 100 circuits 101 Transistors 102 transistors 200 circuits 201 Transistors 202 transistors 203 Transistors 204 Capacitive element 205 transistors 300 circuits 300A circuit 300B circuit 300C circuit 301 Resistor element 302 Capacitive element 303 Transistors 304 transistors 305 Transistors 306 transistors 307 transistors 401 Transistors 402 transistors 403 Transistors 404 transistors 405 transistors 406 transistors 407 Transistors 408 transistors 409 transistors 500 circuits 600 Flip-Flop Circuit 600_1 Flip-flop circuit 600_2 Flip-flop circuit 600_3 Flip-flop circuit 700 circuit boards 701 pixel section 702 Signal Line Drive Circuit 703 Scan line drive circuit 704 terminal 800 circuit boards 802 Gate Insulator 812 Conductive film 813 Semiconductor film 814 Conductive film 815 Conductive film 816 Conductive film 817 Semiconductor film 818 Conductive film 819 Conductive film 820 Insulating film 821 Insulating film 822 Conductive film 823 Contact Hole 824 Insulating film 825 EL layer 826 Conductive film 830 transistors 831 Transistors 832 Light-emitting element 833 Capacitive element 840 pixels 841 Drive Circuit 1602 Gate Shuttle 1603 Gate Insulator 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Shuttle gate 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protective film 1622 Gate 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Shutdown gate 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Support stand 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 Display section 5803 Voice Input Section 5804 Audio output section 5805 Operation Keys 5806 Light receiving section M1 Transistor M2 Transistor M3 Transistor M4 Transistor M11 Transistor M12 Transistor M13 Transistor M14 Transistor M15 Transistor M16 Transistor M17 Transistor M18 Transistor M19 Transistor C11 Capacitive element VDD potential VSS potential N1 node N2 node N3 node N4 node SP signal RE signal CK signal CKB signal IN signal SSP signal OUT signal SOUT signal SOUTa signal SOUTb signal SOUT_1 signal SOUT_i signal SOUT_N signal

Claims

1. It has first to sixth transistors and capacitive elements, Either the source or the drain of the first transistor is electrically connected to the output signal line. The source or drain of the first transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the second transistor is electrically connected to the output signal line. The source or drain of the second transistor, the other of which is electrically connected to a power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The source or drain of the third transistor, the other of which is electrically connected to the first signal line, The gate of the third transistor is electrically connected to the second signal line. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The source or drain of the fourth transistor, the other of which is electrically connected to the power line, One of the electrodes of the capacitive element is electrically connected to the gate of the first transistor. The other electrode of the capacitive element is electrically connected to either the source or the drain of the fifth transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. Either the source or drain of the sixth transistor is electrically connected to the gate of the fourth transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the first wiring, When the power line is in conductivity with the output signal line, at least through the channel formation region of the second transistor, the second transistor turns on. A semiconductor device in which the sixth transistor is turned on when the first wiring is in a conductive state with the gate of the fourth transistor, at least through the channel forming region of the sixth transistor.

2. It has first to sixth transistors and capacitive elements, Either the source or the drain of the first transistor is electrically connected to the output signal line. The source or drain of the first transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the second transistor is electrically connected to the output signal line. The source or drain of the second transistor, the other of which is electrically connected to a power line, Either the source or the drain of the third transistor is electrically connected to the gate of the first transistor. The source or drain of the third transistor, the other of which is electrically connected to the first signal line, The gate of the third transistor is electrically connected to the second signal line. Either the source or drain of the fourth transistor is electrically connected to the gate of the first transistor. The source or drain of the fourth transistor, the other of which is electrically connected to the power line, One of the electrodes of the capacitive element is electrically connected to the gate of the first transistor. The other electrode of the capacitive element is electrically connected to either the source or the drain of the fifth transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the power line, The gate of the fifth transistor is electrically connected to the gate of the first transistor. Either the source or drain of the sixth transistor is electrically connected to the gate of the fourth transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the first wiring, When the power line is in conductivity with the output signal line, at least through the channel formation region of the second transistor, the second transistor turns on. When the first wiring is in a conductive state with the gate of the fourth transistor, at least through the channel forming region of the sixth transistor, the sixth transistor turns on. The first to sixth transistors are semiconductor devices having the same conductivity type.

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