Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can reduce variations in the distance between the conductive material and the semiconductor chip. [Solution] The semiconductor device comprises a conductive material having a first main surface, a plurality of support members arranged on the first main surface, a semiconductor chip supported by the plurality of support members and equipped with electrode pads, and a conductive sintered material that joins the conductive material and the electrode pads.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device in which a semiconductor chip is joined to a conductive material such as a conductive pattern provided on one main surface of a substrate using solder is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, the distance between the conductive material and the semiconductor chip is likely to vary. This variation in distance can lead to variation in characteristics.

[0005] An object of this disclosure is to provide a semiconductor device capable of reducing the variation in the distance between the conductive material and the semiconductor chip.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure includes a conductive material having a first main surface, a plurality of support members disposed on the first main surface, a semiconductor chip supported by the plurality of support members and having electrode pads, and a conductive sintered material joining the conductive material and the electrode pads.

Effects of the Invention

[0007] According to this disclosure, the variation in the distance between the conductive material and the semiconductor chip can be reduced.

Brief Description of the Drawings

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a semiconductor device according to the embodiment. [Figure 4] Figure 4 is a plan view (part 1) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] Figure 5 is a plan view (part 2) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] Figure 6 is a plan view (part 3) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A semiconductor device according to one aspect of the present disclosure comprises a conductive material having a first main surface, a plurality of support members arranged on the first main surface, a semiconductor chip supported by the plurality of support members and having electrode pads, and a conductive sintered material that joins the conductive material and the electrode pads.

[0011] A plurality of support members are arranged on the first main surface of the conductive material, and the semiconductor chip is supported by the plurality of support members. Therefore, when the conductive sintered material is formed, the conductive paste can spread outside the semiconductor chip through the gaps between the support members. For this reason, the plurality of support members function as spacers, reducing the variation in the distance between the semiconductor chip and the conductive material, stabilizing the thermal resistance between the semiconductor chip and the conductive material, and reducing the variation in characteristics.

[0012] 〔2〕 In 〔1〕, the conductive sintered material contains silver or copper, and the support member may contain one or more of silver, copper, or nickel. In this case, a high bonding strength can be obtained between the conductive sintered material and the support member when they are in contact with each other.

[0013] 〔3〕 In 〔1〕 or 〔2〕, in a plan view perpendicular to the first main surface, the plurality of support members may overlap the outer edge of the semiconductor chip. In this case, the portion overlapping the support member at the outer edge is less likely to be restrained by the conductive sintered material, and the stress acting on the semiconductor chip due to the restraint can be reduced.

[0014] 〔4〕 In any of 〔1〕 to 〔3〕, in a plan view perpendicular to the first main surface, the semiconductor chip has a rectangular shape with four corner portions, and the plurality of support members may overlap each of the four corner portions one by one. In this case, the corner portions are less likely to be restrained by the conductive sintered material, and the stress acting on the semiconductor chip due to the restraint can be reduced.

[0015] 〔5〕 In any of 〔1〕 to 〔4〕, each of the plurality of support members has a first surface in contact with the conductive material and a second surface opposite to the first surface, and the semiconductor chip may have a third surface in direct contact with the second surface. In this case, the portion of the third surface overlapping the support member is less likely to be restrained by the conductive sintered material, and the stress acting on the semiconductor chip due to the restraint can be reduced.

[0016] 〔6〕In [5], the second surface and the third surface may not be joined. Even in this case, the portion overlapping with the support member on the third surface is less likely to be constrained by the conductive sintered material, and the stress acting on the semiconductor chip due to the constraint can be reduced.

[0017] 〔7〕In any one of [1] to [6], each of the plurality of support members has a first surface in contact with the conductive material and a second surface opposite to the first surface, and between the plurality of support members, the first distance between the first surface and the second surface may be equal. In this case, it is easier to stabilize the thermal resistance between the semiconductor chip and the conductive material, and it is easier to reduce the variation in characteristics.

[0018] 〔8〕In [7], the conductive sintered material has a fourth surface in contact with the conductive material and a fifth surface opposite to the fourth surface, and the second distance between the fourth surface and the fifth surface may be equal to the first distance. Even in this case, it is easier to stabilize the thermal resistance between the semiconductor chip and the conductive material, and it is easier to reduce the variation in characteristics.

[0019] 〔9〕In any one of [1] to [8], it has a substrate having a second main surface, and the conductive material may be a conductive pattern disposed on the second main surface. In this case, the variation in the distance between the semiconductor chip and the conductive pattern can be reduced, the thermal resistance between the semiconductor chip and the conductive pattern can be stabilized, and the variation in characteristics can be reduced.

[0020] 〔10〕In any one of [1] to [9], the porosity of the support member may be lower than the porosity of the conductive sintered material. In this case, it is easier to mitigate the influence of thermal deformation on the semiconductor chip by the conductive sintered material.

[0021] [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant description may be omitted.

[0022] Embodiments of this disclosure relate to semiconductor devices. Figure 1 is a plan view showing a semiconductor device according to an embodiment. Figures 2 and 3 are cross-sectional views showing a semiconductor device according to an embodiment. Figure 2 shows a cross-section along line II-II in Figure 1. Figure 3 shows a cross-section along line III-III in Figure 1.

[0023] As shown in Figures 1 to 3, the semiconductor device 1 according to the embodiment includes an insulating substrate 20, conductive patterns 31, 32 and 33, support members 41, 42, 43 and 44, a semiconductor chip 10, a conductive sintered material 50, a bonding wire 82, and a bonding wire 83.

[0024] The insulating substrate 20 has a main surface 21. Conductive patterns 31, 32, and 33 are arranged on the main surface 21. For example, conductive pattern 31 is arranged between conductive pattern 32 and conductive pattern 33. Conductive pattern 31 has a main surface 34 facing the main surface 21 and a main surface 35 opposite to the main surface 34. The material of the insulating substrate 20 is, for example, silicon nitride (SiN), aluminum oxide (Al2O3), or aluminum nitride (AlN). The material of the conductive patterns 31, 32, and 33 is, for example, copper (Cu). Conductive pattern 31 is an example of a conductive material. The insulating substrate 20 is an example of a substrate. Main surface 35 is an example of a first main surface. Main surface 21 is an example of a second main surface. Hereinafter, "plan view" refers to a plan view perpendicular to the main surface 35, and "planar shape" refers to the shape in plan view.

[0025] Support members 41, 42, 43, and 44 are arranged on the conductive pattern 31. For example, the support members 41, 42, 43, and 44 are arranged to form the vertices of a quadrilateral in plan view. Each of the support members 41, 42, 43, and 44 has a first surface 46 that is in contact with the conductive pattern 31 and a second surface 47 opposite to the first surface 46. The first distance L1 between the first surface 46 and the second surface 47 is equal among the support members 41, 42, 43, and 44. The first distance L1 corresponds to the thickness of the support members 41, 42, 43, and 44. The support members 41, 42, 43, and 44 have shapes such as cylindrical or prismatic. For example, the support members 41, 42, 43, and 44 contain one or more of the following materials: silver (Ag), copper (Cu), or nickel (Ni), and one or more of the following materials are exposed on the surface of the support members 41, 42, 43, and 44.

[0026] The semiconductor chip 10 is, for example, a MOS-type field-effect transistor (FET) chip. The semiconductor chip 10 has a silicon carbide substrate 19, a drain electrode pad 11, a source electrode pad 12, a gate electrode pad 13, and a passivation film 14. The silicon carbide substrate 19 has a main surface 71 and a main surface 72 opposite to the main surface 71. The drain electrode pad 11 is provided on the main surface 71, and the source electrode pad 12 and gate electrode pad 13 are provided on the main surface 72. The semiconductor chip 10 has a third surface 16. For example, the third surface 16 is on the drain electrode pad 11. The third surface 16 is the surface of the drain electrode pad 11 opposite to the surface in contact with the main surface 71. The passivation film 14 covers the main surface 72, the source electrode pad 12, and the gate electrode pad 13. The passivation film 14 has openings formed in which a portion of the source electrode pad 12 is exposed and an opening in which a portion of the drain electrode pad 11 is exposed.

[0027] A bonding wire 82 is connected between the source electrode pad 12 and the conductive pattern 32. Multiple bonding wires 82 may be connected between the source electrode pad 12 and the conductive pattern 32. The source electrode pad 12 and the conductive pattern 32 are electrically connected through the bonding wires 82. A bonding wire 83 is connected between the gate electrode pad 13 and the conductive pattern 33. The gate electrode pad 13 and the conductive pattern 33 are electrically connected through the bonding wires 83.

[0028] The semiconductor chip 10 is supported by support members 41, 42, 43, and 44. The semiconductor chip 10 has a rectangular shape, for example, in a plan view, with four corners 61, 62, 63, and 64. Corner 61 rests on support member 41, corner 62 rests on support member 42, corner 63 rests on support member 43, and corner 64 rests on support member 44. In a plan view, support members 41, 42, 43, and 44 overlap with the four corners 61, 62, 63, and 64 one by one. Also, in a plan view, support members 41, 42, 43, and 44 overlap with the outer edge 15 of the semiconductor chip 10. The third surface 16 of the semiconductor chip 10 is in direct contact with the second surfaces 47 of the support members 41, 42, 43, and 44, but the second surface 47 and the third surface 16 are not joined to each other.

[0029] The conductive sintered material 50 joins the conductive pattern 31 and the drain electrode pad 11. The drain electrode pad 11 and the conductive pattern 31 are electrically connected through the conductive sintered material 50. The conductive sintered material 50 may be in contact with the support members 41, 42, 43, and 44, or it may be away from the support members 41, 42, 43, and 44. The conductive sintered material 50 has a fourth surface 56 that is in contact with the conductive pattern 31 and a fifth surface 57 opposite to the fourth surface 56. For example, the second distance L2 between the fourth surface 56 and the fifth surface 57 is equal to the first distance L1. The second distance L2 corresponds to the thickness of the conductive sintered material 50. For example, the conductive sintered material 50 contains silver (Ag) or copper (Cu), and the silver or copper is exposed on the surface of the conductive sintered material 50.

[0030] Next, a method for manufacturing the semiconductor device 1 will be described. Figures 4 to 6 are plan views showing a method for manufacturing the semiconductor device according to an embodiment. Figures 7 to 11 are cross-sectional views showing a method for manufacturing the semiconductor device according to an embodiment. Figure 7 shows a cross-section along the line VII-VII in Figure 4. Figure 8 shows a cross-section along the line VIII-VIII in Figure 5. Figure 9 shows a cross-section along the line IX-IX in Figure 6. Figure 10 shows a cross-section along the line XX in Figure 5. Figure 11 shows a cross-section along the line XI-XI in Figure 6.

[0031] As shown in Figures 4 and 7, an insulating substrate 20 is prepared with conductive patterns 31, 32, and 33 provided on the main surface 21. Next, support members 41, 42, 43, and 44 are placed on the main surface 35 of the conductive pattern 31. The support members 41, 42, 43, and 44 can be formed, for example, by film deposition using a sputtering or plating method with a mask, followed by lift-off by removing the mask. With such a method, the support members 41, 42, 43, and 44 can be formed with high positional accuracy.

[0032] Next, as shown in Figures 5, 8, and 10, a conductive paste 51, which will become a conductive sintered material 50 by firing, is applied on the conductive pattern 31. The conductive paste 51 contains silver (Ag) or copper (Cu). The conductive paste 51 can be applied, for example, by coating. The conductive paste 51 is applied to a thickness greater than the height of the support members 41, 42, 43, and 44.

[0033] Next, as shown in Figures 6, 9, and 11, the semiconductor chip 10 is placed on support members 41, 42, 43, and 44. Corner 61 is placed on support member 41, corner 62 on support member 42, corner 63 on support member 43, and corner 64 on support member 44. At this time, the semiconductor chip 10 can be aligned while detecting support members 41, 42, 43, and 44. For example, in detecting support members 41, 42, 43, and 44, image data is acquired by photographing the support members 41, 42, 43, and 44, and image processing is performed on the image data.

[0034] Next, the semiconductor chip 10 is pressed, and the conductive paste 51 is spread, bringing the third surface 16 into direct contact with the second surfaces 47 of the support members 41, 42, 43, and 44. The conductive paste 51 may spread outwards from the semiconductor chip 10 in a plan view through the gaps between support member 41 and support member 42, between support member 42 and support member 43, between support member 43 and support member 44, or between support member 44 and support member 41. The conductive paste 51 may or may not be in contact with the support members 41, 42, 43, and 44.

[0035] Subsequently, the conductive paste 51 is fired to obtain a conductive sintered material 50 (see Figures 1, 2, and 3). Bonding wires 82 and 83 are also provided (see Figure 1).

[0036] In this way, semiconductor device 1 can be manufactured.

[0037] In the semiconductor device 1, support members 41, 42, 43, and 44 are arranged on the main surface 35 of the conductive pattern 31, and the semiconductor chip 10 is supported by the support members 41, 42, 43, and 44. Therefore, when forming the conductive sintered material 50, the conductive paste 51 can spread outwards from the semiconductor chip 10 in a plan view through the gaps between support member 41 and support member 42, the gap between support member 42 and support member 43, the gap between support member 43 and support member 44, or the gap between support member 44 and support member 41. As a result, the support members 41, 42, 43, and 44 function as spacers, reducing variations in the distance between the semiconductor chip 10 and the conductive pattern 31. By reducing variations in the distance between the semiconductor chip 10 and the conductive pattern 31, the thermal resistance between the semiconductor chip 10 and the conductive pattern 31 can be stabilized, and variations in characteristics can be reduced.

[0038] While it is conceivable to use solder instead of the conductive sintered material 50, the conductive sintered material 50 has lower rigidity than solder. Therefore, when the magnitude of thermal deformation differs between the insulating substrate 20 and the semiconductor chip 10, the influence of the thermal deformation of the insulating substrate 20 on the semiconductor chip 10 can be mitigated more effectively than when solder is used. When sputtering or plating is used to form the support members 41, 42, 43, and 44, the support members 41, 42, 43, and 44 contain virtually no voids, and the void ratio of the support members 41, 42, 43, and 44 is lower than that of the conductive sintered material 50. Because the void ratio of the support members 41, 42, 43, and 44 is lower than that of the conductive sintered material 50, the conductive sintered material 50 can more easily mitigate the influence of thermal deformation on the semiconductor chip 10.

[0039] When the conductive sintered material 50 contains silver or copper, and the support members 41, 42, 43, and 44 contain one or more of silver, copper, or nickel, a high bonding strength is obtained between the conductive sintered material 50 and the support members 41, 42, 43, and 44 when the conductive sintered material 50 is in contact with the support members 41, 42, 43, and 44. Particularly high bonding strength is obtained when the conductive sintered material 50 contains silver and the support members 41, 42, 43, and 44 contain silver, and when the conductive sintered material 50 contains copper and the support members 41, 42, 43, and 44 contain copper.

[0040] In a plan view, the support members 41, 42, 43, and 44 overlap with the outer edge 15 of the semiconductor chip 10. As a result, the portion of the outer edge 15 that overlaps with the support members 41, 42, 43, and 44 is less constrained by the conductive sintered material 50, thereby reducing the stress acting on the semiconductor chip 10 due to this constrainment.

[0041] In a plan view, the support members 41, 42, 43, and 44 overlap with the corners 61, 62, 63, and 64 one by one, so that the corners 61, 62, 63, and 64 are less constrained by the conductive sintered material 50, and the stress acting on the semiconductor chip 10 due to constrainment can be reduced.

[0042] Because the third surface 16 of the semiconductor chip 10 is in direct contact with the second surface 47, there is no conductive sintered material 50 between the second surface 47 and the third surface 16, and the second surface 47 and the third surface 16 are not joined together. Therefore, the portion of the third surface 16 that overlaps with the support members 41, 42, 43, and 44 is less likely to be constrained by the conductive sintered material 50, and the stress acting on the semiconductor chip 10 due to this constrainment can be reduced.

[0043] The equality of the first distance L1 between the support members 41, 42, 43, and 44 makes it easier to stabilize the distance between the conductive pattern 31 and the semiconductor chip 10. Furthermore, it makes it easier to stabilize the orientation of the semiconductor chip 10. Also, the equality of the second distance L2 with the first distance L1 makes it easier to stabilize the distance between the conductive pattern 31 and the semiconductor chip 10. Consequently, it is easier to stabilize the thermal resistance between the semiconductor chip 10 and the conductive pattern 31, and to reduce variations in characteristics.

[0044] The conductive material is not limited to the conductive pattern 31 provided on the main surface 21 of the insulating substrate 20. The conductive material may also be a lead frame. The conductive material may or may not have a plating layer. The number of support members is not limited to four, as there may be multiple support members.

[0045] The planar shape of the semiconductor chip 10 does not need to be a polygon such as a rectangle; for example, it may be a rounded rectangle. The semiconductor chip 10 is not limited to a silicon carbide semiconductor chip and may include semiconductors other than silicon carbide. The semiconductor chip 10 is not limited to a MOSFET and may be an insulated gate bipolar transistor (IGBT) or a Schottky barrier diode (SBD), etc.

[0046] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0047] 1 Semiconductor device 10 Semiconductor Chips 11 Drain electrode pad 12 Source electrode pads 13 Gate Pad 14 Passivation membrane 15 Outer edge 16 Page 3 19 Silicon carbide substrate 20 Insulating substrate 21, 34, 35, 71, 72 Main surfaces 31, 32, 33 Conductive patterns 41, 42, 43, 44 Support members 46 Page 1 47 Side 2 50 Conductive sintered material 51 Conductive Paste 56 Page 4 57 Page 5 Corners 61, 62, 63, 64 82, 83 Bonding wires L1 1st distance L2 2nd distance

Claims

1. A conductive material having a first main surface, Multiple support members arranged on the first main surface, A semiconductor chip supported by the aforementioned plurality of support members and equipped with electrode pads, A conductive sintered material that joins the conductive material and the electrode pad, A semiconductor device having

2. The conductive sintered material contains silver or copper, The semiconductor device according to claim 1, wherein the support member comprises one or more of silver, copper, or nickel.

3. In a plan view perpendicular to the first main surface, the plurality of support members overlap with the outer edge of the semiconductor chip. The semiconductor device according to claim 1 or claim 2.

4. In a plan view perpendicular to the first main surface, The semiconductor chip has a square shape with four corners, The aforementioned multiple support members overlap each of the four corners, The semiconductor device according to claim 1 or claim 2.

5. Each of the aforementioned plurality of support members is The first surface in contact with the conductive material, The second side is opposite to the first side, It has, The semiconductor chip has a third surface that is in direct contact with the second surface. The semiconductor device according to claim 1 or claim 2.

6. The second surface and the third surface are not joined. The semiconductor device according to claim 5.

7. Each of the aforementioned plurality of support members is The first surface in contact with the conductive material, The second side is opposite to the first side, It has, Among the plurality of support members, the first distance between the first surface and the second surface is equal. The semiconductor device according to claim 1 or claim 2.

8. The conductive sintered material is The fourth surface in contact with the conductive material, The fifth surface is opposite to the fourth surface mentioned above, It has, The second distance between the fourth and fifth surfaces is equal to the first distance. The semiconductor device according to claim 7.

9. Having a substrate with a second main surface, The conductive material is a conductive pattern arranged on the second main surface. The semiconductor device according to claim 1 or claim 2.

10. The porosity of the support member is lower than that of the conductive sintered material. The semiconductor device according to claim 1 or claim 2.

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