Through-electrode substrate

Abstract

The primary objective is to provide a highly reliable through-electrode substrate. [Solution] The present disclosure provides a through-electrode substrate 1 having a substrate 2 containing silicon and having a first surface 2a and a second surface 2b facing the first surface 2a, and having a through hole 2h, a through electrode 3 disposed in the through hole 2h, and a first wiring layer 4 disposed on the first surface 2a of the substrate 2, wherein the through electrode 3 is in contact with a part of the first wiring layer 4, the through electrode 3 has an adhesion layer 3a and a conductive layer 3b in order from the side wall side of the through hole 2h, the first wiring layer 4 has an adhesion layer 4a and a conductive layer 4b in order from the substrate 2 side, the adhesion layer contains a metal, alloy or metal oxide, and the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate 2 is 2 nm or more and 10 nm or less.

Description

Technical Field

[0001] The present disclosure relates to a through-electrode substrate.

Background Art

[0002] With the increasing sophistication and high performance of various electronic devices, higher reliability has been required for wiring boards. Furthermore, as the wiring boards are becoming more highly integrated and the wiring pitch is becoming finer, ensuring high reliability has become important.

[0003] In recent years, a member having a substrate with a plurality of through-holes and through-electrodes provided inside the through-holes, so-called a through-electrode substrate, has been used in various applications. A through-electrode substrate using a silicon substrate is called TSV (Through Silicon Via), and a through-electrode substrate using a glass substrate is called TGV (Through Glass Via).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a through-electrode substrate, if the through-electrode peels off inside the through-hole, conduction failure will occur, so the adhesion between the side wall of the through-hole and the through-electrode is important. Therefore, as described in Patent Document 1 for example, it has been proposed to dispose an adhesion layer between the side wall of the through-hole and the conductive layer. However, in the formation process of the adhesion layer, high-temperature heat treatment may be included, and there is a concern about a decrease in reliability.

[0006] The present disclosure is an invention made in view of the above circumstances, and the main object thereof is to provide a through-electrode substrate having high reliability. [Means for solving the problem]

[0007] One embodiment of the present disclosure provides a through-electrode substrate having a first surface and a second surface opposite the first surface, having through holes, and containing silicon; a through electrode disposed in the through holes; and a first wiring layer disposed on the first surface of the substrate, wherein the through electrode is in contact with a part of the first wiring layer, the through electrode has an adhesion layer and a conductive layer in order from the side wall side of the through hole, the first wiring layer has an adhesion layer and a conductive layer in order from the substrate side, the adhesion layer contains a metal, alloy, or metal oxide, and the average diffusion thickness of metal atoms contained in the adhesion layer to the substrate is 2 nm or more and 10 nm or less. [Effects of the Invention]

[0008] This disclosure offers the advantage of providing a highly reliable through-electrode substrate. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view illustrating a through-electrode substrate in this disclosure. [Figure 2] This is a schematic cross-sectional view illustrating a through-electrode substrate in this disclosure. [Figure 3] This is a schematic cross-sectional view illustrating an example of a substrate constituting a through-electrode substrate in this disclosure. [Figure 4] This is a schematic cross-sectional view illustrating a through-electrode substrate in this disclosure. [Figure 5] This is a schematic cross-sectional view illustrating a through-electrode substrate in this disclosure. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described below with reference to drawings and other figures. However, this disclosure can be implemented in many different ways and should not be interpreted as being limited to the embodiments described below. In addition, the drawings may be schematically represented in terms of width, thickness, shape, etc. of each part compared to the actual form in order to make the explanation clearer, but these are merely examples and should not limit the interpretation of this disclosure. Furthermore, in this specification and each figure, elements similar to those described above with respect to previously shown figures will be denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] In this specification, when describing a configuration in which one member is placed on top of another member, unless otherwise specified, the terms "on top" or "below" include both cases: one in which the other member is placed directly above or below the other member so as to be in contact with it, and another in which the other member is placed above or below the other member via yet another member. Similarly, when describing a configuration in this specification in which one member is placed on the surface of another member, unless otherwise specified, the terms "on the surface" or "on the surface" include both cases: one in which the other member is placed directly above or below the other member so as to be in contact with it, and another in which the other member is placed above or below the other member via yet another member.

[0012] The through-electrode substrate in this disclosure will be described in detail below.

[0013] The through-electrode substrate in this disclosure has a first surface and a second surface opposite to the first surface, and has through holes, and comprises a silicon-containing substrate, a through-electrode disposed in the through holes, and a first wiring layer disposed on the first surface of the substrate, wherein the through-electrode is in contact with a part of the first wiring layer, the through-electrode has an adhesion layer and a conductive layer in order from the side wall side of the through holes, the first wiring layer has an adhesion layer and a conductive layer in order from the substrate side, the adhesion layer contains a metal, alloy or metal oxide, and the average diffusion thickness of metal atoms contained in the adhesion layer to the substrate is 2 nm or more and 10 nm or less.

[0014] Figure 1 is a schematic cross-sectional view showing an example of a through-electrode substrate in this disclosure. As shown in Figure 1, the through-electrode substrate 1 has a silicon-containing substrate 2 having a first surface 2a and a second surface 2b opposite to the first surface 2a, and a through-hole 2h; a through-electrode 3 disposed in the through-hole 2h; and a first wiring layer 4 disposed on the first surface 2a side of the substrate 2. The through-electrode 3 is in contact with a portion of the first wiring layer 4. The through-electrode 3 has, in order from the side wall side of the through-hole 2h, an adhesion layer 3a and a conductive layer 3b. The first wiring layer 4 has, in order from the substrate 2 side, an adhesion layer 4a and a conductive layer 4b. The adhesion layers 3a and 4a each contain a metal, an alloy, or a metal oxide.

[0015] As mentioned above, in through-electrode substrates, if the through-electrode peels off within the through-hole, a poor conductivity occurs. Therefore, the adhesion between the side wall of the through-hole and the through-electrode is important. For this reason, it has been proposed to place an adhesion layer between the side wall of the through-hole and the conductive layer. For example, Patent Document 1 discloses forming an adhesion layer containing zinc oxide between the side wall of the through-hole and the conductive layer, and between the substrate surface and the conductive layer, using the sol-gel method. In the sol-gel method, a precursor solution is applied and then fired. For example, in the case of zinc oxide, the firing temperature is approximately 400°C to 1000°C. However, when forming an adhesion layer using the sol-gel method, metal atoms in the adhesion layer may diffuse into the substrate during firing. This is not limited to the sol-gel method; similar diffusion of metal atoms in the adhesion layer into the substrate can occur in any method of forming an adhesion layer that involves heat treatment such as firing. In such cases, metal atoms move between wiring layers, causing a short circuit.

[0016] Figure 2(a) is an enlarged view of part A of Figure 1, and Figure 2(b) is an enlarged view of part B of Figure 1. As shown in Figures 2(a) and 2(b), in the through-electrode substrate, the adhesion layers 3a and 4a contain metal, alloy, or metal oxide, and the metal atoms contained in the adhesion layers 3a and 4a diffuse into the substrate 2, and the substrate 2 has a diffusion region 9 at the interface with the adhesion layers 3a and 4a. The average diffusion thickness T1 of the metal atoms contained in the adhesion layers 3a and 4a into the substrate 2 is between 2 nm and 10 nm.

[0017] The metal atoms contained in the adhesion layer are considered to diffuse in both the plane direction and the thickness direction of the substrate. Therefore, the average diffusion thickness T1 of the metal atoms contained in the adhesion layers 3a and 4a into the substrate 2, as shown in FIGS. 2(a) and 2(b), can be regarded as being equivalent to the average diffusion thickness T2 in the plane direction of the substrate 2 of the metal atoms contained in the adhesion layer 4a constituting the first wiring layer, as shown in FIG. 2(b).

[0018] Therefore, in the present disclosure, by ensuring that the average diffusion thickness of the metal atoms contained in the adhesion layer into the substrate is below a predetermined value, even when the distance between the first wiring layers is narrow, short - circuiting between the first wiring layers can be suppressed.

[0019] Also, in the present disclosure, by ensuring that the average diffusion thickness of the metal atoms contained in the adhesion layer into the substrate is above a predetermined value, since the substrate has a diffusion region at the interface with the adhesion layer, the adhesion between the substrate and the adhesion layer can be improved. As a result, the adhesion between the substrate and the through - electrode, and the adhesion between the substrate and the first wiring layer can be enhanced.

[0020] Therefore, in the present disclosure, reliability can be improved.

[0021] Hereinafter, the through - electrode substrate in the present disclosure will be described for each component.

[0022] 1. Average diffusion thickness of metal atoms contained in the adhesion layer into the substrate In this disclosure, the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is 2 nm or more and 10 nm or less, and may be 3 nm or more and 9 nm or less, or 4 nm or more and 8 nm or less. By keeping the above average diffusion thickness below a predetermined value, short circuits between the first wiring layers can be suppressed. Furthermore, as will be described later, if the second wiring layer is arranged on the second surface of the substrate and the second wiring layer has an adhesion layer and a conductive layer in order from the substrate side, short circuits between the second wiring layers can be suppressed. On the other hand, if the above average diffusion thickness is above a predetermined value, the substrate has a diffusion region at the interface with the adhesion layer, so the adhesion between the substrate and the adhesion layer can be improved. As a result, the adhesion between the substrate and the through electrode, and the adhesion between the substrate and the first wiring layer can be improved. Furthermore, as will be described later, if the second wiring layer is arranged on the second surface of the substrate and the second wiring layer has an adhesion layer and a conductive layer in order from the substrate side, the adhesion between the substrate and the second wiring layer can be improved.

[0023] The diffusion thickness of metal atoms contained in the adhesion layer into the substrate refers to the thickness of the metal atoms contained in the adhesion layer that have diffused into the substrate perpendicular to the interface between the substrate and the adhesion layer. The average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is measured by TEM-EDX (energy-dispersive X-ray spectroscopy). Specifically, first, the through-electrode substrate is embedded and fixed, and sections are prepared. A focused ion beam (FIB) is used to prepare the sections. Next, the cross-section of the through-electrode substrate is observed. In the TEM image of the through-electrode substrate, as illustrated in Figure 2(a), line analysis is performed perpendicular to the interface between the substrate 2 and the adhesion layer 3a, i.e., in the direction of arrow C, to measure the amount of silicon and the amount of metal elements. Silicon can be considered as silicon contained in the substrate. Metal elements are metal elements that constitute the metal, alloy, or metal oxide contained in the adhesion layer. When the amount of metallic elements in the adhesion layer is set to 100%, the diffusion thickness is defined as the distance perpendicular to the interface between the substrate and the adhesion layer from the interface to the point where the amount of metallic elements initially reaches 20%. The unit of the amount of metallic elements is atomic%. The above measurement is performed 10 times, and the arithmetic mean of the measured diffusion thickness is defined as the average diffusion thickness. Details of the measurement method and measurement conditions are described in the examples below.

[0024] The average diffusion thickness mentioned above can be adjusted by the heating temperature during the formation of the adhesion layer. Lower heating temperatures tend to result in a thinner average diffusion thickness. The heating temperature during adhesion layer formation will be discussed later.

[0025] 2.First wiring layer The first wiring layer in this disclosure is arranged on the first surface of the substrate and has, in order from the substrate side, an adhesion layer and a conductive layer. Preferably, the first wiring layer is in direct contact with the substrate.

[0026] In this disclosure, as described above, by ensuring that the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is below a predetermined value, short circuits between the first wiring layers can be suppressed even when the distance between the first wiring layers is narrow. The distance between the first wiring layers is, for example, 50 nm or less, and may also be 20 nm or less. This disclosure is useful when the distance between the first wiring layers is as narrow as described above. On the other hand, the distance between the first wiring layers is, for example, 10 nm or more. "Distance between first wiring layers" refers to the shortest distance d from the end of one first wiring layer 4 to the end of an adjacent first wiring layer 4, as shown in Figure 1, for example.

[0027] (1) Adhesion layer The adhesion layer constituting the first wiring layer contains a metal, alloy, or metal oxide. The material of the adhesion layer is not particularly limited as long as it adheres to a silicon-containing substrate. As mentioned above, it is preferable that the heating temperature during adhesion layer formation be low, so it is preferable that the material of the adhesion layer be a material that can be formed by a method with a low heating temperature. As will be described later, examples of methods for forming an adhesion layer with a low heating temperature include atomic layer deposition (ALD) and plasma CVD. Therefore, it is preferable that the material of the adhesion layer be a material that can be formed by the ALD method or plasma CVD. Specifically, examples of materials for the adhesion layer include titanium oxide, tantalum oxide, aluminum oxide, zinc oxide, and magnesium oxide. Among these, it is preferable that the adhesion layer contains titanium oxide. This can improve adhesion to the substrate. In addition, titanium oxide has excellent adhesion to the metal constituting the conductive layer, especially copper. Furthermore, titanium oxide has excellent oxidation resistance.

[0028] The thickness of the adhesion layer is not particularly limited as long as it is a thickness that provides adhesion to the silicon-containing substrate. For example, the thickness of the adhesion layer is preferably 5 nm or more, more preferably 8 nm or more, and even more preferably 10 nm or more. If the thickness of the adhesion layer is within the above range, adhesion to the substrate can be improved. On the other hand, for example, the thickness of the adhesion layer is preferably 100 nm or less, more preferably 60 nm or less, and even more preferably 40 nm or less. If the thickness of the adhesion layer is within the above range, it is easier to ensure the conductivity of the entire first wiring layer. In addition, disconnection due to stress can be mitigated. Furthermore, it is possible to suppress the adhesion layer formation time from becoming too long. Specifically, the thickness of the adhesion layer is preferably 5 nm or more and 100 nm or less, more preferably 8 nm or more and 60 nm or less, and even more preferably 10 nm or more and 40 nm or less.

[0029] In this specification, the thickness of each layer is measured based on cross-sectional images of the through-electrode substrate taken using a scanning electron microscope (SEM). The thickness is the arithmetic mean of the thicknesses at any five locations.

[0030] As described above, the method for forming the adhesion layer is preferably one with a low heating temperature, such as atomic layer deposition (ALD) or plasma CVD. Furthermore, when forming the adhesion layer, annealing may be performed after film formation. The heating temperature during adhesion layer formation is preferably, for example, 350°C or lower, more preferably 300°C or lower, and even more preferably 200°C or lower. By using a heating temperature within the above range, the average diffusion thickness can be reduced. On the other hand, the heating temperature during adhesion layer formation is, for example, 30°C or higher. The heating temperature during adhesion layer formation includes the film formation temperature and the annealing temperature.

[0031] (2) conductive layer The material of the conductive layer constituting the first wiring layer is not particularly limited as long as it is a conductive material, and examples include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys containing these metals. Among these, it is more preferable for the conductive layer to contain copper.

[0032] The conductive layer may be a single layer or a multilayer formed by stacking multiple layers. For example, the conductive layer may have a seed layer and a plating layer in that order from the adhesion layer side. The material of the seed layer can be appropriately selected from materials used for seed layers in general plating methods. Examples of seed layer materials include the conductive layer material described above. Furthermore, as the material of the plating layer, a conductive material that adheres to the seed layer is preferred, and examples of the conductive layer material described above include the plating layer material.

[0033] The thickness of the conductive layer is, for example, 0.5 μm to 30 μm, but may also be 1 μm to 20 μm, or 3 μm to 10 μm. If the thickness of the conductive layer is within the above range, the conductivity of the entire first wiring layer can be ensured. In addition, disconnection due to stress caused by heating processes, etc., can be mitigated.

[0034] Methods for forming the conductive layer include, for example, PVD methods such as vacuum deposition and sputtering, CVD methods, and plating methods.

[0035] 3.Through electrode The through-electrode in this disclosure is disposed within a through-hole in a substrate and has an adhesion layer and a conductive layer in that order from the side wall side of the through-hole. The through-electrode is also in contact with a portion of the first wiring layer. As will be described later, if the through-electrode substrate further has a second wiring layer disposed on the second surface of the substrate, the through-electrode substrate is also in contact with a portion of the second wiring layer.

[0036] The through-electrode only needs to be able to electrically connect the first and second surfaces of the substrate, and its form is not particularly limited. The form of the through-electrode may be, for example, a through-electrode that fills a through-hole, a so-called filled via, or a through-electrode placed only on the side wall of the through-hole, a so-called conformal via. Furthermore, if the through-electrode is a conformal via, a hollow portion may be placed inside the through-hole 2h as illustrated in Figure 1, or the inside of the through-hole 2h may be filled with a resin portion 3c as illustrated in Figure 4.

[0037] (1) Adhesion layer The adhesion layer constituting the through electrode contains a metal, alloy, or metal oxide. Since the adhesion layer constituting the through electrode is the same as the adhesion layer constituting the first wiring layer described above, a detailed explanation is omitted here.

[0038] Since the through-electrode is in contact with a portion of the first wiring layer and a portion of the second wiring layer, it is preferable that the adhesion layer constituting the through-electrode is the same as the adhesion layer constituting the first wiring layer or the adhesion layer constituting the second wiring layer.

[0039] (2) conductive layer The conductive layer constituting the through-electrode is the same as the conductive layer constituting the first wiring layer described above, so its explanation is omitted here.

[0040] Since the through-electrode is in contact with a portion of the first wiring layer and a portion of the second wiring layer, it is preferable that the conductive layer constituting the through-electrode is the same as the conductive layer constituting the first wiring layer or the conductive layer constituting the second wiring layer.

[0041] (3) Resin part When the through-electrode is a conformal via and the through-hole is filled with a resin portion, examples of materials for the resin portion include epoxy resin, acrylic resin, polyimide, polyamide, and polyester.

[0042] 4. Circuit board The substrate in this disclosure contains silicon, has a first surface and a second surface opposite to the first surface, and has through holes that penetrate the substrate in the thickness direction.

[0043] Examples of silicon-containing substrates include glass substrates and silicon substrates.

[0044] Among these, glass substrates are preferred. Glass substrates have excellent optical properties such as flatness, dimensional stability, heat resistance, insulation, and transparency. Furthermore, because glass substrates have good flatness, fine wiring can be formed at a narrow pitch. In addition, since the coefficient of thermal expansion of glass substrates can be adjusted by their composition, a glass substrate with a preferred coefficient of thermal expansion can be selected. Examples of glass used for glass substrates include alkali-free glass and quartz.

[0045] Furthermore, if the substrate is a silicon substrate, the substrate has an insulating film on the first surface, the second surface, and the side walls of the through-holes. Silicon oxide is an example of a material for the insulating film.

[0046] The planar shape of the substrate is not particularly limited and can include, for example, rectangles or squares.

[0047] The plan view shape of the through-hole in the substrate is, for example, approximately circular. The cross-sectional shape of the through-hole 2h in the substrate 2 can be, for example, a straight shape as shown in Figure 1, an inverse tapered shape as shown in Figure 3(a) where the opening diameter on the first surface 2a side is larger than the opening diameter on the second surface 2b side, a forward tapered shape as shown in Figure 3(b) where the opening diameter on the first surface 2a side is smaller than the opening diameter on the second surface 2b side, an hourglass shape as shown in Figure 3(c) which includes a portion where the diameter is smallest at a predetermined position between the first surface 2a and the second surface 2b, or a bowing shape as shown in Figure 3(d) where the diameter is largest at a predetermined position between the first surface 2a and the second surface 2b. Figures 3(a) to 3(d) are schematic cross-sectional views illustrating the cross-sectional shapes of the through-hole in the substrate.

[0048] The substrate thickness is, for example, 100 μm or more, but may also be 200 μm or more, 300 μm or more, or 400 μm or more. By having the substrate thickness within the above range, excessive substrate deflection can be suppressed. This prevents difficulties in handling the substrate during the manufacturing process, and prevents the substrate from warping due to internal stresses such as thin films placed on the first or second surface of the substrate. On the other hand, the substrate thickness is, for example, 2000 μm or less, but may also be 1000 μm or less, or 800 μm or less. If the substrate thickness is within the above range, the time required for the process of forming through holes in the substrate can be shortened. Specifically, the substrate thickness is 100 μm or more and 2000 μm or less, but may also be 200 μm or more and 1000 μm or less, 300 μm or more and 1000 μm or less, or 400 μm or more and 800 μm or less.

[0049] 5.Second wiring layer The through-electrode substrate in this disclosure may further have a second wiring layer 5 disposed on the second surface 2a of the substrate 2, as illustrated in Figure 4. The second wiring layer 5 has, in order from the substrate 2 side, an adhesion layer 5a and a conductive layer 5b. It is preferable that the second wiring layer is in direct contact with the substrate.

[0050] The adhesion layer and conductive layer constituting the second wiring layer are the same as those constituting the first wiring layer described above, so their explanation is omitted here.

[0051] The adhesion layer constituting the first wiring layer and the adhesion layer constituting the second wiring layer may be the same or different from each other. Furthermore, the conductive layer constituting the first wiring layer and the conductive layer constituting the second wiring layer may be the same or different from each other.

[0052] 6. First Wiring Stack The through-electrode substrate in this disclosure may have a first wiring laminate on the side of the substrate facing the first wiring layer, having one or more first insulating layers and one or more third wiring layers. In Figure 5, the through-electrode substrate 1 further comprises a first wiring laminate 10 on the side of the substrate 2 facing the first wiring layer 3, having a first insulating layer 11, a third wiring layer 12, and vias 13. The through-electrode 3 and the third wiring layer 12 are electrically connected via the vias 13.

[0053] (1) First insulating layer The material of the first insulating layer is preferably an insulating resin, and photosensitive resins and thermosetting resins commonly used for insulating layers can be used. If the first wiring laminate has multiple first insulating layers, the materials of the multiple first insulating layers may be the same or different.

[0054] The number of layers in the first insulating layer included in the first wiring laminate is one or more, may be two or more, three or more, or four or more. On the other hand, the number of layers m of the first insulating layer is preferably 10 or less, may be eight or less, or seven or less. Too many layers in the first insulating layer is disadvantageous in terms of cost.

[0055] The thickness of the first insulating layer is, for example, 1.5 μm or more, and may be 2.5 μm or more. On the other hand, the thickness of the first insulating layer is, for example, 30 μm or less. The thickness of the first insulating layer is, for example, 1.5 μm or more and 30 μm or less, and may be 2.5 μm or more and 30 μm or less. When the first wiring laminate has two or more first insulating layers, the thickness of the first insulating layer here is the sum of the thicknesses of each first insulating layer.

[0056] Methods for forming the first insulating layer include, for example, a method for forming a first insulating layer having openings by photolithography or screen printing, or a method for forming openings in the first insulating layer by laser processing.

[0057] (2) Third wiring layer The third wiring layer is preferably electrically connected to the through-electrode.

[0058] The third wiring layer has at least a conductive layer. The third wiring layer may have only a conductive layer, or it may have a base layer and a conductive layer in that order from the substrate side. The conductive layer constituting the third wiring layer is the same as the conductive layer constituting the first wiring layer described above, so its explanation is omitted here.

[0059] The underlayment layer constituting the third wiring layer preferably has good adhesion to the first insulating layer. Examples of materials for the underlayment layer include titanium, nickel, palladium, chromium, tantalum, tungsten, gold, copper, molybdenum, aluminum, their alloys, and their oxides. In particular, the adhesion layer preferably contains titanium, a titanium alloy, or a titanium oxide. This can improve adhesion to the first insulating layer.

[0060] The thickness of the underlayment is preferably such that it adheres to the first insulating layer. For example, the thickness of the underlayment is preferably 5 nm to 100 nm, more preferably 8 nm to 60 nm, and even more preferably 10 nm to 40 nm. If the thickness of the underlayment is within the above range, adhesion to the first insulating layer can be improved. Also, if the thickness of the underlayment is within the above range, it is easier to ensure the conductivity of the entire third wiring layer. Furthermore, it is possible to mitigate wire breakage due to stress.

[0061] Methods for forming the underlying layer include, for example, PVD methods such as vacuum deposition and sputtering, and CVD methods.

[0062] The number of third wiring layers included in the first wiring laminate may be one or two or more. When the first wiring laminate has two or more third wiring layers, each third wiring layer is laminated in the thickness direction via the first insulating layer. In addition, each third wiring layer is electrically connected via vias.

[0063] The method for forming the third wiring layer may be an additive method, a semi-additive method, or a subtractive method.

[0064] The vias connecting each third wiring layer may be so-called filled vias that fill the openings in the first insulating layer, or so-called conformal vias that are positioned only on the side walls of the openings in the first insulating layer.

[0065] The material used for the via is not particularly limited as long as it is a conductive material; any conductive material commonly used for vias can be used, and it can be appropriately selected depending on the via's shape, formation method, etc.

[0066] The method for forming vias can be a general via formation method, and the appropriate method can be selected depending on the via shape and other factors.

[0067] 7. Second Wiring Stack The through-electrode substrate in this disclosure may have a second wiring laminate on the side of the substrate facing the second wiring layer, having one or more second insulating layers and one or more fourth wiring layers. In Figure 5, the through-electrode substrate 1 further comprises a second wiring laminate 20 on the side of the substrate 2 facing the second wiring layer 5, having a second insulating layer 21, a fourth wiring layer 22, and vias 23. The through-electrode 3 and the fourth wiring layer 22 are electrically connected via the vias 23.

[0068] The second insulating layer, fourth wiring layer, and vias constituting the second wiring laminate are the same as the first insulating layer, third wiring layer, and vias constituting the first wiring laminate, respectively, so their explanation is omitted here.

[0069] The number of layers of the first insulating layer in the first wiring laminate and the number of layers of the second insulating layer in the second wiring laminate may be the same or different, but it is preferable that they be the same. When using a large substrate, this can suppress substrate warping. Furthermore, it is preferable because the first insulating layer and the second insulating layer can be alternately laminated on the substrate during the manufacturing process of the through-electrode substrate.

[0070] 8.Applications The through-electrode substrate described herein can be used, for example, in semiconductor devices. Applications of semiconductor devices equipped with the through-electrode substrate are not limited to, but include, for example, notebook personal computers, tablet terminals, mobile phones, smartphones, digital video cameras, digital cameras, digital clocks, servers, car navigation systems, and home appliances.

[0071] This disclosure is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of this disclosure and achieves similar effects is included within the technical scope of this disclosure. [Examples]

[0072] [Example 1] A glass substrate with a thickness of 400 μm and through holes with a diameter of 130 μm was prepared. A titanium oxide layer was formed as an adhesion layer on the first and second surfaces of the glass substrate and on the inner walls of the through holes by atomic layer deposition (ALD). The thickness of the adhesion layer was 10 nm. Next, the adhesion layer was annealed at the temperatures shown in Table 1 below. Subsequently, a copper seed layer was formed on the adhesion layer by electroless copper plating. The thickness of the seed layer was 0.4 μm. Next, a resist pattern was formed on the seed layer using a dry film resist. The resist pattern was placed on the first surface 2a and the second surface 2b of the glass substrate 2 as shown in Figure 1. Next, an electrolytic copper plating process was performed to form a copper plating layer on the exposed parts of the seed layer. The resist pattern was peeled off and removed using a predetermined stripping solution. Next, the exposed parts of the seed layer and adhesion layer were removed using an etching solution. This resulted in a wiring layer having an adhesion layer and a conductive layer including the seed layer and the plating layer. Furthermore, a through-electrode was obtained that is a conformal via having an adhesion layer and a conductive layer including a seed layer and a plating layer. In this way, a through-electrode substrate was obtained.

[0073] [Example 2] A through-electrode substrate was fabricated in the same manner as in Example 1, except that the annealing temperature was changed.

[0074] [Comparative Example 1] A through-electrode substrate was fabricated in the same manner as in Example 1, except that the annealing temperature was changed.

[0075] [Comparative Example 2] A through-electrode substrate was fabricated in the same manner as in Example 1, except that the adhesion layer was formed as described below. A zinc oxide layer was formed as the adhesion layer by a sol-gel method using an ethanol solution containing zinc acetate dihydrate, praseodymium acetate, and diethanolamine. Subsequently, the adhesion layer was annealed at the temperatures shown in Table 1 below. The thickness of the adhesion layer was 10 nm.

[0076] [evaluation] (1) Average diffusion thickness of metal atoms contained in the adhesion layer into the substrate In the fabrication of the through-electrode substrate described above, the sample with the adhesion layer formed was used for measurement. Cross-sections of the glass substrate and adhesion layer were taken at the through-hole in the glass substrate. Specifically, the sample was embedded and fixed, and sections were prepared. A focused ion beam (FIB) was used to prepare the sections. Next, the cross-sections of the glass substrate and adhesion layer were observed by TEM, and the amounts of silicon and titanium were measured by TEM-EDX (energy-dispersive X-ray spectroscopy). JEOL Ltd.'s "JEM-ARM200F" and "JED-2300T" were used for TEM observation and EDX measurement. The detection limit was approximately 1 atomic%. The measurement conditions are shown below.

[0077] <Measurement conditions> • Acceleration voltage: 200kV • Measurement mode: STEM mode • Spot diameter: 0.16nm ·Measurement interval: 1nm

[0078] During TEM observation and EDX measurement, line analysis was performed perpendicular to the interface between the substrate 2 and the adhesion layer 3a, i.e., in the direction of arrow C, as illustrated in Figure 2(a). Silicon was considered to be silicon contained in the glass substrate. When the amount of Ti in the adhesion layer was set to 100%, the diffusion thickness was defined as the distance from the interface between the glass substrate and the adhesion layer to the position where the amount of Ti initially reached 20%, perpendicular to the interface between the glass substrate and the adhesion layer. The above measurement was performed 10 times, and the arithmetic mean of the measured diffusion thicknesses was defined as the average diffusion thickness.

[0079] (2) Reliability In forming the wiring layers of the above-described through-electrode substrate, the wiring layers were formed so that multiple linear wiring layers were arranged in parallel in a plan view. The width of the wiring layers was 50 nm, the thickness of the conductive layer including the seed layer and plating layer was 50 nm, and the distance between wirings was 30 nm. The electrical resistance between one arbitrary wiring layer located near the center and one wiring layer adjacent to it was measured. Specifically, a two-terminal digital ultra-high resistance / micro-current meter (ADC Corporation "5451") was used, with one terminal in contact with an arbitrary wiring layer located near the center and the other terminal in contact with one wiring layer adjacent to it, and the electrical resistance was measured. The electrical resistance was 1 × 10⁻⁶ 12 A value of Ω·cm or higher is considered "good," 1 × 10 6 A value of Ω·cm or less was considered "defective."

[0080] [Table 1]

[0081] As shown in Table 1, it was confirmed that high reliability can be obtained when the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is within a predetermined range.

[0082] This disclosure provides the following inventions. [1] A substrate having a first surface and a second surface opposite the first surface, having through holes, and containing silicon, A through electrode placed inside the above-mentioned through hole, A first wiring layer arranged on the first surface of the above substrate, A through-electrode substrate having, The above-mentioned through electrode is in contact with a part of the first wiring layer. The through electrode has, in order from the side wall side of the through hole, an adhesion layer and a conductive layer. The first wiring layer has, in order from the substrate side, an adhesion layer and a conductive layer. The above-mentioned adhesive layer contains a metal, alloy, or metal oxide. A through-electrode substrate in which the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is 2 nm or more and 10 nm or less. [2] The through-electrode substrate according to [1], wherein the substrate is a glass substrate. [3] The above-mentioned adhesion layer comprises titanium oxide, as described in [1] or [2], a through-electrode substrate. [4] The conductive layer is a through-electrode substrate according to any one of [1] to [3]. [5] The through-electrode substrate has a second wiring layer arranged on the second surface of the substrate, The above-mentioned through electrode is in contact with a part of the second wiring layer. The above-mentioned second wiring layer has, in order from the substrate side, an adhesion layer and a conductive layer. The through-electrode substrate according to any one of [1] to [4], wherein the adhesion layer of the second wiring layer comprises a metal, an alloy, or a metal oxide. [6] The through-electrode substrate is arranged on the surface of the substrate facing the first wiring layer and has a first wiring laminate having one or more first insulating layers and one or more third wiring layers. The above-mentioned third wiring layer has, in order from the substrate side, an underlayment layer and a conductive layer. The above-mentioned underlayer contains titanium, and is a through-electrode substrate according to any one of [1] to [5]. [7] The through-electrode substrate is arranged on the side of the substrate facing the second wiring layer and has a second wiring laminate having one or more second insulating layers and one or more fourth wiring layers. The above fourth wiring layer has, in order from the substrate side, an underlayment layer and a conductive layer. The above-mentioned underlayer is a through-electrode substrate as described in [5], containing titanium. [Explanation of Symbols]

[0083] 1 ... Through-electrode substrate 2… Circuit board 2a… First side of the circuit board 2b… ​​Second side of the circuit board 2h… Through hole 3 … Through electrode 4 … First wiring layer 5 … Second wiring layer 3a, 4a, 5a… Close-packed layers 3b, 4b, 5b… conductive layers 10… First wiring stack 11… First Absolute Layer 12… Third wiring layer 20… Second wiring stack 21… Second Absolute Layer 22… Fourth wiring layer 13, 23…ビア

Claims

1. A substrate having a first surface and a second surface opposite the first surface, having through holes, and containing silicon, A through electrode placed inside the through hole, A first wiring layer disposed on the first surface of the substrate, A through-electrode substrate having, The through electrode is in contact with a part of the first wiring layer, The through electrode has, in order from the side wall side of the through hole, an adhesion layer and a conductive layer, The first wiring layer has, in order from the substrate side, an adhesion layer and a conductive layer. The aforementioned adhesion layer contains a metal, alloy, or metal oxide. A through-electrode substrate in which the average diffusion thickness of metal atoms contained in the adhesion layer into the substrate is 2 nm or more and 10 nm or less.

2. The through-electrode substrate according to claim 1, wherein the substrate is a glass substrate.

3. The through-electrode substrate according to claim 1, wherein the adhesion layer contains titanium oxide.

4. The through-electrode substrate according to claim 1, wherein the conductive layer contains copper.

5. The through-electrode substrate has a second wiring layer disposed on the second surface of the substrate, The through electrode is in contact with a part of the second wiring layer, The aforementioned second wiring layer has, in order from the substrate side, an adhesion layer and a conductive layer, The through-electrode substrate according to claim 1, wherein the adhesion layer of the second wiring layer comprises a metal, an alloy, or a metal oxide.

6. The through-electrode substrate is disposed on the surface of the substrate facing the first wiring layer and has a first wiring laminate having one or more first insulating layers and one or more third wiring layers. The third wiring layer has, in order from the substrate side, an underlayment layer and a conductive layer. The through-electrode substrate according to claim 1, wherein the underlying layer contains titanium.

7. The through-electrode substrate is arranged on the side of the substrate facing the second wiring layer and has a second wiring laminate having one or more second insulating layers and one or more fourth wiring layers. The fourth wiring layer has, in order from the substrate side, an underlayment layer and a conductive layer. The through-electrode substrate according to claim 5, wherein the underlying layer contains titanium.

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