Semiconductor device and method for manufacturing the same
Patent Information
- Application Number
- JP2026020918
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-02-12
- Publication Date
- 2026-04-16
AI Technical Summary
【0009】 このように、上記の製造方法では、クラックを形成する際に、分割予定線(溝)に隣接して伸びる突起部が形成される。このため、分割予定線に沿って半導体ウェハ及び金属層を分割すると、分割後の金属層の主表面には、その外周縁に沿って一巡する突起部が設けられることとなる。したがって、この製造方法により製造された半導体装置では、金属層を対象部材にはんだ接合するときに、突起部によりはんだが塞き止められ、金属層よりも外周側まではんだが濡れ広がることが抑制される。また、金属層は、第1金属層と第2金属層の二層を含んでいるので、分割後の金属層は、その側面にはんだ濡れ性が低い第1金属層が露出した状態となる。したがって、この製造方法により製造された半導体装置では、仮にはんだが突起部を越えた場合であっても、金属層の側面でははんだが濡れ広がり難く、はんだが半導体基板の側面まで到達することが抑制される。以上の通り、この製造方法により製造された半導体装置では、濡れ性を確保しつつ、はんだの不要な濡れ広がりを抑制することができる。
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Figure 2026066356000001_ABST
Abstract
Claims
1. A semiconductor substrate (12) and A metal layer (20) provided on the surface (12a) of the semiconductor substrate, Equipped with, The aforementioned metal layer The first metal layer (22, 24) and A second metal layer (26) covers the surface of the first metal layer and has higher solder wettability than the first metal layer, It has, The second metal layer is exposed on the main surface (20a) of the metal layer, The first metal layer is exposed on the side surface (20b) of the metal layer, A projection (30) is provided on the main surface of the metal layer. The projection extends in a circular manner along the outer edge of the main surface. Semiconductor device (10).
2. The semiconductor device according to claim 1, wherein the first metal layer is exposed with a width of 1 μm or more at the outer peripheral end of the projection.
3. The semiconductor device according to claim 1, wherein the height (h) of the projection is 1 / 2 or more of the thickness (t) of the metal layer.
4. The semiconductor device according to claim 1, wherein the side surface (12c) of the semiconductor substrate is a cleavage plane.
5. The first metal layer is a nickel layer and / or a titanium layer. The semiconductor device according to claim 1, wherein the second metal layer is a gold layer.
6. The semiconductor device according to claim 1, wherein the projection has undulations along the outer edge of the main surface.
7. The semiconductor device according to claim 1, wherein the protrusions are formed intermittently along the outer edge of the main surface.
8. A method for manufacturing a semiconductor device, A step comprising pressing a pressing member (60) against the main surface (20a) of a metal layer (20) formed on the first surface (2a) of a semiconductor wafer (2) along a planned division line (4), thereby deforming the metal layer along the planned division line to form a groove extending along the planned division line and a projection (30) extending adjacent to the groove, and forming a crack (5) in the semiconductor wafer along the planned division line and extending in the thickness direction of the semiconductor wafer, wherein the metal layer comprises a first metal layer (22, 24) and a second metal layer (26) which has higher solder wettability than the first metal layer, covers the surface of the first metal layer and is exposed to the main surface of the metal layer, and After the step of forming the crack, the semiconductor wafer is divided along the planned division line by pressing the dividing member (62) against the second surface (2b) of the semiconductor wafer located on the opposite side of the first surface along the planned division line. A manufacturing method that includes the following features.
9. The pressing member is a scribing wheel, Pressing the aforementioned pressing member against the surface causes the scribing wheel to roll. The manufacturing method according to claim 8, wherein in the step of forming the crack, a scribe line is formed on the first surface along the planned division line, accompanied by the crack extending in the thickness direction of the semiconductor wafer.
10. The first metal layer is a gold layer. The manufacturing method according to claim 8, wherein the second metal layer is a nickel layer and / or a titanium layer.
Citation Information
Patent Citations
Manufacturing method of semiconductor device
JP2004241623A