Display device and method for manufacturing a display device

Abstract

Improve the quality of the display. [Solution] According to one embodiment, the display device comprises a first display element configured to display a first color, a second display element configured to display a second color different from the first color, a third display element configured to display a third color different from the first and second colors, a partition wall formed in an overhang shape that surrounds the first display element, the second display element, and the third display element, a first sealing layer that covers the first display element and extends above the partition wall, a second sealing layer that covers the second display element and extends above the partition wall, and a third sealing layer that covers the third display element and extends above the partition wall, wherein the distance between the second sealing layer and the third sealing layer is greater than the distance between the first sealing layer and the third sealing layer, and no reflective layer is arranged between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, and between the partition wall and the third sealing layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving display quality are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device and a method for manufacturing the display device capable of improving display quality.

Means for Solving the Problems

[0005] According to an embodiment, the display device is The device comprises a substrate, an inorganic insulating layer disposed above the substrate, a first display element configured to display a first color, a second display element configured to display a second color different from the first color, a third display element configured to display a third color different from the first and second colors, a partition wall disposed on the inorganic insulating layer, having conductivity, surrounding the first display element, the second display element, and the third display element, respectively, and formed in an overhanging manner, a first sealing layer covering the first display element and extending above the partition wall, a second sealing layer covering the second display element and extending above the partition wall, and a third sealing layer covering the third display element and extending above the partition wall, wherein the distance between the second sealing layer and the third sealing layer is greater than the distance between the first sealing layer and the third sealing layer, and no reflective layer is disposed between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, and between the partition wall and the third sealing layer.

[0006] According to the embodiment, the display device is The display comprises a substrate, an inorganic insulating layer disposed above the substrate, a conductive partition wall disposed above the inorganic insulating layer and formed in an overhang shape, and a plurality of pixels arranged in a matrix in a first and second direction, each of the plurality of pixels configured to display a first color and surrounded by the partition wall, a second display element configured to display a second color different from the first color and surrounded by the partition wall, a third display element configured to display a third color different from the first and second colors and surrounded by the partition wall, and covering the first display element and above the partition wall The device comprises an extended first sealing layer, a second sealing layer covering the second display element and extending above the partition wall, and a third sealing layer covering the third display element and extending above the partition wall, wherein the third sealing layer is located between the two first sealing layers in the first direction, the distance between one first sealing layer and the third sealing layer in the first direction is greater than the distance between the other first sealing layer and the third sealing layer in the first direction, and no reflective layer is provided between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, and between the partition wall and the third sealing layer.

[0007] According to the embodiment, the method for manufacturing the display device is: A processing substrate is prepared, comprising a first lower electrode, a second lower electrode, and a third lower electrode above the substrate, and overhanging partition walls surrounding the first lower electrode, the second lower electrode, and the third lower electrode, respectively. A first laminated film including a first organic layer, a first upper electrode, and a first cap layer is formed on the first lower electrode, and a first sealing layer is formed on the first laminated film. A second laminated film including a second organic layer, a second upper electrode, and a second cap layer is formed on the second lower electrode, and a second sealing layer is formed on the second laminated film. A third laminated film including a third organic layer, a third upper electrode, and a third cap layer is formed on the second sealing layer, the partition wall, and the third lower electrode; a third sealing layer is formed on the third laminated film; a resist patterned to a predetermined shape is formed on the third sealing layer; the third sealing layer and the third laminated film are patterned using the resist as a mask; the resist is formed such that the distance from the resist to the edge of the second sealing layer is greater than the distance from the resist to the edge of the first sealing layer. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX. [Figure 3] Figure 3 is a diagram illustrating one example of a pixel PX configuration. [Figure 4] Figure 4 shows an example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 5] Figure 5 is a schematic cross-sectional view of the DSP display device along line AB in Figure 4. [Figure 6A] Figure 6A is a diagram illustrating the manufacturing method of a display device DSP. [Figure 6B]FIG. 6B is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6C] FIG. 6C is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6D] FIG. 6D is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6E] FIG. 6E is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6F] FIG. 6F is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6G] FIG. 6G is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6H] FIG. 6H is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6I] FIG. 6I is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6J] FIG. 6J is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6K] FIG. 6K is a diagram for explaining a manufacturing method of the display device DSP. [Figure 6L] FIG. 6L is a diagram for explaining a manufacturing method of the display device DSP. [Figure 7A] FIG. 7A is a diagram for explaining a manufacturing method of a comparative example. [Figure 7B] FIG. 7B is a diagram for explaining a manufacturing method of a comparative example. [Figure 7C] FIG. 7C is a diagram for explaining a manufacturing method of a comparative example. [Figure 8] [Figure 9] FIG. 8 is a diagram showing another configuration example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 10] FIG. 9 is a diagram showing another configuration example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 11] ​Figure 11 shows another example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 12] Figure 12 shows another example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 13] Figure 13 shows another example of the layout of the sealing layers SE11, SE12, and SE13. [Figure 14] Figure 14 shows another example of the layout of the sealing layers SE11, SE12, and SE13. [Modes for carrying out the invention]

[0009] Embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing various elements parallel to the third direction Z is called a plan view. In addition, terms such as "up," "above," "between," and "opposite" refer to the positional relationship between two or more constituent elements, and include not only cases where the two or more constituent elements of an object are in direct contact, but also cases where they are separated from each other by gaps or other constituent elements. The positive direction of the Z axis will be referred to as "up" or "above."

[0011] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] Figure 1 shows an example configuration of a display device DSP.

[0013] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0014] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in plan view. However, the shape of the display area DA in plan view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0015] The display area DA comprises a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors from each other. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0016] Note that the rounded portion RD of the display area DA is a shape that is visible macroscopically, while microscopically it is a shape formed by the arrangement of multiple pixels PX in a stepped pattern.

[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0018] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. In the illustrated example, the scan line GL and power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0021] The display device DSP further includes a terminal section T located in the peripheral region SA. The terminal section T has multiple terminals and is electrically connected to, for example, an IC chip for driving a display element DE or a flexible circuit board.

[0022] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX.

[0023] In the illustrated example, sub-pixels SP2 and SP3 are aligned in the second direction Y, sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0024] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown.

[0025] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs.

[0026] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the apertures AP1, AP2, and AP3. Similar to the inorganic insulating layer 5, the partition wall 6 can also be said to have apertures OP1, OP2, and OP3 in the sub-pixels SP1, SP2, and SP3, respectively. Aperture OP1 overlaps with aperture AP1, aperture OP2 overlaps with aperture AP2, and aperture OP3 overlaps with aperture AP3. The partition wall 6 is conductive and is electrically connected to the common voltage terminal at the terminal section T shown in Figure 1.

[0027] The sub-pixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively.

[0028] The display element DE1 of the sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, organic layer OR1, and upper electrode UE1 constituting the display element DE1 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view.

[0029] The display element DE2 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, organic layer OR2, and upper electrode UE2 constituting the display element DE2 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view.

[0030] The sub-pixel SP3 display element DE3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, organic layer OR3, and upper electrode UE3 constituting the display element DE3 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown with dashed lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown with dotted lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown may not accurately reflect their actual shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode and are in contact with the partition wall 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0034] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. Note that the relative sizes of the areas of opening AP1, opening AP2, and opening AP3 are not limited to the illustrated example.

[0035] Figure 3 is a diagram illustrating one example of a pixel PX configuration.

[0036] In the sub-pixel SP1, the display element DE1 comprises a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, which includes the light-emitting layer EM1, is positioned between the lower electrode LE1 and the upper electrode UE1. The cap layer CP1 is positioned on top of the upper electrode UE1. The sealing layer SE11 is positioned on top of the cap layer CP1 and covers the display element DE1.

[0037] In the sub-pixel SP2, the display element DE2 comprises a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a cap layer CP2. The organic layer OR2, which includes the light-emitting layer EM2, is positioned between the lower electrode LE2 and the upper electrode UE2. The cap layer CP2 is positioned on top of the upper electrode UE2. The sealing layer SE12 is positioned on top of the cap layer CP2 and covers the display element DE2.

[0038] In the sub-pixel SP3, the display element DE3 comprises a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a cap layer CP3. The organic layer OR3, which includes the light-emitting layer EM3, is positioned between the lower electrode LE3 and the upper electrode UE3. The cap layer CP3 is positioned on top of the upper electrode UE3. The sealing layer SE13 is positioned on top of the cap layer CP3 and covers the display element DE3.

[0039] In the following explanation, a multilayer including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 may be referred to as multilayer film FL1, a multilayer including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 may be referred to as multilayer film FL2, and a multilayer including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 may be referred to as multilayer film FL3.

[0040] The light-emitting layers EM1, EM2, and EM3 are made of different materials. In one example, light-emitting layer EM1 is made of a material that emits light in the blue wavelength range, light-emitting layer EM2 is made of a material that emits light in the green wavelength range, and light-emitting layer EM3 is made of a material that emits light in the red wavelength range. In other words, display element DE1 is configured to display blue as the first color, display element DE2 is configured to display green as the second color, and display element DE3 is configured to display red as the third color.

[0041] Furthermore, the light-emitting layer EM1 may be formed from a material that emits light in the green wavelength range, and the light-emitting layer EM2 may be formed from a material that emits light in the blue wavelength range. In other words, the display element DE1 may be configured to display green as the first color, and the display element DE2 may be configured to display blue as the second color.

[0042] Figure 4 shows an example of the layout of the sealing layers SE11, SE12, and SE13.

[0043] Here, we show the four pixels PX1, PX2, PX3, and PX4 in the display area DA shown in Figure 1. Each of the pixels PX1, PX2, PX3, and PX4 has sub-pixels SP1, SP2, and SP3 in the layout shown in Figure 2.

[0044] Pixels PX1 and PX2 are aligned in the first direction X, and pixels PX3 and PX4 are aligned in the first direction X. Pixels PX1 and PX3 are aligned in the second direction Y, and pixels PX2 and PX4 are aligned in the second direction Y.

[0045] In each of the pixels PX1, PX2, PX3, and PX4, the display element DE1 of sub-pixel SP1 is covered with the sealing layer SE11, the display element DE2 of sub-pixel SP2 is covered with the sealing layer SE12, and the display element DE3 of sub-pixel SP3 is covered with the sealing layer SE13.

[0046] The sealing layer SE11 is positioned at the opening OP1 of the partition wall 6 that overlaps the display element DE1, and extends further above the partition wall 6. The sealing layer SE12 is positioned at the opening OP2 of the partition wall 6 that overlaps the display element DE2, and extends further above the partition wall 6. The sealing layer SE13 is positioned at the opening OP3 of the partition wall 6 that overlaps the display element DE3, and extends further above the partition wall 6. The edges of each sealing layer SE11, SE12, and SE13 are generally located above the partition wall 6.

[0047] A slit-shaped region ST is formed between pixel PX1 and pixel PX2, and between pixel PX3 and pixel PX4, where none of the sealing layers SE11, SE12, and SE13 are provided. The partition wall 6 is exposed from the sealing layers SE11, SE12, and SE13 in region ST.

[0048] Now, let's focus on pixel PX4.

[0049] The sealing layers SE11 and SE13 are aligned in the first direction X, and the sealing layers SE12 and SE13 are aligned in the second direction Y. As shown in the diagram, the distance between sealing layer SE12 and sealing layer SE13 along the second direction Y is greater than the distance between sealing layer SE11 and sealing layer SE13 along the first direction X.

[0050] In a plan view, the sealing layer SE13 is formed in a rectangular shape extending in a first direction X, and has a pair of edges E1 and E3 extending in a second direction Y, and a pair of edges E2 and E4 extending in the first direction X. Edge E1 is close to the sealing layer SE11 and may be in contact with it. Edge E2 is spaced apart from the sealing layer SE12. In other words, the slit-shaped region ST extends between edge E2 and the sealing layer SE12. When edge E1 is spaced apart from the sealing layer SE11, the slit-shaped region ST also extends between edge E1 and the sealing layer SE11.

[0051] We focus on pixels PX3 and PX4, which are adjacent to the first direction X.

[0052] The sealing layer SE13 of pixel PX4 is located between the sealing layer SE11 of pixel PX3 and the sealing layer SE11 of pixel PX4 in the first direction X. The edge E3 of the sealing layer SE13 is spaced apart from the sealing layer SE11 of pixel PX3. The slit-shaped region ST extends between the edge E3 and the sealing layer SE11. As shown, the distance between the sealing layer SE11 of pixel PX3 and the sealing layer SE13 of pixel PX4 along the first direction X is greater than the distance between the sealing layer SE11 of pixel PX4 and the sealing layer SE13 of pixel PX4 along the first direction X.

[0053] We focus on pixels PX2 and PX4, which are adjacent in the second direction Y.

[0054] The sealing layer SE13 of pixel PX4 is located between the sealing layer SE12 of pixel PX2 and the sealing layer SE12 of pixel PX4 in the second direction Y. The edge E4 of the sealing layer SE13 is spaced apart from the sealing layer SE12 of pixel PX3. The slit-shaped region ST extends between the edge E4 and the sealing layer SE12.

[0055] As shown in the illustrated example, slit-shaped regions ST extend around the sealing layer SE13 of pixel PX4 between edge E2 and sealing layer SE12, between edge E3 and sealing layer SE11, and between edge E4 and sealing layer SE12. Similarly, slit-shaped regions ST are formed along the three edges of the sealing layer SE13 of the other pixels.

[0056] Figure 5 is a schematic cross-sectional view of the DSP display device along line AB in Figure 4.

[0057] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, various wirings such as scan lines GL, signal lines SL, and power lines PL, and various insulating layers.

[0058] The organic insulating layer 12 is placed on top of the circuit layer 11. The organic insulating layer 12 is formed, for example, to flatten the irregularities caused by the circuit layer 11.

[0059] The lower electrode LE1 of sub-pixel SP1, LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are arranged on the organic insulating layer 12 and spaced apart from each other.

[0060] The inorganic insulating layer 5 is placed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps the lower electrode LE1, the aperture AP2 overlaps the lower electrode LE2, and the aperture AP3 overlaps the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the organic insulating layer 12. Note that the contact holes of the organic insulating layer 12 are not shown in the illustration.

[0061] The partition wall 6 is formed in an overhang shape and comprises a conductive lower part 61 placed on the inorganic insulating layer 5 and an upper part 62 placed on the lower part 61.

[0062] In the illustrated example, the lower part 61 comprises a bottom layer 63 placed on top of the inorganic insulating layer 5, and an axial layer 64 placed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a greater width than the axial layer 64. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0063] The upper section 62 is positioned on top of the axial layer 64. The upper section 62 has a greater width than the axial layer 64. Both ends of the upper section 62 protrude from the sides of the axial layer 64. In this specification, the sides of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper section 62. In the illustrated example, the upper section 62 has a greater width than the bottom layer 63. The bottom layer 63 may also have a greater width than the upper section 62.

[0064] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0065] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0066] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0067] Furthermore, contact between each of the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper part 62.

[0068] Cap layer CP1 is placed on top of upper electrode UE1. Cap layer CP2 is placed on top of upper electrode UE2. Cap layer CP3 is placed on top of upper electrode UE3. Cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the efficiency of light extraction from organic layers OR1, OR2, and OR3, respectively. Note that cap layers CP1, CP2, and CP3 may be omitted.

[0069] The sealing layer SE11 is positioned on top of the cap layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE11 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE1.

[0070] The sealing layer SE12 is positioned on top of the cap layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE12 is in contact with the axial layer 64 and upper layer 62 of the partition wall 6 surrounding the display element DE2.

[0071] The sealing layer SE13 is positioned on top of the cap layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. The sealing layer SE13 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE3.

[0072] The sealing layers SE11, S12, and SE13 each extend above the partition wall 6. Furthermore, the edges of the sealing layers SE11, SE12, and SE13 are located above the partition wall 6.

[0073] In the illustrated example, above the partition wall 6 between sub-pixels SP1 and SP3, the sealing layer SE13 is close to the sealing layer SE11 and rises up near the edge of the sealing layer SE11. The sealing layer SE13 may also be in contact with the sealing layer SE11. Furthermore, above the partition wall 6 between sub-pixels SP2 and SP3, the sealing layer SE13 is separated from the sealing layer SE12. The distance L32 between sealing layer SE13 and sealing layer SE12 is greater than the distance L31 between sealing layer SE13 and sealing layer SE11 (L32 > L31). The distance L32 is more than 10 times the distance L31. In one example, the distance L32 is 5 μm or more, and the distance L31 is 0.5 μm or less.

[0074] No reflective layers are placed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, or between the sealing layer SE13 and the partition wall 6. Here, a reflective layer refers to a thin film capable of reflecting ambient light, such as a metal layer or a dielectric multilayer film.

[0075] None of the laminated films FL1, FL2, and FL3 are positioned on the partition wall 6. Cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6.

[0076] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills the cavities formed between sealing layer SE11 and partition wall 6, between sealing layer SE12 and partition wall 6, and between sealing layer SE13 and partition wall 6.

[0077] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 is placed on top of the sealing layer SE2.

[0078] The inorganic insulating layer 5, sealing layers SE11, SE12, SE13, and sealing layer SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). In one example, the inorganic insulating layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride.

[0079] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is made of a titanium-based material, such as titanium or a titanium compound. The axial layer 64 is made of a different material from the bottom layer 63 and the upper part 62, and is made of an aluminum-based material, such as aluminum or an aluminum compound.

[0080] The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper part 62 is formed of a different material from the lower part 61. For example, the upper part 62 is a multilayer structure consisting of a first thin film located on the axial layer 64 and formed of a titanium-based material such as titanium or a titanium compound, and a second thin film located on the first thin film and formed of an oxide conductive material such as indium tin oxide (ITO). The second thin film has the function of suppressing the reflection of ambient light at the partition wall 6.

[0081] The lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a transparent layer formed from an oxide conductive material such as indium tin oxide (ITO), and a reflective layer formed from a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a reflective layer between a pair of transparent layers.

[0082] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Furthermore, each of organic layers OR1, OR2, and OR3 includes multiple functional layers such as hole injection layers, hole transport layers, electron blocking layers, hole blocking layers, electron transport layers, and electron injection layers.

[0083] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0084] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0085] None of the organic layers OR1, OR2, OR3, upper electrodes UE1, UE2, UE3, and cap layers CP1, CP2, CP3, which can serve as reflective layers, are located on the upper part 62 of the partition wall 6.

[0086] The illustrated circuit layer 11, organic insulating layer 12, inorganic insulating layer 5, and partition wall 6 are arranged across the display area DA and the surrounding area SA.

[0087] Next, the manufacturing method of the display device DSP will be described. Figures 6A to 6L are cross-sectional views of the processing substrate SUB along the AB line in Figure 4, with elements below the organic insulating layer 12 omitted.

[0088] First, a processing substrate SUB is prepared as shown in Figure 6A. The process of preparing the processing substrate SUB includes the steps of forming the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 on the organic insulating layer 12, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively, and forming an overhanging partition wall 6 having a lower part 61 located on the inorganic insulating layer 5 and an upper part 62 located on the lower part 61. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 having openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition wall 6 is formed.

[0089] Next, the display element DE1 is formed.

[0090] First, as shown in Figure 6B, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The laminated film FL1 is formed on the lower electrodes LE1, LE2, and LE3, as well as on the partition wall 6. The laminated film FL1 includes an organic layer OR1 containing an emissive layer EM1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed continuously in a vacuum environment in the deposition apparatus. The upper electrode UE1 is formed from a magnesium and silver alloy.

[0091] The multilayer film FL1 is divided by an overhanging partition wall 6. In other words, in the multilayer film FL1, the portions located above the lower electrodes LE1, LE2, and LE3 are separated from the portions located above the partition wall 6.

[0092] Next, as shown in Figure 6C, a sealing layer SE11 is formed that continuously covers the laminated film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0093] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and in the display area DA, they are located not only on the sub-pixel SP1 but also on the sub-pixels SP2 and SP3.

[0094] Next, as shown in Figure 6D, a resist R1 patterned to a predetermined shape is formed on the sealing layer SE11. The resist R1 overlaps the subpixel SP1 and a portion of the surrounding partition wall 6.

[0095] Next, as shown in Figure 6E, the sealing layer SE11 and the multilayer film FL1 are patterned using the resist R1 as a mask. By performing various etching processes using the resist R1 as a mask, the sealing layer SE11 exposed from the resist R1 is removed, and then the cap layer CP1, upper electrode UE1, and organic layer OR1 contained in the multilayer film FL1 are sequentially removed. Through this patterning, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0096] Next, as shown in Figure 6F, the resist R1 is removed. This forms the display element DE1 on the sub-pixel SP1. Also, the laminated film FL1 formed on the partition wall 6 is removed during the process from patterning the laminated film FL1 to removing the resist R1. Therefore, the laminated film FL1 including the upper electrode UE1 does not exist on the partition wall 6. A cavity GP is formed between the sealing layer SE11 and the partition wall 6.

[0097] Next, as shown in Figure 6G, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL2 is formed on the lower electrode LE2. The multilayer film FL2 includes an organic layer OR2 containing the light-emitting layer EM2, an upper electrode UE2, and a cap layer CP2. The light-emitting layer EM2 is formed from a different material than the light-emitting layer EM1. The upper electrode UE2 is formed from a magnesium and silver alloy, similar to the upper electrode UE1.

[0098] Next, a sealing layer SE12 is formed on the multilayer film FL2. Then, a resist is formed on the sealing layer SE12. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE12 and multilayer film FL2 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0099] As a result, the display element DE2 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed. Also, the multilayer film FL2 formed on the partition wall 6 is removed during the process from patterning of the multilayer film FL2 to the removal of the resist. Therefore, the multilayer film FL2 including the upper electrode UE2 does not exist on the partition wall 6. A cavity GP is formed between the sealing layer SE12 and the partition wall 6.

[0100] Next, as shown in Figure 6H, the display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, the laminated film FL3 is formed on the lower electrode LE3. At this time, the laminated film FL3 is also formed on the sealing layer SE11, the sealing layer SE12, and the partition wall 6. Since the laminated film FL3 is formed by vapor deposition using the partition wall 6 as a mask, it is divided by the overhanging partition wall 6. In other words, in the laminated film FL3, the portion located on the lower electrode LE3 is separated from the portion located on the partition wall 6.

[0101] The multilayer film FL3 includes an organic layer OR3 containing an emissive layer EM3, an upper electrode UE3, and a cap layer CP3. The emissive layer EM3 is formed from a different material than emissive layers EM1 and EM2, for example, a material that emits light in the red wavelength range. The upper electrode UE3 is formed from a magnesium-silver alloy, similar to the upper electrode UE1.

[0102] Subsequently, a sealing layer SE13 is formed on the multilayer film FL3 using the same method as for the sealing layer SE11.

[0103] Then, as shown in Figure 6I, a resist R3 patterned to a predetermined shape is formed on the sealing layer SE13. The resist R3 overlaps with the subpixel SP3 and a portion of the surrounding partition wall 6. At this time, the resist R3 is formed such that the distance from the resist R3 to the edge E12 of the sealing layer SE12 is greater than the distance from the resist R3 to the edge E11 of the sealing layer SE11. The resist R3 may overlap with the edge E11. On the other hand, the resist R3 is formed away from the edge E12.

[0104] Then, as shown in Figure 6J, the resist R3 is used as a mask to pattern the sealing layer SE13 and the multilayer film FL3. By performing various etchings using the resist R3 as a mask, the sealing layer SE13 exposed from the resist R3 is removed, and then the cap layer CP3, upper electrode UE3, and organic layer OR3 contained in the multilayer film FL3 are sequentially removed. Through this patterning, the sealing layer SE11 of the sub-pixel SP1 and the sealing layer SE12 of the sub-pixel SP2 are exposed. Because the resist R3 was formed away from the edge E12, a relatively wide slit-shaped region ST is formed between the sealing layer SE12 and the sealing layer SE13.

[0105] Then, as shown in Figure 6K, the resist R3 is removed. This forms the display element DE3 on the sub-pixel SP3.

[0106] Furthermore, the multilayer film FL3 formed on the partition wall 6 is removed by etching solution or etching gas that penetrates from a large area ST between the edge E2 of the sealing layer SE13 and the edge E12 of the sealing layer SE12 during the process from patterning of the multilayer film FL3 to removal of the resist R3. Therefore, the multilayer film FL3 including the upper electrode UE3 does not exist on the partition wall 6. A cavity GP is formed between the sealing layer SE13 and the partition wall 6.

[0107] In the above manufacturing process, we assumed that the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0108] Next, as shown in Figure 6L, an organic insulating material is applied to the sealing layers SE11, SE12, and SE13, and the resin layer RS1 is formed by curing the organic insulating material. At this time, the applied organic insulating material fills the cavities formed between the partition wall 6 and the sealing layer SE11, between the partition wall 6 and the sealing layer SE12, and between the partition wall 6 and the sealing layer SE13, respectively.

[0109] Next, an inorganic insulating material (e.g., silicon nitride) is deposited to form a sealing layer SE2. Then, an organic insulating material is applied and cured to form a resin layer RS2.

[0110] After the above steps, the DSP display device is completed.

[0111] As described above, during the process of forming the display element DE1, the laminated film FL1 formed on the partition wall 6 is exposed to the etching solution of wet etching or the etching gas of dry etching over its entire circumference. Therefore, the laminated film FL1 on the partition wall 6 is removed during the process of forming the display element DE1.

[0112] During the process of forming display element DE2 adjacent to display element DE1, the laminated film FL2 formed on the partition wall 6 is exposed to etching solution or etching gas, except for the edges adjacent to display element DE1. Therefore, the laminated film FL2 on the partition wall 6 is removed during the process of forming display element DE2.

[0113] In the process of forming display element DE3 adjacent to display elements DE1 and DE2, a slit-shaped region ST is formed between the sealing layer SE12 of display element DE2 and the sealing layer SE13 of display element DE3. As a result, the laminated film FL3 formed on the partition wall 6 is exposed to etching solution or etching gas that penetrates from region ST. The etching solution or etching gas spreads from region ST around the entire circumference of display element DE3. This allows the laminated film FL3 on the partition wall 6 to be removed.

[0114] Next, we will explain the comparative examples.

[0115] First, as explained with reference to Figures 6A to 6H, after forming the display elements DE1 and DE2, the laminated film FL3 and the sealing layer SE13 are formed.

[0116] Subsequently, as shown in Figure 7A, a resist R3 patterned to a predetermined shape is formed on the sealing layer SE13. The resist R3 overlaps with the subpixel SP3 and a portion of the surrounding partition wall 6. At this time, the resist R3 is formed to be close to the edge E11 of the sealing layer SE11 and the edge E12 of the sealing layer SE12.

[0117] Subsequently, as shown in Figure 7B, the resist R3 is used as a mask to pattern the encapsulation layer SE13 and the multilayer film FL3. At this time, because the resist R3 is close to the edges E11 and E12, a wide region ST as shown in Figure 6J is less likely to form between the encapsulation layer SE13 and the encapsulation layer SE11, and between the encapsulation layer SE13 and the encapsulation layer SE12.

[0118] Subsequently, the resist R3 is removed as shown in Figure 7C.

[0119] In this comparative example, during the process of forming the display element DE3 adjacent to the display elements DE1 and DE2, the gaps between the sealing layer SE11 and the sealing layer SE13, and the gaps between the sealing layer SE12 and the sealing layer SE13 are both small, making it difficult for etching solution or etching gas to penetrate. Therefore, the laminated film FL3 formed on the partition wall 6 is less likely to be exposed to etching solution or etching gas and is less likely to be removed. As shown in Figure 7C, if a portion of the laminated film FL3 remains on the partition wall 6, the reflective layer (e.g., upper electrode UE3) contained in the laminated film FL3 can reflect ambient light.

[0120] The laminated film FL1 does not exist on the partition wall 6 surrounding the display element DE1, and the laminated film FL2 does not exist on the partition wall 6 surrounding the display element DE2. However, a portion of the laminated film FL3 exists on the partition wall 6 surrounding the display element DE3. As a result, ambient light is reflected in localized areas of the display region DA, leading to a deterioration of display quality.

[0121] According to this embodiment, none of the laminated films FL1, FL2, or FL3 are present on the partition wall 6. Therefore, unwanted reflection of ambient light is suppressed, and the display quality can be improved.

[0122] Next, other configuration examples will be described. Note that for elements identical to those in the above configuration examples, the same reference numerals may be used, and detailed explanations may be omitted.

[0123] Figure 8 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0124] The configuration example shown in Figure 8 differs from the configuration example shown in Figure 4 in that the distance between one sealing layer SE12 and one sealing layer SE13 in the second direction Y is greater than the distance between the other sealing layer SE12 and one sealing layer SE13 in the second direction Y.

[0125] For example, let's focus on pixels PX2 and PX4, which are adjacent in the second direction Y.

[0126] The sealing layer SE13 of pixel PX4 is located between the sealing layer SE12 of pixel PX2 and the sealing layer SE12 of pixel PX4 in the second direction Y. The edge E4 of the sealing layer SE13 is close to the sealing layer SE12 of pixel PX2 and may be in contact with it. The edge E2 of the sealing layer SE13 is spaced apart from the sealing layer SE12 of pixel PX4. In other words, the slit-shaped region ST extends between the edge E2 and the sealing layer SE12.

[0127] As shown in the illustrated example, slit-shaped regions ST extend around the sealing layer SE13 of pixel PX4, between the edge E2 and the sealing layer SE12, and between the edge E3 and the sealing layer SE11 of pixel PX3. Similarly, slit-shaped regions ST are formed along the two edges of the sealing layer SE13 of the other pixels.

[0128] In this configuration example as well, when forming the display element DE3, the laminated film FL3 on the partition wall 6 is removed by an etching solution or etching gas that penetrates from region ST. Therefore, the same effect as in the above configuration example can be obtained.

[0129] Figure 9 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0130] The configuration example shown in Figure 9 differs from the configuration example shown in Figure 4 in that, in the second direction Y, the edge E2 of the sealing layer SE13 is close to one sealing layer SE12, and the edge E4 of the sealing layer SE13 is close to the other sealing layer SE12.

[0131] For example, focusing on the sealing layer SE13 of pixel PX4, the edge E2 of the sealing layer SE13 is close to the sealing layer SE12 of pixel PX4, and the edge E4 of the sealing layer SE13 is close to the sealing layer SE12 of pixel PX2. Around such a sealing layer SE13, a slit-shaped region ST extends between the edge E3 and the sealing layer SE11 of pixel PX3. Similarly, for the sealing layer SE13 of other pixels, a slit-shaped region ST is formed along one edge. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0132] Figure 10 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0133] The configuration example shown in Figure 10 differs from the configuration example shown in Figure 4 in that a slit-shaped region ST is formed around the entire circumference of the sealing layer SE13.

[0134] For example, around the sealing layer SE13 of pixel PX4, slit-shaped regions ST extend between edge E1 and the sealing layer SE11 of pixel PX4, between edge E2 and the sealing layer SE12 of pixel PX4, between edge E3 and the sealing layer SE11 of pixel PX3, and between edge E4 and the sealing layer SE12 of pixel PX2. Similarly, slit-shaped regions ST are formed along the four edges of the sealing layer SE13 of the other pixels. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0135] Figure 11 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0136] The configuration example shown in Figure 11 differs from the configuration example shown in Figure 4 in that, in the first direction X, the sealing layer SE12 is close to one sealing layer SE11 and also close to the other sealing layer SE11.

[0137] For example, in the sealing layer SE12 of pixel PX4, edge E5 is close to the sealing layer SE11 of pixel PX4, and edge E6 is close to the sealing layer SE11 of pixel PX3. Around the sealing layer SE13 of pixel PX4, slit-shaped regions ST extend between edge E2 and the sealing layer SE12 of pixel PX4, between edge E3 and the sealing layer SE11 of pixel PX3, and between edge E4 and the sealing layer SE12 of pixel PX2. Similarly, slit-shaped regions ST are formed along the three edges of the sealing layer SE13 of the other pixels. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0138] Figure 12 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0139] The configuration example shown in Figure 12 differs from the configuration example shown in Figure 11 in that the distance between one sealing layer SE12 and one sealing layer SE13 in the second direction Y is greater than the distance between the other sealing layer SE12 and one sealing layer SE13 in the second direction Y.

[0140] For example, in the sealing layer SE13 of pixel PX4, edge E2 is spaced apart from the sealing layer SE12 of pixel PX4, while edge E4 is close to the sealing layer SE12 of pixel PX2. Around the sealing layer SE13, slit-shaped regions ST extend between edge E2 and the sealing layer SE12 of pixel PX4, and between edge E3 and the sealing layer SE11 of pixel PX3. Similarly, slit-shaped regions ST are formed along the two edges of the sealing layer SE13 of the other pixels. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0141] Figure 13 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0142] The configuration example shown in Figure 13 differs from the configuration example shown in Figure 11 in that a slit-shaped region ST is formed around the entire circumference of the sealing layer SE13.

[0143] For example, around the sealing layer SE13 of pixel PX4, slit-shaped regions ST extend between edge E1 and the sealing layer SE11 of pixel PX4, between edge E2 and the sealing layer SE12 of pixel PX4, between edge E3 and the sealing layer SE11 of pixel PX3, and between edge E4 and the sealing layer SE12 of pixel PX2. Similarly, slit-shaped regions ST are formed along the four edges of the sealing layer SE13 of the other pixels. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0144] Figure 14 shows another example of the layout of the sealing layers SE11, SE12, and SE13.

[0145] In the configuration example shown in Figure 14, a slit-shaped region ST is formed around the entire circumference of each of the sealing layers SE11, SE12, and SE13. Therefore, when forming each of the display elements DE1, DE2, and DE3, the etching solution or etching gas can circulate around the entire circumference of each display element, ensuring that the laminated film on the partition wall 6 is reliably removed. Even in this configuration example, the same effects as in the configuration example above can be obtained.

[0146] In the above embodiment, for example, display element DE1 corresponds to the first display element, display element DE2 corresponds to the second display element, and display element DE3 corresponds to the third display element.

[0147] The sealing layer SE11 corresponds to the first sealing layer, the sealing layer SE12 corresponds to the second sealing layer, and the sealing layer SE13 corresponds to the third sealing layer.

[0148] Lower electrode LE1 corresponds to the first lower electrode, lower electrode LE2 corresponds to the second lower electrode, and lower electrode LE3 corresponds to the third lower electrode.

[0149] Organic layer OR1 corresponds to the first organic layer, organic layer OR2 corresponds to the second organic layer, organic layer OR3 corresponds to the third organic layer, light-emitting layer EM1 corresponds to the first light-emitting layer, light-emitting layer EM2 corresponds to the second light-emitting layer, and light-emitting layer EM3 corresponds to the third light-emitting layer.

[0150] Upper electrode UE1 corresponds to the first upper electrode, upper electrode UE2 corresponds to the second upper electrode, and upper electrode UE3 corresponds to the third upper electrode.

[0151] Cap layer CP1 corresponds to the first cap layer, cap layer CP2 corresponds to the second cap layer, and cap layer CP3 corresponds to the third cap layer.

[0152] The multilayer film FL1 corresponds to the first multilayer film, the multilayer film FL2 corresponds to the second multilayer film, and the multilayer film FL3 corresponds to the third multilayer film.

[0153] As described above, this embodiment provides a display device and a method for manufacturing a display device that can improve the quality of the display.

[0154] All display devices and manufacturing methods thereof that a person skilled in the art can implement by appropriately modifying the design based on the display devices and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0155] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0156] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0157] DSP...Display device DA...Display area SA...Peripheral area DE1, DE2, DE3... Display elements LE1, LE2, LE3…lower electrode OR1, OR2, OR3…Organic layer UE1, UE2, UE3...upper electrode CP1, CP2, CP3...cap layers SE11, SE12, SE13, SE2...Sealing layer RS1, RS2…Resin layer 5…Inorganic insulating layer 12…Organic insulating layer 6...Bulkhead 61...Lower 62...Upper FL1, FL2, FL3… Multilayer film

Claims

1. circuit board and An inorganic insulating layer disposed above the substrate, A first display element configured to display a first color, A second display element configured to display a second color different from the first color, A third display element configured to display a third color different from the first and second colors, Displaced on the inorganic insulating layer, conductive, and surrounding the first display element, the second display element, and the third display element, respectively, a partition wall formed in an overhanging manner, A first sealing layer covering the first display element and extending above the partition wall, A second sealing layer covering the second display element and extending above the partition wall, The third display element is covered by a third sealing layer that extends above the partition wall, The distance between the second sealing layer and the third sealing layer is greater than the distance between the first sealing layer and the third sealing layer. No reflective layer is provided between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, or between the partition wall and the third sealing layer. Display device.

2. The distance between the second sealing layer and the third sealing layer is 10 times or more the distance between the first sealing layer and the third sealing layer. The display device according to claim 1.

3. The distance between the second sealing layer and the third sealing layer is 5 μm or more. The display device according to claim 2.

4. The distance between the first sealing layer and the third sealing layer is 0.5 μm or less. The display device according to claim 2.

5. circuit board and An inorganic insulating layer disposed above the substrate, A partition wall, which is disposed on the inorganic insulating layer, is conductive, and is formed in an overhanging manner, It comprises a plurality of pixels arranged in a matrix in a first direction and a second direction, Each of the aforementioned plurality of pixels is A first display element, configured to display a first color and surrounded by the partition wall, A second display element, which is configured to display a second color different from the first color and is surrounded by the partition wall, A third display element, enclosed by the partition wall, is configured to display a third color different from the first and second colors, A first sealing layer covering the first display element and extending above the partition wall, A second sealing layer covering the second display element and extending above the partition wall, The third display element is covered by a third sealing layer that extends above the partition wall, The third sealing layer is located between the two first sealing layers in the first direction. The distance between one of the first sealing layers and the third sealing layer in the first direction is greater than the distance between the other of the first sealing layer and the third sealing layer in the first direction. No reflective layer is provided between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, or between the partition wall and the third sealing layer. Display device.

6. The third sealing layer is located between the two second sealing layers in the second direction. The distance between one of the second sealing layers and the third sealing layer in the second direction is greater than the distance between the other of the second sealing layers and the third sealing layer in the second direction. The display device according to claim 5.

7. Each of the first display element, the second display element, and the third display element includes an upper electrode formed of a magnesium-silver alloy. The upper electrode is not positioned on the partition wall. The display device according to claim 1 or 5.

8. Each of the first display element, the second display element, and the third display element is: A lower electrode having a peripheral portion covered with the inorganic insulating layer, The lower electrode is positioned above the aforementioned lower electrode and comprises a laminated film including an organic layer containing a light-emitting layer, an upper electrode, and a cap layer. The aforementioned laminated film is not positioned on the partition wall. The display device according to claim 1 or 5.

9. Furthermore, it comprises a resin layer covering the first sealing layer, the second sealing layer, and the third sealing layer, The resin layer is filled into the cavities formed between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, and between the partition wall and the third sealing layer. The display device according to claim 1 or 5.

10. The aforementioned partition wall is Displaced on the inorganic insulating layer, formed of a conductive material, and having a lower part that contacts the upper electrode, The system comprises an upper part positioned above the lower part, The display device according to claim 7.

11. The lower part comprises a bottom layer disposed on the inorganic insulating layer and an axial layer disposed between the bottom layer and the upper part. Both ends of the bottom layer and both ends of the upper part protrude from the side surface of the axial layer. The display device according to claim 10.

12. The third color is red. The display device according to claim 1 or 5.

13. A processing substrate is prepared, comprising a first lower electrode, a second lower electrode, and a third lower electrode above the substrate, and overhanging partition walls surrounding the first lower electrode, the second lower electrode, and the third lower electrode, respectively. A first laminated film including a first organic layer, a first upper electrode, and a first cap layer is formed on the first lower electrode. A first sealing layer is formed on the first laminated film. A second laminated film is formed on the second lower electrode, comprising a second organic layer, a second upper electrode, and a second cap layer. A second sealing layer is formed on the second laminated film. A third laminated film is formed on the first sealing layer, the second sealing layer, the partition wall, and the third lower electrode, including a third organic layer, a third upper electrode, and a third cap layer. A third sealing layer is formed on the aforementioned third laminated film. A resist patterned in a predetermined shape is formed on the third sealing layer. Using the resist as a mask, the third sealing layer and the third multilayer film are patterned. The resist is formed such that the distance from the resist to the edge of the second sealing layer is greater than the distance from the resist to the edge of the first sealing layer. A method for manufacturing a display device.

14. Furthermore, the process includes removing the resist after patterning the third sealing layer and the third multilayer film. The third layer film on the partition wall is removed before the step of removing the resist. A method for manufacturing a display device according to claim 13.

15. Furthermore, the process includes a step of forming a resin layer on the first sealing layer, the second sealing layer, and the third sealing layer after removing the resist. The resin layer is filled into the cavities formed between the partition wall and the first sealing layer, between the partition wall and the second sealing layer, and between the partition wall and the third sealing layer. A method for manufacturing a display device according to claim 14.

16. Each of the first upper electrode, the second upper electrode, and the third upper electrode is formed of a magnesium-silver alloy, and none of them are present on the partition wall after the resist has been removed. A method for manufacturing a display device according to claim 14.

17. Each of the first, second, and third laminated films is formed by vapor deposition using the partition wall as a mask. A method for manufacturing a display device according to claim 13.

18. The third laminated film is divided into a portion formed on the partition wall and a portion formed on the third lower electrode. A method for manufacturing a display device according to claim 17.

19. The light-emitting layers contained in the first organic layer, the second organic layer, and the third organic layer are formed from different materials. A method for manufacturing a display device according to claim 13.

20. The light-emitting layer contained in the third organic layer is formed of a material that emits light in the red wavelength band. A method for manufacturing a display device according to claim 13.

Images