Semiconductor packages

Abstract

The present invention provides a semiconductor package with a structure that can improve thermal characteristics and increase wiring density. [Solution] The semiconductor package according to the present invention comprises a first semiconductor chip having a first upper surface which is an active surface and a first lower surface facing the first upper surface, and having through electrodes disposed inside; a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface which is an active surface and a second upper surface facing the second lower surface, and having a larger size in the horizontal direction than the first semiconductor chip; and an external through electrode disposed adjacent to the first semiconductor chip and below the second semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip by HCB (Hybrid Copper Bonding).

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and particularly to a semiconductor package having a structure in which a large-sized semiconductor chip and a small-sized semiconductor chip are stacked.

Background Art

[0002] There have been developed semiconductor packages having a structure in which a small-sized second semiconductor chip (e.g., a cache memory circuit) is disposed at the bottom of the semiconductor package and a large-sized first semiconductor chip (e.g., a logic circuit) is disposed at the top, and these two chips are hybrid-bonded by D2W bonding, and semiconductor packages having a structure in which a small chip is disposed at the bottom of the semiconductor package and a large chip is disposed at the top, and these two chips are face-to-face HCB by D2W bonding. Improvement in performance and the like of such semiconductor packages in which semiconductor chips are disposed at the bottom and the top has been an issue on a daily basis.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the problems in the above-described conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package having a structure capable of improving thermal characteristics and increasing wiring density.

Means for Solving the Problems

[0004] To achieve the above objective, the semiconductor package according to the present invention comprises: a first semiconductor chip having a first upper surface which is an active surface and a first lower surface facing the first upper surface, and having through electrodes disposed inside; a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface which is an active surface and a second upper surface facing the second lower surface, and having a larger size in the horizontal direction than the first semiconductor chip; and an external through electrode disposed adjacent to the first semiconductor chip and below the second semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip by HCB (Hybrid Copper Bonding).

[0005] Furthermore, the semiconductor package according to the present invention, made to achieve the above objective, comprises: a first semiconductor chip having a first upper surface which is an active surface and a first lower surface facing the first upper surface, and having through electrodes disposed inside; a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface which is an active surface and a second upper surface facing the second lower surface, and having a size larger than the first semiconductor chip in the horizontal direction; a sealing material that seals the first semiconductor chip on the lower surface of the second semiconductor chip; an external through electrode disposed below the second semiconductor chip adjacent to the first semiconductor chip and penetrating the sealing material; the lower surface of the external through electrode; and an external connection terminal disposed on the lower surface of the first lower pad of the first semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip by HCB, and the lower surface of the external through electrode forms substantially the same plane as the lower surface of the first lower pad.

[0006] Furthermore, the semiconductor package according to the present invention, made to achieve the above objective, has a package structure comprising: a package substrate; a first semiconductor element disposed on the package substrate; and at least one second semiconductor element disposed on the package substrate adjacent to the first semiconductor element, wherein the first semiconductor element has a first upper surface which is an active surface and a first lower surface facing the first upper surface, and a through-electrode disposed inside; a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface which is an active surface and a second upper surface facing the second lower surface, and having a larger size in the horizontal direction than the first semiconductor chip; and an external through-electrode disposed below the second semiconductor chip adjacent to the first semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip by HCB. [Effects of the Invention]

[0007] According to the semiconductor package of the present invention, a small first semiconductor chip is placed at the bottom, a larger second semiconductor chip is placed at the top, and the first and second semiconductor chips are coupled front-to-front (F2F), thereby greatly improving the thermal characteristics of the second semiconductor chip, which is a logic chip. Furthermore, there is no need to place a separate dummy chip. Furthermore, the number of bonding pads can be increased without regard to the through-electrodes of the first semiconductor chip. In other words, the number of chips can be increased by reducing the pitch between the upper pad of the first semiconductor chip and the second chip pad of the second semiconductor chip. In this way, by reducing the pitch and increasing the number of coupling pads, the wiring density can be increased even with the same product, thereby improving the speed of the device. Furthermore, it can be effectively utilized for future generations of chip scaling, and power transmission characteristics can be improved via external through-electrodes. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 1B] This is an enlarged view of a semiconductor package according to an embodiment of the present invention. [Figure 2A] This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 2B] This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 2C] This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 3A] This is a perspective view of a system package according to an embodiment of the present invention. [Figure 3B] This is a cross-sectional view of a system package according to an embodiment of the present invention. [Figure 4A] This is a cross-sectional view of a system package according to an embodiment of the present invention. [Figure 4B] This is a cross-sectional view of a system package according to an embodiment of the present invention. [Figure 4C] This is a cross-sectional view of a system package according to an embodiment of the present invention. [Figure 4D] This is a cross-sectional view of a system package according to an embodiment of the present invention. [Figure 5A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5D] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5E] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5F] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5G]A cross-sectional view for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6A] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6B] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6C] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6D] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6E] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6F] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6G] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 6H] A cross-sectional view showing the process of the stage of FIG. 5A in more detail. [Figure 7A] A cross-sectional view showing the process from the stage of FIG. 5A to the stage of FIG. 5B in more detail. [Figure 7B] A cross-sectional view showing the process from the stage of FIG. 5A to the stage of FIG. 5B in more detail. [Figure 8A] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8B] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8C] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8D] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8E] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8F] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8G] A cross-sectional view showing the process from the stage of FIG. 5C to the stage of FIG. 5D in more detail. [Figure 8H] This is a cross-sectional view showing the process from stage 5C to stage 5D in more detail. [Figure 8I] This is a cross-sectional view showing the process from stage 5C to stage 5D in more detail. [Modes for carrying out the invention]

[0009] Next, specific examples of embodiments for implementing the semiconductor package according to the present invention will be described with reference to the drawings. The same reference numerals are used for identical components in the drawings, and redundant descriptions of them are omitted.

[0010] Figures 1A and 1B are a cross-sectional view and an enlarged view showing the schematic configuration of a semiconductor package according to an embodiment of the present invention, with Figure 1B being an enlarged cross-sectional view of portion A in Figure 1A. Referring to Figures 1A and 1B, the semiconductor package 1000 according to an embodiment of the present invention includes a first semiconductor chip 100, a second semiconductor chip 200, an external connection terminal 300, an external through-electrode 400, and a encapsulating material 500.

[0011] The first semiconductor chip 100 is located below the second semiconductor chip 200 and is smaller in size than the second semiconductor chip 200. For example, in the horizontal direction, i.e., in both the x and y directions, the width of the first semiconductor chip 100 is smaller than the width of the second semiconductor chip 200. The first semiconductor chip 100 includes, for example, a logic chip. For example, it is a modem chip that supports communication for the second semiconductor chip 200. However, the types of the first semiconductor chip 100 are not limited to modem chips. For example, the first semiconductor chip 100 may support the operation of the second semiconductor chip 200, or may include various types of logic chips for various signal processing in conjunction with the second semiconductor chip 200. Logic chips will be explained in more detail in the section describing the second semiconductor chip 200.

[0012] In one embodiment, the first semiconductor chip 100 may include a memory chip. Therefore, the first semiconductor chip 100 may include multiple memory elements inside. Memory elements may include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash memory, EEPROM (Electrically Erasable and Programmable Read-Only Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetic Random Access Memory), or RRAM (Resistive Random Access Memory) elements. On the other hand, in the semiconductor package 1000 of this embodiment, if the first semiconductor chip 100 includes a memory chip, the first semiconductor chip 100 includes, for example, an SRAM chip.

[0013] The first semiconductor chip 100 includes a first semiconductor substrate 101, a first active layer 110, a through-electrode 120, a first chip pad 130, and a first protective layer 140. The first semiconductor substrate 101 constitutes the body of the first semiconductor chip 100 and contains silicon (Si). However, the material of the first semiconductor substrate 101 is not limited to Si. For example, the first semiconductor substrate 101 may contain germanium (Ge), other semiconductor materials such as Si-Ge, or III-V group compounds such as GaP, GaAs, and GaSb. In one embodiment, the first semiconductor substrate 101 may include an SOI (Silicon-On-Insulator) substrate or a GOI (Germanium-On-Insulator) substrate.

[0014] The first active layer 110 includes a first integrated circuit layer and a first wiring layer. The first integrated circuit layer includes a plurality of integrated elements 113. The integrated element 113 includes, for example, a transistor. However, the integrated element 113 is not limited to transistors. The first wiring layer is located below the first integrated circuit layer. The first wiring layer includes an interlayer insulating layer 111, wiring 115, and an internal pad 117. The wiring 115 is arranged in two or more layers, and wiring 115 in different layers may be connected to each other via vertical vias. The internal pad 117 is located on top of the first wiring layer and contains aluminum (Al). However, the material of the internal pad 117 is not limited to aluminum.

[0015] The through electrode 120 extends through the first semiconductor substrate 101 in the vertical direction, i.e., the z direction. Since the first semiconductor substrate 101 contains Si, the through-electrode 120 corresponds to a TSV (Through Silicon Via). For reference, the through-electrode 120 is classified into via-first structures formed before the formation of the integrated circuit layer, via-middle structures formed after the formation of the integrated circuit layer and before the formation of the wiring layer, and via-last structures formed after the formation of the wiring layer. In Figure 1A, the through electrode 120 corresponds to a via-middle structure. However, the invention is not limited to this, and in the semiconductor package 1000 of this embodiment, the through-electrode 120 may be formed in a via-first or via-last structure.

[0016] The first chip pad 130 includes a lower pad 130d and an upper pad 130u. The lower pad 130d is positioned on the underside of the first semiconductor chip 100. As shown in Figure 1A, the lower pad 130d is directly connected to the through electrode 120. The upper pad 130u is positioned on the upper surface of the first semiconductor chip 100. The upper pad 130u is connected to the through electrode 120 via the first wiring layer. The first tip pad 130 may include, for example, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In the semiconductor package 1000 of this embodiment, the first chip pad 130 contains Cu. However, the material of the first chip pad 130 is not limited to Cu.

[0017] The first protective layer 140 is placed on the bottom and top surfaces of the first semiconductor chip 100. The first protective layer 140 includes a lower protective layer 140d on the underside of the first semiconductor chip 100 and an upper protective layer 140u on the upper side. In the semiconductor package 1000 of this embodiment, the lower protective layer 140d and the upper protective layer 140u each have a multilayer structure. For example, as shown in Figure 1B, the lower protective layer 140d includes a first lower insulating layer 142d and a second lower insulating layer 144d, and the upper protective layer 140u includes a first upper insulating layer 142u and a second upper insulating layer 144u. However, the number of layers in both the lower protective layer 140d and the upper protective layer 140u is not limited to two. The first protective layer 140 may include, for example, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

[0018] In the first semiconductor chip 100, the top surface is the active front side (FS), and the bottom surface is the inactive back side (BS). In other words, the upper surface of the first wiring layer corresponds to the front surface FS1 of the first semiconductor chip 100, and the lower surface of the first semiconductor substrate 101 corresponds to the back surface (BS) of the first semiconductor chip 100. Therefore, the lower protective layer 140d and the lower pad 130d are positioned on the lower surface, which is the inactive surface of the first semiconductor chip 100, while the upper protective layer 140u and the upper pad 130u are positioned on the upper surface, which is the active surface of the first semiconductor chip 100. On the other hand, the lower pad 130d is positioned to penetrate the lower protective layer 140d, and the lower pad 130d is exposed from the lower surface of the lower protective layer 140d. As mentioned above, the lower pad 130d is directly connected to the lower surface of the through electrode 120. The upper pad 130u is positioned to penetrate the upper protective layer 140u, and the upper pad 130u is exposed from the upper surface of the upper protective layer 140u. The upper pad 130u is connected to the internal pad 117 of the first wiring layer and to the upper surface of the through electrode 120 via the wiring 115.

[0019] The second semiconductor chip 200 is stacked on top of the first semiconductor chip 100. The second semiconductor chip 200 includes, for example, a logic chip. As a result, the second semiconductor chip 200 includes multiple logic elements inside. Logic elements may include, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), DLY (delay), FIL (filter), multiplexer (MXT / MXIT), OAI (OR / AND / INVERTER), AO (AND / OR), AOI (AND / OR / INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, counter, or buffer elements.

[0020] Logic elements perform various types of signal processing, including analog signal processing, A / D conversion (Analog-to-Digital Conversion), and control. The second semiconductor chip 200 may be referred to as a CPU (Central Processing Unit) chip, an MPU (Micro-Processor Unit) chip, a GPU (Graphics Processing Unit) chip, an NPU (Neural Processing Unit) chip, an AP (Application Processor) chip, or a control chip, depending on its function. The second semiconductor chip 200 includes a second semiconductor substrate 201, a second active layer 110, a second chip pad 230, and a second protective layer 240. The second substrate 201 is based on a semiconductor substrate. The details regarding the second semiconductor substrate 201 are as described for the first semiconductor substrate 101 of the first semiconductor chip 100.

[0021] The second active layer 210 is located below the second semiconductor substrate 201. The second active layer 210 includes a second integrated circuit layer and a second wiring layer. The second integrated circuit layer includes a plurality of integrated elements 213. The second wiring layer includes an interlayer insulating layer 211, wiring 215, and an internal pad 217. The details of the second active layer 210 are as described for the first active layer 110 of the first semiconductor chip 100. However, the integrated element 113 included in the first integrated circuit layer and the integrated element 213 included in the second integrated circuit layer may be different from each other. For example, if the first semiconductor chip 100 is a memory chip and the second semiconductor chip 200 is a logic chip, then the integrated element 113 of the first integrated circuit layer includes memory elements, and the integrated element 213 of the second integrated circuit layer includes logic elements. On the other hand, if the first semiconductor chip 100 is a logic chip, the integrated elements 113 of the first integrated circuit layer may also include logic elements.

[0022] The second chip pad 230 is positioned on the underside of the second semiconductor chip 200. Specifically, the second chip pad 230 is positioned on the underside of the second active layer 210 and connected to the internal pad 217 of the second wiring layer. The material of the second chip pad 230 is the same as the material of the first chip pad 130 of the first semiconductor chip 100, as described above. The second protective layer 240 is placed on the underside of the second semiconductor chip 200. In Figure 1A, the second protective layer 240 is shown as a single-layer structure, but it is not limited to this, and the second protective layer 240 may include a multi-layer structure. The material of the second protective layer 240 is the same as described for the material of the first protective layer 140 of the first semiconductor chip 100.

[0023] In the second semiconductor chip 200, the bottom surface is the active surface (front FS), and the top surface is the inactive surface (back BS). In other words, the lower surface of the second wiring layer corresponds to the front surface (FS) of the second semiconductor chip 200, and the upper surface of the second semiconductor substrate 201 corresponds to the back surface (BS) of the second semiconductor chip 200. Therefore, the second protective layer 240 and the second chip pad 230 are positioned on the bottom surface, which is the active surface of the second semiconductor chip 200. The second chip pad 230 is positioned to penetrate the second protective layer 240, and the second chip pad 230 is exposed from the lower surface of the second protective layer 240. The second chip pad 230 is connected to the internal pad 217 of the second wiring layer.

[0024] The first semiconductor chip 100 and the second semiconductor chip 200 are directly bonded to each other by hybrid copper bonding (HCB). Here, HCB refers to a junction that combines a pad-to-pad junction, in which the pads of the first semiconductor chip 100 and the second semiconductor chip 200 are joined to each other, and an insulator-to-insulator junction, in which the insulating layers of the first semiconductor chip 100 and the second semiconductor chip 200 are joined to each other. On the other hand, since the pads are typically formed from copper (Cu), pad-to-pad joints are also called copper-to-copper (Cu-to-Cu) joints. Furthermore, in an insulator-to-insulator joint, the insulator may include, for example, a nitride film such as SiNx or an oxide film such as SiO2. However, the insulating layer is not limited to nitride or oxide films. In the semiconductor package 1000 of this embodiment, the coupling of the first semiconductor chip 100 and the second semiconductor chip 200 is not limited to HCB. For example, in one embodiment, the first semiconductor chip 100 and the second semiconductor chip 200 can be joined via connection terminals such as bumps. Furthermore, the first semiconductor chip 100 and the second semiconductor chip 200 may be joined via an ACF (Anisotropic Conductive Film). Here, ACF refers to an anisotropic conductive film formed by mixing fine conductive particles with an adhesive resin to create a film that conducts electricity in only one direction.

[0025] The external connection terminal 300 is located on the lower surface of the first semiconductor chip 100 and the lower surface of the external through-electrode 400. On the lower surface of the first semiconductor chip 100, the external connection terminal 300 is located on the lower pad 130d of the first semiconductor chip 100. The external connection terminal 300 includes the pillar 310 and the bump 320. The pillar 310 has a cylindrical shape and may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. In the semiconductor package 1000 of this embodiment, the pillar 310 contains Cu. In one embodiment, the pillar 310 acts as a chip pad, and a chip pad, i.e., a lower pad, may not be formed on the lower surface of the first semiconductor chip 100. Meanwhile, a package protection layer 330 is formed on the lower surface of the first semiconductor chip 100 and the external through-electrode 400, and the pillar 310 is arranged in a structure that penetrates the package protection layer 330. The package protection layer 330 includes, for example, solder resist (SR). However, the material of the package protection layer 330 is not limited to SR.

[0026] Bump 320 is positioned on pillar 310. Bump 320 includes, for example, solder. Solder may contain tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and / or alloys thereof. For example, the solder may include Sn, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn, and the like. In one embodiment, the bump 320 may also be called solder, solder bump, etc. On the other hand, an intermediate layer is formed at the contact interface between the pillar 310 and the bump 320. The intermediate layer may contain an intermetallic compound (IMC) formed by the reaction of metallic substances contained in the pillar 310 and bump 320 at relatively high temperatures.

[0027] The external through-electrode 400 is positioned horizontally adjacent to the first semiconductor chip 100 and below the second semiconductor chip 200. The external through-electrode 400 has a structure that extends vertically, i.e., in the z-direction, through the sealing material 500. The external through-electrode 400 connects the second chip pad 230 and the external connection terminal 300. For example, power / ground is supplied to the second semiconductor chip 200 via an external through-electrode 400. The external through-electrode 400 is formed by creating a through-hole in the sealing material 500 and filling the through-hole with a metallic substance. The external through electrode 400 is made of, for example, Cu and is formed together with the lower pad 130d by plating. As a result, as shown by the dotted line in Figure 1B, the lower surface of the external through electrode 400 and the lower surface of the lower pad 130d each have a first height H1 and form substantially the same plane. In the semiconductor package 1000 of this embodiment, multiple external through-electrodes 400 are arranged in a single row along the y-direction adjacent to both sides of the first semiconductor chip 100 in the x-direction. In other embodiments, the external through electrodes 400 may be arranged in two or more rows along the y-direction. On the other hand, the external through-electrode 400 penetrates the encapsulating material 500, which is the dielectric layer, and therefore corresponds to a TDV (Through Dielectric Via).

[0028] The encapsulating material 500 is placed on the underside of the second semiconductor chip 200 and covers part of the sides and underside of the first semiconductor chip 100. Furthermore, the sealing material 500 covers the sides of the external through-electrode 400. Furthermore, the encapsulating material 500 covers a portion of the underside of the second semiconductor chip 200. Specifically, the sealing material 500 includes a side sealing material 510 and a bottom sealing material 520. The side encapsulant 510 covers the side of the first semiconductor chip 100, and the bottom encapsulant 520 covers the bottom surface of the first semiconductor chip 100. As can be seen from Figure 1A, the side sealant 510 is placed on the first gap fill liner 515, and the lower sealant 520 is placed on the second gap fill liner 525. The sealing material 500 may include inorganic composite materials. For example, the sealing material 500 includes a resin containing silica filler. Here, the resin corresponds to an organic substance, and the silica filler corresponds to an inorganic substance.

[0029] On the other hand, the sealing material 500 may contain a substance with a low dielectric constant. For example, the sealing material 500 includes a substance having a dielectric constant of 3.8 or less. In one embodiment, the encapsulant 500 may include, for example, polymers such as PI (Polyimide), PBO (PolyBenzoxazole), PHS (PolyHydroxyStyrene), epoxy, and BCB (BenzoCycloButene) series. On the other hand, the encapsulant 500 may be formed during the manufacturing of the semiconductor package 1000 through a process that fills the gaps between the first semiconductor chips 100. Thus, the encapsulant 500 may be called a gap-fill layer. Furthermore, in the semiconductor package 1000 of this embodiment, the encapsulant 500 can effectively fill the gaps by including a composite material with or without a high filler density.

[0030] In a semiconductor package 1000 according to an embodiment of the present invention, a small-sized first semiconductor chip 100 is placed at the bottom, and a larger-sized second semiconductor chip 200 is placed at the top. The first semiconductor chip 100 and the second semiconductor chip 200 are coupled front-to-front (F2F), which greatly improves the thermal characteristics of the second semiconductor chip 200, which is a logic chip. Furthermore, there is no need to place a separate dummy chip. Furthermore, the number of bonding pads can be increased without regard to the through-electrode 120 of the first semiconductor chip 100. In other words, the number of chips can be increased by shrinking the pitch between the upper pad 130u of the first semiconductor chip 100 and the second chip pad 230 of the second semiconductor chip 200. In this way, by reducing the pitch and increasing the number of coupling pads, the interconnect density can be increased even with the same product, thereby improving the speed of the device, and this can also be effectively utilized for future generations of chip scaling. In addition, the semiconductor package 1000 of this embodiment can improve power transfer characteristics via the external through-electrode 400.

[0031] Furthermore, the semiconductor package 1000 according to the embodiment of the present invention constitutes a GPU / CPU / SOC chip, etc., depending on the type of second semiconductor chip 200. Furthermore, the semiconductor package 1000 of this embodiment can be used for server semiconductor devices, mobile semiconductor devices, and the like, depending on the type of logic elements contained inside the second semiconductor chip 200. For reference, in a package structure where the larger logic chip is located at the bottom and the smaller SRAM chip is located at the top, it is combined with a front-to-back (F2B) structure, and a dummy chip is placed on top of the logic chip to dissipate heat. Furthermore, the presence of dummy chips can increase the size of the logic chip. On the other hand, the placement area for through-electrodes is constrained by the logic chip's KOZ (keep out zone), which limits the increase in coupling pads and therefore limits the improvement in wiring density. Here, KOZ refers to a region around the transistor that cannot be patterned, and through electrodes cannot be placed in such a KOZ.

[0032] In recent years, the power consumption of logic chips in HPC (High Performance Computing) / server products has been steadily increasing, and die sizes have been growing to realize high-performance logic functions. As a result, 3DIC (Integrated Circuit), or logic chiplet, technology has attracted attention. Here, 3DIC means that, as in the structure of the semiconductor package 1000 according to an embodiment of the present invention, the memory chip and the logic chip are combined and utilized as a single integrated chip. Furthermore, the term "logic chiplet" refers to a semiconductor chip manufactured according to its size and function, and is used in essentially the same sense as "3DIC." Furthermore, in order to realize high system performance, there is a growing need for 3D packages that stack logic chips and memory chips in 3D. The performance considerations for 3D packaging include power delivery, thermal characteristics, and cost. In particular, improving thermal characteristics is becoming crucial due to the increasing power consumption of logic chips. To ensure the power transfer characteristics of large logic chips, logic chips are generally placed at the bottom, and smaller memory chips are stacked on top. However, in this type of structure, the logic chip is located at the bottom, which can degrade its thermal characteristics, thus requiring a dummy chip.

[0033] Figures 2A to 2C are cross-sectional views of a semiconductor package according to an embodiment of the present invention. The information already explained in the explanatory sections of Figures 1A and 1B will be briefly explained or omitted. Referring to Figure 2A, the semiconductor package 1000a of this embodiment differs from the semiconductor package 1000 of Figure 1A in the arrangement structure of the external through-electrode 400. Specifically, the semiconductor package 1000a of this embodiment includes a first semiconductor chip 100, a second semiconductor chip 200, an external connection terminal 300, an external through-electrode 400, and a encapsulating material 500. The first semiconductor chip 100, the second semiconductor chip 200, the external connection terminal 300, and the encapsulating material 500 are as described in the section describing the semiconductor package 1000 in Figure 1A.

[0034] In the semiconductor package 1000a of this embodiment, the external through-electrode 400 is positioned adjacent to one side of the first semiconductor chip 100 in the x-direction, for example, only the left side. As a result, the first semiconductor chip 100 is coupled to the second semiconductor chip 200 with an imbalance to the right in the x-direction. On the other hand, multiple external through-electrodes 400 are arranged in a single row along the y-direction adjacent to the left side of the first semiconductor chip 100 in the x-direction. In another embodiment, the external through-electrodes 400 may be arranged in two or more rows along the y-direction adjacent to the left side surface of the first semiconductor chip 100 in the x-direction.

[0035] Referring to Figure 2B, the semiconductor package 1000b of this embodiment differs from the semiconductor package 1000 of Figure 1A in that it does not have external through-electrodes. Specifically, the semiconductor package 1000b of this embodiment includes a first semiconductor chip 100, a second semiconductor chip 200, an external connection terminal 300, and a encapsulating material 500. The first semiconductor chip 100, the second semiconductor chip 200, the external connection terminal 300, and the encapsulating material 500 are as described in the section describing the semiconductor package 1000 in Figure 1A. Since no external through-electrodes are provided in the semiconductor package 1000b of this embodiment, power / ground to the second semiconductor chip 200 is provided via the through-electrode 120 of the first semiconductor chip 100. If the through-electrode 120 of the first semiconductor chip 100 is sufficient, a separate external through-electrode is not required, which reduces the size of the second semiconductor chip 200 and thereby reduces the size of the overall semiconductor package 1000b.

[0036] Referring to Figure 2C, the semiconductor package 1000c of this embodiment differs from the semiconductor package 1000 of Figure 1A in that it further includes a redistribution layer 600. Specifically, the semiconductor package 1000c of this embodiment includes a first semiconductor chip 100, a second semiconductor chip 200, an external connection terminal 300, an external through-electrode 400, a encapsulating material 500, and a redistribution layer 600. The first semiconductor chip 100, the second semiconductor chip 200, the external connection terminal 300, the external through-electrode 400, and the encapsulating material 500 are as described in the section describing the semiconductor package 1000 in Figure 1A.

[0037] In the semiconductor package 1000c of this embodiment, a redistribution layer 600 is arranged below the first semiconductor chip 100 and the external through-electrode 400. The redistribution layer 600 includes a redistribution insulation layer 601, a redistribution 610, and a redistribution pad 630. The rewiring insulating layer 601 is formed of, for example, a PID (Photo Imageable Dielectric) resin and further contains an inorganic filler. However, the material of the rewiring insulation layer 601 is not limited to PID resin. If the rerouting 610 is located on two or more layers, the rerouting 610 on different layers are connected to each other via vertical vias. The rewiring pads 630 are positioned on the lower and upper surfaces of the rewiring layer 600. The rewiring pad 630 includes a lower rewiring pad 630d positioned on the lower surface of the rewiring layer 600 and an upper rewiring pad 630u positioned on the upper surface. An external connection terminal 300 is located on the lower rewiring pad 630d. The upper rewiring pad 630u is connected to the through electrode 120 and the external through electrode 400.

[0038] Figures 3A and 3B are perspective and cross-sectional views of a system package according to an embodiment of the present invention, with Figure 3B being a cross-sectional view taken along the line I-I' in Figure 3A. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the sections from Figure 1A to Figure 2C will be briefly explained or omitted. Referring to Figures 3A and 3B, the system package 2000 of this embodiment includes a semiconductor package 1000, a package substrate 1100, an interposer 1200, a semiconductor element 1300, and an external encapsulant 1500.

[0039] The semiconductor package 1000 is, for example, the semiconductor package 1000 shown in Figure 1A. As a result, the semiconductor package 1000 includes a first semiconductor chip 100, a second semiconductor chip 200, an external connection terminal 300, an external through-electrode 400, and a encapsulating material 500. The second semiconductor chip 200 is larger than the first semiconductor chip 100, and the first semiconductor chip 100 and the second semiconductor chip 200 are coupled by an HCB. On the other hand, in Figures 3A and 3B, the semiconductor package 1000 is shown with only the external connection terminals 300 visible, and the remaining parts are simplified into block shapes.

[0040] The package substrate 1100 is a support substrate, and an interposer 1200, a semiconductor package 1000, and semiconductor elements 1300 are stacked on the package substrate 1100. The package substrate 1100 includes at least one layer of wiring lines inside. When wiring lines are formed in multiple layers, wiring lines in other layers are connected to each other via vertical vias. The package substrate 1100 can be formed based on, for example, a ceramic substrate, a PCB, an organic substrate, an interposer substrate, and the like. The first connection terminal 1150 is positioned on the lower surface of the package substrate 1100. The system package 2000 is stacked on an external system board or main board via the first connection terminal 1150.

[0041] The interposer 1200 includes an interposer substrate 1201, a wiring layer 1210, a through electrode 1220, and a second connection terminal 1250. The semiconductor package 1000 and the semiconductor element 1300 are mounted on the package substrate 1100 via the interposer 1200. The interposer 1200 connects the semiconductor package 1000 and the semiconductor element 1300 to each other. Furthermore, the interposer 1200 connects the semiconductor package 1000 and the semiconductor element 1300 to the package substrate 1100. The interposer substrate 1201 includes, for example, Si. Therefore, the interposer 1200 is a "Si-interposer". The through electrode 1220 extends through the interposer substrate 1201. Since the interposer substrate 1201 contains Si, the through-electrode 1220 corresponds to a TSV (Through-Silicon Via). The through electrode 1220 extends to the wiring layer 1210 and is connected to the wiring of the wiring layer 1210. Depending on the embodiment, the interposer 1200 may include only a wiring layer internally and may not include through electrodes. The wiring layer 1210 is placed on the upper or lower surface of the interposer substrate 1201. For example, the positional relationship between the wiring layer 1210 and the through electrode 1220 is relative. The pads on the top surface of the interposer 1200 are connected to the through-electrode 1220 via the wiring layer 1210.

[0042] The second connection terminal 1250 is located on the underside of the interposer 1200 and is connected to the through electrode 1220. The interposer 1200 is stacked on the package substrate 1100 via the second connection terminal 1250. The second connection terminal 1250 is connected to a pad on the upper surface of the interposer 1200 via the through electrode 1220 and the wiring lines of the wiring layer 1210. In the system package 2000 of this embodiment, the interposer 1200 is used for the purpose of converting or transmitting electrical signals between the semiconductor package 1000 and the semiconductor element 1300. As a result, the interposer 1200 may not contain elements such as active or passive components. However, in one embodiment, the interposer 1200 may include elements for controlling signal transmission. Meanwhile, underfill 1260 is filled between the interposer 1200 and the package substrate 1100, and between the second connection terminal 1250. In other embodiments, the underfill 1260 may be replaced by an adhesive layer or adhesive film.

[0043] As shown in Figure 3A, the semiconductor element 1300 includes the first to fourth semiconductor elements (1300-1 to 1300-4). For example, two semiconductor elements 1300 are placed on each side of the semiconductor package 1000 on the interposer 1200. However, the number of semiconductor elements 1300 in the system package 2000 of this embodiment is not limited to four. For example, one to three or five or more semiconductor elements 1300 may be arranged on the interposer 1200. The semiconductor device 1300 includes, for example, an HBM (High Bandwidth Memory) package. However, the semiconductor device 1300 is not limited to HBM packages. For example, the semiconductor device 1300 may have a single-chip structure or a general package structure different from the HBM package.

[0044] To elaborate further on the case where the semiconductor device 1300 is in an HBM package, the semiconductor device 1300 includes a base chip 1310 and a plurality of memory chips 1320 on the base chip 1310, and the base chip 1310 and the memory chips 1320 include through-electrodes 1360 inside. On the other hand, the uppermost memory chip among the memory chips 1320 may not include the through-hole electrode 1360. The base chip 1310 includes a logic chip. As a result, the base chip 1310 includes logic elements internally. Such a base chip 1310 is positioned below the memory chip 1320, integrates the signals of the memory chip 1320 and transmits them externally, and also transmits external signals and power to the memory chip 1320. Therefore, the base chip 1310 may be referred to as a buffer chip or a control chip.

[0045] The memory chip 1320 is stacked on the base chip 1310. In the semiconductor element 1300 of the system package 2000 of this embodiment, twelve memory chips 1320 are stacked on a base chip 1310. However, the number of memory chips 1320 stacked on the base chip 1310 is not limited to 12. For example, two to eleven or thirteen or more memory chips 1320 can be stacked on the base chip 1310. Each of the memory chips 1320 may include, for example, a DRAM chip. The memory chip 1320 can be referred to as the core chip. On the other hand, the memory chip 1320 is stacked on the base chip 1310 or the lower memory chip 1320 by means of bonding using the aforementioned HCB, connection terminals, or bonding using ACF.

[0046] A third connection terminal 1330 is located on the underside of the base chip 1310. The third connection terminal 1330 is connected to the through electrode 1360. The semiconductor element 1300 is mounted on the interposer 1200 via the third connection terminal 1330. The memory chip 1320 on the base chip 1310 is sealed by an internal encapsulant 1350. The external sealing material 1500 covers and seals the semiconductor package 1000 and semiconductor element 1300 on the interposer 1200. As shown in Figure 3B, the external encapsulant 1500 does not cover the top surfaces of the semiconductor package 1000 and the semiconductor element 1300. However, in one embodiment, the external encapsulant 1500 may cover the upper surface of at least one of the semiconductor package 1000 and the semiconductor element 1300.

[0047] For reference, the structure of the system package 2000 as in this embodiment is referred to as a 2.5D package structure, and the 2.5D package structure is a concept relative to a 3D package structure in which all semiconductor chips are stacked together and there is no interposer. Both the 2.5D package structure and the 3D package structure are included in the SIP (System In Package) structure. In addition, although the system package 2000 of this embodiment is also a semiconductor package, it is referred to as a system package in order to distinguish it from the semiconductor package 1000, which is a component of the system.

[0048] Figures 4A to 4D are cross-sectional views of a system package according to an embodiment of the present invention. The information already explained in the explanatory sections of Figures 1A to 3B will be briefly explained or omitted. For reference, Figures 4A to 4D are cross-sectional views corresponding to Figure 3B, and from the perspective of the connection structure between the semiconductor package 1000 and the semiconductor element 1300, they schematically show only the semiconductor package 1000, the mounting substrate (1100, 1200), and the semiconductor element 1300, and do not show the first connection terminal and external encapsulant, etc.

[0049] Referring to Figure 4A, the system package 2000a of this embodiment includes a semiconductor package 1000, a package substrate 1100, and a semiconductor element 1300. The system package 2000a of this embodiment does not include an interposer, unlike the system package 2000 shown in Figure 3B. As a result, the semiconductor package 1000 is directly mounted onto the package substrate 1100 via the external connection terminals 300. Furthermore, the semiconductor element 1300 is directly mounted on the package substrate 1100 via the third connection terminal 1330. The specific structure and function of the package substrate 1100, semiconductor package 1000, and semiconductor element 1300 are as described in the explanation section of the system package 2000 in Figure 3B. As shown in Figure 4A, in the system package 2000a of this embodiment, the semiconductor package 1000 and the semiconductor element 1300 are connected via the first connection wiring In1 of the package substrate 1100. The first connection wiring In1 is part of the wiring lines on the package substrate 1100.

[0050] Referring to Figure 4B, the system package 2000b of this embodiment includes a semiconductor package 1000, a package substrate 1100a, a semiconductor element 1300, and a "Si-bridge" 1400. The system package 2000b of this embodiment further includes a "Si-bridge" 1400 compared to the system package 2000a in Figure 4A. The "Si-bridge" 1400 is positioned within the package substrate 1100a, as shown in Figure 4B. The "Si-bridge" 1400 is positioned inside the package substrate 1100a at a location corresponding to the position between the semiconductor package 1000 and the semiconductor element 1300. Furthermore, the "Si-bridge" 1400 is superimposed together with a portion of the semiconductor package 1000 and a portion of the semiconductor element 1300. In the system package 2000b of this embodiment, the semiconductor element 1300 is arranged on both sides of the semiconductor package 1000 in the x direction. Therefore, the "Si-bridge" 1400 is positioned on both sides of the semiconductor package 1000 in the x-direction. The "Si-Bridge" 1400 includes a second connection wiring In2 internally. The "Si-bridge" 1400 connects the semiconductor package 1000 and the semiconductor element 1300 via a second connection wiring In2. In short, in the system package 2000b of this embodiment, the semiconductor package 1000 and the semiconductor element 1300 are connected to each other by a "Si-bridge" 1400 separately located within the package substrate 1100a.

[0051] Referring to Figure 4C, the system package 2000 of this embodiment is substantially identical to the system package 2000 in Figure 3B. Accordingly, the system package 2000 of this embodiment includes a semiconductor package 1000, a package substrate 1100, an interposer 1200, and a semiconductor element 1300. The semiconductor package 1000 is mounted on the interposer 1200 via an external connection terminal 300, and the semiconductor element 1300 is mounted on the interposer 1200 via a third connection terminal 1330. As shown in Figure 4C, in the system package 2000 of this embodiment, the semiconductor package 1000 and the semiconductor element 1300 are connected via the third connection wiring In3 of the interposer 1200. On the other hand, the third connecting wiring In3 includes the wiring lines of the wiring layer 1210 and the through-electrode 1220, or includes only the wiring lines of the wiring layer 1210.

[0052] Referring to Figure 4D, the system package 2000c of this embodiment includes a semiconductor package 1000, a package substrate 1100, an interposer 1200a, a semiconductor element 1300, and a "Si-bridge" 1400. The system package 2000c of this embodiment further includes a "Si-bridge" 1400 compared to the system package 2000 in Figure 4C. The "Si-bridge" 1400 is positioned within the interposer 1200a, as shown in Figure 4D. The "Si-bridge" 1400 is located inside the interposer 1200a at a corresponding position between the semiconductor package 1000 and the semiconductor element 1300. Furthermore, the "Si-bridge" 1400 is superimposed together with a portion of the semiconductor package 1000 and a portion of the semiconductor element 1300. In the system package 2000c of this embodiment, the semiconductor elements 1300 are arranged on both sides of the semiconductor package 1000 in the x direction. Therefore, the "Si-bridge" 1400 is arranged on both sides of the semiconductor package 1000 in the x direction. The "Si-Bridge" 1400 includes a second connection wiring In2 internally. The "Si-bridge" 1400 connects the semiconductor package 1000 and the semiconductor element 1300 via a second connection wiring In2. In the end, in the system package 2000c of this embodiment, the semiconductor package 1000 and the semiconductor element 1300 are connected to each other by a "Si-bridge" 1400 separately located within the interposer 1200a.

[0053] Figures 5A to 5G are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A through 4D will be briefly explained or omitted.

[0054] Referring to Figure 5A, the method for manufacturing a semiconductor package according to an embodiment of the present invention first involves forming a plurality of initial first semiconductor chips on a first semiconductor substrate 101Wb. The first semiconductor substrate 101Wb is in wafer form and is bonded and fixed onto the first carrier substrate 3000 via an adhesive layer. The adhesive layer includes, for example, a TBM (Temporary Bonding Material) layer 3100 and a release layer 3200. Each initial first semiconductor chip includes a first semiconductor substrate 101Wb, a first active layer 110, a through-electrode 120, an upper pad 130u, and an upper protective layer 140u. The first semiconductor substrate 101Wb, the first active layer 110, the through-electrode 120, the upper pad 130u, and the upper protective layer 140u are as described in the section describing the first semiconductor chip 100 of the semiconductor package 1000 in Figure 1A. The process of forming multiple initial first semiconductor chips on the first semiconductor substrate 101Wb will be explained in more detail in the explanatory sections of Figures 6A to 6H.

[0055] Referring to Figure 5B, the initial first semiconductor chip 100a is then individualized through a plasma dicing process (P / D). The plasma dicing process P / D will be explained in more detail in the explanatory sections of Figures 7A and 7B. On the other hand, in the semiconductor package manufacturing method of this embodiment, the individualization of the initial first semiconductor chip 100a is not limited to the plasma dicing process P / D. For example, an initial first semiconductor chip 100a can be individualized through a blade dicing process or a laser dicing process. On the other hand, the dicing process is sometimes referred to as the sewing process.

[0056] Referring to Figure 5C, after the initial first semiconductor chip 100a is individualized, the initial first semiconductor chip 100a is stacked on the initial second semiconductor chip using HCB. The TCB (Thermal Compression Bonding) method is applied to the lamination process using HCB. Each of the initial first semiconductor chips 100a is stacked on top of the corresponding initial second semiconductor chip. On the other hand, before stacking the initial first semiconductor chip 100a, the process of forming the initial second semiconductor chip on the second semiconductor substrate 201W is carried out first. For example, the process of forming an initial second semiconductor chip on a second semiconductor substrate 201W can be carried out in parallel with and / or independently of the process of forming an initial first semiconductor chip on a first semiconductor substrate 101Wb. Each initial second semiconductor chip includes a second semiconductor substrate 201W, a second active layer 210a, a second chip pad 230, and a second protective layer 240. The second semiconductor substrate 201W, the second active layer 210a, the second chip pad 230, and the second protective layer 240 are as described in the section describing the second semiconductor chip 200 of the semiconductor package 1000 in Figure 1A.

[0057] Referring to Figure 5D, after stacking the initial first semiconductor chip 100a, a encapsulating material 500 and a lower protective layer 140d are formed to cover the initial first semiconductor chip 100a. Furthermore, a lower pad 130d is formed on each of the initial first semiconductor chips 100a, and an external through-electrode 400 is formed between the initial first semiconductor chips 100a. The lower pad 130d and the external through electrode 400 are formed together through a plating process. The process of forming the lower pad 130d and the external through electrode 400 will be explained in more detail in the explanatory sections of Figures 8A to 8I.

[0058] Referring to Figure 5E, after the formation of the sealing material 500, lower protective layer 140d, lower pad 130d, and external through-electrode 400, a package protective layer 330a is formed on the sealing material 500, lower protective layer 140d, lower pad 130d, and external through-electrode 400. The package protective layer 330a includes, for example, SR. However, the material of the package protective layer 330a is not limited to SR.

[0059] Referring to Figure 5F, after the package protection layer 330a is formed, the package protection layer 330a is patterned to open the lower pad 130d, and the external connection terminal 300 is formed on the lower pad 130d. Specifically, the external connection terminal 300 is placed on the lower pad 130d connected to the through electrode 120 and on the lower pad 130d connected to the external through electrode 400. The external connection terminal 300 is as described in the section explaining the external connection terminal 300 of the semiconductor package 1000 in Figure 1A.

[0060] Referring to Figure 5G, the semiconductor package 1000 shown in Figure 1A is then completed by proceeding with the sawing process S to individualize the semiconductor package. The sawing process S can be performed, for example, by a ring mounting device.

[0061] Figures 6A to 6H are cross-sectional views showing the process at the stage shown in Figure 5A in more detail. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A through 5G will be briefly explained or omitted.

[0062] Referring to Figure 6A, the first integrated circuit layer is formed on the first semiconductor substrate 101W. The first integrated circuit layer includes, for example, an integrated element 113 and wiring connected to the integrated element 113. Here, the integrated element 113 includes, for example, a transistor. However, the integrated element 113 is not limited to transistors.

[0063] Referring to Figure 6B, after the formation of the first integrated circuit layer, a through-electrode 120 is formed that penetrates a portion of the first semiconductor substrate 101W. Since the through-electrode 120 is formed after the formation of the first integrated circuit layer, the through-electrode 120 corresponds to a via-middle structure. The through-electrode 120 is as described in the section explaining the through-electrode 120 of the semiconductor package 1000 in Figure 1A.

[0064] Referring to Figure 6C, after the formation of the through-electrode, the first wiring layer is formed on the first integrated circuit layer and the through-electrode 120. The first wiring layer includes an interlayer insulating layer 111, wiring 115, and an internal pad 117. The internal pad 117 includes, for example, aluminum (Al). However, the material of the internal pad 117 is not limited to aluminum. After the formation of the first wiring layer, the first wiring layer is flattened. As mentioned above, the first integrated circuit layer and the first wiring layer constitute the first active layer 110 on the first semiconductor substrate 101W. Next, an upper pad 130u and an upper protective layer 140u are formed on the first active layer 110. The upper pad 130u and upper protective layer 140u are as described in the section explaining the upper pad 130u and upper protective layer 140u of the semiconductor package 1000 in Figure 1A.

[0065] Referring to Figure 6D, after the formation of the upper pad 130u and the upper protective layer 140u, a trimming process is performed on the first semiconductor substrate 101W to form the first semiconductor substrate 101Wa with a cutting portion CP formed on its outer edge. After the trimming process, additional processes such as cleaning and / or buffing (CMP) are performed. The buffing CMP process flattens the upper surfaces of the upper pad 130u and the upper protective layer 140u, resulting in reduced roughness.

[0066] Referring to Figure 6E, after the cutting portion CP is formed, the first semiconductor substrate 101Wa and the entire upper structure are bonded and fixed onto the second carrier substrate 4000 via an adhesive layer. The adhesive layer includes, for example, a TBM layer 4100 and a release layer 4200. As shown in Figure 6E, the first semiconductor substrate 101Wa and the upper structure are bonded together with the upper pad 130u and upper protective layer 140u toward the second carrier substrate 4000.

[0067] Referring to Figure 6F, a back grinding process (BG) is then performed on the first semiconductor substrate 101Wa to remove a portion of the back side of the first semiconductor substrate 101Wa. The back grinding process (BG) will proceed to the first level (1st-BG). The first level (1st-BG) has a sufficient distance from the through electrode 120, as shown by the solid line. However, in one embodiment, the back grinding process (BG) can also be advanced to a second level (2nd-BG) indicated by a dotted line. If the back grinding process (BG) is performed up to the second level (2nd-BG) at the stage shown in Figure 6F, the subsequent additional back grinding process can be omitted.

[0068] Referring to Figure 6G, after the back grinding process BG, the first carrier substrate 3000 is bonded to the back side of the first semiconductor substrate 101Wb via an adhesive layer. The adhesive layer includes, for example, a TBM layer 3100 and a release layer 3200.

[0069] Referring to Figure 6H, after the first carrier substrate 3000 is bonded, the second carrier substrate 4000 is separated from the first semiconductor substrate 101Wb and the upper structure. The second carrier substrate 4000 is separated by irradiation with a UV laser. As shown in Figure 6H, during the separation process of the second carrier substrate 4000 by UV laser irradiation, the release layer 4200 is held on the upper pad 130u and the upper protective layer 140u. This release layer 4200 is removed by a cleaning process or the like. By removing the release layer 4200, the process of forming multiple initial first semiconductor chips on the first semiconductor substrate 101Wb at the stage shown in Figure 5A is completed. For reference, the process of binding carriers for back grinding and dicing processes, and then separating the carriers after these processes, is called the WSS (Wafer Supporting System) process. Furthermore, the WSS process may include a WSS bonding process, which is a process for bonding carriers, and a WSS debonding process, which is a process for separating carriers.

[0070] Figures 7A and 7B are cross-sectional views showing the process from the stage in Figure 5A to the stage in Figure 5B in more detail. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A to 6H will be briefly explained or omitted.

[0071] Referring to Figure 7A, after forming multiple initial first semiconductor chips on the first semiconductor substrate 101Wb in Figure 5A, a photoresist (PR) pattern 700 is formed on the initial first semiconductor chips. The PR pattern 700 has a configuration that covers each of the initial first semiconductor chips. Next, the first semiconductor substrate 101Wb and the upper structure are individually separated into initial first semiconductor chips 100a by a plasma dicing process P / D. The plasma dicing process P / D is performed by etching using plasma, with PR pattern 700 as the mask.

[0072] For reference, a brief explanation of the plasma dicing process (P / D) for wafers is as follows: a protective tape or PLC (Protective Layer Coating) is formed on a wafer containing multiple semiconductor chips. Next, the scribe lanes between semiconductor chips are removed using a laser grooving process. Laser grooving is also referred to as laser sawing. Alternatively, blade sawing may be used instead of laser sawing. On the other hand, the laser grooving process may not completely remove the scribed lines. Therefore, a plasma dicing process P / D is performed to completely remove the scribe lane. In the plasma dicing process P / D, protective tape or PLC acts as a mask. In the semiconductor package manufacturing method of this embodiment, instead of the PR pattern 700, a laser grooving process using protective tape or PLC is performed first, followed by a plasma dicing process P / D.

[0073] Referring to Figure 7B, after the plasma dicing process P / D, the PR pattern 700 is removed, and as indicated by the arrows, the release layer 3200 is irradiated with a UV laser to separate each of the initial first semiconductor chips 100a from the first carrier substrate 3000. As can be seen from Figure 5B, a release layer 3200 is held on the underside of each initial first semiconductor chip 100a. After the initial first semiconductor chip 100a is stacked on the initial second semiconductor chip, this release layer 3200 is removed by a cleaning process.

[0074] Figures 8A to 8I are cross-sectional views showing the process from stage 5C to stage 5D in more detail. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A through 7B will be briefly explained or omitted.

[0075] Referring to Figure 8A, after stacking the initial first semiconductor chip 100a in Figure 5C, an additional back grinding process is performed to reduce the thickness of the initial first semiconductor chip 100a. Through an additional back grinding process, the thickness of the initial first semiconductor chip 100a is reduced to the second level (2nd-BG) shown in Figure 6F. After an additional back grinding process, a first gap fill liner 515a is formed to cover the top and sides of the initial first semiconductor chip 100a. Next, a first sealing layer 510a is formed on the first gap fill liner 515a. The first sealing layer 510a covers the top surface of the initial first semiconductor chip 100a and also fills the gaps between the initial first semiconductor chips 100a. For example, the first gap fill liner 515a includes a silicon nitride film, and the first sealing layer 510a includes a silicon oxide film. However, the materials of the first gap fill liner 515a and the first sealing layer 510a are not limited to the substances described above.

[0076] Referring to Figure 8B, after the formation of the first gap fill liner 515a and the first sealing layer 510a, an insulating film grinding process (IG) is performed to remove the upper portion of the first sealing layer 510a. The upper surface of the first sealing layer 510b is flattened through an insulating film grinding process (IG). On the other hand, if the first sealing layer 510a contains an oxide film, the insulating film grinding step (IG) corresponds to the oxide film grinding step.

[0077] Referring to Figure 8C, after the insulating film grinding process (IG), a first CMP process CMP1 is performed to remove the portion of the first sealing layer 510b and the portion of the first gap fill liner 515a on the upper part of the first semiconductor substrate 101a. Through the first CMP process CMP1, the first sealing layer 510c and the first gap fill liner 515b are maintained only on the side surface of the first semiconductor substrate 101a.

[0078] Referring to Figure 8D, after the first CMP process CMP1, a semiconductor recess (SR) process is performed to remove the upper portion of the first semiconductor substrate 101a. The through-electrode 120 protrudes from the upper surface of the first semiconductor substrate 101 during the semiconductor recess process (SR). The semiconductor recess process (SR) is performed using a dry-etch process. However, in one embodiment, the semiconductor recess (SR) process may also be a wet-etch process. For reference, the upper surface of the first semiconductor substrate 101 corresponds to the lower surface of the first semiconductor substrate 101 of the first semiconductor chip 100 in the semiconductor package 1000 shown in Figure 1A. Meanwhile, the upper portion of the first gap fill liner 515b is also removed during the semiconductor recess process (SR). The first gap fill liner 515 is formed by removing the upper portion of the first gap fill liner 515b. On the other hand, since the first semiconductor substrate 101 contains Si, the semiconductor recess process (SR) corresponds to the Si recess process.

[0079] Referring to Figure 8E, after the semiconductor recess (SR) process, a second gap fill liner 525a is formed to cover the initial first semiconductor chip 100c and the first sealing layer 510c. Next, a second sealing layer 520a is formed on the second gap fill liner 525a. For example, the second gap fill liner 525a includes a silicon nitride film, and the second sealing layer 520a includes a silicon oxide film. However, the materials of the second gap fill liner 525a and the second sealing layer 520a are not limited to the substances described above.

[0080] Referring to Figure 8F, after the formation of the second gap fill liner 525a and the second sealing layer 520a, the second CMP process CMP2 is performed on the first sealing layer 510c, the second gap fill liner 525a, and the second sealing layer 520a. Through the second CMP process CMP2, the upper surface of the through electrode 120 is exposed. Furthermore, through the second CMP process CMP2, the first sealing layer 510d is maintained on the side surface of the first semiconductor substrate 101, and the second gap fill liner 525 and the lower sealing material 520 are formed on the upper surface of the first semiconductor substrate 101. For reference, the upper surface of the through-electrode 120 corresponds to the lower surface of the through-electrode 120 of the first semiconductor chip 100 in the semiconductor package 1000 shown in Figure 1A.

[0081] Referring to Figure 8G, after the second CMP process CMP2, a lower protective layer 140d' is formed on the through electrode 120, the first sealing layer 510d, the second gap fill liner 525, and the lower sealing material 520. The lower protective layer 140d' includes a first lower insulating layer 142d' and a second lower insulating layer 144d'. For example, the first insulating layer 142d' contains a silicon carbon nitride (SiCN) film, and the second insulating layer 144d' contains a silicon oxide film. However, the materials of the first insulating layer 142d' and the second insulating layer 144d' are not limited to the substances mentioned above.

[0082] Referring to Figure 8H, after the formation of the lower protective layer 140d', the lower protective layer 140d' is patterned to form the lower protective layer 140d. The lower protective layer 140d includes an open section. The upper surface of the through electrode 120 is exposed through the open portion of the lower protective layer 140d. The patterning of the lower protective layer 140d' is performed through the exposure process.

[0083] Referring to Figure 8I, after the formation of the lower protective layer 140d, the first sealing layer 510d is patterned to form the side sealing material 510. The side sealing material 510 includes a trench T. The second tip pad 230 is exposed through the bottom surface of the trench T in the side sealant 510. The patterning of the first sealing layer 510d is performed by an exposure process using the PR layer 800. Next, the PR layer 800 is removed, and the open portion of the lower protective layer 140d and the trench T of the side sealant 510 are filled with metal, such as Cu, by a plating process. Next, the copper in the open section and the outer portion of the trench T is removed by the CMP process. By removing the Cu from the open portion and the outer portion of the trench T, a lower pad 130d is formed in the open portion and an external through electrode 400 is formed in the trench T, as shown in Figure 5D. On the other hand, since the lower pad 130d and the external through electrode 400 are formed together by the plating process and the CMP process, the upper surfaces of the lower pad 130d and the external through electrode 400 form the same plane. For reference, the upper surfaces of the lower pad 130d and the external through-electrode 400 correspond to the lower surfaces of the lower pad 130d and the external through-electrode 400 of the first semiconductor chip 100 in the semiconductor package 1000 in Figure 1A.

[0084] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0085] 100, 100a~100g First Semiconductor Chip 101, 101a, 101W, 101Wa, 101Wb First Semiconductor Substrate 110 First Active Layer 111, 211 Interlayer insulating layer 113, 213 Integrated elements 115, 215 wiring 117, 217 Internal pads 120 Through electrode 130 First Chip Pad 130d Lower pad 130u upper pad 140 1st protective layer 140d bottom protective layer 140u top protective layer 200 Second Semiconductor Chip 201 Second Semiconductor Substrate 210 Second Active Layer 230 First Chip Pad 240 Second protective layer 300 External connection terminals 310 Pillar 320 Bump 330 Package protective layer 400 External through electrode 500 sealing material 510 Side sealing material 515 1st Gap Fill Liner 520 Lower sealing material 525 Second Gap Fill Liner 600 redistribution layer 700, 800 PR (Photo-Resist) pattern 1000, 1000a~1000c Semiconductor Packages 1100 Package Substrate 1150, 1250, 1330 (1st, 2nd, 3rd) connection terminals 1200 Interposer 1260 Underfill 1300 semiconductor devices 1400 Si-Bridge 1500 External sealing material 2000, 2000a~2000c System Package 3000, 4000 (1st, 2nd) carrier substrates

Claims

1. A first semiconductor chip comprising a first upper surface which is an active surface, and a first lower surface facing the first upper surface, with through electrodes disposed inside, A second semiconductor chip is stacked on the first semiconductor chip and comprises a second lower surface which is an active surface and a second upper surface facing the second lower surface, and has a larger size in the horizontal direction than the first semiconductor chip. It has an external through-electrode located adjacent to the first semiconductor chip and below the second semiconductor chip, A semiconductor package characterized in that the second semiconductor chip is stacked on the first semiconductor chip by HCB (Hybrid Copper Bonding).

2. The first semiconductor chip includes a first upper pad on the first upper surface and a first lower pad on the first lower surface. The second semiconductor chip includes a second lower pad on the second lower surface, The semiconductor package according to claim 1, characterized in that the lower surface of the external through electrode forms substantially the same plane as the lower surface of the first lower pad.

3. The upper surface of the external through electrode is connected to the second lower pad, The semiconductor package according to claim 2, characterized in that an external connection terminal is arranged on the lower surface of the external through electrode and the lower surface of the first lower pad.

4. The semiconductor package according to claim 2, characterized in that the first lower pad is directly connected to the through electrode.

5. The semiconductor package according to claim 2, characterized in that the arrangement area of ​​the first upper pad is not limited by the arrangement area of ​​the through-electrode.

6. A first semiconductor chip comprising a first upper surface which is an active surface, and a first lower surface facing the first upper surface, with through electrodes disposed inside, A second semiconductor chip is stacked on the first semiconductor chip and comprises a second lower surface which is an active surface and a second upper surface facing the second lower surface, and has a larger size in the horizontal direction than the first semiconductor chip. A sealing material that seals the first semiconductor chip on the lower surface of the second semiconductor chip, An external through-electrode is positioned adjacent to the first semiconductor chip and below the second semiconductor chip, and penetrates the encapsulating material, The external through electrode has a lower surface and an external connection terminal positioned on the lower surface of the first lower pad of the first semiconductor chip, The second semiconductor chip is stacked on the first semiconductor chip using an HCB. A semiconductor package characterized in that the lower surface of the external through-electrode forms substantially the same plane as the lower surface of the first lower pad.

7. The first semiconductor chip includes a first upper pad on the first upper surface and a first lower pad on the first lower surface. The first lower pad is directly connected to the through electrode, The semiconductor package according to claim 6, characterized in that the first upper pad is connected to the through-electrode via the multi-wiring layer of the first semiconductor chip.

8. Package substrate and A first semiconductor element disposed on the package substrate, The first semiconductor element is adjacent to at least one second semiconductor element disposed on the package substrate, The first semiconductor element has a package structure that includes: a first semiconductor chip having a first upper surface which is an active surface and a first lower surface facing the first upper surface, and having through electrodes disposed inside; a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface which is an active surface and a second upper surface facing the second lower surface, and having a larger size in the horizontal direction than the first semiconductor chip; and external through electrodes disposed adjacent to the first semiconductor chip and below the second semiconductor chip. A semiconductor package characterized in that the second semiconductor chip is stacked on the first semiconductor chip by an HCB.

9. The first semiconductor chip includes a first upper pad on the first upper surface and a first lower pad on the first lower surface. The second semiconductor chip includes a second lower pad on the second lower surface, The semiconductor package according to claim 8, characterized in that the lower surface of the external through electrode forms substantially the same plane as the lower surface of the first lower pad.

10. The first semiconductor device includes a logic chip, The semiconductor package according to claim 8, characterized in that the second semiconductor element includes an HBM (High Bandwidth Memory) package.

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