Semiconductor packages

Abstract

The present invention provides a semiconductor package that includes multiple silicon bridges of different sizes, and in which the integration density is improved by stacking and arranging the multiple silicon bridges. [Solution] The semiconductor package according to the present invention comprises a package substrate, a bridge chip structure containing a plurality of bridge chips housed within the package substrate and stacked vertically, and a plurality of semiconductor chips arranged on the package substrate and electrically connected via the bridge chip structure, wherein the plurality of bridge chips have different sizes.

Description

Technical Field

[0005] ,

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including a silicon bridge.

Background Art

[0002] In recent years, the market for electronic products has seen a rapid increase in the demand for portable devices, which has led to a requirement for miniaturization and weight reduction of the electronic components mounted on these electronic products. For the miniaturization and weight reduction of electronic components, the semiconductor packages mounted on them are required to process high-capacity data while gradually reducing their size, and their development has become an everyday issue.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the problems in the above-mentioned conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package including a plurality of silicon bridges having different sizes, wherein the plurality of silicon bridges are stacked and arranged to improve the integration degree.

Means for Solving the Problems

[0004] The semiconductor package according to the present invention made to achieve the above object has a package substrate, a bridge chip structure including a plurality of bridge chips housed in the package substrate and stacked in the vertical direction, and a plurality of semiconductor chips arranged on the package substrate and electrically connected through the bridge chip structure, wherein the plurality of bridge chips have different sizes.

[0005] Furthermore, a semiconductor package according to an embodiment of the present invention comprises a package substrate, a bridge chip structure including a plurality of bridge chips housed within the package substrate and stacked vertically, and a plurality of semiconductor chips arranged on the package substrate and electrically connected via the bridge chip structure, wherein the plurality of bridge chips include a first bridge chip having a first width in a first horizontal direction, and a second bridge chip arranged on the lower surface of the first bridge chip and having a second width greater than the first width in the first horizontal direction, and the second bridge chip further includes a first through-via penetrating the second bridge chip in the vertical direction.

[0006] Furthermore, an embodiment of the present invention provides a semiconductor package comprising: a package substrate including a wiring structure and a cavity; a bridge chip structure comprising: a first bridge chip housed within the package substrate and having a first width in a first horizontal direction; a second bridge chip stacked vertically on the lower surface of the first bridge chip and having a second width greater than the first width in the first horizontal direction; and a plurality of semiconductor chips arranged on the package substrate along the first horizontal direction, each comprising a first region electrically connected to the first bridge chip and a second region electrically connected to the second bridge chip, wherein the bridge chip structure further comprises a plurality of vertical wires electrically connecting the second regions and the second bridge chip of the plurality of semiconductor chips. [Effects of the Invention]

[0007] According to the semiconductor package of the present invention, by including a bridge chip structure in which multiple bridge chips are stacked, the area of ​​the bridge chip structure can be reduced and the integration density can be improved. Furthermore, by stacking and arranging multiple bridge chips, multiple bridge circuits can be arranged so as to be superimposed in the vertical direction Z. Therefore, it is possible to increase the number of bridge circuits while minimizing the area of ​​the bridge chip structure. Furthermore, by placing a second bridge chip larger than the first bridge chip at the lower end of the first bridge chip, the second bridge chip can be electrically connected to multiple semiconductor chips via multiple vertical wires. By electrically connecting the second bridge chip to multiple semiconductor chips via multiple vertical wires, structures such as TSVs that penetrate the upper end of the first bridge chip can be omitted, thereby reducing the difficulty of manufacturing the semiconductor package. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 2] This is an enlarged cross-sectional view of the "EX1" portion in Figure 1. [Figure 3] This is a plan view showing a schematic configuration of a bridge chip structure for a semiconductor package according to an embodiment of the present invention. [Figure 4A] This is a plan view showing a schematic configuration of a bridge chip structure for a semiconductor package according to an embodiment of the present invention. [Figure 4B] This is a plan view showing a schematic configuration of a bridge chip structure for a semiconductor package according to an embodiment of the present invention. [Figure 4C] This is a plan view showing a schematic configuration of a bridge chip structure for a semiconductor package according to an embodiment of the present invention. [Figure 5A] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 5B] This is an enlarged cross-sectional view of the "EX2" portion in Figure 5A. [Figure 6A] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 6B] This is an enlarged cross-sectional view of the "EX3" portion in Figure 6A. [Figure 7] This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8]This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view illustrating, in sequence, a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] Next, specific examples of embodiments for implementing the semiconductor package according to the present invention will be described with reference to the drawings. The same reference numerals are used for identical components in the drawings, and redundant explanations for them are omitted.

[0010] Figure 1 is a cross-sectional view showing the schematic configuration of a semiconductor package according to an embodiment of the present invention, Figure 2 is an enlarged cross-sectional view of the "EX1" portion of Figure 1, and Figure 3 is a plan view showing the schematic configuration of a bridge chip structure of a semiconductor package according to an embodiment of the present invention.

[0011] Referring to Figures 1 to 3, the semiconductor package 10 of the present invention includes a package substrate 100, a bridge chip structure 200, a plurality of semiconductor chips (300a, 300b), and a encapsulating material 400. In one embodiment, the package substrate 100 includes, for example, a ceramic substrate, a PCB (Printed Circuit Board), an organic substrate, an interposer substrate, and the like. In one embodiment, the package substrate 100 may include an active wafer such as a silicon wafer.

[0012] The package substrate 100 includes a core layer 110, a lower wiring structure 120, an upper wiring structure 130, and a protective layer 140. The core layer 110 includes, for example, glass fiber such as FR4 and resin. Also, the core layer may include a BT (Bismaleimide-Triazine) resin, a PC (Poly Carbonate) resin, build up films such as ABF (Ajinomoto Build-up Film (registered trademark)), or other laminate resins. In one embodiment, the core layer may be omitted.

[0013] In one embodiment, the lower wiring structure 120 is disposed below the core layer 110. The lower wiring structure 120 includes a plurality of lower conductive layers 121, a plurality of lower conductive vias 123, and a lower insulating layer 122. The lower insulating layer 122 is disposed below the core layer 110 and includes a plurality of stacked layers. The lower insulating layer 122 covers the plurality of lower conductive layers 121 and the plurality of lower conductive vias 123. In one embodiment, the plurality of lower conductive layers 121 and the plurality of lower conductive vias 123 are provided within the lower insulating layer 122. The plurality of lower conductive layers 121 are spaced apart from each other in the vertical direction Z within the lower insulating layer 122 and each extend in the horizontal direction (X and / or Y). For example, the plurality of lower conductive layers 121 are arranged at different vertical levels to form a multilayer wiring structure. The plurality of lower conductive vias 123 are each extended between the plurality of lower conductive layers 121 arranged at different vertical levels to electrically connect between the plurality of lower conductive layers 121 located at different vertical levels.

[0014] In this specification, the first horizontal direction X and the second horizontal direction Y are directions that intersect each other within the horizontal direction. For example, the first horizontal direction X and the second horizontal direction Y are directions perpendicular to each other. The vertical direction Z intersects both the first horizontal direction X and the second horizontal direction Y. For example, the vertical direction Z is the direction perpendicular to the first horizontal direction X and the second horizontal direction Y. Furthermore, the multiple lower conductive vias 123 electrically connect the multiple lower conductive layers 121 to the multiple lower pads 141. Furthermore, the multiple lower conductive vias 123 electrically connect the multiple lower conductive layers 121 to the core layer 110.

[0015] In one embodiment, the upper wiring structure 120 is positioned on top of the core layer 110. The upper wiring structure 120 includes a plurality of upper conductive layers 131, a plurality of upper conductive vias 133, a plurality of upper pads 135, and an upper insulating layer 132. The upper insulating layer 132 is located on top of the core layer 110 and includes multiple stacked layers. The upper insulating layer 132 covers a plurality of upper conductive layers 131, a plurality of upper conductive vias 133, and a plurality of upper pads 135. In one embodiment, a plurality of upper conductive layers 131, a plurality of upper conductive vias 133, and a plurality of upper pads 135 are provided within an upper insulating layer 132. Multiple upper conductive layers 131 are separated from each other in the vertical direction Z within the upper insulating layer 132 and each extends horizontally (X and / or Y). For example, multiple upper conductive layers 131 are arranged at different vertical levels to form a multilayer wiring structure. Multiple upper conductive vias 133 extend between multiple upper conductive layers 131 located at different vertical levels, thereby electrically connecting the multiple upper conductive layers 131 located at different vertical levels. Furthermore, the multiple upper conductive vias 133 electrically connect the multiple upper conductive layers 131 to the multiple upper pads 135. Furthermore, the multiple upper conductive vias 133 electrically connect the multiple upper conductive layers 131 to the core layer 110. In one embodiment, the number of layers of the lower wiring structure 120 and the upper wiring structure 130 may be the same or different.

[0016] In one embodiment, the upper surfaces and side walls of multiple upper pads 135 are covered by an upper insulating layer 132. The upper surfaces of the multiple upper pads 135 are coplanar with the upper surface of the upper insulating layer 132. Multiple upper pads 135 contain copper (Cu). In one embodiment, the lower insulating layer 122 and the upper insulating layer 132 each include a prepreg, but are not limited to these. For example, the lower insulating layer 122 and the upper insulating layer 132 are each made of at least one material selected from phenolic resin, epoxy resin, and polyimide.

[0017] The lower insulating layer 122 and the upper insulating layer 132 may each contain at least one substance selected from FR-4 (Frame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0018] The conductive pattern, such as the plurality of lower conductive layers 121, the plurality of lower conductive vias 123, the plurality of upper conductive layers 131, and the plurality of upper conductive vias 133, may be, but are not limited to, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), or alloys thereof. In one embodiment, the conductive pattern is formed by laminating a metal or metal alloy on a seed layer containing copper, titanium, titanium nitride, or tungsten titanium. On the other hand, in one embodiment, the package substrate 100 is a redistribution substrate. In such cases, the package substrate 100 may not include a separate core layer, but may include an interlayer insulating layer of PID (Photo-Imageable Dielectric) resin and multiple layers of wiring.

[0019] In one embodiment, a protective layer 140 is placed on the lower surface of the lower wiring structure 120. The lower surface of the protective layer 140 is flush with the lower surfaces of the multiple lower pads 141. However, the lower surface of the protective layer 140 is not necessarily on the same plane as the lower surface of the lower pad 141, and the lower surface of the protective layer 140 may be located higher than the lower surface of the lower pad 141. The protective layer 140 may include, for example, solder resist, but the material of the protective layer 140 is not limited to solder resist. Multiple lower pads 141 are electrically isolated by a protective layer 140. In one embodiment, an external connection terminal 150, such as a solder ball, is placed on the lower pad 141. The external connection terminal 150 connects the semiconductor package 10 to the package substrate of an external system, or to the main board of an electronic device such as a mobile device. The external connection terminal 150 includes at least one of the following conductive materials: solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). However, the material of the external connection terminal 150 is not limited to the aforementioned substances.

[0020] In one embodiment, the bridge chip structure 200 is housed within the package substrate 100. For example, the bridge chip structure 200 is placed in the cavity C (see Figure 10) of the package substrate 100. At this time, the upper surface of the bridge chip structure 200 is in the same plane as the upper surface of the upper wiring structure 130. In one embodiment, the bridge chip structure 200 is formed within the package substrate 100 and is configured to electrically connect the package substrate 100 with a plurality of semiconductor chips (300a, 300b). The bridge chip structure 200 includes a plurality of bridge chips stacked in the vertical direction Z. For example, the bridge chip structure 200 includes a first bridge chip 210 and a second bridge chip 220. The first bridge chip 210 is stacked on top of the second bridge chip 220. In Figures 1 and 2, the bridge chip structure 200 is shown to contain two bridge chips (210, 220), but it is not limited to this, and the bridge chip structure 200 may contain three or more bridge chips.

[0021] In one embodiment, the upper surface of the first bridge chip 210 is a surface adjacent to the active surface of the semiconductor substrate constituting the first bridge chip 210, and the lower surface of the first bridge chip 210 is a surface adjacent to the inactive surface of the semiconductor substrate constituting the first bridge chip 210. Furthermore, the upper surface of the second bridge chip 220 is adjacent to the active surface of the semiconductor substrate constituting the second bridge chip 220, and the lower surface of the second bridge chip 220 is adjacent to the inactive surface of the semiconductor substrate constituting the second bridge chip 220. In one embodiment, the multiple bridge chips stacked in the vertical direction Z have different sizes. At this time, the size of the multiple bridge chips increases as they move away from the top surface of the package substrate 100. For example, multiple bridge chips are arranged in a stepped pattern, with their size increasing as they move away from the top surface of the package substrate 100.

[0022] Specifically, the bridge chip positioned downwards in the vertical Z direction among the multiple bridge chips has an even larger width in the same direction as the arrangement of the multiple semiconductor chips (300a, 300b). For example, as shown in Figures 1 and 2, when multiple semiconductor chips (300a, 300b) are arranged in a first horizontal direction X, the bridge chip among the multiple bridge chips that is positioned downwards in the vertical direction Z has an even larger width in the first horizontal direction. For example, the first bridge tip 210 has a first width in the first horizontal direction X, and the second bridge tip 220 has a second width in the first horizontal direction X. In this case, the second panel is larger than the first panel. At this time, the widths of the first bridge tip 210 and the second bridge tip 220 in the second horizontal direction Y are the same, but are not limited to this.

[0023] In one embodiment, the first bridge chip 210 includes a plurality of first bridge circuits 211 internally. The first bridge circuit 211 is configured to electrically connect the first regions of multiple semiconductor chips (300a, 300b). For example, the first region of the first semiconductor chip 300a is electrically connected to the first region of the second semiconductor chip 300b via the first bridge circuit 211. The second bridge chip 220 includes a plurality of second bridge circuits 221 internally. The second bridge circuit 221 is configured to electrically connect the second regions of multiple semiconductor chips (300a, 300b). For example, the second region of the first semiconductor chip 300a is electrically connected to the second region of the second semiconductor chip 300b via the second bridge circuit 221.

[0024] In one embodiment, a plurality of first bridge circuits 211 are arranged within the first bridge chip 210, spaced apart in the second horizontal direction Y and / or vertical direction Z, and extending in the first horizontal direction X. Multiple second bridge circuits 221 are arranged within the second bridge chip 220, spaced apart in the second horizontal direction Y and / or vertical direction Z, and extended in the first horizontal direction X. At this time, the vertical levels of the multiple second bridge circuits 221 are lower than the vertical levels of the multiple first bridge circuits 211. By stacking and arranging multiple bridge chips (210, 220), multiple bridge circuits (211, 221) can be arranged so that they are superimposed in the vertical Z direction.

[0025] In one embodiment, the bridge chip structure 200 includes a plurality of upper bridge pads 240. Multiple upper bridge pads 240 are coplane with the upper surface of the bridge chip structure 200. The first upper bridge pad 241 is electrically connected to the first bridge circuit 211 of the first bridge chip 210. The first upper bridge pad 241 is electrically connected to the first regions of multiple semiconductor chips (300a, 300b) via multiple first connection terminals 411. The second upper bridge pad 242 is electrically connected to the second bridge circuit 221 of the second bridge chip 220. The second upper bridge pad 242 is electrically connected to the second regions of multiple semiconductor chips (300a, 300b) via multiple second connection terminals 412.

[0026] In one embodiment, the bridge chip structure 200 further includes a plurality of vertical wires 250 connecting the second bridge circuit 221 and the second upper bridge pad 242. Multiple vertical wires 250 extend vertically in the Z direction between the second bridge tip 220 and the second upper bridge pad 242. Multiple vertical wires 250 electrically connect the second bridge chip 220 to the second region of the multiple semiconductor chips (300a, 300b). Although not shown, if the bridge chip structure 200 contains three or more bridge chips, the remaining bridge chips, excluding the bridge chip located at the top, are electrically connected to multiple vertical wires 250. In this case, the multiple vertical wires 250 may include, but are not limited to, gold (Au), aluminum (Al), and copper (Cu).

[0027] In one embodiment, a plurality of vertical wires 250 are arranged horizontally apart from the first bridge tip 210. For example, if multiple semiconductor chips (300a, 300b) are arranged in a first horizontal direction X, the multiple vertical wires 250 are arranged spaced apart from the first bridge chip 210 in the first horizontal direction X, but are not limited to this arrangement. Furthermore, the multiple vertical wires 250 are arranged horizontally, spaced apart from each other, with the first bridge tip 210 in between. At this time, the length of the multiple vertical wires 250 in the vertical direction Z is greater than or equal to the height of the first bridge tip 210 in the vertical direction Z.

[0028] For comparison, in the case of conventional semiconductor package bridge chip structures, a larger area is required in the horizontal direction (e.g., the second horizontal direction Y) to accommodate multiple bridge circuits, which increases the difficulty of manufacturing the semiconductor package and reduces its structural stability. On the other hand, the semiconductor package 10 according to an embodiment of the present invention includes a bridge chip structure 200 in which a plurality of bridge chips (210, 220) are stacked, thereby reducing the area of ​​the bridge chip structure 200 and improving the integration density. By stacking and arranging multiple bridge chips (210, 220), multiple bridge circuits (211, 221) can be arranged so that they are superimposed in the vertical Z direction. Therefore, the number of bridge circuits (211, 221) can be increased while minimizing the area of ​​the bridge chip structure 200. Furthermore, by placing a second bridge chip 220, which is larger than the first bridge chip 210, at the lower end of the first bridge chip 210, the second bridge chip 220 can be electrically connected to multiple semiconductor chips (300a, 300b) via multiple vertical wires 250. By electrically connecting the second bridge chip 220 to multiple semiconductor chips (300a, 300b) via multiple vertical wires 250, structures such as TSVs that penetrate the upper first bridge chip 210 can be omitted, thereby reducing the manufacturing difficulty of the semiconductor package 10.

[0029] In one embodiment, a first adhesive layer 232 is interposed between the first bridge tip 210 and the second bridge tip 220. The first adhesive layer 232 is configured to bond the lower surface of the first bridge tip 210 and the upper surface of the second bridge tip 220. The first adhesive layer 232 contains a material that electrically insulates the first bridge tip 210 and the second bridge tip 220. Furthermore, a second adhesive layer 234 is interposed between the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100. The second adhesive layer 234 is configured to bond the lower surface of the second bridge chip 220 to the upper surface of the upper wiring structure 130. The second adhesive layer 234 contains a substance that electrically insulates the second bridge chip 220 from the upper wiring structure 130.

[0030] In one embodiment, the bridge chip structure 200 includes a first bridge chip 210, a second bridge chip 220, and a sealing layer 260 covering a plurality of vertical wires 250. The sealing layer 260 is placed on the package substrate 100 to seal the bridge chip structure 200. Specifically, the sealing layer 260 is formed to fill the inside of the cavity C (see Figure 10) and cover the bridge chip structure 200 and the upper wiring structure 130. The sealing layer 260 can be formed from thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or resins containing strengthening materials such as inorganic fillers, specifically ABF (Ajinomoto Build-up Film®), FR-4, BT, etc., but is not limited to these. The sealing layer 260 can also be formed from molding materials such as epoxy mold compound (EMC) or photosensitive materials such as PIE (photoimagable encapsulant).

[0031] In one embodiment, the semiconductor package 10 includes a plurality of semiconductor chips (300a, 300b) arranged horizontally on a package substrate 100. In Figure 1, the multiple semiconductor chips (300a, 300b) are shown to be spaced apart in the first horizontal direction X, but this is not the only way in which they can be arranged. For example, multiple semiconductor chips (300a, 300b) are arranged spaced apart in the first horizontal direction X and / or the second horizontal direction Y. In one embodiment, the first semiconductor chip 300a is electrically connected to the second semiconductor chip 300b.

[0032] Each of the semiconductor chips (300a, 300b) includes a first region electrically connected to the first bridge chip 210 and a second region electrically connected to the second bridge chip 220. The first and second regions each contain circuit patterns. The first region may be the core power region of a logic semiconductor chip. The second domain could be the physical hierarchy of a logic semiconductor chip. The physical layer in a logic semiconductor chip performs the role of converting terminal data into electrical signals and transmitting them, and receiving electrical signals and interpreting them as data. In one embodiment, the first region of each of the multiple semiconductor chips (300a, 300b) is superimposed on the bridge chip structure 200 in the direction Z perpendicular to it. Furthermore, the second regions of each of the multiple semiconductor chips (300a, 300b) are superimposed on the bridge chip structure 200 in the vertical Z direction.

[0033] In one embodiment, the plurality of semiconductor chips (300a, 300b) may be logic chips, memory chips, or bridge chips. Memory chips include, for example, volatile memory chips such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), and non-volatile memory chips such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). Logic chips include, for example, microprocessors such as central processing units (CPUs), graphics processing units (GPUs), or application processors (APs), analog elements, or digital signal processors. Alternatively, the multiple semiconductor chips (300a, 300b) could be HBM (High Bandwidth Memory) chips with increased bandwidth due to the stacking of multiple DRAM layers.

[0034] In one embodiment, the multiple connection terminals 410 electrically connect the multiple semiconductor chips (300a, 300b) to the bridge chip structure 200 and / or the upper wiring structure 130. Specifically, the multiple connection terminals 410 are electrically connected to the bridge chip structure 200 via the multiple upper bridge pads 240, and the multiple connection terminals 410 are electrically connected to the upper wiring structure 130 via the multiple upper pads 135. At this time, the multiple first connection terminals 411 electrically connect the first bridge chip 210 to the first regions of the multiple semiconductor chips (300a, 300b). Multiple second connection terminals 412 electrically connect the second bridge chip 220 to the second regions of multiple semiconductor chips (300a, 300b). In one embodiment, the encapsulating material 400 covers a plurality of semiconductor chips (300a, 300b). Furthermore, the sealing material 400 covers the upper surface of the upper wiring structure 130 and the connection terminals 410. The encapsulant 400 contains, but is not limited to, EMC (Epoxy Mold Compound).

[0035] Figures 4A to 4C are plan views showing the schematic configuration of a bridge chip structure for a semiconductor package according to an embodiment of the present invention. In explaining with reference to Figures 4A to 4C, the same reference numbers as in Figures 1 to 3 refer to the same components, and specific explanations regarding them will be omitted.

[0036] Referring to Figure 4A, the bridge chip structure 200a includes a first bridge chip 210, a second bridge chip 220, and a third bridge chip 230. A second bridge tip 220 is positioned on the underside of the first bridge tip 210, and a third bridge tip 230 is positioned on the underside of the second bridge tip 220. At this time, the first bridge chip 210, the second bridge chip 220, and the third bridge chip 230 have different sizes. For example, the first bridge tip 210 has a first width in the first horizontal direction X, the second bridge tip 220 has a second width in the first horizontal direction X, and the third bridge tip 230 has a third width in the first horizontal direction X. In this case, the second panel is larger than the first panel, and the third panel is larger than the second panel. At this time, the widths of the first bridge tip 210, the second bridge tip 220, and the third bridge tip 230 in the second horizontal direction Y are the same, but are not limited to this.

[0037] In one embodiment, the first bridge chip 210 includes a first bridge circuit 211 internally, the second bridge chip 220 includes a second bridge circuit 221 internally, and the third bridge chip 230 includes a third bridge circuit 231 internally. The first bridge circuit 211, the second bridge circuit 221, and the third bridge circuit 231 electrically connect multiple semiconductor chips (300a, 300b). The first bridge circuit 211 is electrically connected to multiple semiconductor chips (300a, 300b) via the first upper bridge pad 241. The second bridge circuit 221 is electrically connected to multiple semiconductor chips (300a, 300b) via the second upper bridge pad 242. At this time, a vertical wire 250 (see Figure 1) extending in the vertical direction Z is placed between the second bridge circuit 221 and the second upper bridge pad 242. The third bridge circuit 231 is electrically connected to multiple semiconductor chips (300a, 300b) via the third upper bridge pad 243. At this time, a vertical wire 250 (see Figure 1) extending in the vertical direction Z is placed between the third bridge circuit 231 and the third upper bridge pad 243.

[0038] Referring to Figures 4B and 4C, the bridge chip structure 200a includes a first bridge chip 210 and a second bridge chip 220. A second bridge tip 220 is positioned on the underside of a first bridge tip 210, and the first bridge tip 210 and the second bridge tip 220 have different sizes. For example, the first bridge tip 210 has a first width in the first horizontal direction X, and the second bridge tip 220 has a second width in the first horizontal direction X. In this case, the second panel is larger than the first panel. Furthermore, the first bridge tip 210 and the second bridge tip 220 have different widths in the second horizontal direction Y. For example, the first bridge tip 210 has a third width in the second horizontal direction Y, and the second bridge tip 220 has a fourth width in the second horizontal direction Y. In this case, the third panel may be larger than the fourth panel (see Figure 4B), and the third panel may be smaller than the fourth panel (see Figure 4C).

[0039] The semiconductor package 10 according to an embodiment of the present invention includes a bridge chip structure (200a, 200b, 200c) in which a plurality of bridge chips (210, 220, 230) are stacked, thereby reducing the area of ​​the bridge chip structure (200a, 200b, 200c) and improving the integration density. By stacking multiple bridge chips (210, 220, 230), multiple bridge circuits (211, 221, 231) can be arranged so that they are superimposed in the vertical Z direction. Therefore, the number of bridge circuits (211, 221, 231) can be increased while minimizing the area of ​​the bridge chip structures (200a, 200b, 200c).

[0040] Figure 5A is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, and Figure 5B is an enlarged cross-sectional view of the "EX2" portion of Figure 5A. In explaining with reference to Figures 5A and 5B, the same reference numbers as in Figures 1 to 3 refer to the same components, and specific explanations regarding them will be omitted.

[0041] Referring to Figures 5A and 5B, the bridge chip structure 500 of the semiconductor package 20 according to an embodiment of the present invention includes a plurality of bridge chips stacked in the vertical direction Z. For example, the bridge chip structure 500 includes a first bridge chip 210 and a second bridge chip 220. In one embodiment, the second bridge chip 220 further includes a first through via 580. The first through via 580 penetrates the second bridge tip 220 in the vertical Z direction. The first through via 580 is positioned to penetrate the second bridge tip 220 in a location that does not overlap the first bridge tip 210 in the vertical Z direction, but is not limited to this. For example, the first through via 580 may be positioned to overlap the first bridge tip 210 in the vertical Z direction and penetrate the second bridge tip 220. In this case, the first through via 580 is a TSV (Through Silicon Via), but it is not limited to this.

[0042] In one embodiment, the first through via 580 is electrically connected to a plurality of vertical wires 250. In other words, the first through-via 580 is electrically connected to the second region of multiple semiconductor chips (300a, 300b) via multiple vertical wires 250. Furthermore, the first through-via 580 is electrically connected to the package substrate 100. The bridge tip structure 500 further includes a lower bridge pad 570, and the first through via 580 is in contact with the lower bridge pad 570. The first through-via 580 is electrically connected to the package substrate 100 via the lower bridge pad 570 and the upper conductive via 133 of the upper wiring structure 130. In this case, the second adhesive layer 234 (see Figure 1), which is configured to bond the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100, is omitted. Multiple lower bridge pads 570 are positioned between the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100. Furthermore, the sealing layer 260 covers the space between the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100, as well as the space between the multiple lower bridge pads 570.

[0043] The semiconductor package 20 according to an embodiment of the present invention includes a bridge chip structure 500 in which a plurality of bridge chips (210, 220) are stacked, thereby reducing the area of ​​the bridge chip structure 500 and improving the integration density. By stacking and arranging multiple bridge chips (210, 220), multiple bridge circuits (211, 221) can be arranged so that they are superimposed in the vertical Z direction. Therefore, the number of bridge circuits (211, 221) can be increased while minimizing the area of ​​the bridge chip structure 500.

[0044] Figure 6A is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, and Figure 6B is an enlarged cross-sectional view of the "EX3" portion of Figure 6A. In explaining with reference to Figures 6A and 6B, the same reference numbers as in Figures 1 to 3 refer to the same components, and specific explanations regarding them will be omitted.

[0045] Referring to Figures 6A and 6B, the bridge chip structure 600 of the semiconductor package 30 according to an embodiment of the present invention includes a plurality of bridge chips stacked in the vertical direction Z. For example, the bridge chip structure 600 includes a first bridge chip 210 and a second bridge chip 220. In one embodiment, the second bridge chip 220 further includes a first through via 580, and the first bridge chip 210 further includes a second through via 680. The first through via 580 penetrates the second bridge tip 220 in the vertical Z direction, and the second through via 680 penetrates the first bridge tip 210 in the vertical Z direction. In this case, the first through via 580 and the second through via 680 are TSVs (Through Silicon Vias), but are not limited to them. In Figures 6A and 6B, the first through via 580 and the second through via 680 are shown to be positioned so as not to overlap each other in the vertical Z direction, but the design is not limited to this arrangement. For example, the first through via 580 and the second through via 680 may be positioned so that they overlap each other in the vertical Z direction.

[0046] In one embodiment, the first through via 580 is electrically connected to a plurality of vertical wires 250. In other words, the first through-via 580 is electrically connected to the second region of multiple semiconductor chips (300a, 300b) via multiple vertical wires 250. The second through-via 680 is electrically connected to the first region of multiple semiconductor chips (300a, 300b) via the first upper bridge pad 241. In one embodiment, the bridge chip structure 600 further includes a lower bridge pad 570 and an intermediate bridge pad 670. The lower bridge pad 570 is in contact with the first through via 580, and the intermediate bridge pad 670 is in contact with the second through via 680. The first through-via 580 is electrically connected to the package substrate 100 via the lower bridge pad 570 and the upper conductive via 133 of the upper wiring structure 130. The second through-via 680 is electrically connected to the second bridge chip 220 via the intermediate bridge pad 670. In other words, the bridge chip structure 600 is electrically connected to multiple semiconductor chips (300a, 300b) and the package substrate 100 via the lower bridge pad 570 and the intermediate bridge pad 670.

[0047] In this case, the second adhesive layer 234 (see Figure 1), which is configured to join the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100, is omitted. Multiple lower bridge pads 570 are positioned between the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100. The first adhesive layer 234 (see Figure 1), which is configured to bond the first bridge tip 210 and the second bridge tip 220, is omitted. Multiple intermediate bridge pads 670 are positioned between the first bridge tip 210 and the second bridge tip 220. Furthermore, the sealing layer 260 covers the space between the first bridge chip 210 and the second bridge chip 220, the space between the second bridge chip 220 and the upper wiring structure 130 of the package substrate 100, the space between the multiple lower bridge pads 570, and the space between the multiple intermediate bridge pads 670.

[0048] The semiconductor package 30 according to an embodiment of the present invention includes a bridge chip structure 600 in which a plurality of bridge chips (210, 220) are stacked, thereby reducing the area of ​​the bridge chip structure 600 and improving the integration density. By stacking and arranging multiple bridge chips (210, 220), multiple bridge circuits (211, 221) can be arranged so that they are superimposed in the vertical Z direction. Therefore, the number of bridge circuits (211, 221) can be increased while minimizing the area of ​​the bridge chip structure 600.

[0049] Figures 7 to 12 are cross-sectional views illustrating, in order, the method for manufacturing a semiconductor package according to an embodiment of the present invention. In explaining with reference to Figures 7 to 12, the same reference numbers as in Figures 1 to 3 refer to the same components, and specific explanations regarding them will be omitted.

[0050] Referring to Figure 7, the first bridge chip 210 is placed on the second bridge chip 220. The lower surface of the first bridge tip 210 and the upper surface of the second bridge tip 220 are joined using the first adhesive layer 232. At this time, the first bridge chip 210 includes a first bridge circuit 211, and the second bridge chip 220 includes a second bridge circuit 221. The first bridge tip 210 and the second bridge tip 220 have different sizes. For example, the first bridge tip 210 has a first width in the first horizontal direction X, and the second bridge tip 220 has a second width in the first horizontal direction X that is larger than the first width.

[0051] Referring to Figure 8, multiple vertical wires 250 are formed. Multiple vertical wires 250 are connected to the second bridge circuit 221 of the second bridge tip 220 and are formed to extend in the vertical direction Z. Multiple vertical wires 250 are positioned horizontally away from the first bridge tip 210. Furthermore, the multiple vertical wires 250 are arranged horizontally, spaced apart from each other, with the first bridge tip 210 in between. At this time, the length of the multiple vertical wires 250 in the vertical direction Z is greater than or equal to the height of the first bridge tip 210 in the vertical direction Z.

[0052] Referring to Figure 9, a sealing layer 260 is formed to cover the first bridge chip 210, the second bridge chip 220, and the multiple vertical wires 250. Subsequently, the upper surface of the sealing layer 260 is flattened. For example, the upper surface of the sealing layer 260 is flattened through a grinding process so that the upper surface of the sealing layer 260 and the upper surface of the first bridge chip 210 form a coplane. Subsequently, multiple upper bridge pads 240 are formed. Multiple first upper bridge pads 241 are electrically connected to the first bridge circuit 211 of the first bridge chip 210, and multiple second upper bridge pads 242 are electrically connected to the second bridge circuit 221 of the second bridge chip 220.

[0053] Referring to Figure 10, prepare the package substrate 100. The package substrate 100 may include, for example, a ceramic substrate, a PCB (Printed Circuit Board), an organic substrate, an interposer substrate, and the like. The package substrate 100 includes a core layer 110, a lower wiring structure 120, an upper wiring structure 130, and a protective layer 140. At this time, a cavity C is formed in the upper wiring structure 130.

[0054] Referring to Figure 11, the bridge chip structure 200 is placed in the cavity C (see Figure 10) of the package substrate 100. The bridge chip structure 200 is placed on the upper wiring structure 130 via a second adhesive layer 234. The lower surface of the second bridge chip 220 and the upper surface of the upper wiring structure 130 are joined using the second adhesive layer 234. Subsequently, an additional sealing layer 260 is formed to fill the space between the bridge chip structure 200 and the cavity C.

[0055] Referring to Figure 12, multiple semiconductor chips (300a, 300b) are arranged on the package substrate 100. At this time, multiple semiconductor chips (300a, 300b) are electrically connected to the bridge chip structure 200 and / or upper wiring structure 130 via multiple connection terminals 410. Specifically, multiple connection terminals 410 are electrically connected to the bridge chip structure 200 via multiple upper bridge pads 240, and multiple connection terminals 410 are electrically connected to the upper wiring structure 130 via multiple upper pads 135. Subsequently, a sealing material 400 is formed to cover multiple semiconductor chips (300a, 300b), the upper surface of the upper wiring structure 130, and the connection terminals 410.

[0056] Referring again to Figure 1, a semiconductor package 10 according to an embodiment of the present invention is manufactured by forming a plurality of external connection terminals 150 on each of the plurality of lower pads 141.

[0057] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0058] 10, 20, 30 semiconductor packages 100 Package Substrates 110 core layers 120 Lower wiring structure 121 Lower conductive layer 122 Lower insulating layer 123 Lower conductive via 130 Upper wiring structure 131 Upper conductive layer 132 Upper insulating layer 133 Upper conductive via 135 Upper pad 140 Protective layer 141 Lower pad 150 External connection terminals 200, 200a, 200b, 200c Bridge Chip Structure 210 First Bridge Chip 211 First Bridge Circuit 220 Second Bridge Chip 221 Second Bridge Circuit 230 Third Bridge Chip 232 1st adhesive layer 234 Second adhesive layer 240 Upper Bridge Pad 241 First Upper Bridge Pad 242 Second Upper Bridge Pad 243 Third Upper Bridge Pad 250 vertical wire 260 Sealing layer 300a semiconductor chip 300b semiconductor chip 400 sealing material 410 Connection terminals 411 First connection terminal 412 Second connection terminal

Claims

1. Package substrate and A bridge chip structure comprising a plurality of bridge chips housed within the package substrate and stacked vertically, The package substrate comprises a plurality of semiconductor chips arranged on the aforementioned package substrate and electrically connected via the aforementioned bridge chip structure, The semiconductor package is characterized in that the plurality of bridge chips have different sizes.

2. The aforementioned multiple bridge chips are A first bridge tip having a first width in the first horizontal direction, The first bridge tip is positioned on the lower surface of the first bridge tip and includes a second bridge tip having a second width in the first horizontal direction, The semiconductor package according to claim 1, characterized in that the second width is greater than the first width.

3. Each of the aforementioned multiple semiconductor chips A first region electrically connected to the first bridge chip, The semiconductor package according to claim 2, further comprising a second region electrically connected to the second bridge chip.

4. The semiconductor package according to claim 3, wherein the bridge chip structure further includes a plurality of vertical wires that electrically connect the second region and the second bridge chip.

5. The semiconductor package according to claim 4, characterized in that the plurality of vertical wires are arranged spaced apart in the first horizontal direction, sandwiching the first bridge chip.

6. The semiconductor package according to claim 4, characterized in that the vertical length of the plurality of vertical wires is greater than or equal to the vertical height of the first bridge chip.

7. The aforementioned bridge chip structure is A first adhesive layer interposed between the first bridge tip and the second bridge tip, The semiconductor package according to claim 2, further comprising a second adhesive layer interposed between the second bridge chip and the package substrate.

8. The first bridge chip includes a first bridge circuit that extends in the first horizontal direction and electrically connects the first regions of the plurality of semiconductor chips to each other. The semiconductor package according to claim 2, characterized in that the second bridge chip includes a second bridge circuit that extends in the first horizontal direction and electrically connects the second regions of the plurality of semiconductor chips to one another.

9. The semiconductor package according to claim 1, characterized in that the size of the plurality of bridge chips increases as they move away from the upper surface of the package substrate.

10. A package substrate including wiring structures and cavities, A bridge chip structure comprising: a first bridge chip housed within the package substrate and having a first width in a first horizontal direction; and a second bridge chip stacked vertically on the lower surface of the first bridge chip and having a second width greater than the first width in a first horizontal direction; The package substrate comprises a plurality of semiconductor chips, each including a first region electrically connected to the first bridge chip and a second region electrically connected to the second bridge chip, arranged along a first horizontal direction on the package substrate. The semiconductor package is characterized in that the bridge chip structure further includes a plurality of vertical wires that electrically connect the second region of the plurality of semiconductor chips and the second bridge chip.

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