Display device

Abstract

We realize high-resolution and high-quality display devices through a stable manufacturing process. [Solution] One embodiment of the present invention discloses a display device comprising a substrate, a first thin-film transistor, and a second thin-film transistor, wherein the first thin-film transistor comprises a first active layer containing an oxide and is positioned above the substrate, and the second thin-film transistor comprises a second active layer containing an oxide and is positioned above the substrate, and the first thin-film transistor is positioned between the substrate and the second thin-film transistor with respect to the thickness direction of the substrate such that the distance between the substrate and the first thin-film transistor is smaller than the distance between the substrate and the second thin-film transistor.

Description

Technical Field

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[0001] Embodiments of the present invention relate to a display apparatus.

Background Art

[0002] In recent years, the uses of display apparatuses have diversified. In addition, display apparatuses are becoming thinner and lighter, and their uses tend to expand.

[0003] Also, as the fields of use of display apparatuses expand and technologies utilizing display apparatuses develop, the image quality characteristics and high-resolution characteristics required for display apparatuses are increasing.

[0004] On the other hand, display apparatuses are in a form similar to a flat plate, and as they become thinner, the number of stages in the manufacturing process increases, and the complexity of the manufacturing process also tends to increase.

[0005] Therefore, there is a limit to implementing a display apparatus with high resolution and high image quality in a stable manufacturing process.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] Embodiments of the present invention provide a display apparatus with high resolution and high image quality.

Means for Solving the Problems

[0008] One embodiment of the present invention discloses a display device comprising a substrate, a first thin-film transistor, and a second thin-film transistor, wherein the first thin-film transistor comprises a first active layer containing an oxide and is positioned above the substrate, and the second thin-film transistor comprises a second active layer containing an oxide and is positioned above the substrate, and the first thin-film transistor is positioned between the substrate and the second thin-film transistor with respect to the thickness direction of the substrate such that the distance between the substrate and the first thin-film transistor is smaller than the distance between the substrate and the second thin-film transistor.

[0009] In this embodiment, one or more interlayer insulating layers may be provided between the first thin-film transistor and the second thin-film transistor.

[0010] In this embodiment, the first thin-film transistor and the second thin-film transistor may be arranged such that at least one region overlaps (contiguous) with respect to the thickness direction of the substrate.

[0011] In this embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may be arranged such that at least one region overlaps with respect to the thickness direction of the substrate.

[0012] In this embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may have different characteristics from each other.

[0013] In this embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may have different electrical properties.

[0014] In this embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may have different electron mobility values.

[0015] In this embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may contain different oxides.

[0016] In this embodiment, a conductive pattern portion may be further included, which is arranged to overlap with the first active layer of the first thin-film transistor or the second active layer of the second thin-film transistor.

[0017] In this embodiment, one or more insulating layers may be disposed between the conductive pattern portion and the first active layer or the second active layer.

[0018] In this embodiment, the conductive pattern portion may be connected to a region of the first thin-film transistor or a region of the second thin-film transistor via one or more contact holes.

[0019] In this embodiment, the first thin-film transistor or the second thin-film transistor may include one or more connecting electrodes connected to the first active layer or the second active layer, and the conductive pattern portion may be electrically connected to at least one region of the connecting electrode.

[0020] In this embodiment, an intermediate conductive layer disposed between the first thin-film transistor and the second thin-film transistor may be further included.

[0021] In this embodiment, the intermediate conductive layer may be formed to correspond to at least the width of the first active layer or the second active layer in one direction.

[0022] In this embodiment, the intermediate conductive layer can include one or more conductive patterns connected to the first thin film transistor or one or more conductive patterns disposed in the same layer or a different layer as the first thin film transistor.

[0023] In this embodiment, the intermediate conductive layer can include being connected to one or more conductive patterns disposed in the second thin film transistor or the same layer or a different layer as the second thin film transistor.

[0024] In this embodiment, through a region where the intermediate conductive layer does not exist, one or more conductive patterns disposed in the first thin film transistor or the same layer or a different layer as the first thin film transistor are electrically connected to one or more conductive patterns disposed in the second thin film transistor or the same layer or a different layer as the second thin film transistor, which can be included.

[0025] In this embodiment, it can include a plurality of thin film transistors disposed in the same layer as the first thin film transistor so as to be adjacent to the first thin film transistor and including an active layer containing an oxide.

[0026] In this embodiment, it can include that a plurality of thin film transistors disposed in the same layer as the second thin film transistor so as to be adjacent to the second thin film transistor and including an active layer containing an oxide are further disposed.

[0027] In this embodiment, it includes a display area on the substrate and a peripheral area disposed on at least one side of the display area, one or more pixels are disposed in the display area, and a driving circuit unit area for generating or controlling one or more signals for the operation of the pixels is disposed in the peripheral area, which can be included.

[0028] In this embodiment, it can include that the first thin film transistor and the second thin film transistor are disposed corresponding to one pixel among the pixels.

[0029] In this embodiment, the pixel may include an active layer containing an oxide adjacent to the first thin-film transistor, and one or more thin-film transistors necessary for driving the pixel may be arranged therein, and the second thin-film transistor may include an active layer containing an oxide adjacent to the second thin-film transistor, and one or more thin-film transistors necessary for driving the pixel may be arranged therein.

[0030] In this embodiment, the one or more thin-film transistors adjacent to the first thin-film transistor are arranged on the same layer, and the one or more thin-film transistors adjacent to the second thin-film transistor are arranged on the same layer.

[0031] In this embodiment, the first thin-film transistor and the second thin-film transistor may be arranged in the drive circuit region in a corresponding manner.

[0032] In this embodiment, the first thin-film transistor and the second thin-film transistor may correspond to each of two different types of drive circuit sections arranged in the drive circuit section region.

[0033] In this embodiment, the drive circuit region may include a plurality of drive circuit sections arranged in the upper and lower layers, respectively, with respect to the interlayer insulating layer, and a plurality of thin-film transistors having an active layer containing oxide adjacent to the first thin-film transistor and arranged in the same layer as the first thin-film transistor, corresponding to each of the plurality of drive circuit sections, and a plurality of thin-film transistors having an active layer containing oxide adjacent to the second thin-film transistor and arranged in the same layer as the second thin-film transistor.

[0034] In this embodiment, the types of drive circuits arranged in the upper and lower layers relative to the interlayer insulating layer may be different.

[0035] In this embodiment, depending on the type of the different drive circuit, the electrical characteristics of the active layer of the first thin-film transistor or an adjacent thin-film transistor may differ from the electrical characteristics of the active layer of the second thin-film transistor or an adjacent thin-film transistor.

[0036] In this embodiment, at least one of the plurality of drive circuit sections may be a buffer circuit section that includes a buffer circuit.

[0037] In this embodiment, at least one of the plurality of drive circuit units may include a plurality of scanning control circuit units that control different scanning control signals.

[0038] In this embodiment, at least one of the plurality of drive circuit units may include a light emission control circuit unit that controls the light emission signal of the pixel.

[0039] In this embodiment, the pixel may include one or more display elements.

[0040] In this embodiment, the display element may include an organic light-emitting element.

[0041] Other aspects, features, and advantages not mentioned above will become clear from the following drawings, claims, and detailed description of the invention. [Effects of the Invention]

[0042] The display device according to the embodiment of the present invention can easily realize high resolution and high image quality characteristics. [Brief explanation of the drawing]

[0043] [Figure 1] This is a schematic cross-sectional view showing a display device according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing a display device according to another embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing a display device according to yet another embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view showing a display device according to yet another embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view showing a display device according to yet another embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing a display device according to yet another embodiment of the present invention. [Figure 7] This is a schematic plan view showing a display device according to yet another embodiment of the present invention. [Figure 8] This is a cross-sectional view taken along the line VII-VII in Figure 7. [Figure 9] This is a schematic cross-sectional view showing a display device according to yet another embodiment of the present invention. [Figure 10] This is a schematic plan view showing a display device according to yet another embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view illustrating the K region in Figure 10. [Figure 12] This figure shows an example of the structure shown in Figure 11. [Figure 13] This figure shows one modified form of Figure 11. [Figure 14] This is a schematic plan view showing a display device according to yet another embodiment of the present invention. [Figure 15] This is a schematic cross-sectional view illustrating the K region in Figure 14. [Figure 16] This figure shows an example of the structure shown in Figure 15. [Figure 17] This is a circuit diagram of a single pixel in a display device according to one embodiment of the present invention. [Figure 18] Figure 17 shows the waveform diagram of the drive signal used to drive the pixels. [Modes for carrying out the invention]

[0044] The present invention can be modified in various ways and has various embodiments, with specific embodiments illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as methods for achieving them, will become clear by referring in detail to the embodiments described below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various forms.

[0045] In the following embodiments, terms such as "first," "second," etc., are not limited in meaning but are used to distinguish one component from another.

[0046] In the following embodiments, a singular expression includes plural expressions unless the context clearly indicates otherwise.

[0047] In the following embodiments, terms such as "includes" or "has" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0048] In the following embodiments, when we say that a part such as a film, region, or component is on or above another part, this includes not only cases where it is directly above the other part, but also cases where another film, region, component, etc. is interposed between them.

[0049] In the drawings, the size of the components may be exaggerated or reduced for illustrative purposes. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for illustrative purposes and the present invention is not necessarily limited to those shown.

[0050] In the following embodiments, the x, y, and z axes are not limited to the three axes on a Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x, y, and z axes may be orthogonal to each other, or they may point to different directions that are not orthogonal to each other.

[0051] If one embodiment can be embodied in other ways, a particular sequence of steps may be performed in a different order than that described. For example, two steps described consecutively may be performed substantially simultaneously, or in the reverse order of the description.

[0052] Embodiments of the present invention will be described in detail below with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components will be given the same reference numerals, and redundant descriptions thereof will be omitted.

[0053] Figure 1 is a schematic cross-sectional view showing a display device according to one embodiment of the present invention.

[0054] Referring to Figure 1, the display device 100 may include a substrate 101, a first thin-film transistor 110, and a second thin-film transistor 120.

[0055] The first thin-film transistor 110 and the second thin-film transistor 120 may be arranged to generate one or more signals for the display device 100, respectively. For example, the display device 100 includes one or more pixels, and the first thin-film transistor 110 and the second thin-film transistor 120 may be placed at each pixel and generate the same or different signals necessary for the pixel to operate.

[0056] As another example, the display device 100 may include a non-display area surrounding a display area containing one or more pixels. The display device 100 may include a drive circuit area in such a non-display area, and the drive circuit area has one or more drive circuits, which can generate and transmit one or more signals necessary for the operation of the pixels to the pixels. The first thin-film transistor 110 and the second thin-film transistor 120 may each be located in the drive circuit area of ​​the non-display area, and may be located in the same drive circuit or in different drive circuit areas.

[0057] The first thin-film transistor 110 includes an active layer 113 containing at least an oxide, and the second thin-film transistor 120 includes an active layer 123 containing at least an oxide. The distance between the substrate 101 and the first thin-film transistor 110 can be smaller than the distance between the substrate 101 and the second thin-film transistor 120. Also, with reference to the thickness direction of the substrate 101 (for example, the Z-axis direction in Figure 1), the first thin-film transistor 110 can be positioned between the substrate 101 and the second thin-film transistor 120.

[0058] The display device 100 will be described in more detail below.

[0059] The substrate 101 can be made of various materials. Specifically, the substrate 101 can be formed from materials such as glass, metal, or organic matter.

[0060] In an optional embodiment, the substrate 101 can be formed from a flexible material. For example, the substrate 101 can be formed to be flexible, foldable, or rollable.

[0061] As an optional embodiment, the substrate 101 may consist of ultrathin glass, metal, or plastic. For example, when using plastic, the substrate 101 may contain polyimide (PI), and as other specific examples, the substrate 101 may contain at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polycarbonate, triacetate cellulose, or cellulose acetate propionate.

[0062] Furthermore, the substrate 101 may have one or more layers, for example, a multi-layer structure. For example, the substrate 101 may include an organic layer (e.g., a resin-based material) and an inorganic layer, and as a specific example, it may include a structure in which an inorganic layer is placed between two organic layers.

[0063] In an optional embodiment, one or more buffer layers 102 may be placed between the substrate 101 and the first thin-film transistor 110.

[0064] The buffer layer 102 may be placed on the substrate 101. The buffer layer 102 can reduce or prevent the diffusion of impurities into the first thin-film transistor 110.

[0065] The buffer layer 102 can contain various materials, for example, inorganic materials. Specifically, it can contain silicon-based materials. In an optional embodiment, the buffer layer 102 may contain at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy).

[0066] As another example, the buffer layer 102 may contain an oxide, specifically, at least one of the metal oxides such as aluminum oxide (AlOx).

[0067] Furthermore, as an optional embodiment, the buffer layer 102 may include at least two or more layers.

[0068] The first thin-film transistor 110 may include a first active layer 113 and a first gate electrode 115.

[0069] Furthermore, the first thin-film transistor 110 may include a first connecting electrode 116 and a second connecting electrode 117.

[0070] The first active layer 113 can be placed on the buffer layer 102.

[0071] In one embodiment, the first active layer 113 may include an oxide semiconductor. For example, the first active layer 113 may include zinc oxide (ZnOx), gallium oxide (GaOx), titanium oxide (TiOx), indium oxide (InOx), indium-gallium oxide (IGO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-magnesium oxide (ZMO), zinc-zirconium oxide (ZnZrxOy), indium-gallium-zinc oxide (IGZO), or indium-gallium-hafnium oxide (IGHO), and these oxides may be included individually or in combination with each other.

[0072] As another example, the first active layer 113 may include indium-tin-gallium-zinc oxide (ITGZO).

[0073] In one embodiment, the first active layer 113 may include a first connection region 113a, a second connection region 113b, and a first channel region 113c located between them.

[0074] The first gate electrode 115 can be positioned so as to overlap the first active layer 113, for example, it can be positioned above the first active layer 113 with respect to the thickness direction of the substrate 101.

[0075] The first gate insulating film 114 can be positioned to insulate the first active layer 113 from the first gate electrode 115.

[0076] As a specific example, the first gate insulating film 114 can be placed on the first active layer 113. Alternatively, the first gate insulating film 114 can be superimposed on the first active layer 113. Furthermore, as another example, the first gate insulating film 114 can be placed in contact with the first active layer 113.

[0077] In an optional embodiment, the first gate insulating film 114 may overlap the first channel region 113c of the first active layer 113 and be spaced apart from the first connection region 113a and the second connection region 113b of the first active layer 113. This allows the first interlayer insulating layer ILD1 to be in direct contact with the first connection region 113a and the second connection region 113b. Through such a structure, hydrogen diffuses from the first interlayer insulating layer ILD1 adjacent to the first connection region 113a and the second connection region 113b, which can increase the conductivity of the first connection region 113a and the second connection region 113b, for example, by making them conductive.

[0078] In one embodiment, the first gate insulating film 114 may include an insulating material. For example, the first gate insulating film 114 may be silicon oxide, silicon nitride, silicon oxynitride, etc., and these can be used alone or in combination with each other.

[0079] The first gate electrode 115 can be placed on the first gate insulating film 114. The first gate electrode 115 can be placed so as to overlap with the first active layer 113, or for example, so as to be in contact with the first gate insulating film 114.

[0080] The first gate electrode 115 may contain a conductive material and may be formed from, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0081] As a specific example, the first gate electrode 115 may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), silver (Ag), tungsten (W), tungsten nitride (WN), nickel (Ni), chromium (Cr), chromium nitride (CrN), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), and indium zinc oxide (IZO), and may also contain alloys of the aforementioned conductive materials. Furthermore, the first gate electrode 115 may be a single layer or a multilayer (multilayer film) containing the aforementioned materials.

[0082] The first interlayer insulating layer ILD1 can be positioned to insulate the first gate electrode 115 from the first connecting electrode 116 and the second connecting electrode 117. For example, the first interlayer insulating layer ILD1 can be formed above the first gate electrode 115 and the first active layer 113, covering the first gate electrode 115 and the first active layer 113.

[0083] Furthermore, the first interlayer insulating layer ILD1 can be placed on the buffer layer 102. The first interlayer insulating layer ILD1 may contain insulating material.

[0084] For example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, and the like. In one embodiment, a plurality of contact holes may be partitioned (defined) in the first interlayer insulating layer ILD1.

[0085] The first connecting electrode 116 and the second connecting electrode 117 can be placed on the first interlayer insulating layer ILD1.

[0086] The first connecting electrode 116 and the second connecting electrode 117 can each contact the first active layer 113 through contact holes in the first interlayer insulating layer ILD1. For example, the first connecting electrode 116 can contact the first connection region 113a of the first active layer 113, and the second connecting electrode 117 can contact the second connection region 113b of the first active layer 113.

[0087] Based on the signal applied to the first gate electrode 115, the first connecting electrode 116 and the second connecting electrode 117 can be electrically connected.

[0088] The first connecting electrode 116 and the second connecting electrode 117 can contain one or more of various conductive materials, for example, metals, alloys, conductive metal oxides, transparent conductive materials, etc. Specifically, the first connecting electrode 116 and the second connecting electrode 117 can contain silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0089] The second thin-film transistor 120 can be positioned above the first thin-film transistor 110. For example, the second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 120 can be formed on the second interlayer insulating layer ILD2.

[0090] As a specific example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 110.

[0091] The second interlayer insulating layer (ILD2) can be formed from various insulating materials, including, for example, inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. Furthermore, the second interlayer insulating layer (ILD2) can contain organic materials such as polyacrylic resins, polyimide resins, and acrylic resins.

[0092] In an optional embodiment, an intermediate insulating layer (not shown) may be further arranged between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0093] The second thin-film transistor 120 may include a second active layer 123 and a second gate electrode 125.

[0094] Furthermore, the second thin-film transistor 120 may include a third connecting electrode 126 and a fourth connecting electrode 127.

[0095] The second active layer 123 can be placed on the second interlayer insulating layer ILD2.

[0096] In one embodiment, the second active layer 123 may include an oxide semiconductor. For example, the second active layer 123 may include zinc oxide (ZnOx), gallium oxide (GaOx), titanium oxide (TiOx), indium oxide (InOx), indium-gallium oxide (IGO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-magnesium oxide (ZMO), zinc-zirconium oxide (ZnZrxOy), indium-gallium-zinc oxide (IGZO), or indium-gallium-hafnium oxide (IGHO), and these oxides may be included individually or in combination with each other.

[0097] As another example, the second active layer 123 may include indium-tin-gallium-zinc oxide (ITGZO).

[0098] In one embodiment, the second active layer 123 may include a first connection region 123a, a second connection region 123b, and a second channel region 123c located between them.

[0099] The second active layer 123 may contain the same oxide-based material as the first active layer 113, and for example, it may be formed from the same material.

[0100] The second active layer 123 can superimpose (overlap) at least a portion of the first active layer 113; for example, the second active layer 123 may superimpose on the first active layer 113 as a whole.

[0101] By arranging the second active layer 123 so that at least a portion of it overlaps with the first active layer 113, the integration density of the display device 100 can be improved and the specific surface area can be easily reduced.

[0102] The second gate electrode 125 can be positioned so as to overlap the second active layer 123, for example, it can be positioned above the second active layer 123 with respect to the thickness direction of the substrate 101.

[0103] The second gate insulating film 124 can be positioned to insulate the second active layer 123 from the second gate electrode 125.

[0104] As a specific example, the second gate insulating film 124 may be placed on the second active layer 123. Alternatively, the second gate insulating film 124 may be superimposed on the second active layer 123. Furthermore, as another example, the second gate insulating film 124 may be positioned in contact with the second active layer 123.

[0105] In an optional embodiment, the second gate insulating film 124 may overlap the second channel region 123c of the second active layer 123 and be separated from the first connection region 123a and the second connection region 123b of the second active layer 123. This allows the third interlayer insulating layer ILD3 to be in direct contact with the first connection region 123a and the second connection region 123b. Through such a structure, hydrogen diffuses from the third interlayer insulating layer ILD3 adjacent to the first connection region 123a and the second connection region 123b, which can increase the conductivity of the first connection region 123a and the second connection region 123b, potentially making them conductive.

[0106] In one embodiment, the second gate insulating film 124 may include an insulating material. For example, the second gate insulating film 124 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and these can be used alone or in combination with each other.

[0107] The second gate electrode 125 can be placed on the second gate insulating film 124. The second gate electrode 125 can be placed so as to overlap with the second active layer 123, or for example, so as to be in contact with the second gate insulating film 124.

[0108] The second gate electrode 125 may contain a conductive material and may be formed from, for example, a metal, an alloy, a conductive metal oxide, or a transparent conductive material.

[0109] As a specific example, the second gate electrode 125 may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), silver (Ag), tungsten (W), tungsten nitride (WN), nickel (Ni), chromium (Cr), chromium nitride (CrN), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), and indium zinc oxide (IZO), and may also contain alloys of the aforementioned conductive materials. Furthermore, the second gate electrode 125 may contain a single layer or multiple layers of the aforementioned materials.

[0110] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 125 from the third connecting electrode 126 and the fourth connecting electrode 127. For example, the third interlayer insulating layer ILD3 may be formed to cover the second gate electrode 125 and the second active layer 123 above them.

[0111] Furthermore, the third interlayer insulating layer ILD3 can be placed on top of the second interlayer insulating layer ILD2.

[0112] The third interlayer insulating layer ILD3 may contain an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. In one embodiment, a plurality of contact holes may be partitioned (defined) in the third interlayer insulating layer ILD3.

[0113] The third connecting electrode 126 and the fourth connecting electrode 127 can be placed on the third interlayer insulating layer ILD3.

[0114] The third connecting electrode 126 and the fourth connecting electrode 127 can each contact the second active layer 123 through contact holes in the third interlayer insulating layer ILD3. For example, the third connecting electrode 126 can contact the first connection region 123a of the second active layer 123, and the fourth connecting electrode 127 can contact the second connection region 123b of the second active layer 123.

[0115] Based on the signal applied to the second gate electrode 125, the third connecting electrode 126 and the fourth connecting electrode 127 can be electrically connected.

[0116] The third connecting electrode 126 and the fourth connecting electrode 127 can contain one or more of various conductive materials, for example, metals, alloys, conductive metal oxides, transparent conductive materials, etc. Specifically, the third connecting electrode 126 and the fourth connecting electrode 127 can contain silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0117] The first thin-film transistor 110 and the second thin-film transistor 120 can be arranged so that they have overlapping regions with respect to the thickness direction of the substrate 101 (for example, the Z-axis direction in Figure 1). For example, at least the first active layer 113 of the first thin-film transistor 110 may overlap with the second active layer 123 of the second thin-film transistor 120, and in other specific examples, the first gate electrode 115 may overlap with the second gate electrode 125.

[0118] In this embodiment, the display device 100 has a first thin-film transistor 110 arranged on a substrate 101, and a second thin-film transistor 120 may be arranged on top of the first thin-film transistor 110. Furthermore, a second active layer 123 containing the oxide of the second thin-film transistor 120 can be arranged on top of the first active layer 113 containing the oxide of the first thin-film transistor 110.

[0119] Through this structure, when forming the first thin-film transistor 110, which is positioned lower relative to the thickness direction of the substrate 101, the first active layer 113 is formed without a high-energy process (e.g., laser crystallization). Similarly, when forming the second thin-film transistor 120, which is positioned higher, the second active layer 123 is formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 110 located below it. Furthermore, it reduces or prevents unevenness in the first active layer 113 and the second active layer 123 that may occur when performing such a high-energy process (e.g., laser crystallization).

[0120] Furthermore, through this process, a structure in which the second thin-film transistor 120 is positioned above the first thin-film transistor 110, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 100 can be easily realized.

[0121] Figure 2 is a schematic cross-sectional view showing a display device according to another embodiment of the present invention.

[0122] Referring to Figure 2, the display device 200 may include a substrate 201, a first thin-film transistor 210, and a second thin-film transistor 220.

[0123] For the sake of explanation, this explanation will focus on the differences from the previously described embodiment.

[0124] The first thin-film transistor 210 includes an active layer 213 containing at least an oxide, and the second thin-film transistor 220 includes an active layer 223 containing at least an oxide. The distance between the substrate 201 and the first thin-film transistor 210 can be smaller than the distance between the substrate 201 and the second thin-film transistor 220. Also, with respect to the thickness direction of the substrate 201 (for example, the Z-axis direction in Figure 2), the first thin-film transistor 210 can be positioned between the substrate 201 and the second thin-film transistor 220.

[0125] The display device 200 will be described in more detail below.

[0126] The substrate 201 can contain various materials, and since other details, including the material of the substrate 201, are substantially the same as those of the substrate 101 in the embodiments described above, a detailed explanation will be omitted.

[0127] As an optional embodiment, one or more buffer layers 202 can be placed between the substrate 201 and the first thin-film transistor 210. Since the details of the buffer layers 202 are substantially the same as those of the buffer layer 102 in the embodiments described above, a detailed explanation will be omitted.

[0128] The first thin-film transistor 210 may include a first active layer 213 and a first gate electrode 215.

[0129] Furthermore, the first thin-film transistor 210 may include a first connecting electrode 216 and a second connecting electrode 217.

[0130] The first active layer 213 can be placed on the buffer layer 202. In one embodiment, the first active layer 213 may include an oxide semiconductor. The other details, including the material of the first active layer 213, are substantially the same as those of the first active layer 113 in the embodiments described above, and therefore a detailed explanation is omitted.

[0131] The first gate electrode 215 can be positioned so as to overlap the first active layer 213, for example, above the first active layer 213 with respect to the thickness direction of the substrate 201.

[0132] The first gate insulating film 214 can be positioned to insulate the first active layer 213 from the first gate electrode 215.

[0133] Since the details of the first gate insulating film 214 are substantially the same as those of the first gate insulating film 114 in the embodiment described above, a detailed explanation will be omitted.

[0134] The first gate electrode 215 can be placed on the first gate insulating film 214. The first gate electrode 215 can be placed so as to overlap with the first active layer 213, or for example, so as to be in contact with the first gate insulating film 214.

[0135] Since the details of the first gate electrode 215 are substantially the same as those of the first gate electrode 115 in the embodiment described above, a detailed explanation will be omitted.

[0136] The first interlayer insulating layer ILD1 can be arranged to insulate the first gate electrode 215 from the first connecting electrode 216 and the second connecting electrode 217. The details of the first interlayer insulating layer ILD1 are substantially the same as those of the first interlayer insulating layer ILD1 in the embodiments described above, so a detailed explanation will be omitted.

[0137] The first connecting electrode 216 and the second connecting electrode 217 can be placed on the first interlayer insulating layer ILD1. The details of the first connecting electrode 216 and the second connecting electrode 217 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the embodiment described above, so a detailed explanation is omitted.

[0138] The second thin-film transistor 220 can be positioned above the first thin-film transistor 210. For example, the second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 220 can be formed on the second interlayer insulating layer ILD2.

[0139] As a specific example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 210. The details of the second interlayer insulating layer ILD2 are substantially the same as those described in the embodiments above, so a detailed explanation will be omitted.

[0140] The second thin-film transistor 220 may include a second active layer 223 and a second gate electrode 225.

[0141] Furthermore, the second thin-film transistor 220 may include a third connecting electrode 226 and a fourth connecting electrode 227.

[0142] The second active layer 223 can be placed on the second interlayer insulating layer ILD2.

[0143] In one embodiment, the second active layer 223 may include an oxide semiconductor.

[0144] Other details, including the material of the second active layer 223, are substantially the same as those of the second active layer 123 in the embodiments described above, so a detailed explanation is omitted.

[0145] The second active layer 223 may contain the same oxide-based material as the first active layer 213, and may even be formed from the same material as an example.

[0146] The second active layer 223 may overlap with the first active layer 213 in at least part of its area. For example, the overlapping region ORA, which is one region of the second active layer 223, may overlap with the first active layer 213. Furthermore, the overlapping region ORA, which is one region of the second active layer 223, and its adjacent non-overlapping region NRA1 may not overlap with the first active layer 213. Also, the non-overlapping region NRA2, which is one region of the first active layer 213, may not overlap with the second active layer 223.

[0147] By arranging the second active layer 223 to overlap at least partially with the first active layer 213, the integration density of the display device 200 can be improved, and a reduction in specific surface area can be easily achieved.

[0148] Furthermore, by partially overlapping the second active layer 223 with the first active layer 213 and partially not overlapping it, the regions where mutual interference is reduced and the regions where it is not can be controlled, and when designing the upper and lower stacked circuit regions with respect to the thickness direction of the substrate 201, it is possible to precisely realize a design that reduces mutual signal interference.

[0149] The second gate electrode 225 can be positioned so as to overlap the second active layer 223, for example, it can be positioned above the second active layer 223 with respect to the thickness direction of the substrate 201.

[0150] The second gate insulating film 224 can be positioned to insulate the second active layer 223 from the second gate electrode 225.

[0151] Since the details of the second gate insulating film 224 are substantially the same as those of the second gate insulating film 124 in the embodiment described above, a detailed explanation will be omitted.

[0152] The second gate electrode 225 can be placed on the second gate insulating film 224. The second gate electrode 225 can be placed so as to overlap with the second active layer 223, or for example, so as to be in contact with the second gate insulating film 224.

[0153] Since the details of the second gate electrode 225 are substantially the same as those of the second gate electrode 125 in the embodiment described above, a detailed explanation will be omitted.

[0154] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 225 from the third connecting electrode 226 and the fourth connecting electrode 227. For example, the third interlayer insulating layer ILD3 can be formed to cover the second gate electrode 225 and the second active layer 223 above them. The details of the third interlayer insulating layer ILD3 are substantially the same as those of the third interlayer insulating layer ILD3 in the embodiments described above, so a detailed explanation will be omitted.

[0155] The third connecting electrode 226 and the fourth connecting electrode 227 can be placed on the third interlayer insulating layer ILD3. The details of the third connecting electrode 226 and the fourth connecting electrode 227 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the embodiment described above, so a detailed explanation is omitted.

[0156] The first thin-film transistor 210 and the second thin-film transistor 220 may be arranged such that one region has an overlapping region with respect to the thickness direction of the substrate 201 (for example, the Z-axis direction in Figure 2), and the other adjacent region has a non-overlapping region. For example, at least the first active layer 213 of the first thin-film transistor 210 may overlap with the second active layer 223 of the second thin-film transistor 220 in one region and not overlap in the other region.

[0157] In this embodiment, the display device 200 has a first thin-film transistor 210 arranged on a substrate 201, and a second thin-film transistor 220 may be arranged above the first thin-film transistor 210. Furthermore, a second active layer 223 containing the oxide of the second thin-film transistor 220 can be arranged on top of the first active layer 213 containing the oxide of the first thin-film transistor 210.

[0158] Through this structure, when forming the first thin-film transistor 210, which is located at a lower position relative to the thickness direction of the substrate 201, the first active layer 213 is formed without a high-energy process (e.g., laser crystallization). Similarly, when forming the second thin-film transistor 220, which is located at a higher position, the second active layer 223 is formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 210 located below it. Furthermore, when performing such a high-energy process (e.g., laser crystallization), the occurrence of unevenness in the first active layer 213 and the second active layer 223 can be reduced or prevented.

[0159] Furthermore, through this process, a structure in which the second thin-film transistor 220 is positioned above the first thin-film transistor 210, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 200 can be easily realized.

[0160] Furthermore, by partially overlapping the second active layer 223 with the first active layer 213 and partially not overlapping it, the regions where mutual interference is reduced and the regions where it is not can be controlled, and when designing the upper and lower stacked circuit regions with respect to the thickness direction of the substrate 201, it is possible to precisely realize a design that reduces mutual signal interference.

[0161] Figure 3 is a schematic cross-sectional view showing a display device according to a further embodiment of the present invention.

[0162] Referring to Figure 3, the display device 300 may include a substrate 301, a first thin-film transistor 310, and a second thin-film transistor 320.

[0163] For the sake of explanation, this explanation will focus on the differences from the previously described embodiment.

[0164] The first thin-film transistor 310 includes a first active layer 313 containing at least an oxide, and the second thin-film transistor 320 includes a second active layer 323 containing at least an oxide. The distance between the substrate 301 and the first thin-film transistor 310 can be smaller than the distance between the substrate 301 and the second thin-film transistor 320. Also, with respect to the thickness direction of the substrate 301 (for example, the Z-axis direction in Figure 3), the first thin-film transistor 310 can be positioned between the substrate 301 and the second thin-film transistor 320.

[0165] The display device 300 will be described in more detail below.

[0166] The substrate 301 can contain various materials, and since the other details, including the material of the substrate 301, are substantially the same as those of the substrate 101 in the embodiments described above, a detailed explanation will be omitted.

[0167] As an optional embodiment, one or more buffer layers 302 may be placed between the substrate 301 and the first thin-film transistor 310. Since the details of the buffer layer 302 are substantially the same as those of the buffer layer 102 in the embodiments described above, a detailed explanation will be omitted.

[0168] The first thin-film transistor 310 may include a first active layer 313 and a first gate electrode 315.

[0169] Furthermore, the first thin-film transistor 310 may include a first connecting electrode 316 and a second connecting electrode 317.

[0170] The first active layer 313 can be placed on the buffer layer 302. In one embodiment, the first active layer 313 may include an oxide semiconductor. The other details, including the material of the first active layer 313, are substantially the same as those of the first active layer 113 in the embodiments described above, so a detailed explanation is omitted.

[0171] The first gate electrode 315 can be positioned so as to overlap the first active layer 313, for example, above the first active layer 313 with respect to the thickness direction of the substrate 301.

[0172] The first gate insulating film 314 can be positioned to insulate the first active layer 313 from the first gate electrode 315.

[0173] Since the details of the first gate insulating film 314 are substantially the same as those of the first gate insulating film 114 in the embodiment described above, a detailed explanation will be omitted.

[0174] The first gate electrode 315 can be placed on the first gate insulating film 314. The first gate electrode 315 can be placed so as to overlap with the first active layer 313, or for example, so as to be in contact with the first gate insulating film 314.

[0175] Since the details of the first gate electrode 315 are substantially the same as those of the first gate electrode 115 in the embodiment described above, a detailed explanation will be omitted.

[0176] The first interlayer insulating layer ILD1 can be positioned to insulate the first gate electrode 315 from the first connecting electrode 316 and the second connecting electrode 317. The details of the first interlayer insulating layer ILD1 are substantially the same as those of the first interlayer insulating layer ILD1 in the embodiments described above, so a detailed explanation will be omitted.

[0177] The first connecting electrode 316 and the second connecting electrode 317 can be placed on the first interlayer insulating layer ILD1. The details of the first connecting electrode 316 and the second connecting electrode 317 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the embodiment described above, so a detailed explanation is omitted.

[0178] The second thin-film transistor 320 can be positioned above the first thin-film transistor 310. For example, the second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 320 can be formed on the second interlayer insulating layer ILD2.

[0179] As a specific example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 310. The details of the second interlayer insulating layer ILD2 are substantially the same as those described in the embodiments above, so a detailed explanation will be omitted.

[0180] The second thin-film transistor 320 may include a second active layer 323 and a second gate electrode 325.

[0181] Furthermore, the second thin-film transistor 320 may include a third connecting electrode 326 and a fourth connecting electrode 327.

[0182] The second active layer 323 can be placed on the second interlayer insulating layer ILD2.

[0183] In one embodiment, the second active layer 323 may include an oxide semiconductor.

[0184] Other details, including the material of the second active layer 323, are substantially the same as those of the second active layer 123 in the embodiments described above, so a detailed explanation is omitted.

[0185] The second active layer 323 may contain the same oxide-based material as the first active layer 313, and may even be formed from the same material as the first active layer.

[0186] The second active layer 323 can be arranged so as not to overlap with the first active layer 313. For example, with respect to the thickness direction of the substrate 301 (the z-axis direction in Figure 3), the second active layer 323 can be arranged so as not to overlap with the first active layer 313.

[0187] As a specific example, the extension lines of the side surface of the first active layer 313 and the extension lines of the side surface of the second active layer 323 can be arranged to have a separation interval LO.

[0188] Alternatively, the first active layer 313 and the second active layer 323 can be arranged so as to be spaced apart with respect to the thickness direction of the substrate 301. This makes it easy to implement a stacked structure of the first thin-film transistor 310 and the second thin-film transistor 320 with respect to the thickness direction of the substrate 301, while reducing interference between the signals of the first thin-film transistor 310 and the second thin-film transistor 320.

[0189] The second gate electrode 325 can be positioned so as to overlap the second active layer 323, for example, it can be positioned on top of the second active layer 323 with respect to the thickness direction of the substrate 301.

[0190] The second gate insulating film 324 can be positioned to insulate the second active layer 323 from the second gate electrode 325.

[0191] Since the details of the second gate insulating film 324 are substantially the same as those of the second gate insulating film 124 in the embodiment described above, a detailed explanation will be omitted.

[0192] The second gate electrode 325 can be placed on the second gate insulating film 324. The second gate electrode 325 can be placed so as to overlap with the second active layer 323, or for example, so as to be in contact with the second gate insulating film 324.

[0193] Since the details of the second gate electrode 325 are substantially the same as those of the second gate electrode 125 in the embodiment described above, a detailed explanation will be omitted.

[0194] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 325 from the third connecting electrode 326 and the fourth connecting electrode 327. For example, the third interlayer insulating layer ILD3 can be formed to cover the second gate electrode 325 and the second active layer 323 above them. The details of the third interlayer insulating layer ILD3 are substantially the same as those of the third interlayer insulating layer ILD3 in the embodiments described above, so a detailed explanation will be omitted.

[0195] The third connecting electrode 326 and the fourth connecting electrode 327 can be placed on the third interlayer insulating layer ILD3. The details of the third connecting electrode 326 and the fourth connecting electrode 327 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the embodiment described above, so a detailed explanation is omitted.

[0196] The first thin-film transistor 310 and the second thin-film transistor 320 can be formed to have a stacked relationship with respect to the thickness direction of the substrate 301 (for example, the Z-axis direction in Figure 3). Furthermore, the second active layer 323 can be arranged so as not to overlap with the first active layer 313. For example, with respect to the thickness direction of the substrate 301 (the z-axis direction in Figure 3), the second active layer 323 may not overlap with the first active layer 313.

[0197] In this embodiment, the display device 300 has a first thin-film transistor 310 arranged on a substrate 301, and a second thin-film transistor 320 may be arranged above the first thin-film transistor 310. Furthermore, a second active layer 323 containing the oxide of the second thin-film transistor 320 can be arranged above the first active layer 313 containing the oxide of the first thin-film transistor 310.

[0198] Through this structure, when forming the first thin-film transistor 310, which is located at a lower position relative to the thickness direction of the substrate 301, the first active layer 313 is formed without a high-energy process (e.g., laser crystallization). Similarly, when forming the second thin-film transistor 320, which is located at a higher position, the second active layer 323 is formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 310 located below it. Furthermore, it reduces or prevents unevenness in the first active layer 313 and the second active layer 323 that may occur when performing such a high-energy process (e.g., laser crystallization).

[0199] Furthermore, through this process, a structure in which the second thin-film transistor 320 is positioned above the first thin-film transistor 310, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 300 can be easily realized.

[0200] Furthermore, by arranging the first active layer 313 and the second active layer 323 so as to be separated from each other with respect to the thickness direction of the substrate 301, interference between the mutual signals of the first thin-film transistor 310 and the second thin-film transistor 320 can be reduced, and a stacked structure of the first thin-film transistor 310 and the second thin-film transistor 320 can be easily realized with respect to the thickness direction of the substrate 301.

[0201] Figure 4 is a schematic cross-sectional view showing a display device according to another embodiment of the present invention.

[0202] Referring to Figure 4, the display device 400 may include a substrate 401, a first thin-film transistor 410, and a second thin-film transistor 420.

[0203] Furthermore, the first conductive pattern section BML1 or the second conductive pattern section BML2 may be further included. Figure 4 shows the first conductive pattern section BML1 and the second conductive pattern section BML2, but this is an optional embodiment, and the display device 400 may include only one of these.

[0204] For the sake of explanation, this explanation will focus on the differences from the previously described embodiment.

[0205] Referring to Figure 4, the display device 400 may include a substrate 401, a first thin-film transistor 410, and a second thin-film transistor 420.

[0206] The first thin-film transistor 410 includes a first active layer 413 containing at least an oxide, and the second thin-film transistor 420 includes a second active layer 423 containing at least an oxide. The distance between the substrate 401 and the first thin-film transistor 410 can be smaller than the distance between the substrate 401 and the second thin-film transistor 420. Also, with reference to the thickness direction of the substrate 401 (for example, the Z-axis direction in Figure 4), the first thin-film transistor 410 can be positioned between the substrate 401 and the second thin-film transistor 420.

[0207] The display device 400 will be described in more detail below.

[0208] The substrate 401 can contain various materials, and since other details, including the material of the substrate 401, are substantially the same as those of the substrate 101 in the embodiments described above, a detailed explanation will be omitted.

[0209] As an optional embodiment, one or more buffer layers 402 may be placed between the substrate 401 and the first thin-film transistor 410. Since the details of the buffer layer 402 are substantially the same as those of the buffer layer 102 in the embodiment described above, a detailed explanation will be omitted.

[0210] The first thin-film transistor 410 may include a first active layer 413 and a first gate electrode 415.

[0211] Furthermore, the first thin-film transistor 410 may include a first connecting electrode 416 and a second connecting electrode 417.

[0212] Furthermore, the first conductive pattern portion BML1 can be placed between the first active layer 413 and the substrate 401.

[0213] As an example, the first conductive pattern portion BML1 has a region that overlaps with the first active layer 413 and can be placed between the substrate 401 and the buffer layer 402.

[0214] The first conductive pattern portion BML1 can be used as a light-shielding member to reduce or block light that may flow into the substrate 401 and protect the first active layer 413 or the first thin-film transistor 410. For this purpose, the first conductive pattern portion BML1 may contain light-shielding and / or light-absorbing materials. As an example, the first conductive pattern portion BML1 may also contain an opaque metal layer.

[0215] In an optional embodiment, the first conductive pattern portion BML1 can also be electrically connected to a first connecting electrode 416 or a second connecting electrode 417 via contact holes that sequentially penetrate the first interlayer insulating layer ILD1 and the buffer layer 402. This expands the driving range of a predetermined voltage supplied to the first gate electrode 415 of the first thin-film transistor 410, and, as another example, stabilizes the channel region of the first active layer 413.

[0216] As an optional embodiment, the first conductive pattern BML1 may contain various metals and may form a single layer of suitable (or selected) material from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and their alloys, or it may be formed as a double or multilayer laminate of three or more layers of low-resistance material molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance.

[0217] The first active layer 413 can be placed on the buffer layer 402. In one embodiment, the first active layer 413 may include an oxide semiconductor. The other details, including the material of the first active layer 413, are substantially the same as those of the first active layer 113 in the embodiments described above, and therefore a detailed explanation is omitted.

[0218] The first gate electrode 415 can be positioned so as to overlap the first active layer 413, for example, on top of the first active layer 413 with respect to the thickness direction of the substrate 401.

[0219] The first gate insulating film 414 can be positioned to insulate the first active layer 413 from the first gate electrode 415.

[0220] Since the details of the first gate insulating film 414 are substantially the same as those of the first gate insulating film 114 in the embodiment described above, a detailed explanation will be omitted.

[0221] The first gate electrode 415 can be placed on the first gate insulating film 414. The first gate electrode 415 can be placed so as to overlap with the first active layer 413, or for example, so as to be in contact with the first gate insulating film 414.

[0222] Since the details of the first gate electrode 415 are substantially the same as those of the first gate electrode 115 in the embodiment described above, a detailed explanation will be omitted.

[0223] The first interlayer insulating layer ILD1 can be positioned to insulate the first gate electrode 415 from the first connecting electrode 416 and the second connecting electrode 417. The details of the first interlayer insulating layer ILD1 are substantially the same as those of the first interlayer insulating layer ILD1 in the embodiments described above, so a detailed explanation will be omitted.

[0224] The first connecting electrode 416 and the second connecting electrode 417 can be placed on the first interlayer insulating layer ILD1. The details of the first connecting electrode 416 and the second connecting electrode 417 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the embodiment described above, so a detailed explanation is omitted.

[0225] The second thin-film transistor 420 can be placed on top of the first thin-film transistor 410. For example, the second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 420 can be formed on the second interlayer insulating layer ILD2.

[0226] As a specific example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 410. The details of the second interlayer insulating layer ILD2 are substantially the same as those described in the embodiments above, so a detailed explanation will be omitted.

[0227] The second thin-film transistor 420 may include a second active layer 423 and a second gate electrode 425.

[0228] Furthermore, the second thin-film transistor 420 may include a third connecting electrode 426 and a fourth connecting electrode 427.

[0229] Furthermore, the second conductive pattern portion BML2 can be placed between the second active layer 423 and the second interlayer insulating layer ILD2.

[0230] As an example, the second conductive pattern portion BML2 has a region that overlaps with the second active layer 423 and can be placed between the second active layer 423 and the second interlayer insulating layer ILD2.

[0231] The second conductive pattern portion BML2 can be used as a light-shielding member to reduce or block light that may flow into the substrate 401 and protect the second active layer 423 or the second thin-film transistor 420. For this purpose, the second conductive pattern portion BML2 may contain light-shielding and / or light-absorbing materials. As an example, the second conductive pattern portion BML2 may also contain an opaque metal layer.

[0232] In an optional embodiment, the second conductive pattern portion BML2 may also be electrically connected to a third connecting electrode 426 or a fourth connecting electrode 427 via contact holes that sequentially penetrate the third interlayer insulating layer ILD3 and the upper buffer layer 403. This expands the driving range of a predetermined voltage supplied to the second gate electrode 425 of the second thin-film transistor 420, and, as another example, stabilizes the channel region of the second active layer 423.

[0233] As an optional embodiment, the second conductive pattern portion BML2 may contain various metals and may form a single layer consisting of a suitable (or selected) single or mixed material from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and their alloys, or it may be formed as a multilayer structure of two or more layers of low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance.

[0234] One or more upper buffer layers 403 can be placed between the second conductive pattern portion BML2 and the second active layer 423, and the upper buffer layers 403 can contain one or more of the materials included in the buffer layer 402, for example, they can be formed from the same material as the buffer layer 402.

[0235] The second active layer 423 can be placed on the second interlayer insulating layer ILD2.

[0236] In one embodiment, the second active layer 423 may include an oxide semiconductor.

[0237] Other details, including the material of the second active layer 423, are substantially the same as those of the second active layer 123 in the embodiments described above, so a detailed explanation will be omitted.

[0238] The second active layer 423 may contain the same oxide-based material as the first active layer 413, and may even be formed from the same material as the first active layer 413.

[0239] The second active layer 423 can be superimposed on the first active layer 413 in at least part, and in other optional embodiments, it may be non-superimposed as shown in Figure 3.

[0240] The second gate electrode 425 can be positioned so as to overlap the second active layer 423, for example, it can be positioned on top of the second active layer 423 with respect to the thickness direction of the substrate 401.

[0241] The second gate insulating film 424 can be positioned to insulate the second active layer 423 from the second gate electrode 425.

[0242] Since the details of the second gate insulating film 424 are substantially the same as those of the second gate insulating film 124 in the embodiment described above, a detailed explanation will be omitted.

[0243] The second gate electrode 425 can be placed on the second gate insulating film 424. The second gate electrode 425 can be placed so as to overlap with the second active layer 423, or for example, so as to be in contact with the second gate insulating film 424.

[0244] Since the details of the second gate electrode 425 are substantially the same as those of the second gate electrode 125 in the embodiment described above, a detailed explanation will be omitted.

[0245] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 425 from the third connecting electrode 426 and the fourth connecting electrode 427. For example, the third interlayer insulating layer ILD3 can be formed to cover the second gate electrode 425 and the second active layer 423 on top of them. The details of the third interlayer insulating layer ILD3 are substantially the same as those of the third interlayer insulating layer ILD3 in the embodiments described above, so a detailed explanation will be omitted.

[0246] The third connecting electrode 426 and the fourth connecting electrode 427 can be placed on the third interlayer insulating layer ILD3. The details of the third connecting electrode 426 and the fourth connecting electrode 427 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the embodiment described above, so a detailed explanation is omitted.

[0247] In this embodiment, the display device 400 has a first thin-film transistor 410 arranged on a substrate 401, and a second thin-film transistor 420 may be arranged above the first thin-film transistor 410. Furthermore, a second active layer 423 containing the oxide of the second thin-film transistor 420 may be arranged above a first active layer 413 containing the oxide of the first thin-film transistor 410.

[0248] Through this structure, when forming the first thin-film transistor 410, which is located at a lower position relative to the thickness direction of the substrate 401, the first active layer 413 can be formed without a high-energy process (e.g., laser crystallization), and when forming the second thin-film transistor 420, which is located at a higher position, the second active layer 423 can also be formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 410 located below it. Furthermore, it reduces or prevents unevenness in the first active layer 413 and the second active layer 423 that may occur when performing such a high-energy process (e.g., laser crystallization).

[0249] Furthermore, through this process, a structure in which the second thin-film transistor 420 is positioned above the first thin-film transistor 410, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 400 can be easily realized.

[0250] Furthermore, the display device 400 includes a first conductive pattern section BML1 or a second conductive pattern section BML2, which can reduce or prevent changes in the physical or electrical properties of the oxide-containing first active layer 413 or second active layer 423 due to light. Additionally, by arranging the first conductive pattern section BML1 or the second conductive pattern section BML2 to be electrically connected to the conductive layer of the first thin-film transistor 410 (e.g., one of the connecting electrodes) or the conductive layer of the second thin-film transistor 420 (e.g., one of the connecting electrodes), the electrical properties of the first thin-film transistor 410 or the second thin-film transistor 420 can be improved, thereby enhancing their precise control characteristics. This improves the precise driving characteristics of the display device 400 and easily enhances the possibility of realizing high resolution.

[0251] Figure 5 is a schematic cross-sectional view showing a display device according to another embodiment of the present invention.

[0252] Referring to Figure 5, the display device 500 may include a substrate 501, a first thin-film transistor 510, and a second thin-film transistor 520.

[0253] Furthermore, the display device 500 may further include an intermediate conductive layer BBM between the first thin-film transistor 510 and the second thin-film transistor 520.

[0254] For the sake of explanation, this explanation will focus on the differences from the previously described embodiment.

[0255] The first thin-film transistor 510 includes a first active layer 513 containing at least an oxide, and the second thin-film transistor 520 includes a second active layer 523 containing at least an oxide. The distance between the substrate 501 and the first thin-film transistor 510 can be smaller than the distance between the substrate 501 and the second thin-film transistor 520. Also, with reference to the thickness direction of the substrate 501 (for example, the Z-axis direction in Figure 5), the first thin-film transistor 510 can be positioned between the substrate 501 and the second thin-film transistor 520.

[0256] The display device 500 will be described in more detail below.

[0257] The substrate 501 can contain various materials, and since the other details, including the material of the substrate 501, are substantially the same as those of the substrate 101 in the embodiments described above, a detailed explanation will be omitted.

[0258] As an optional embodiment, one or more buffer layers 502 can be placed between the substrate 501 and the first thin-film transistor 510. Since the details of the buffer layers 502 are substantially the same as those of the buffer layer 102 in the embodiments described above, a detailed explanation will be omitted.

[0259] The first thin-film transistor 510 may include a first active layer 513 and a first gate electrode 515.

[0260] Furthermore, the first thin-film transistor 510 may include a first connecting electrode 516 and a second connecting electrode 517.

[0261] Furthermore, as an optional embodiment, the first conductive pattern portion BML1 can be placed between the first active layer 513 and the substrate 501. The details of the first conductive pattern portion BML1 are substantially the same as those of the first conductive pattern portion BML1 in the embodiments described above, so a detailed explanation will be omitted.

[0262] The first active layer 513 can be placed on the buffer layer 502. In one embodiment, the first active layer 513 may include an oxide semiconductor. The other details, including the material of the first active layer 513, are substantially the same as those of the first active layer 113 in the embodiments described above, and therefore a detailed explanation is omitted.

[0263] The first gate electrode 515 can be positioned so as to overlap the first active layer 513, for example, above the first active layer 513 with respect to the thickness direction of the substrate 501.

[0264] The first gate insulating film 514 can be positioned to insulate the first active layer 513 from the first gate electrode 515.

[0265] Since the details of the first gate insulating film 514 are substantially the same as those of the first gate insulating film 114 in the embodiment described above, a detailed explanation will be omitted.

[0266] The first gate electrode 515 can be placed on the first gate insulating film 514. The first gate electrode 515 can be placed so as to overlap with the first active layer 513, or for example, so as to be in contact with the first gate insulating film 514.

[0267] Since the details of the first gate electrode 515 are substantially the same as those of the first gate electrode 115 in the embodiment described above, a detailed explanation will be omitted.

[0268] The first interlayer insulating layer ILD1 can be positioned to insulate the first gate electrode 515 from the first connecting electrode 516 and the second connecting electrode 517. The details of the first interlayer insulating layer ILD1 are substantially the same as those of the first interlayer insulating layer ILD1 in the embodiments described above, so a detailed explanation will be omitted.

[0269] The first connecting electrode 516 and the second connecting electrode 517 can be placed on the first interlayer insulating layer ILD1. The details of the first connecting electrode 516 and the second connecting electrode 517 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the embodiment described above, so a detailed explanation is omitted.

[0270] The second thin-film transistor 520 can be positioned above the first thin-film transistor 510.

[0271] As an example, an intermediate conductive layer BBM can be placed between the first thin-film transistor 510 and the second thin-film transistor 520.

[0272] The intermediate conductive layer BBM contains a conductive material, which can include one of various metals.

[0273] The intermediate conductive layer BBM is placed between the first thin-film transistor 510 and the second thin-film transistor 520, and can reduce interference of electrical signals that may occur between the first thin-film transistor 510 and the second thin-film transistor 520.

[0274] The intermediate conductive layer BBM can be formed so as to overlap with at least one region of the first thin-film transistor 510 and the second thin-film transistor 520.

[0275] Furthermore, in an optional embodiment, the intermediate conductive layer BBM may be electrically connected to a conductive layer of the same layer as or above the intermediate conductive layer BBM. For example, it may be electrically connected via a contact hole to a conductive layer of the same layer as or above a part of the components of the second thin-film transistor 520.

[0276] Also, as another optional embodiment, the intermediate conductive layer BBM can be electrically connected to the same layer as the intermediate conductive layer BBM or a conductive layer below it. For example, it can be electrically connected via a contact hole to the same layer as one of the members of the first thin film transistor 510 or a conductive layer above it.

[0277] To smoothly implement the above structure, the intermediate conductive layer BBM can have a width corresponding to or larger than the width in one direction of the first thin film transistor 510 and the second thin film transistor 520. As an optional embodiment, the intermediate conductive layer BBM can be formed to overlap while corresponding to the width, at least in one direction of the first active layer 513 and the second active layer 523, and can also be formed to have a width extending larger than that.

[0278] The intermediate conductive layer BBM can be disposed between insulating layers. For example, the intermediate conductive layer BBM can be disposed between the lower layer ILD21 and the upper layer ILD22 of the second interlayer insulating layers ILD21 and ILD22.

[0279] The second thin film transistor 520 can include a second active layer 523 and a second gate electrode 525.

[0280] Furthermore, the second thin film transistor 520 can include a third connection electrode 526 and a fourth connection electrode 527.

[0281] Also, as an optional embodiment, the second conductive pattern portion BML2 can be disposed between the second active layer 523 and the second interlayer insulating layer ILD22. Since the detailed content of the second conductive pattern portion BML2 is substantially the same as that of the second conductive pattern portion BML2 in the foregoing embodiment, a specific description thereof is omitted.

[0282] As an optional embodiment, one or more upper buffer layers 503 can be disposed between the second conductive pattern portion BML2 and the second active layer 523.

[0283] The second active layer 523 can be disposed on the second interlayer insulating layer ILD22.

[0284] In one embodiment, the second active layer 523 can include an oxide semiconductor.

[0285] Since other details of the material of the second active layer 523 are substantially the same as those of the second active layer 123 in the foregoing embodiment, specific descriptions thereof are omitted.

[0286] The second active layer 523 can contain the same oxide-based material as the first active layer 513 and may, for example, be formed of the same material.

[0287] The second active layer 523 can at least partially overlap with the first active layer 513 and may, as another optional embodiment, be non-overlapping as shown in FIG. 3.

[0288] The second gate electrode 525 can be disposed so as to overlap with the second active layer 523. For example, the second gate electrode 525 can be disposed above the second active layer 523 with reference to the thickness direction of the substrate 501.

[0289] The second gate insulating film 524 can be disposed so as to insulate between the second active layer 523 and the second gate electrode 525.

[0290] Since details of the second gate insulating film 524 are substantially the same as those of the second gate insulating film 124 in the foregoing embodiment, specific descriptions thereof are omitted.

[0291] The second gate electrode 525 can be disposed on the second gate insulating film 524. The second gate electrode 525 can be disposed so as to overlap with the second active layer 523. For example, the second gate electrode 525 can be disposed so as to contact the second gate insulating film 524.

[0292] Since the details of the second gate electrode 525 are substantially the same as those of the second gate electrode 125 in the embodiment described above, a detailed explanation will be omitted.

[0293] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 525 from the third connecting electrode 526 and the fourth connecting electrode 527. For example, the third interlayer insulating layer ILD3 can be formed to cover the second gate electrode 525 and the second active layer 523 on top of them. The details of the third interlayer insulating layer ILD3 are substantially the same as those of the third interlayer insulating layer ILD3 in the embodiments described above, so a detailed explanation will be omitted.

[0294] The third connecting electrode 526 and the fourth connecting electrode 527 can be placed on the third interlayer insulating layer ILD3. The details of the third connecting electrode 526 and the fourth connecting electrode 527 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the embodiment described above, so a detailed explanation is omitted.

[0295] In this embodiment, the display device 500 has a first thin-film transistor 510 arranged on a substrate 501, and a second thin-film transistor 520 may be arranged above the first thin-film transistor 510. Furthermore, a second active layer 523 containing the oxide of the second thin-film transistor 520 can be arranged above the first active layer 513 containing the oxide of the first thin-film transistor 510.

[0296] Through this structure, when forming the first thin-film transistor 510, which is positioned lower relative to the thickness direction of the substrate 501, the first active layer 513 can be formed without a high-energy process (e.g., laser crystallization), and when forming the second thin-film transistor 520, which is positioned higher, the second active layer 523 can also be formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 510 below it. Furthermore, when performing such a high-energy process (e.g., laser crystallization), it is possible to reduce or prevent the occurrence of unevenness in the first active layer 513 and the second active layer 523.

[0297] Furthermore, through this process, a structure in which the second thin-film transistor 520 is placed on top of the first thin-film transistor 510, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 500 can be easily realized.

[0298] Furthermore, the display device 500 can have an intermediate conductive layer BBM placed between the first thin-film transistor 510 and the second thin-film transistor 520. This configuration can reduce or prevent interference between the electrical signals of the first thin-film transistor 510 and the second thin-film transistor 520.

[0299] Furthermore, by using the thickness direction of the substrate 501 as a reference, the conductive layers and the intermediate conductive layer BBM in different regions on the upper and lower sides can be electrically connected (for example, through one or more contact holes), thereby enabling the connection of various electrical signals.

[0300] Furthermore, by using the intermediate conductive layer BBM, it is possible to electrically connect conductive layers in different regions on the upper and lower sides of the substrate 501, based on the thickness direction, and to connect the parts of the upper and lower conductive layers that require electrical connection.

[0301] As a result, various electrical circuit configurations of the display device 500 can be easily implemented.

[0302] FIG. 6 is a cross-sectional view schematically showing a display device according to another embodiment of the present invention.

[0303] Referring to FIG. 6, the display device 600 can include a substrate 601, a first thin film transistor 610, and a second thin film transistor 620.

[0304] For convenience of explanation, the description will focus on the differences from the above-described embodiments.

[0305] The first active layer 613 of the first thin film transistor 610 and the second active layer 623 of the second thin film transistor 620 in the present embodiment can be formed to have at least one or more different characteristics.

[0306] This will be further specifically described below.

[0307] The first thin film transistor 610 includes a first active layer 613 containing at least an oxide, and the second thin film transistor 620 includes a second active layer 623 containing at least an oxide. The distance between the substrate 601 and the first thin film transistor 610 can have a value smaller than that between the substrate 601 and the second thin film transistor 620. Also, with respect to the thickness direction of the substrate 601 (for example, the Z-axis direction in FIG. 6), the first thin film transistor 610 can be disposed between the substrate 601 and the second thin film transistor 620.

[0308] Hereinafter, the display device 600 will be described more specifically. ]>

[0309] The substrate 601 can include various materials, and since other detailed contents including the material of the substrate 601 are substantially the same as those of the substrate 101 in the above-described embodiment, a specific description thereof will be omitted.

[0310] As an optional embodiment, one or more buffer layers 602 can be placed between the substrate 601 and the first thin-film transistor 610. Since the details of the buffer layers 602 are substantially the same as those of the buffer layer 102 in the embodiments described above, a detailed explanation will be omitted.

[0311] The first thin-film transistor 610 may include a first active layer 613 and a first gate electrode 615.

[0312] Furthermore, the first thin-film transistor 610 may include a first connecting electrode 616 and a second connecting electrode 617.

[0313] The first active layer 613 can be placed on the buffer layer 602.

[0314] In one embodiment, the first active layer 613 may include an oxide semiconductor. For example, the first active layer 613 may include zinc oxide (ZnOx), gallium oxide (GaOx), titanium oxide (TiOx), indium oxide (InOx), indium-gallium oxide (IGO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-magnesium oxide (ZMO), zinc-zirconium oxide (ZnZrxOy), indium-gallium-zinc oxide (IGZO), or indium-gallium-hafnium oxide (IGHO), and these oxides can be used individually or in combination with each other.

[0315] As an example, the first active layer 613 may contain indium-tin-gallium-zinc oxide (ITGZO).

[0316] The first gate electrode 615 can be positioned so as to overlap the first active layer 613, for example, it can be positioned above the first active layer 613 with respect to the thickness direction of the substrate 601.

[0317] The first gate insulating film 614 can be positioned to insulate the first active layer 613 from the first gate electrode 615.

[0318] Since the details of the first gate insulating film 614 are substantially the same as those of the first gate insulating film 114 in the embodiment described above, a detailed explanation will be omitted.

[0319] The first gate electrode 615 can be placed on the first gate insulating film 614. The first gate electrode 615 can be placed so as to overlap with the first active layer 613, or for example, so as to be in contact with the first gate insulating film 614.

[0320] Since the details of the first gate electrode 615 are substantially the same as those of the first gate electrode 115 in the embodiment described above, a detailed explanation will be omitted.

[0321] The first interlayer insulating layer ILD1 can be positioned to insulate the first gate electrode 615 from the first connecting electrode 616 and the second connecting electrode 617. The details of the first interlayer insulating layer ILD1 are substantially the same as those of the first interlayer insulating layer ILD1 in the embodiments described above, so a detailed explanation will be omitted.

[0322] The first connecting electrode 616 and the second connecting electrode 617 can be placed on the first interlayer insulating layer ILD1. The detailed contents of the first connecting electrode 616 and the second connecting electrode 617 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the embodiment described above, so a detailed explanation is omitted.

[0323] The second thin-film transistor 620 can be positioned above the first thin-film transistor 610. For example, the second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 620 can be formed on the second interlayer insulating layer ILD2.

[0324] As a specific example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 610. The details of the second interlayer insulating layer ILD2 are substantially the same as those described in the embodiments above, so a detailed explanation will be omitted.

[0325] The second thin-film transistor 620 may include a second active layer 623 and a second gate electrode 625.

[0326] Furthermore, the second thin-film transistor 620 may include a third connecting electrode 626 and a fourth connecting electrode 627.

[0327] The second active layer 623 can be placed on the second interlayer insulating layer ILD2.

[0328] In one embodiment, the second active layer 623 may include an oxide semiconductor.

[0329] For example, the second active layer 623 may contain zinc oxide (ZnOx), gallium oxide (GaOx), titanium oxide (TiOx), indium oxide (InOx), indium-gallium oxide (IGO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-magnesium oxide (ZMO), zinc-zirconium oxide (ZnZrxOy), indium-gallium-zinc oxide (IGZO), and indium-gallium-hafnium oxide (IGHO), and these oxides can be used individually or in combination with each other.

[0330] As another example, the second active layer 623 may include indium-tin-gallium-zinc oxide (ITGZO).

[0331] Furthermore, in this embodiment, the second active layer 623 may be formed to have different characteristics from the first active layer 613. For example, the electrical characteristics of the second active layer 623 may differ from those of the first active layer 613.

[0332] For example, the electron mobility of the first active layer 613 and the electron mobility of the second active layer 623 may be different. Specifically, the electron mobility of the first active layer 613 may be higher than that of the second active layer 623. Various methods can be used to achieve such mutual properties, and the oxide materials of the first active layer 613 and the second active layer 623 can be different. For example, the first active layer 613 may contain indium-tin-gallium-zinc oxide (ITGZO), and the second active layer 623 may contain indium-gallium-zinc oxide (IGZO). In an optional embodiment, the materials of the first active layer 613 and the second active layer 623 can be determined such that a difference in electron mobility occurs through various oxide combinations.

[0333] Furthermore, as another example of various methods to achieve such mutual properties, the oxide material of the first active layer 613 and the oxide material of the second active layer 623 can be the same. For example, the first active layer 613 and the second active layer 623 may contain indium-gallium-zinc oxide (IGZO), and the electron mobilities of the first active layer 613 and the second active layer 623 can be made different by adjusting the amount of hydrogen diffusion or by using dopants, for example, the electron mobility of the first active layer 613 can be made higher than that of the second active layer 623.

[0334] This makes it easy to realize the efficient arrangement of the first thin-film transistor 610 and the second thin-film transistor 620, which are regions for signal generation in the pixel region or the drive circuit region. For example, by using the first thin-film transistor 610, which includes a first active layer 613 having high electron mobility, a drive circuit section (e.g., a buffer circuit section) that requires a relatively large area or a lot of signal generation can be formed, and above that, by using the second thin-film transistor 620, which includes a second active layer 623 having lower electron mobility, a drive circuit section (e.g., a light emission signal control circuit section) that occupies a relatively small area can be formed, thereby improving the design efficiency of each region through the stacked structure of thin-film transistors. As a result, high integration and high resolution of the display device 600 can be easily realized.

[0335] On the other hand, as another optional embodiment, the opposite structure is possible, and the electron mobility of the first active layer 613 and the electron mobility of the second active layer 623 may be different. For example, the electron mobility of the first active layer 613 may be lower than that of the second active layer 623. The characteristics of the first active layer 613 and the second active layer 623 can be selected according to the design conditions of the display device 600.

[0336] The second active layer 623 can be superimposed on the first active layer 613 in at least part, for example, the second active layer 623 may be superimposed on the first active layer 613 as a whole. Another example is that the second active layer 623 may not be superimposed on the first active layer 613, as shown in Figure 3 of the embodiment described above.

[0337] The second gate electrode 625 can be positioned so as to overlap the second active layer 623, for example, it can be positioned above the second active layer 623 with respect to the thickness direction of the substrate 601.

[0338] The second gate insulating film 624 can be positioned to insulate the second active layer 623 from the second gate electrode 625.

[0339] Since the details of the second gate insulating film 624 are substantially the same as those of the second gate insulating film 124 in the embodiment described above, a detailed explanation will be omitted.

[0340] The second gate electrode 625 can be placed on the second gate insulating film 624. The second gate electrode 625 can be placed so as to overlap the second active layer 623, or for example, so as to be in contact with the second gate insulating film 624.

[0341] Since the details of the second gate electrode 625 are substantially the same as those of the second gate electrode 125 in the embodiment described above, a detailed explanation will be omitted.

[0342] The third interlayer insulating layer ILD3 can be positioned to insulate the second gate electrode 625 from the third connecting electrode 626 and the fourth connecting electrode 627. For example, the third interlayer insulating layer ILD3 can be formed above the second gate electrode 625 and the second active layer 623, covering the second gate electrode 625 and the second active layer 623. The details of the third interlayer insulating layer ILD3 are substantially the same as those of the third interlayer insulating layer ILD3 in the embodiments described above, so a detailed explanation will be omitted.

[0343] The third connecting electrode 626 and the fourth connecting electrode 627 can be placed on the third interlayer insulating layer ILD3. The details of the third connecting electrode 626 and the fourth connecting electrode 627 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the embodiment described above, so a detailed explanation is omitted.

[0344] In this embodiment, the display device 600 has a first thin-film transistor 610 arranged on a substrate 601, and a second thin-film transistor 620 may be arranged above the first thin-film transistor 610. Furthermore, a second active layer 623 containing the oxide of the second thin-film transistor 620 may be arranged above a first active layer 613 containing the oxide of the first thin-film transistor 610.

[0345] Through this structure, when forming the first thin-film transistor 610, which is positioned lower relative to the thickness direction of the substrate 601, the first active layer 613 can be formed without a high-energy process (e.g., laser crystallization), and when forming the second thin-film transistor 620, which is positioned higher, the second active layer 623 can also be formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 610 below it. Furthermore, it reduces or prevents unevenness in the first active layer 613 and the second active layer 623 that may occur when performing such a high-energy process (e.g., laser crystallization).

[0346] Furthermore, through this process, a structure in which a second thin-film transistor 620 is positioned above the first thin-film transistor 610, that is, a structure in which multiple thin-film transistors are stacked, can be easily and safely formed. As a result, one or more circuits can be highly integrated and arranged, and the high resolution of the display device 600 can be easily realized.

[0347] Furthermore, the second active layer 623 in this embodiment can be formed to have different characteristics from the first active layer 613. For example, the electrical characteristics of the second active layer 623 may differ from those of the first active layer 613. As an example, the electron mobility of the first active layer 613 and the electron mobility of the second active layer 623 may be different. Specifically, the electron mobility of the first active layer 613 may be higher than that of the second active layer 623.

[0348] This makes it easy to efficiently arrange the first thin-film transistor 610 and the second thin-film transistor 620 in an upper and lower stacked configuration in the pixel region or the drive circuit region. For example, by arranging thin-film transistors that can embody high electron mobility (e.g., the first thin-film transistor) in regions requiring a relatively large number of circuit configurations or a large number of signal generation, and thin-film transistors that can embody low electron mobility (e.g., the second thin-film transistor) in regions requiring a relatively small number of circuit configurations or a small number of signal generation, the precise arrangement design characteristics between the upper and lower layers in each region of the display device 600 can be easily controlled as needed.

[0349] Furthermore, the configuration in which the second active layer 623 and the first active layer 613 of this embodiment have different characteristics, for example, different electrical characteristics, and the various descriptions of the second active layer 623 and the first active layer 613 described above can be optionally applied to the embodiments shown in Figures 1 to 5 described above, and can also be optionally applied to the embodiments described later in the specification.

[0350] Figure 7 is a schematic plan view showing a display device according to yet another embodiment of the present invention. Figure 8 is a cross-sectional view taken along the line VIII-VIII in Figure 7.

[0351] The display device 800 may include a display area DA and a peripheral area PA.

[0352] The display area DA may be provided with one or more display elements (not shown), such as organic light-emitting elements (OLEDs), to display an image. Other examples of display elements include quantum dot light-emitting elements and liquid crystal display elements, and other examples include one of various types such as light-emitting diodes (LEDs), micro LEDs or mini LEDs, and nano LEDs.

[0353] Furthermore, multiple pixels (not shown) can be placed in the display area DA, and one or more display elements (not shown) can be placed in each pixel (not shown).

[0354] A peripheral region PA can be formed around the display region DA. The peripheral region PA may include a non-display region (not shown), and for example, the non-display region can be formed to surround the display region DA. In another optional embodiment, the peripheral region PA or the non-display region of the peripheral region PA may be formed to be adjacent only to one or both sides of the display region DA.

[0355] The peripheral region PA can be configured with a drive circuit area that generates various signals for the operation of pixels in the display region DA, and the drive circuit area can have one or more drive circuits.

[0356] Referring to Figures 7 and 8, the display device 800 may include a substrate 801, a first thin-film transistor 810, and a second thin-film transistor 820.

[0357] Figure 8 can specifically show a schematic representation of at least one region of a single pixel of the display device 800. For example, a single pixel of the display device 800 may include a first thin-film transistor 810 and a second thin-film transistor 820.

[0358] The first thin-film transistor 810 and the second thin-film transistor 820 can each generate the same signal or different signals necessary for the pixel to operate.

[0359] The configurations of the substrate 801, buffer layer 802, first active layer 813 and first gate electrode 815 of the first thin-film transistor 810, and first gate insulating film 814, first connecting electrode 816, and second connecting electrode 817 are substantially the same as those of the embodiments described above, for example, the configurations of the substrate 101, buffer layer 102, first active layer 113 and first gate electrode 115 of the first thin-film transistor 110, and first gate insulating film 114, first connecting electrode 116, and second connecting electrode 117 as described in Figure 1, so a detailed explanation will be omitted.

[0360] Furthermore, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 are substantially the same as those described in the embodiments described above, so a detailed explanation will be omitted.

[0361] Furthermore, the configurations of the second active layer 823 and second gate electrode 825 of the second thin-film transistor 820, as well as the second gate insulating film 824, third connecting electrode 826, and fourth connecting electrode 827, are substantially the same as those of the second active layer 123 and second gate electrode 125, as well as the second gate insulating film 124, third connecting electrode 126, and fourth connecting electrode 127 of the second thin-film transistor 120 described in Figure 1, so a detailed explanation will be omitted.

[0362] Furthermore, as an optional embodiment, an upper buffer layer 803, a first conductive pattern section BML1, and a second conductive pattern section BML2 can be further arranged. Since this is substantially the same as the embodiment described in Figure 4 above, a detailed explanation will be omitted.

[0363] It goes without saying that, although not shown in the figures, at least one of the structures shown in Figures 2 to 6 can be applied to the display device 800 of this embodiment.

[0364] The protective insulating layer PVX is positioned above the second thin-film transistor 820, and can be positioned, for example, to cover the second thin-film transistor 820.

[0365] The protective insulating layer PVX may contain insulating material to protect and insulate the second thin-film transistor 820.

[0366] Furthermore, in an optional embodiment, the protective insulating layer PVX can eliminate the step difference from the second thin-film transistor 820, provide a flat surface on top of the second thin-film transistor 820, and reduce or prevent defects in the display element 850 caused by irregularities on the bottom.

[0367] The protective insulating layer (PVX) can be formed from a variety of materials, and can be formed using organic or inorganic materials alone or in combination. Furthermore, the protective insulating layer (PVX) may include a single layer or multiple layers containing organic materials. Another example is that the protective insulating layer (PVX) may include a composite laminate of an inorganic insulating film and an organic insulating film.

[0368] The display element 850 can be placed above the protective insulating layer PVX. As mentioned above, the display element 850 can be one of various types, for example, an organic light-emitting element, and the following explanation will use an organic light-emitting element as an example.

[0369] The display element 850 may be electrically connected to a lower circuit, such as a first thin-film transistor 810 or a second thin-film transistor 820, although this is not shown in the diagram.

[0370] The display element 850 includes a first electrode 851, a second electrode 852, and an intermediate layer 853 interposed between the two electrodes.

[0371] The first electrode 851 can be electrically connected to a circuit below it, for example, a first thin-film transistor 810 or a second thin-film transistor 820.

[0372] The first electrode 851 can have various forms, for example, it can be formed by patterning in an island shape.

[0373] The first electrode 851 can contain a variety of conductive materials. For example, the first electrode 851 can contain at least one selected from the group including transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum-doped zinc oxide (AZO). The first electrode 851 can also contain a highly reflective metal such as silver (Ag).

[0374] The intermediate layer 853 includes an organic light-emitting layer, and the organic light-emitting layer can be made of a low-molecular-weight organic material or a high-molecular-weight organic material. In an optional embodiment, the intermediate layer 853 may further include, together with the organic light-emitting layer, at least one selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0375] On the other hand, the organic light-emitting layer can be formed separately for each organic light-emitting element. In this case, each organic light-emitting element can emit red, green, and blue light, respectively. However, the present invention is not limited to this, and the organic light-emitting layer can be formed in common for the entire organic light-emitting element. For example, multiple organic light-emitting layers emitting red, green, and blue light can be stacked or mixed vertically to form a device that emits white light. Needless to say, the combination of colors for emitting white light is not limited to those described above. On the other hand, in this case, a color conversion layer or color filter can be provided separately to convert the emitted white light into a predetermined color.

[0376] The second electrode 852 can be formed from various conductive materials. For example, the second electrode 852 may contain lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or silver (Ag), and may form a single or multilayer structure with at least one of these materials, or may include an alloy material containing at least two of these materials.

[0377] A pixel definition film PDL can be placed on the protective insulating layer PVX, and the pixel definition film PDL can be positioned so as not to cover a predetermined area of ​​the first electrode 851. Then, an intermediate layer 853 can be placed on the area of ​​the first electrode 851 that is not covered by the pixel definition film PDL, and a second electrode 852 can be placed on the intermediate layer 853.

[0378] Pixel delimiting (defining) films (PDLs) can be formed from a variety of insulating materials. For example, pixel delimiting (defining) films (PDLs) can contain organic materials, and specifically, they can be formed from one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, by methods such as spin coating.

[0379] In an optional embodiment, a functional layer (not shown) having one or more layers can be further arranged on the second electrode 852. Specifically, at least one layer of the functional layer can reduce contamination of the second electrode 852 during subsequent processes, and another layer of the functional layer can improve the efficiency of visible light extracted from the intermediate layer 853.

[0380] The sealing portion 890 can be positioned to protect the display element 850. For example, the sealing portion 890 having one or more sealing layers can be positioned on the second electrode 852 to block or reduce the ingress of moisture or other foreign matter into the display element 850.

[0381] As an example, the sealing portion 890 may have two or more sealing layers, or four or more sealing layers. In an optional embodiment, the sealing portion 890 may include one or more inorganic layers or one or more organic layers, and as an example, it may include a structure in which inorganic layers and organic layers are laminated alternately one or more times, and as a specific example, it may include a structure in which inorganic layers and organic layers are laminated alternately multiple times.

[0382] In this embodiment, the display device 800 has a first thin-film transistor 810 arranged on a substrate 801, and a second thin-film transistor 820 can be arranged above the first thin-film transistor 810. Furthermore, a second active layer 823 containing the oxide of the second thin-film transistor 820 can be arranged above a first active layer 813 containing the oxide of the first thin-film transistor 810.

[0383] When forming the first thin-film transistor 810, which is positioned lower relative to the thickness direction of the substrate 801, through this structure, the first active layer 813 is formed without a high-energy process (e.g., laser crystallization). Similarly, when forming the second thin-film transistor 820, which is positioned higher, the second active layer 823 is formed without a high-energy process (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 810 below it. Furthermore, it reduces or prevents unevenness in the first active layer 813 and the second active layer 823 that may occur when performing such a high-energy process (e.g., laser crystallization).

[0384] Furthermore, by having multiple thin-film transistors included in one pixel of the display device 800 include an active layer containing an oxide, and by having multiple such thin-film transistors arranged vertically with respect to the substrate 801, the circuits included in the pixels can be easily highly integrated and arranged, thereby easily realizing the high resolution of the display device 800.

[0385] Figure 9 is a schematic cross-sectional view showing a display device according to another embodiment of the present invention.

[0386] For the sake of explanation, we will focus on the differences between this display device 800 and the one shown in Figure 8.

[0387] The display device 900 may include a substrate 901, a first thin-film transistor 910, a second thin-film transistor 920, a third thin-film transistor 930, and a fourth thin-film transistor 940.

[0388] Figure 9 may specifically show a schematic representation of at least one region of a single pixel of the display device 900. For example, a single pixel of the display device 900 may include a first thin-film transistor 910, a second thin-film transistor 920, a third thin-film transistor 930, and a fourth thin-film transistor 940.

[0389] The first thin-film transistor 910, the second thin-film transistor 920, the third thin-film transistor 930, and the fourth thin-film transistor 940 can each generate the same or different signals necessary for the pixel to operate.

[0390] The first thin-film transistor 910, the second thin-film transistor 920, the third thin-film transistor 930, and the fourth thin-film transistor 940 each include an active layer containing an oxide, and may include, for example, a first active layer 913, a second active layer 923, a third active layer 933, and a fourth active layer 943, each containing an oxide.

[0391] The distance between the substrate 901 and the first thin-film transistor 910 can be smaller than the distance between the substrate 901 and the second thin-film transistor 920. Furthermore, with respect to the thickness direction of the substrate 901 (for example, the Z-axis direction in Figure 9), the first thin-film transistor 910 can be positioned between the substrate 901 and the second thin-film transistor 920.

[0392] The distance between the substrate 901 and the third thin-film transistor 930 can be smaller than the distance between the substrate 901 and the fourth thin-film transistor 940. Also, with reference to the thickness direction of the substrate 901 (for example, the Z-axis direction in Figure 9), the third thin-film transistor 930 can be positioned between the substrate 901 and the fourth thin-film transistor 940.

[0393] As an optional embodiment, the first active layer 913 of the first thin-film transistor 910 and the third active layer 933 of the third thin-film transistor 930 can be formed on the same layer (for example, a buffer layer 902). For example, the first active layer 913 and the third active layer 933 can be formed simultaneously using the same oxide material.

[0394] Furthermore, as an optional embodiment, the second active layer 923 of the second thin-film transistor 920 and the fourth active layer 943 of the fourth thin-film transistor 940 can be formed on the same layer (for example, the upper buffer layer 903). For example, the second active layer 923 and the fourth active layer 943 can be formed simultaneously using the same oxide material.

[0395] The substrate 901 can include one of various forms and materials, for example, it can have multiple layers, and the substrate 901 can include one or more organic layers (e.g., resin-based materials) and one or more inorganic layers, and specifically, it can also include an inorganic layer 901c disposed between two organic layers 901a and a second organic layer 901b.

[0396] As an optional embodiment, one or more barrier layers BRL1, BRL2 can be placed between the substrate 901 and the buffer layer 902. The one or more barrier layers BRL1, BRL2 may include a first barrier layer BRL1 and a second barrier layer BRL2.

[0397] The barrier layers BRL1 and BRL2 reduce or prevent the inflow of foreign matter from the outside and may contain an insulator, which may include a single-layer or multi-layer structure of inorganic materials such as a silicon oxide layer and a silicon nitride layer.

[0398] In an optional embodiment, the first conductive pattern portion BML1 and the third conductive pattern portion BML3 can be arranged between the first barrier layer BRL1 and the second barrier layer BRL2.

[0399] An intermediate conductive layer BBM can be placed between the first thin-film transistor 910 and the third thin-film transistor 930 and the second thin-film transistor 920 and the fourth thin-film transistor 940. The intermediate conductive layer BBM can be placed between insulating layers; for example, the intermediate conductive layer BBM can be placed between the lower layer ILD21 and the upper layer ILD22 of the second interlayer insulating layers ILD21 and ILD22.

[0400] The configuration of the first active layer 913 and the first gate electrode 915 of the first thin-film transistor 910, as well as the first gate insulating film 914, can be modified and applied within a range substantially identical or similar to any of the embodiments described above, and a first connecting electrode (not shown) or a second connecting electrode (not shown) can be optionally further arranged.

[0401] The configuration of the second active layer 923 and the second gate electrode 925 of the second thin-film transistor 920, as well as the second gate insulating film 924, can be modified and applied within a range substantially identical or similar to any of the embodiments described above, and a first connecting electrode 926 or a second connecting electrode (not shown) can be optionally further arranged.

[0402] The configuration of the third active layer 933 and the third gate electrode 935, as well as the third gate insulating film 934 of the third thin-film transistor 930, can be modified and applied within the same or similar range as any of the first thin-film transistors described in the above-described embodiments, and a first connecting electrode (not shown) or a second connecting electrode (not shown) can be optionally further arranged.

[0403] The configuration of the fourth active layer 943 and the fourth gate electrode 945, as well as the fourth gate insulating film 944 of the fourth thin-film transistor 940, can be modified and applied within the same or similar range as any of the second thin-film transistors described in the above-described embodiments, and a first connecting electrode (not shown) or a second connecting electrode (not shown) can be optionally further arranged.

[0404] Furthermore, although the figure shows the first conductive pattern section BML1, the third conductive pattern section BML3, and the fourth conductive pattern section BML4, these are illustrative examples, and a second conductive pattern section (not shown) may be further included to correspond to the second thin-film transistor 920.

[0405] Another example is to exclude at least one of the first conductive pattern section BML1, the third conductive pattern section BML3, and the fourth conductive pattern section BML4, or to exclude all of them.

[0406] The buffer layer 902, the upper buffer layer 903, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 are substantially the same as those described in the embodiments described above, so a detailed explanation will be omitted.

[0407] In an optional embodiment, one or more lower conductive connection patterns GT11, GT12, GT13, GT14, and GT15 can be placed on top of the first thin-film transistor 910 and the third thin-film transistor 930. Each of the lower conductive connection patterns GT11, GT12, GT13, GT14, and GT15 can be electrically connected to a region of the first thin-film transistor 910 and the third thin-film transistor 930, or to the first conductive pattern portion BML1 and the third conductive pattern portion BML3 below them, for example, through a contact hole penetrating at least one of the buffer layer 902, the second barrier layer BRL2, and the first interlayer insulating layer ILD1.

[0408] In an optional embodiment, one or more upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 can be arranged above the second thin-film transistor 920 and the fourth thin-film transistor 940. Each of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 can be electrically connected to a region of the second thin-film transistor 920 and the fourth thin-film transistor 940 or to a fourth conductive pattern portion BML4 below it, for example, through a contact hole penetrating at least one of the upper buffer layer 903 and the third interlayer insulating layer ILD3.

[0409] Furthermore, in an additional optional embodiment, one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, CN16 (e.g., CN11) may be electrically connected to any one of the lower conductive connection patterns GT11, GT12, GT13, GT14, GT15 (e.g., GT11).

[0410] In addition, as an optional embodiment, one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 (for example, CN16) may be electrically connected to the intermediate conductive layer BBM.

[0411] The first protective insulating layer PVX1 is positioned on top of the second thin-film transistor 920 and the fourth thin-film transistor 940, and may be positioned to cover, for example, the second thin-film transistor 920 and the fourth thin-film transistor 940.

[0412] The first protective insulating layer PVX1 may contain insulating material to protect and insulate the second thin-film transistor 920 and the fourth thin-film transistor 940.

[0413] Furthermore, as an optional embodiment, a second protective insulating layer PVX2 can be formed on the first protective insulating layer PVX1.

[0414] As an optional embodiment, a second upper conductive connection pattern CN2 can be placed on the first protective insulating layer PVX1. In this case, the second upper conductive connection pattern CN2 can be electrically connected to one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 (for example, CN13), and can be electrically connected to the first electrode 951 of the display element 950.

[0415] The display element 950 can be placed above the second protective insulating layer PVX2. For example, it may include an organic light-emitting element, and the display element 950 can be electrically connected to the circuit below, for example, one of the first to fourth thin-film transistors 910, 920, 930, 940 (for example, the second thin-film transistor).

[0416] The display element 950 includes a first electrode 951, a second electrode 952, and an intermediate layer 953 interposed between the two electrodes. The specific details of the display element 950 are substantially the same as those described for the display element 850 in the above-mentioned embodiment, so a more detailed explanation will be omitted.

[0417] A pixel definition film PDL can be placed on the second protective insulating layer PVX2, and the pixel definition film PDL can be placed so as not to cover a predetermined area of ​​the first electrode 951. Then, an intermediate layer 953 can be placed on the area of ​​the first electrode 951 that is not covered by the pixel definition film PDL, and the second electrode 952 can be placed on the intermediate layer 953.

[0418] The sealing portion 990 can be positioned to protect the display element 950, and since it is substantially the same as that described in the above-mentioned embodiment, a detailed explanation will be omitted.

[0419] In this embodiment, the display device 900 has a first thin-film transistor 910 and a third thin-film transistor 930 arranged on a substrate 901, and a second thin-film transistor 920 and a fourth thin-film transistor 940 may be arranged above them.

[0420] Furthermore, the first thin-film transistor 910, the third thin-film transistor 930, the second thin-film transistor 920, and the fourth thin-film transistor 940 may have an active layer containing an oxide.

[0421] Furthermore, although not shown in the diagram, a single pixel can contain five or more (for example, six or seven or more) thin-film transistors, and even in that case, they can be arranged in a stacked configuration between the lower and upper layers, with respect to the thickness direction of the substrate.

[0422] Through this structure, when forming the first thin-film transistor 910 and the third thin-film transistor 930, which are located at lower positions relative to the thickness direction of the substrate 901, the first active layer 913 and the third active layer 933 are formed without high-energy processes (e.g., laser crystallization). Similarly, when forming the second thin-film transistor 920 and the fourth thin-film transistor 940, which are located at higher positions, the second active layer 923 and the fourth active layer 943 are formed without high-energy processes (e.g., laser crystallization). This reduces or prevents thermal damage to the first thin-film transistor 910 and the third thin-film transistor 930 located below them. Furthermore, it reduces or prevents unevenness in the first active layer 913, the second active layer 923, the third active layer 933, and the fourth active layer 943 that may occur when performing such high-energy processes (e.g., laser crystallization).

[0423] Furthermore, by ensuring that multiple thin-film transistors included in one pixel of the display device 900 include an active layer containing an oxide, and that at least two of such multiple thin-film transistors are arranged on the same layer with respect to the substrate 901, they can also be arranged in a layered configuration with two layers stacked vertically, the increase in pixel area can be reduced even when the circuitry included in the pixel becomes complex, for example, when the number of thin-film transistors increases, and the high resolution of the display device 900 can be easily realized.

[0424] Figure 10 is a schematic cross-sectional view showing a display device according to another embodiment of the present invention. Figure 11 is a schematic cross-sectional view illustrating region K of Figure 10. Figure 12 is a diagram showing an example of the structure of Figure 11.

[0425] The display device 1000 may include a display area DA and a peripheral area PA.

[0426] The display area DA may be provided with one or more display elements (not shown), such as organic light-emitting elements (OLEDs), to display an image. Other examples of display elements include quantum dot light-emitting elements and liquid crystal display elements, and other examples include one of various types such as light-emitting diodes (LEDs), micro LEDs or mini LEDs, and nano LEDs.

[0427] It can include one of several other types.

[0428] Furthermore, multiple pixels (not shown) can be placed in the display area DA, and one or more display elements (not shown) can be placed in each pixel (not shown).

[0429] A peripheral region PA can be formed around the display region DA. The peripheral region PA may include a non-display region (not shown), and for example, the non-display region may be formed to surround the display region DA. In other optional embodiments, the peripheral region PA, or the non-display region of the peripheral region PA, may be formed to be adjacent only to one or both edges of the display region DA.

[0430] The peripheral region PA can be configured with a drive circuit area that generates various signals for the operation of pixels in the display region DA, and the drive circuit area can have one or more drive circuits.

[0431] For example, multiple drive circuit units can be placed in the peripheral PA area, and multiple different types of drive circuit units can be placed there.

[0432] Referring to Figure 11, two different types of drive circuit sections, BFR and ELG, can be placed on the substrate 1001, and arranged in the upper and lower layers based on the thickness direction of the substrate 1001. Specifically, they can be placed in the lower and upper layers with an interlayer insulating layer ILD in between.

[0433] As an optional embodiment, a buffer circuit section BFR can be placed in the lower layer and a light emission control circuit section ELG in the upper layer, with the interlayer insulating layer ILD in between. This is for illustrative purposes only, and various types of drive circuits can be optionally arranged.

[0434] The buffer circuit section (BFR) can be arranged to embody various functions, but for example, it may be included in a shift register that sequentially shifts the scan output signals based on the clock signal.

[0435] Referring to Figure 12, the first thin-film transistor 1010 and the second thin-film transistor 1020 are shown arranged on the substrate 1001.

[0436] The buffer circuit BFR may include a first thin-film transistor 1010. For example, it may include a first thin-film transistor 1010 that includes a first active layer 1013 containing an oxide. In an optional embodiment, the buffer circuit BFR may include a plurality of first thin-film transistors 1010, in which case the plurality of first thin-film transistors 1010 may be arranged side by side in the same layer.

[0437] The light emission control circuit ELG may include a second thin-film transistor 1020. For example, it may include a second thin-film transistor 1020 that includes a second active layer 1023 containing an oxide. In an optional embodiment, the light emission control circuit ELG may include a plurality of second thin-film transistors 1020, in which case the plurality of second thin-film transistors 1020 may be arranged side by side in the same layer.

[0438] The configurations of the buffer layer 1002, the first gate electrode 1015, the first gate insulating film 1014, the first connecting electrode 1016 and the second connecting electrode 1017, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3, the second gate electrode 1025, the second gate insulating film 1024, the third connecting electrode 1026 and the fourth connecting electrode 1027 can be modified and applied within a range that is substantially the same as or similar to that described in the above-described embodiments, so a detailed explanation is omitted.

[0439] Figure 13 shows one modified form of Figure 11.

[0440] Referring to Figure 13, two or more drive circuit sections of different types, BFR, ELG1, ELG2, GCL, GRL, and GWL, can be arranged on the substrate 1001, and can be placed in the upper and lower layers with respect to the thickness direction of the substrate 1001. Specifically, multiple sections can be placed below and multiple sections above, separated by an interlayer insulating layer ILD.

[0441] As an optional embodiment, a plurality of buffer circuit sections BFR and different types of circuit sections, such as a first light emission control section ELG1, a second light emission control section ELG2, a first scan control section GCL, a second scan control section GRL, and a third scan control section GWL, can be arranged in the layer below the interlayer insulating layer ILD. The first scan control section GCL, the second scan control section GRL, and the third scan control section GWL can each output or control different scan signals and may include a start scan signal control section, a reference scan signal control section, and a write scan signal control section, and may further include a compensation scan signal control section or an initialization scan signal control section.

[0442] This is for illustrative purposes only, and various types of drive circuit sections can be optionally arranged.

[0443] The specific structure shown in Figure 12 can also be applied to the embodiment shown in Figure 13.

[0444] As an example, multiple first thin-film transistors 1010 can be arranged to correspond to multiple buffer circuit sections (BFRs).

[0445] Furthermore, after the interlayer insulating layer ILD is placed on top of the multiple first thin-film transistors 1010, multiple second thin-film transistors 1020 corresponding to the first light emission control unit ELG1, the second light emission control unit ELG2, the first scanning control unit GCL, the second scanning control unit GRL, and the third scanning control unit GWL can be arranged.

[0446] In this embodiment, one or more drive circuit sections are arranged on the substrate 1001 to correspond to one or more drive circuit sections arranged in the peripheral region PA of the display device 1000. Specifically, one or more types of drive circuit sections can be arranged below an interlayer insulating layer (ILD), and other types of drive circuit sections can be arranged above. The first thin-film transistor 1010 and the second thin-film transistor 1020 can be arranged to correspond to each of these drive circuit sections.

[0447] One or more first thin-film transistors and one or more second thin-film transistors can be arranged such that at least one region overlaps in the thickness direction of the substrate, and a plurality of drive circuit sections can be easily arranged to overlap in the thickness direction of the substrate accordingly.

[0448] This makes it possible to reduce the area of ​​the surrounding PA region, easily realize high integration of the drive circuit section, and improve the manufacturing convenience of the high-resolution display device 1000.

[0449] On the other hand, as an optional embodiment, in the case of a buffer circuit that occupies a relatively large area of ​​the drive circuit, when arranging the corresponding first thin-film transistor 1010, the first active layer 1013 has a higher electron mobility than the second active layer 1023 of the second thin-film transistor 1020, thereby reducing the formation area of ​​the circuit and increasing the reduction effect on the surrounding area PA. In addition, depending on the characteristics of different types of drive circuit sections and the required number and area, it is possible to decide whether to use the same type of active layer or different types of active layers with different electrical characteristics, such as different electron mobility values.

[0450] Furthermore, even when stacking various types of drive circuit sections, thin-film transistors having an active layer containing oxide are used throughout. This ensures thermal stability during manufacturing, reduces or prevents active layer striping, and improves uniformity between multiple thin-film transistors.

[0451] Figure 14 is a schematic plan view showing a display device according to another embodiment of the present invention. Figure 15 is a schematic cross-sectional view illustrating region K in Figure 14.

[0452] Figure 16 shows an example of the structure shown in Figure 15. For the sake of explanation, we will focus on the differences from the previously described embodiment.

[0453] The display device 2000 may include a display area DA and a peripheral area PA.

[0454] A peripheral area PA can be formed around the display area DA.

[0455] The peripheral region PA can be configured with a drive circuit area that generates various signals for the operation of pixels in the display region DA, and the drive circuit area can have one or more drive circuits.

[0456] For example, multiple drive circuit units can be placed in the peripheral PA area, and multiple different types of drive circuit units can be placed there.

[0457] Referring to Figure 15, two or more drive circuit units DB1, DB2, DB3, DB4, and DB5 of different types can be arranged on the substrate 2001, and can be placed in the upper and lower layers with respect to the thickness direction of the substrate 2001. Specifically, multiple units can be placed below and multiple units above, separated by an interlayer insulating layer ILD.

[0458] As an optional embodiment, the interlayer insulating layer ILD can be used to sandwich the first drive circuit area DB1 and the third drive circuit area DB3 in the lower layer, and the second drive circuit area DB2, the fourth drive circuit area DB4, and the fifth drive circuit area DB5 in the upper layer.

[0459] As shown in the figure, the lower-level first drive circuit region DB1 and third drive circuit region DB3 can be arranged so that at least one region overlaps with the upper-level second drive circuit region DB2, fourth drive circuit region DB4, and fifth drive circuit region DB5.

[0460] Two or more drive circuit area regions DB1, DB2, DB3, DB4, DB5 can each contain multiple drive circuit sections of one or more types.

[0461] For example, the first drive circuit region DB1 may include one or more buffer circuit sections and a first scanning control circuit section; the second drive circuit region DB2 may include one or more buffer circuit sections and a first light emission control circuit section; the third drive circuit region DB3 may include one or more buffer circuit sections and a third scanning control circuit section; the fourth drive circuit region DB4 may include one or more buffer circuit sections and a second light emission control circuit section; and the fifth drive circuit region DB5 may include one or more buffer circuit sections and a second scanning control circuit section.

[0462] Here, the first scanning control circuit unit, the second scanning control circuit unit, and the third scanning control circuit unit can each output or control different scanning signals, and may include a start scanning signal control unit, a reference scanning signal control unit, and a write scanning signal control unit, and may further include a compensation scanning signal control unit or an initialization scanning signal control unit.

[0463] Referring to Figure 16, the first to eighth thin-film transistors 2010 to 2080 are shown arranged on the substrate 2001.

[0464] The first drive circuit region DB1 may include a first thin-film transistor 2010 and a third thin-film transistor 2030. For example, it may include a first thin-film transistor 2010 containing an oxide-containing first active layer 2013, and a third thin-film transistor 2030 containing an oxide-containing third active layer. In an optional embodiment, the first thin-film transistor 2010 and the third thin-film transistor 2030 may be arranged side by side on the same layer.

[0465] The second drive circuit region DB2 may include a second thin-film transistor 2020 and a fourth thin-film transistor 2040. For example, it may include a second active layer containing an oxide, and a fourth thin-film transistor 2040 containing an oxide. In an optional embodiment, the second thin-film transistor 2020 and the fourth thin-film transistor 2040 may be arranged side by side on the same layer.

[0466] Furthermore, the second thin-film transistor 2020 and the fourth thin-film transistor 2040 may be arranged to overlap with the first thin-film transistor 2010 and the third thin-film transistor 2030 in at least one region, for example, the upper and lower active layers may overlap each other.

[0467] The third drive circuit region DB3 may include a fifth thin-film transistor 2050 and a seventh thin-film transistor 2070. For example, it may include a fifth thin-film transistor 2050 containing an oxide-containing fifth active layer, and it may also include a seventh thin-film transistor 2070 containing an oxide-containing seventh active layer. In an optional embodiment, the fifth thin-film transistor 2050 and the seventh thin-film transistor 2070 may be arranged side by side on the same layer.

[0468] The fourth drive circuit region DB4 may include the sixth thin-film transistor 2060 and the eighth thin-film transistor 2080. For example, it may include the sixth thin-film transistor 2060 which includes a sixth active layer containing an oxide, and the eighth thin-film transistor 2080 which includes an eighth active layer containing an oxide. In an optional embodiment, the sixth thin-film transistor 2060 and the eighth thin-film transistor 2080 may be arranged side by side on the same layer.

[0469] Furthermore, the sixth thin-film transistor 2060 and the eighth thin-film transistor 2080 may be arranged so as to superimpose on the fifth thin-film transistor 2050 and the seventh thin-film transistor 2070 in at least one region, for example, the upper and lower active layers may be superimposed on each other.

[0470] Although not shown in the diagram, the fifth drive circuit region DB5 may include multiple thin-film transistors, and may include multiple thin-film transistors that include an active layer containing an oxide.

[0471] The configurations of the buffer layer 2002, the first to eighth gate electrodes (only 2015 is shown), the first to eighth gate insulating films (only 2014 is shown), the connecting electrodes (only 2016 is shown) and the connecting electrodes (only 2017 is shown), the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 can be applied with modifications within a range that is substantially the same as or similar to that described in the embodiments above, so a detailed explanation is omitted.

[0472] In this embodiment, a lower layer and an upper layer can be arranged on the substrate 2001 to correspond to one or more drive circuit sections arranged in the peripheral region PA of the display device 2000. Specifically, one or more types of drive circuit sections can be arranged in the lower layer and other types of drive circuit sections in the upper layer, separated by an interlayer insulating layer ILD. Multiple thin-film transistors can be arranged to correspond to each of the drive circuit sections.

[0473] In this case, in order to efficiently arrange multiple drive circuit sections, multiple regions can be partitioned (defined) in the upper layer and multiple regions in the lower layer, separated by an interlayer insulating layer, and one or more drive circuit sections of one or more types can be placed in each region. This improves the efficiency when arranging drive circuit sections in a stacked configuration.

[0474] For example, a circuit section with a relatively large area or a large number of circuits, such as a buffer circuit section, can be placed in the upper and lower layers, while the remaining drive circuit sections can be placed in the upper and lower layers. In this case, drive circuit sections that are related to each other can be placed adjacent to each other or on the same layer, making it easier to precisely control the circuit layout design.

[0475] This increases the effect of reducing the area of ​​the surrounding PA region, making it easy to realize a highly integrated and high-resolution display device 2000.

[0476] On the other hand, as an optional embodiment, a thin-film transistor having a different active layer than other regions may be placed in the drive circuit region, which has a relatively wide area or a large amount of signal processing capacity. Such a different active layer may include an oxide semiconductor with relatively high electrical characteristics, specifically electron mobility, compared to other regions.

[0477] Figure 17 is a circuit diagram of a single pixel in a display device according to one embodiment of the present invention.

[0478] Figure 18 is a waveform diagram of the drive signal used to drive the pixels shown in Figure 17.

[0479] In this embodiment, the pixel circuit may, as an optional embodiment, include seven pixel transistors (hereinafter referred to as the first to seventh pixel transistors T1 to T7) and three capacitors. However, as an example, it may also include a smaller number of transistors and capacitors.

[0480] Furthermore, the pixel transistors included in the pixel circuit may include at least several or all of the configurations of the embodiments described above, and may include, for example, thin-film transistors that include an active layer containing an oxide. Therefore, a description of the configuration of specific thin-film transistors, such as the active layer, gate electrode, and connecting electrodes, will be omitted.

[0481] One gate of the first pixel transistor T1 can be electrically connected to the source of the first pixel transistor T1.

[0482] In this embodiment, for example, the first pixel transistor T1 may be a driving transistor. The second pixel transistor T2 may also be called a switching transistor.

[0483] The organic light-emitting element (see the embodiment described above) may be connected to the first electrode and the first power supply voltage ELVSS.

[0484] The first pixel transistor T1 can be electrically connected to a power line that receives the second power supply voltage ELVDD. In an optional embodiment, the first pixel transistor T1 may include multiple gates, for example, an upper gate and a lower gate.

[0485] The second pixel transistor T2 can be electrically connected to the data line.

[0486] The third pixel transistor T3 may be electrically connected to a voltage line that receives a reference voltage VREF. The third pixel transistor T3 may be connected to a reference scanning line GR, for example, its gate may be connected to the reference scanning line GR.

[0487] The fourth pixel transistor T4 may be electrically connected to a voltage line that receives the initialization voltage Vint. The fourth pixel transistor T4 may be connected to an initialization scan line, for example, its gate may be connected to an initialization scan line.

[0488] The fifth pixel transistor T5 can be connected to a power line that receives the second power supply voltage ELVDD and can be connected to an illumination signal line EM, for example, its gate can be connected to the illumination signal line EM.

[0489] The sixth pixel transistor T6 can be electrically connected to the light-emitting element.

[0490] The seventh pixel transistor T7 may be connected to a voltage line that receives the initialization voltage Vaint. In one example of the present invention, the initialization voltage Vaint may have a different level from the initialization voltage Vint.

[0491] Referring to Figures 17 and 18, during the initialization interval IP, one pixel transistor (e.g., the fourth pixel transistor) is turned on, and the first electrode of the light-emitting element may be initialized to the initialization voltage via the turned-on fourth pixel transistor. At this time, one capacitor may be initialized with the difference between the first power supply voltage ELVSS and the initialization voltage Vint.

[0492] Subsequently, during the light-emitting interval, the sixth pixel transistor T6 is turned on simultaneously with the fifth pixel transistor T5. The current output through the first pixel transistor T1 can be supplied to the light-emitting element via the turned-on sixth pixel transistor T6.

[0493] More specifically, the display device displays the image frame by frame. Each of the write scan line, reference scan line, initialization scan line, and light emission signal line sequentially receives scan signals or light emission control signals during the frame interval. Figure 18 may show a portion of the frame interval. Each of the scan signals or light emission control signals EM, EMB, GR, GW, and GI may have a high voltage (V-HIGH, or high level) during some intervals and a low voltage (V-LOW, or low level) during other intervals. For example, the first to fifth pixel transistors T1 to T5 of the N-type are turned on when the corresponding scan signal has a high voltage (V-HIGH).

[0494] During the initialization interval IP, the third pixel transistor T3 and the fourth pixel transistor T4 are turned on. During the initialization interval IP, the initialization process can be performed with the reference voltage VREF, or it can be performed with the initialization voltage Vint. The capacitor Cst between these points is initialized to the difference between the reference voltage VREF and the initialization voltage Vint. In addition, the other capacitor Chold is initialized to the difference between the second power supply voltage ELVDD and the initialization voltage Vint.

[0495] During the compensation interval CP, the third pixel transistor T3 and the fifth pixel transistor T5 are turned on. Capacitor coupling can compensate for the rise voltage of the first pixel transistor T1.

[0496] During the writing interval WP, the second pixel transistor T2 is turned on. The second pixel transistor T2 outputs a voltage corresponding to the data signal. As a result, the capacitor Cst is charged with a voltage value corresponding to the data signal. Then, regardless of the deviation in the rise voltage of the first pixel transistor T1 for each pixel, a current proportional to the data signal can be supplied to the light-emitting element.

[0497] Subsequently, during the light-emitting interval, the fifth pixel transistor T5 is turned on, and the first pixel transistor T1 supplies a current to the light-emitting element corresponding to the voltage value stored in a capacitor Cst, allowing the light-emitting element to emit light with a brightness corresponding to the data signal.

[0498] In this embodiment, the circuit included in one pixel includes, exemplary, seven transistors. Such seven pixel transistors may include at least one first thin-film transistor and a second thin-film transistor from any of the embodiments described above. That is, thin-film transistors, each containing an oxide-containing active layer, may be arranged along the thickness direction of the substrate in different layers, for example, with an interlayer insulating layer between the lower and upper layers.

[0499] As a specific example, the first pixel transistor T1 and the second pixel transistor T2 may include, or directly correspond to, the first thin-film transistor and the second thin-film transistor of the embodiment described above.

[0500] Another example is that all seven pixel transistors are thin-film transistors containing oxide, and multiple units of each can be arranged in the lower and upper layers, separated by an interlayer insulating layer, relative to the thickness direction of the substrate. For example, 2 to 5 pixel transistors can be arranged in the lower layer and 5 to 2 pixel transistors in the upper layer.

[0501] This configuration makes it easy to integrate circuits to a high degree in a single pixel.

[0502] Furthermore, a drive circuit section for controlling or generating signals for pixel driving may be arranged in the non-display area. For example, a drive circuit section for generating or controlling one or more light emission control signals EM, EMB, and one or more scanning control signals GR, GI, GW may be arranged in the non-display area. Such a drive circuit section can be arranged on the substrate in upper and lower layers with an interlayer insulating layer in between. For example, it can be arranged by applying Figures 10 to 16 of the embodiment described above. This makes it possible to reduce the non-display area or bezel of the display device and easily realize high integration and high resolution.

[0503] Thus, the present invention has been described with reference to one embodiment shown in the figures, but this is merely illustrative, and a person with ordinary skill in the art will understand that various modifications and changes to the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical idea of ​​the appended claims.

[0504] A preferred specific embodiment is as follows:

[0505] The background and issues of this matter are as follows (i) to (iii).

[0506] (i) In display panels in which light-emitting elements such as organic light-emitting elements (OLEDs) or other pixels (subpixels) are arranged in a matrix, in order to meet the demands for higher resolution and higher image quality, it is necessary to reduce the installation area of ​​the pixel circuit for each pixel in the display area and the peripheral drive circuit in the peripheral non-display area.

[0507] (ii) In particular, in a display panel in which light-emitting elements such as organic light-emitting elements (OLEDs) are arranged, for example, seven or more thin-film transistors are arranged in each pixel (subpixel).

[0508] (iii) A thin-film transistor on the lower layer, made of polycrystalline silicon, and a thin-film transistor on the upper layer, with a metal oxide as the active layer, are also partially superimposed (for example, Figures 7A to 7B in Patent Document 1 and Figure 11 in Patent Document 2).

[0509] In specific embodiments of this application, at least one of the following A1 to A8 is used.

[0510] A1 In each pixel circuit, all transistors on the upper and lower layers (for example, T1 to T7 in Figure 17 of this application) have an oxide semiconductor as their active layer.

[0511] A2 In each pixel circuit, drive transistors (T1, 910) that supply drive current to the light-emitting element (950) and light-emitting control transistors (T5, 930; T6, 920) can be placed in the lower layer, while switching transistors (T2, 940) for writing data signals and initialization transistors (T3, T4, T7) that supply initialization voltages (VREF-Vint, Vaint) to the gates of the drive transistors (T1, 910) and the pixel electrodes (951, anode) of the light-emitting element (950), respectively, can be placed in the upper layer. (Figures 9 and 17 of this application)

[0512] In the specific example shown in Figure 17 of this application, the gate of the drive transistor (T1, 910) is connected to the reference power supply (VREF) via the first initialization transistor (T3), and to the initialization power supply (Vint) via the first capacitor (Cst) and the second initialization transistor (T4). Furthermore, as shown in Figure 9 of this application, a resin planarization film (protective insulating layer PVX1, PVX2) may be placed between the upper transistor and the light-emitting element (950).

[0513] The lower-layer transistors (910, 930), such as the A3 drive transistor (T1), have a higher electron mobility in their semiconductor active layer compared to the upper-layer transistors (T2, 940), for example, 1.1 times or more, 1.2 times or more, 1.3 times or more, 1.4 times or more, 1.5 times or more, or 1.6 times or more.

[0514] A4 In the drive transistor (T1), etc., light-shielding bias electrodes (BML1, BML3~4) can be placed so as to sandwich the semiconductor active layer (913) together with the gate electrode (915). (See Figures 9 and 17 in this application, etc.)

[0515] A5 The light-shielding bias electrode (BML1) can be electrically connected to the semiconductor active layer (2013) via the connecting electrode (2016).

[0516] In the specific example shown in Figure 17, the drain electrode of the drive transistor (T1) and the drain electrode of the other initialization transistor (T4) are connected to the drive power supply (EVLDD) via a second capacitor (Chold). The coupling between the first capacitor (Cst) and the second capacitor (Chold) can compensate for the rise voltage of the drive transistor (first pixel transistor T1). (Figures 17-18 of this application,

[0495] )

[0517] A7 A metal layer (intermediate conductive layer BBM) can be placed between the lower layer transistors (910, 930) and the upper layer transistors (920, 940). (See Figure 9 of this application, etc.)

[0518] In the drive circuit within the peripheral non-display area (A8), a series of transistors forming a buffer circuit (BFR) can be arranged on the lower layer, while the logic circuit section (first light emission control section ELG1, second light emission control section ELG2, first scan control section GCL, second scan control section GRL, third scan control section GWL) can be arranged on the upper layer. (See Figure 13 of this application, etc.) [Explanation of Symbols]

[0519] 101, 201, 301, 401, 501, 601, 801, 901, 1001, 2001: Circuit board 110, 210, 310, 410, 510, 610, 810, 910, 1010, 2010: First thin-film transistor 120, 220, 320, 420, 520, 620, 820, 920, 1020, 2020: Second thin-film transistor 113, 213, 313, 413, 513, 613, 813, 913, 1013, 2013: 1st active layer 123, 223, 323, 423, 523, 623, 823, 923, 1023: 2nd active layer

Claims

1. A display device comprising a substrate, a first thin-film transistor, and a second thin-film transistor, The first thin-film transistor includes a first active layer containing an oxide and is disposed above the substrate. The second thin-film transistor includes a second active layer containing an oxide and is positioned above the substrate. A display device comprising the arrangement of the first thin-film transistor between the substrate and the second thin-film transistor, with reference to the thickness direction of the substrate, such that the distance between the substrate and the first thin-film transistor is smaller than the distance between the substrate and the second thin-film transistor.

2. The display apparatus according to claim 1, further comprising one or more interlayer insulating layers disposed between the first thin-film transistor and the second thin-film transistor.

3. The display device according to claim 1, wherein the first thin-film transistor and the second thin-film transistor are arranged such that at least one region of them overlaps with respect to the thickness direction of the substrate.

4. The display device according to claim 3, wherein the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor are arranged so that at least one region of them overlaps with respect to the thickness direction of the substrate.

5. The display apparatus according to claim 1, wherein the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor have different characteristics from each other.

6. The display apparatus according to claim 1, wherein the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor have different electrical characteristics.

7. The display device according to claim 1, wherein the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor have different electron mobility values.

8. The display apparatus according to claim 1, wherein the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor contain different oxides.

9. The display device according to claim 1, further comprising a conductive pattern portion arranged to overlap with the first active layer of the first thin-film transistor or the second active layer of the second thin-film transistor.

10. The display apparatus according to claim 9, further comprising one or more insulating layers disposed between the conductive pattern portion and the first active layer or the second active layer.

11. The display device according to claim 9, wherein the conductive pattern portion is connected to one region of the first thin-film transistor or one region of the second thin-film transistor via one or more contact holes.

12. The first thin-film transistor or the second thin-film transistor includes one or more connecting electrodes connected to the first active layer or the second active layer, The display device according to claim 11, wherein the conductive pattern portion is electrically connected to at least one region of the connecting electrode.

13. The display apparatus according to claim 1, further comprising an intermediate conductive layer disposed between the first thin-film transistor and the second thin-film transistor.

14. The display apparatus according to claim 13, wherein the intermediate conductive layer is formed to correspond to at least the width of the first active layer or the second active layer in one direction.

15. The display apparatus according to claim 13, wherein the intermediate conductive layer is connected to the first thin-film transistor or one or more conductive patterns arranged in the same layer as or different from the first thin-film transistor.

16. The display apparatus according to claim 13, wherein the intermediate conductive layer is connected to the second thin-film transistor or one or more conductive patterns arranged in the same layer as or different from the second thin-film transistor.

17. Through the region where the aforementioned intermediate conductive layer is absent, The display device according to claim 13, wherein the first thin-film transistor or one or more conductive patterns arranged in the same layer or a different layer as the first thin-film transistor is electrically connected to the second thin-film transistor or one or more conductive patterns arranged in the same layer or a different layer as the second thin-film transistor.

18. The display apparatus according to claim 1, further comprising a plurality of thin-film transistors arranged adjacent to the first thin-film transistor in the same layer as the first thin-film transistor, each thin-film transistor including an active layer containing an oxide.

19. The display apparatus according to claim 1, further comprising a plurality of thin-film transistors arranged adjacent to the second thin-film transistor in the same layer as the second thin-film transistor, each comprising an active layer containing an oxide.

20. The substrate includes a display area and a peripheral area disposed on at least one side of the display area, The display area has one or more pixels arranged within it. The display device according to claim 1, further comprising a drive circuit region in the peripheral region for generating or controlling one or more signals for the operation of the pixels.

21. The display device according to claim 20, further comprising the arrangement of the first thin-film transistor and the second thin-film transistor so as to correspond to one of the pixels.

22. The aforementioned single pixel contains, The first thin-film transistor is adjacent to an active layer containing an oxide, and one or more thin-film transistors necessary for driving the one pixel are arranged therein. The display apparatus according to claim 21, further comprising an active layer containing an oxide adjacent to the second thin-film transistor, wherein one or more thin-film transistors necessary for driving one pixel are arranged.

23. The one or more thin-film transistors adjacent to the first thin-film transistor are arranged on the same layer as each other, The display apparatus according to claim 22, wherein one or more thin-film transistors adjacent to the second thin-film transistor are arranged on the same layer as each other.

24. The display device according to claim 20, further comprising the arrangement of the first thin-film transistor and the second thin-film transistor in the drive circuit region.

25. The display device according to claim 24, wherein the first thin-film transistor and the second thin-film transistor correspond to each other so as to correspond to each of two different types of drive circuit sections arranged in the drive circuit section region.

26. In the aforementioned drive circuit region, multiple drive circuit units are arranged in the upper and lower layers, respectively, with respect to the interlayer insulating layer. To correspond to each of the aforementioned multiple drive circuit sections, Multiple thin-film transistors, each having an active layer containing an oxide, are arranged adjacent to the first thin-film transistor in the same layer as the first thin-film transistor. The display apparatus according to claim 24, further comprising a plurality of thin-film transistors adjacent to the second thin-film transistor and having an active layer containing an oxide, arranged in the same layer as the second thin-film transistor.

27. The display device according to claim 26, further comprising the fact that the types of drive circuits arranged in the upper and lower layers are different, with respect to the interlayer insulating layer.

28. The display apparatus according to claim 27, wherein, depending on the type of different drive circuit, the electrical characteristics of the active layer of the first thin-film transistor or an adjacent thin-film transistor are different from those of the active layer of the second thin-film transistor or an adjacent thin-film transistor.

29. The display device according to claim 26, wherein at least one of the plurality of drive circuit sections is a buffer circuit section including a buffer circuit.

30. The display device according to claim 26, wherein at least one of the plurality of drive circuit units includes a plurality of scanning control circuit units that control different scanning control signals.

31. The display device according to claim 26, wherein at least one of the plurality of drive circuit units includes a light emission control unit for controlling the light emission signal of the pixel.

32. The display device according to claim 20, wherein the pixel includes one or more display elements.

33. The display device according to claim 32, wherein the display element includes an organic light-emitting element.

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