Thin-film transistor substrate, method for manufacturing the same, and display device including the same

Abstract

A thin-film transistor substrate is provided in which a layer with a step is placed below the active layer, separating each active layer from one another. [Solution] A display device comprising a thin-film transistor substrate, the thin-film transistor substrate comprising a buffer layer disposed on a base substrate; and a plurality of thin-film transistors on the buffer layer, the plurality of thin-film transistors comprising a plurality of active layers and gate electrodes superimposed on at least a portion of each of the plurality of active layers, the buffer layer comprising alternately arranged flat regions and sloped regions, and the plurality of active layers being disposed in the flat regions while spaced apart from each other.

Description

Technical Field

[0001] The present invention relates to a display device, a thin film transistor substrate, a display device including such a thin film transistor substrate, and a method for manufacturing the same.

Background Art

[0002] Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is widely used as a switching element or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] Thin film transistors can be classified into amorphous silicon thin film transistors in which amorphous silicon is used as an active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as an active layer, and oxide semiconductor thin film transistors in which an oxide semiconductor is used as an active layer, based on the material constituting the active layer.

[0004] A GIP (Gate in panel) structure in which a gate driver is incorporated in a display panel in the form of a thin film transistor is applied to a display device. When a large number of thin film transistors are arranged in the gate driver to improve the performance of the display device, a method of forming thin film transistors by dividing an active layer is used.

[0005] Particularly, thin film transistors arranged at the output part in a stage of the gate driver are formed with a large width, and when manufactured under the same process conditions, there is a risk that the threshold voltage will shift in the negative direction. Therefore, in order to improve such a problem, a method of forming thin film transistors by dividing an active layer is adopted.

[0006] Recently, when dividing the active layer, ongoing research is being conducted to reduce the spacing between each active layer in order to decrease the area of ​​the bezel region, which corresponds to the outer casing of the display panel. [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One embodiment of the present invention aims to provide a thin-film transistor substrate in which a layer having a step is arranged below the active layer, thereby separating each active layer from one another.

[0008] One embodiment of the present invention aims to provide a thin-film transistor substrate in which the spacing between each active layer is minimized.

[0009] Another embodiment of the present invention aims to provide a display device in which the area of ​​the bezel region is reduced. [Means for solving the problem]

[0010] One embodiment of the present invention for achieving the above-mentioned technical problems provides a thin-film transistor substrate comprising a buffer layer disposed on a base substrate, and a plurality of thin-film transistors on the buffer layer, wherein the plurality of thin-film transistors include a plurality of active layers and gate electrodes superimposed on at least a portion of each of the plurality of active layers, the buffer layer includes alternately arranged flat regions and sloped regions, and the plurality of active layers are disposed in the flat regions while being spaced apart from each other.

[0011] The plurality of active layers may contain an oxide semiconductor material and have a crystalline structure.

[0012] The plurality of active layers are arranged side by side and spaced apart along a first direction, the flat region and the inclined region are each extended along a second direction perpendicular to the first direction, and the flat region and the inclined region may be arranged side by side along the first direction.

[0013] The buffer layer includes a first flat surface and a second flat surface located in the flat region, and an inclined surface located in the inclined region, and the plurality of active layers do not necessarily have to be located on the inclined surface.

[0014] The first flat surface, the inclined surface, and the second flat surface are connected along a first direction, the inclined surface is positioned between the first flat surface and the second flat surface, and the shortest distance between the first flat surface and the base substrate may be shorter than the shortest distance between the second flat surface and the base substrate.

[0015] The inclined surface may have a taper angle of 45° to 90°. According to one embodiment of the present invention, the taper angle may be 45° to 50°, 50° to 55°, 45° to 65°, 65° to 75°, or 75° to 90°.

[0016] The plurality of active layers can have a spacing of 0.5 μm or less on a plane.

[0017] The plurality of active layers include a lower active layer disposed on the first flat surface and an upper active layer disposed on the second flat surface, wherein the lower active layer and the upper active layer are arranged alternately along a first direction, and the shortest distance between the upper surface of the lower active layer and the base substrate may be shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

[0018] The gate electrode may extend along a first direction across the plurality of active layers and be positioned on the flat region and the inclined region.

[0019] The present invention further includes a gate insulating film disposed on the buffer layer, wherein the plurality of active layers in the flat region are disposed between the buffer layer and the gate insulating film, and the gate insulating film in the sloped region may be in contact with the buffer layer.

[0020] The buffer layer includes a trench, the inclined surfaces are arranged on both sides of the trench, and a first flat surface may be arranged between each of the inclined surfaces.

[0021] Another embodiment of the present invention provides a method for manufacturing a thin-film transistor substrate, comprising the steps of: forming a buffer layer on a base substrate; forming a photoresist pattern on the buffer layer; etching the buffer layer using the photoresist pattern as a mask to form alternately arranged flat regions and sloped regions; forming an active material layer on the buffer layer; annealing the active material layer; and wet etching and removing a portion of the active material layer located in the sloped regions.

[0022] The active material layer placed in the flat region can be crystallized by the annealing process described above.

[0023] The thickness of the active material layer located in the inclined region is 10% to 60% of the thickness of the active material layer located in the flat region, and the thickness of the active material layer can be measured in a direction perpendicular to the surface of the buffer layer.

[0024] The width of a single channel may be approximately 10 μm to 20 μm with respect to the first direction X. The thin-film transistor substrate may be 60 μm to 122.5 μm (120 + (0.5 × 5 μm)). The spacing between each active layer may be 0.5 μm or less. The length of a single channel may be 5 μm to 10 μm with respect to the second direction Y. For example, the length of a single active layer may be 18 μm to 23 μm with respect to the second direction Y. The thin-film transistor substrate may have a length of 18 μm to 23 μm.

[0025] Yet another embodiment of the present invention can provide a display device including a thin-film transistor substrate.

[0026] The thin film transistor substrate according to an embodiment of the present invention arranges a layer having a step below the active layer, and each active layer can be separated from each other.

[0027] The thin film transistor substrate according to another embodiment of the present invention can minimize the interval between each active layer.

[0028] The display device according to still another embodiment of the present invention can have a bezel region with a reduced area.

Brief Description of the Drawings

[0029] [Figure 1] It is a plan view of the thin film transistor substrate according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view taken along line I-I' of FIG. 1. <00001​​​​​​​​​​​​​​​​​​​​​​​​​​​​This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 6H] This is a process diagram showing the manufacturing process of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 7] This is a schematic diagram of a display device according to yet another embodiment of the present invention. [Figure 8] This is a schematic diagram of a display panel according to one embodiment of the present invention. [Figure 9] This is a block diagram schematically showing a stage according to one embodiment of the present invention. [Figure 10] This is a cross-sectional view taken along line III-III' in Figure 8. [Figure 11] This is an enlarged view of area B in Figure 10. [Modes for carrying out the invention]

[0030] The advantages and features of the present invention, and the methods for achieving them, will become clear with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, although these embodiments are provided to complete the disclosure of the present invention and to inform those who are ordinary skill in the art to which the invention pertains of the invention. The present invention is defined only by the scope of the claims.

[0031] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating each embodiment of the present invention are illustrative only, and the present invention is not limited to what is shown in the drawings. Components identical throughout the specification may be referred to by the same reference numerals. Furthermore, when describing the present invention, if a specific explanation of related prior art is deemed to obscure the gist of the invention, such detailed explanation will be omitted.

[0032] Wherever "includes," "possesses," etc., as used herein, other parts may be added unless the expression "only" is used. When a component is expressed singularly, it includes multiple components unless otherwise explicitly stated.

[0033] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0034] For example, when describing the positional relationship between two parts, such as "on top," "above," "below," or "next to," unless the expression "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0035] Spatially relative terms such as "down," "bottom," "up," and "top" can be used to easily describe the correlation between one element or component and other elements or components, as shown in the drawings. Spatially relative terms should be understood to include not only the directions shown in the drawings but also the different directions of elements during use or operation. For example, if an element shown in the drawing is turned over, an element described as "down" of another element may be placed "up" of the other element. Thus, the exemplary term "down" can include both down and up directions. Similarly, the exemplary term "up" can include both up and down directions.

[0036] When describing temporal relationships, for example, when describing temporal sequence using phrases like "after," "following," "next," or "before," unless expressions like "immediately" or "directly" are used, it can include cases that are not continuous.

[0037] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from others. Therefore, the first component referred to below may also be the second component within the technical concept of the present invention.

[0038] The term "at least one" must be understood to include all possible combinations of one or more related items. For example, "at least one of items 1, 2, and 3" could mean not just each of items 1, 2, or 3 individually, but all possible combinations of items that can be presented from two or more of items 1, 2, and 3.

[0039] The features of many embodiments of the present invention can be partially or entirely combined or combined with one another, enabling a variety of technically diverse interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or in conjunction with them.

[0040] When assigning reference numerals to each component in each drawing illustrating each embodiment of the present invention, the same component may, as far as possible, have the same reference numeral, even if it is shown in other drawings.

[0041] In each embodiment of the present invention, the source electrode and the drain electrode are distinguished only for the sake of explanation, and the source electrode and the drain electrode can be interchangeable. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Furthermore, the source electrode in one embodiment can become the drain electrode in another embodiment, and the drain electrode in one embodiment can become the source electrode in another embodiment.

[0042] In some embodiments of the present invention, for the sake of explanation, the source region and source electrode may be distinguished, and the drain region and drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0043] Figure 1 is a plan view of a thin-film transistor substrate 100 according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line I-I' in Figure 1. Figure 3 is a cross-sectional view taken along line II-II' in Figure 1. Figure 4 is an enlarged view showing area A in Figure 2 in detail. Figure 5 is an enlarged view of a thin-film transistor substrate according to another embodiment of the present invention.

[0044] A thin-film transistor substrate 100 according to one embodiment of the present invention includes a plurality of thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6.

[0045] Figure 1 shows a thin-film transistor substrate 100 containing six thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6. However, one embodiment of the present invention is not limited to this and may contain fewer than six thin-film transistors, or seven or more thin-film transistors.

[0046] In one embodiment of the present invention, the multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 are not driven individually, but rather the thin-film transistor substrate 100 is driven as a single transistor. That is, the multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 are driven simultaneously. Therefore, the thin-film transistor substrate 100 in one embodiment of the present invention can be named as a single thin-film transistor.

[0047] According to one embodiment of the present invention, a buffer layer 120 is arranged on a base substrate 110, and a plurality of thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 can be arranged on the buffer layer 120.

[0048] According to one embodiment of the present invention, a plurality of thin-film transistors TR1, TR2, TR3, TR4, TR5, TR6 include a plurality of active layers 130 and gate electrodes 150.

[0049] The components of the base substrate 110, buffer layer 120, and multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 will be described in detail below.

[0050] Glass or plastic can be used as the base substrate 110. As the plastic, a transparent plastic with flexible properties, such as polyimide, can be used. For example, referring to Figure 3, a third thin-film transistor TR3 can be placed on the base substrate 110.

[0051] A light-shielding layer (not shown) may be placed on the base substrate 110. The light-shielding layer (not shown) blocks light incident from the base substrate 110 and protects the multiple active layers 130. The light-shielding layer (not shown) may be omitted if other structures serve to block light.

[0052] According to one embodiment of the present invention, a buffer layer 120 can be placed on a base substrate 110.

[0053] The buffer layer 120 is insulating and protects the multiple active layers 130. The buffer layer 120 may contain at least one of the insulating materials silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0054] Figures 2 and 3 show the buffer layer 120 as a single layer, but one embodiment of the present invention is not limited to this, and may consist of multiple layers. Furthermore, other layers may be arranged between the base substrate 110 and the buffer layer 120, and even more layers may be arranged between the buffer layer 120 and the multiple active layers 130.

[0055] According to one embodiment of the present invention, the buffer layer 120 includes alternately arranged flat regions P1, P2, P3, P4, P5 and inclined regions T1, T2, T3, T4.

[0056] The flat regions P1, P2, P3, P4, and P5 include the first flat region P1, the second flat region P2, the third flat region P3, the fourth flat region P4, and the fifth flat region P5, and the inclined regions T1, T2, T3, and T4 may include the first inclined region T1, the second inclined region T2, the third inclined region T3, and the fourth inclined region T4.

[0057] Figure 2 shows a state including flat regions P1, P2, P3, P4, P5 and inclined regions T1, T2, T3, T4 in which buffer layers 120 are alternately arranged. Although Figure 2 shows five flat regions P1, P2, P3, P4, P5, one embodiment of the present invention is not limited thereto, and there may be six or more, or fewer than five. Similarly, although Figure 2 shows four inclined regions T1, T2, T3, T4, one embodiment of the present invention is not limited thereto, and there may be five or more, or fewer than four.

[0058] According to one embodiment of the present invention, a plurality of active layers 130 are arranged on a buffer layer 120. For example, the plurality of active layers 130 may be arranged in flat regions P1, P2, P3, and P4 while being spaced apart from each other.

[0059] According to one embodiment of the present invention, the multiple active layers 130 include an oxide semiconductor material.

[0060] The oxide semiconductor material may include, for example, at least one of the following: IZO (InZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, ITO (InSnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, and FIZO (FeInZnO)-based oxide semiconductor material. However, one embodiment of the present invention is not limited thereto, and the active layer 130 may be made from other oxide semiconductor materials known in the art.

[0061] The multiple active layers 130 may include a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, a fifth active layer 135, and a sixth active layer 136. However, one embodiment of the present invention is not limited thereto and may include fewer than six active layers, or seven or more active layers.

[0062] For example, Figure 2 shows a configuration in which, among multiple active layers 130, the first active layer 131 is located in the first flat region P1, the second active layer 132 is located in the second flat region P2, the third active layer 133 is located in the third flat region P3, the fourth active layer 134 is located in the fourth flat region P4, and the fifth active layer 135 is located in the fifth flat region P5. In this configuration, the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, and the fifth active layer 135 are spaced apart from each other.

[0063] According to one embodiment of the present invention, when the direction connecting the source electrode 161 and the drain electrode 162 by the shortest distance is defined as the second direction Y, the direction perpendicular to the second direction Y can be defined as the first direction X.

[0064] According to one embodiment of the present invention, the multiple active layers 130 are arranged side by side and spaced apart along a first direction X. According to one embodiment of the present invention, the multiple active layers 130 are arranged extending along a second direction Y.

[0065] For example, Figure 1 shows a state in which the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, the fifth active layer 135, and the sixth active layer 136 are arranged side by side and spaced apart along the first direction X. For example, Figure 1 also shows a state in which the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, the fifth active layer 135, and the sixth active layer 136 are arranged extended along the second direction Y.

[0066] According to one embodiment of the present invention, the flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120 are each extended and arranged along the second direction Y.

[0067] For example, referring to Figures 1 and 3, the third flat region P3 of the buffer layer may be extended along the second direction Y.

[0068] According to one embodiment of the present invention, the flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120 may be arranged side by side along the first direction X.

[0069] For example, referring to Figures 1 and 2, the flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120 may be arranged side by side along the first direction X. Also, one of the flat regions P1, P2, P3, P4, P5 may be placed between the other two inclined regions T1, T2, T3, T4. Also, one of the inclined regions T1, T2, T3, T4 may be placed between the other two flat regions P1, P2, P3, P4, P5.

[0070] According to one embodiment of the present invention, the buffer layer 120 includes a first flat surface TS1 and a second flat surface TS2 located in the flat regions P1, P2, P3, P4, and P5, and may include an inclined surface SS located in the inclined regions T1, T2, T3, and T4.

[0071] Figure 4 shows a state in which the buffer layer 120 includes a first flat surface TS1, a second flat surface TS2, and an inclined surface SS.

[0072] According to one embodiment of the present invention, a flat surface may mean a surface in the buffer layer 120 that is parallel to the upper surface of the base substrate 110. An inclined surface may mean a surface in the buffer layer 120 that has a certain angle with respect to the upper surface of the base substrate 110.

[0073] According to one embodiment of the present invention, the shortest distance between the first flat surface TS1 and the base substrate 110 may be shorter than the shortest distance between the second flat surface TS2 and the base substrate 110. For example, the first flat surface TS1 is positioned closer to the base substrate 110 than the second flat surface TS2.

[0074] According to one embodiment of the present invention, multiple active layers 130 are arranged on the first flat surface TS1 and the second flat surface TS2, but not on the inclined surface SS (see Figure 4).

[0075] According to one embodiment of the present invention, a plurality of active layers 130 may be arranged on a first flat surface TS1 and a second flat surface TS2. The plurality of active layers 130 may include regions a1 and a2 remaining at the end of the inclined surface SS (see Figure 5). The thickness of the regions a1 and a2 remaining at the end of the inclined surface SS may be less than the thickness of the plurality of active layers 130 arranged on the first flat surface TS1 and the second flat surface TS2.

[0076] Since the regions a1 and a2 remaining at the end of the inclined surface SS are arranged along the inclined surface SS, the regions a1 and a2 remaining at the end of the inclined surface SS may be extended and arranged along the second direction Y. The regions a1 and a2 remaining at the end of the inclined surface SS may include region a1 remaining at the lower end of the inclined surface SS and region a2 remaining at the upper end of the inclined surface SS.

[0077] According to one embodiment of the present invention, the first flat surface TS1, the inclined surface SS, and the second flat surface TS2 are connected along the first direction X.

[0078] Figures 2 and 4 show a state in which the first flat surface TS1, the inclined surface SS, and the second flat surface TS2 are sequentially connected along the first direction X.

[0079] According to one embodiment of the present invention, the inclined surface SS is positioned between the first flat surface TS1 and the second flat surface TS2. Figure 4 shows a state in which the first flat surface TS1 is positioned on one side of the inclined surface SS, and the second flat surface TS2 is positioned on the other side of the inclined surface SS.

[0080] According to one embodiment of the present invention, when an active material layer 130m is formed in the flat regions P1, P2, P3, P4, P5 and the gradient regions T1, T2, T3, T4 of the buffer layer 120, in the gradient regions T1, T2, T3, T4, the active material layer 130m is formed with a thin thickness due to the taper angle of the buffer layer 120 (see Figure 6c). On the other hand, the flat regions P1, P2, P3, P4, P5 are flat with respect to the base substrate 110, and in the flat regions P1, P2, P3, P4, P5, the active material layer 130m is formed thicker than in the gradient regions T1, T2, T3, T4.

[0081] For example, the thickness of the 130m active material layer in gradient regions T1, T2, T3, and T4 may be 10% to 60% of the thickness of the 130m active material layer in flat regions P1, P2, P3, P4, and P5.

[0082] For example, if the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, and P5 is 30nm, the thickness of the active material layer 130m in the gradient regions T1, T2, T3, and T4 may be between 3nm and 18nm. In this case, the thickness of the active material layer 130m is measured in a direction perpendicular to the surface of the buffer layer 120.

[0083] Subsequently, when the active material layer 130m is subjected to annealing treatment, the active material layer 130m formed in the flat regions P1, P2, P3, P4, and P5 has sufficient thickness for crystallization to occur, and therefore can have a crystalline structure.

[0084] On the other hand, the active material layer 130m formed in the gradient regions T1, T2, T3, and T4 does not have sufficient thickness for crystallization to occur, and therefore can have an amorphous structure, and can have both a crystalline structure and an amorphous structure simultaneously.

[0085] According to one embodiment of the present invention, a layer is said to have a crystalline structure if, in the cross-section of any layer, the sum of the areas of regions with a grain size of 1 nm or more accounts for 50% or more of the total cross-sectional area. For example, using the total cross-sectional area of ​​an active material layer 130 m formed in a first flat region P1, the sum of the areas of regions with a grain size of 1 nm or more may be 50% or more, preferably 80% or more. For example, using the total cross-sectional area of ​​an active material layer 130 m formed in a first gradient region T1, the sum of the areas of regions with a grain size of 1 nm or more may be less than 50%. Specifically, the grain size is measured based on a transmission electron microscope (TEM) image of the cross-section of the layer to be measured.

[0086] Subsequently, when wet etching is performed on the active material layer 130m, the active material layer 130m having an amorphous structure can be removed. Nevertheless, the active material layer 130m without an amorphous structure may not be removed because it has strong resistance to wet etching.

[0087] In this case, if the active material layer 130m having an amorphous structure is completely removed, it is not necessary for multiple active layers 130 to be arranged on the inclined surface SS, as shown in Figure 4. However, if the active material layer 130m having an amorphous structure is not completely removed by wet etching, or if the active material layer 130m having both a crystalline and amorphous structure is removed by wet etching, some of the multiple active layers 130 may remain at the end of the inclined surface SS.

[0088] As a result, multiple active layers 130 having a crystalline structure can be formed in the flat regions P1, P2, P3, P4, and P5 of the buffer layer 120, separated from each other.

[0089] If the thickness of the active material layer (130m) in gradient regions T1, T2, T3, and T4 is excessively high, crystallization may occur in these regions during annealing, and even if wet etching is performed, the crystallized material may not be removed by wet etching.

[0090] Furthermore, if the thickness of the 130m active material layer in the gradient regions T1, T2, T3, and T4 is excessively low, the thickness of the 130m active material layer in the flat regions P1, P2, P3, P4, and P5 will also be low, and crystallization may not occur during the annealing process.

[0091] According to one embodiment of the present invention, the inclined surface SS of the buffer layer 120 can have a taper angle of 45° to 90°.

[0092] If the taper angle of the inclined surface SS is less than 45°, the difference between the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, and P5 and the thickness of the active material layer 130m in the inclined regions T1, T2, T3, and T4 decreases, which may make it difficult to completely separate the multiple active layers 130.

[0093] Furthermore, if the taper angle of the inclined surface SS exceeds 90°, it may be difficult to actually achieve a taper angle of 90° or more on the inclined surface SS.

[0094] Therefore, in order to separate the multiple active layers 130, the inclined surface SS of the buffer layer 120 needs to have a taper angle of 45° to 90°.

[0095] According to one embodiment of the present invention, the multiple active layers 130 can have a spacing of 0.5 μm or less on a plane.

[0096] Referring to Figure 4, the multiple active layers 130 can have a spacing W of 0.5 μm or less.

[0097] Figures 2 and 4 show that the second active layer 132 and the third active layer 133 of the multiple active layers 130 can have a spacing W of 0.5 μm or less.

[0098] According to one embodiment of the present invention, the multiple active layers 130 may include lower active layers 132, 134 arranged on a first flat surface TS1, and upper active layers 131, 133, 135 arranged on a second flat surface TS2. For example, the lower active layers 132, 134 may include a second active layer 132 and a fourth active layer 134, and the upper active layers 131, 133, 135 may include a first active layer 131, a third active layer 133, and a fifth active layer 135.

[0099] According to one embodiment of the present invention, the shortest distance between the upper surfaces of the lower active layers 132 and 134 and the base substrate 110 may be shorter than the shortest distance between the upper surfaces of the upper active layers 131, 133, and 135 and the base substrate 110. For example, Figure 2 shows a state in which the lower active layers 132 and 134 are positioned closer to the base substrate 110 than the upper active layers 131, 133, and 135.

[0100] Referring to Figures 2 and 4, the lower active layers 132 and 134 are located on the first flat surface TS1, and the upper active layers 131, 133, and 135 are located on the second flat surface TS2. For example, the lower active layers 132 and 134 are located on the second flat region P2 and the fourth flat region P4, and the upper active layers 131, 133, and 135 are located on the first flat region P1, the third flat region P3, and the fifth flat region P5.

[0101] According to one embodiment of the present invention, the lower active layers 132, 134 and the upper active layers 131, 133, 135 can be arranged alternately along the first direction X. For example, Figure 2 shows a state in which the lower active layers 132, 134 and the upper active layers 131, 133, 135 are arranged alternately. For example, the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, and the fifth active layer 135 can be arranged sequentially along the first direction X.

[0102] According to one embodiment of the present invention, the buffer layer 120 may include trenches 126. According to one embodiment of the present invention, the trenches 126 may represent regions in which the buffer layer 120 has been etched.

[0103] Referring to Figures 2 and 4, inclined surfaces SS may be arranged on both sides of the trench 126, and a first flat surface TS1 may be arranged between the inclined surfaces SS on both sides.

[0104] According to one embodiment of the present invention, a gate insulating film 140 is arranged on a plurality of active layers 130. Specifically, the gate insulating film 140 is arranged between the plurality of active layers 130 and the gate electrode 150.

[0105] According to one embodiment of the present invention, the gate insulating film 140 can cover the entire upper surface of multiple active layers 130. Figures 2 and 3 show a state in which the gate insulating film 140 covers the entire upper surface of multiple active layers 130. However, one embodiment of the present invention is not limited thereto, and the gate insulating film 140 may expose a portion of the multiple active layers 130.

[0106] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-film structure or a multilayer structure. The gate insulating film 140 protects multiple active layers 130.

[0107] According to one embodiment of the present invention, multiple active layers 130 are arranged between the buffer layer 120 and the gate insulating film 140 in flat regions P1, P2, P3, P4, and P5. For example, multiple active layers 130 in regions overlapping with flat regions P1, P2, P3, P4, and P5 are arranged between the buffer layer 120 and the gate insulating film 140. For example, referring to Figure 2, a third active layer 133 may be arranged between the buffer layer 120 and the gate insulating film 140 in a region overlapping with the third flat region P3.

[0108] According to one embodiment of the present invention, the gate insulating film 140 in the gradient regions T1, T2, T3, and T4 may come into contact with the buffer layer 120. For example, the gate insulating film 140 in the region overlapping with the gradient regions T1, T2, T3, and T4 may come into contact with the buffer layer 120. For example, referring to Figure 2, the gate insulating film 140 in the region overlapping with the second gradient region T2 may come into contact with the buffer layer 120.

[0109] According to one embodiment of the present invention, a gate electrode 150 can be arranged on a gate insulating film 140.

[0110] Referring to Figures 1, 2, and 3, the gate electrode 150 can be superimposed on at least a portion of each of the multiple active layers 130. For example, referring to Figure 1, the gate electrode 150 can be superimposed on a portion of each of the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, the fifth active layer 135, and the sixth active layer 136. Each of the multiple active layers 130 may have a channel portion that is superimposed on the gate electrode 150.

[0111] The gate electrode 150 may include at least one of the following: aluminum (Al) or aluminum alloys (aluminum series metals), silver (Ag) or silver alloys (silver series metals), copper (Cu) or copper alloys (copper series metals), molybdenum (Mo) or molybdenum alloys (molybdenum series metals), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may also have a multilayer structure comprising at least two conductive films with different physical properties.

[0112] According to one embodiment of the present invention, the gate electrode 150 may extend along a first direction X across a plurality of active layers 130.

[0113] Figure 1 shows a state in which the gate electrode 150 extends along the first direction X across the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, the fifth active layer 135, and the sixth active layer 136. For example, the gate electrode 150 may be positioned on the flat regions P1, P2, P3, P4, P5 and the sloped regions T1, T2, T3, T4 of the buffer layer 120.

[0114] An interlayer insulating film 160 is placed on the gate electrode 150. The interlayer insulating film 160 is an insulating layer made of an insulating material. Specifically, the interlayer insulating film 160 may be made of organic material, inorganic material, or a laminate of an organic layer and an inorganic layer.

[0115] A source electrode 171 and a drain electrode 172 are arranged on an interlayer insulating film 160. The source electrode 171 and the drain electrode 172 are connected to a plurality of active layers 130, each while being spaced apart from each other. The source electrode 171 and the drain electrode 172 are connected to a plurality of active layers 130, each via contact holes formed in the interlayer insulating film 160. According to one embodiment of the present invention, the source electrode 171 and the drain electrode 172 may be formed integrally.

[0116] The source electrode 171 and the drain electrode 172 may each contain at least one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrode 171 and the drain electrode 172 may each consist of a single layer of metal or a metal alloy, or a multilayer of two or more layers.

[0117] Figures 6A to 6H are manufacturing process diagrams for a thin-film transistor substrate 100 according to yet another embodiment of the present invention. Details regarding the configuration already described above are omitted.

[0118] The cross-sectional views shown in Figures 6A to 6H correspond to the cross-sectional view shown in Figure 2.

[0119] Referring to Figure 6A, a buffer layer 120 can be formed on the base substrate 110, and a photoresist pattern 125 can be formed on the buffer layer 120. For example, the photoresist pattern 125 is arranged superimposed on a portion of the buffer layer 120.

[0120] Referring to Figure 6B, the buffer layer 120 can be etched using the photoresist pattern 125 as a mask to form a trench 126. Specifically, the buffer layer 120 can be etched to form alternately arranged flat regions P1, P2, P3, P4, P5 and gradient regions T1, T2, T3, T4. More specifically, after etching the buffer layer 120, the photoresist pattern 125 placed on the buffer layer 120 can be removed.

[0121] According to one embodiment of the present invention, the buffer layer 120 can have a taper angle of 45° to 90° in the inclined regions T1, T2, T3, and T4.

[0122] Referring to Figure 6C, an active material layer 130m can be formed on the buffer layer 120. The active material layer 130m may include an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of the following: IZO(InZnO)-based oxide semiconductor material, IGO(InGaO)-based oxide semiconductor material, ITO(InSnO)-based oxide semiconductor material, IGZO(InGaZnO)-based oxide semiconductor material, IGZTO(InGaZnSnO)-based oxide semiconductor material, GZTO(GaZnSnO)-based oxide semiconductor material, GZO(GaZnO)-based oxide semiconductor material, ITZO(InSnZnO)-based oxide semiconductor material, and FIZO(FeInZnO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited thereto, and the active material layer 130m may be made from other oxide semiconductor materials known in the art.

[0123] According to one embodiment of the present invention, the thickness L2 of the active material layer 130m located in the inclined regions T1, T2, T3, and T4 may be 10% to 60% of the thickness L1 of the active material layer 130m located in the flat regions P1, P2, P3, P4, and P5. The thickness of the active material layer 130m is measured in a direction perpendicular to the surface of the buffer layer 120.

[0124] Referring to Figure 6D, the active material layer 130m can be subjected to annealing treatment. When annealing treatment is performed on the active material layer 130m, the active material layer 130m formed in the flat regions P1, P2, P3, P4, and P5 has sufficient thickness for crystallization to occur and can therefore have a crystalline structure. On the other hand, the active material layer 130m formed in the gradient regions T1, T2, T3, and T4 does not have sufficient thickness for crystallization to occur and can therefore have an amorphous structure, thus allowing for the simultaneous presence of both crystalline and amorphous structures.

[0125] For example, the annealing process may be carried out at a temperature of 350°C to 450°C. However, one embodiment of the present invention is not limited to this and may be carried out at a temperature different from 350°C to 450°C.

[0126] Referring to Figure 6E, a portion of the active material layer 130m can be removed through wet etching.

[0127] For example, active material layers 130m located in gradient regions T1, T2, T3, and T4, where crystallization has not occurred, can be selectively removed by wet etching.

[0128] According to one embodiment of the present invention, a plurality of active layers 130 separated from each other can be formed by wet etching. For example, a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, and a fifth active layer 135 separated from each other can be formed.

[0129] According to one embodiment of the present invention, a separate mask is not required during the wet etching process. Specifically, even if wet etching is performed on the entire active material layer 130m, the active material layer 130m having a crystalline structure has strong resistance to the etching solution and may not be selectively removed.

[0130] Referring to Figure 6F, a gate insulating film 140 can be formed on the buffer layer 120 and the multiple active layers 130. The explanation of the gate insulating film 140 is omitted as it overlaps with the content described above.

[0131] Referring to Figure 6G, a gate electrode 150 can be formed on the gate insulating film 140. The explanation of the gate electrode 150 is omitted as it overlaps with the above description.

[0132] Referring to Figure 6H, an interlayer insulating film 160 can be formed on the gate electrode 150. The explanation of the interlayer insulating film 160 is omitted as it overlaps with the content described above.

[0133] Figure 7 is a schematic diagram of a display device 1000 according to yet another embodiment of the present invention.

[0134] A display device 1000 according to yet another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340, as shown in Figure 7.

[0135] The display panel 310 includes each gate line GL and each data line DL, and pixels P are arranged in the intersection region of each gate line GL and each data line DL. An image is displayed by driving the pixels P. Each gate line GL, each data line DL and each pixel P may be arranged on the base substrate 110.

[0136] The control unit 340 controls the gate driver 320 and the data driver 330.

[0137] The control unit 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330, using signals supplied from an external system (not shown). The control unit 340 also samples the input video data received from the external system, rearranges it, and supplies the rearranged digital video data RGB to the data driver 330.

[0138] The gate control signal GCS includes the gate start pulse GSP, gate shift clock GSC, gate output enable signal GOE, start signal Vst, and gate clock GCLK. The gate control signal GCS may also include various control signals for controlling the shift register.

[0139] The data control signal DCS includes the source start pulse SSP, source shift clock signal SSC, source output enable signal SOE, polarity control signal POL, and others.

[0140] The data driver 330 supplies data voltage to each data line DL of the display panel 310. Specifically, the data driver 330 converts the video data RGB input from the control unit 340 into analog data voltage and supplies the data voltage to each data line DL.

[0141] According to one embodiment of the present invention, the gate driver 320 can be mounted on the display panel 310. This structure, in which the gate driver 320 is directly mounted on the display panel 310, is called a Gate In Panel (GIP) structure. Specifically, in a Gate In Panel (GIP) structure, the gate driver 320 can be placed on a base substrate 110.

[0142] A display device 1000 according to one embodiment of the present invention may include the thin-film transistor substrate 100 described above. According to one embodiment of the present invention, the gate driver 320 may include the thin-film transistor substrate 100 described above.

[0143] The gate driver 320 may include a shift register 350.

[0144] The shift register 350 sequentially supplies gate pulses to each gate line GL during one frame using a start signal and gate clock transferred from the control unit 340. Here, one frame refers to the period during which one image is output through the display panel 310. The gate pulses have a turn-on voltage that can turn on the switching element (thin-film transistor) placed on the pixel P.

[0145] Furthermore, the shift register 350 supplies a gate-off signal to the gate line GL during the remaining period of a frame when no gate pulse is supplied, which can turn off the switching element. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as the scan signal (SS or Scan).

[0146] The shift register 350 may include the thin-film transistor substrate 100 described above.

[0147] Referring to Figure 7, the shift register 350 according to one embodiment of the present invention may include a plurality of stages ST.

[0148] Figure 8 is a schematic diagram of a display panel 310 according to one embodiment of the present invention.

[0149] The display panel 310 may include a display area AA and a non-display area IA.

[0150] Multiple pixels P for displaying an image may be arranged on the display area AA. An image does not necessarily have to be displayed in the non-display area IA. The non-display area IA may be configured to surround the display area AA. A gate driver 320 may be located in the non-display area IA.

[0151] Figure 9 is a schematic block diagram showing stage ST according to one embodiment of the present invention.

[0152] Referring to Figure 9, the stage ST includes a node control unit 105 that controls the voltages of the first and second nodes Q and Qb in response to the carry signal CR and the reset signal RST, and an output unit 200 that outputs the clock signal CLK input by the voltage levels of the first and second nodes Q and Qb as the scan pulse and the auxiliary scan pulse. At this time, the scan pulse is output via the first output terminal OUT1 of the stage ST, and the auxiliary scan pulse is output via the second output terminal OUT2 of the stage ST.

[0153] Stage ST can receive inputs of gate-on voltage VGH, first gate-off voltage VGL1, and second gate-off voltage VGL2.

[0154] Figure 10 is a cross-sectional view taken along line III-III' in Figure 8. Figure 11 is an enlarged view of area B in Figure 10.

[0155] Referring to Figure 10, the first thin-film transistor T1, the second thin-film transistor T2, and the display element 710 are arranged in the display area AA, and the third thin-film transistor T3 and the fourth thin-film transistor T4 are arranged in the non-display area IA. The first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4 are arranged on the base substrate 110.

[0156] Specifically, the gate driver 320 located in the non-display area IA may include a third thin-film transistor T3 and a fourth thin-film transistor T4.

[0157] The explanation for the base board 110 is omitted as it would be redundant.

[0158] A first buffer layer 111 and a second buffer layer 112 may be arranged on the base substrate 110.

[0159] The first buffer layer 111 and the second buffer layer 112 are made of insulating material and protect the active layers A1, A2, A3, and A4 of the thin-film transistors T1, T2, T3, and T4 from moisture and oxygen flowing in from the outside. The second buffer layer 112 is extended from the non-display area IA to the display area AA.

[0160] According to one embodiment of the present invention, the second buffer layer 112 may include a trench TCH. The trench TCH may have a first taper angle θ1. The first taper angle θ1 of the trench TCH may be smaller than the second taper angle θ2 of the second intermediate buffer layer 138, which will be described later. There may be multiple trench TCHs. For example, the first taper angle θ1 of the trench TCH may be 5° smaller than the second taper angle θ2 of the second intermediate buffer layer 138. For example, the first taper angle θ1 of the trench TCH may be 0° to 10° smaller than the second taper angle θ2 of the second intermediate buffer layer 138. For example, the first taper angle θ1 of the trench TCH may be 10° to 20° smaller than the second taper angle θ2 of the second intermediate buffer layer 138.

[0161] According to one embodiment of the present invention, the trench TCH of the second buffer layer 112 may be superimposed on the third thin-film transistor T3. The trench TCH of the second buffer layer 112 does not have to be located in the display area AA. Also, the trench TCH of the second buffer layer 112 does not have to be superimposed on the fourth thin-film transistor T4. Specifically, the trench TCH of the second buffer layer 112 does not have to be superimposed on the fourth active layer A4 of the fourth thin-film transistor T4. At least a portion of the trench TCH of the second buffer layer 112 may be superimposed on the third active layer A3 of the third thin-film transistor T3.

[0162] According to one embodiment of the present invention, the second buffer layer 112 may correspond to the buffer layer 120 shown in Figure 1. Therefore, a description of the second buffer layer 112 is omitted.

[0163] The fourth active layer A4 of the fourth thin-film transistor T4 is placed on the second buffer layer 112. The fourth active layer A4 may include a fourth channel portion CN4 superimposed on the fourth gate electrode G4 of the fourth thin-film transistor T4.

[0164] A bottom shield metal (BSM) may be placed below the fourth thin-film transistor T4. The bottom shield metal (BSM) may be placed on the first buffer layer 111.

[0165] A first lower interlayer insulating film 121 may be placed on the second buffer layer 112. The first lower interlayer insulating film 121 is insulating.

[0166] Referring to Figure 10, a first capacitor electrode CE1, a first light-shielding layer LS1, a third light-shielding layer LS3, and a fourth gate electrode G4 may be arranged on the first lower interlayer insulating film 121. The first capacitor electrode CE1, the first light-shielding layer LS1, the third light-shielding layer LS3, and the fourth gate electrode G4 may be arranged on the same layer and made of the same material.

[0167] A second lower interlayer insulating film 122 is placed on the first capacitor electrode CE1, the first light-shielding layer LS1, the third light-shielding layer LS3, and the fourth gate electrode G4, and a second capacitor electrode CE2 may be placed on the second lower interlayer insulating film 122. The first capacitor electrode CE1 and the second capacitor electrode CE2 are superimposed to form the first capacitor C1.

[0168] According to one embodiment of the present invention, the fourth gate electrode G4 of the fourth thin-film transistor T4 can be formed integrally with the third light-shielding layer LS3 of the third thin-film transistor T3.

[0169] A first intermediate buffer layer 137 may be placed on the second capacitor electrode CE2, and a second light-shielding layer LS2 may be placed on the first intermediate buffer layer 137.

[0170] Referring to Figure 10, a second intermediate buffer layer 138 can be placed on the second light-shielding layer LS2.

[0171] Active layers A1, A2, and A3 are arranged on the second intermediate buffer layer 138. The active layers A1, A2, and A3 may include the first active layer A1 of the first thin-film transistor T1, the second active layer A2 of the second thin-film transistor T2, and the third active layer A3 of the third thin-film transistor T3.

[0172] The active layers A1, A2, and A3 may include, for example, oxide semiconductor materials. The active layers A1, A2, and A3 may be oxide semiconductor layers made of oxide semiconductor materials. Specifically, the third active layer A3 may have a crystalline structure.

[0173] According to one embodiment of the present invention, after a third active layer A3 is formed from an amorphous oxide semiconductor material, the third active layer A3 is crystallized by an annealing process, and a third active layer A3 having a crystalline structure can be formed through wet etching.

[0174] The fourth active layer A4 may include a low-temperature polycrystalline silicon (LTPS) semiconductor material. However, the present invention is not limited thereto.

[0175] The active layers A1, A2, and A4 may each have channel sections CN1, CN2, and CN4, respectively.

[0176] Referring to Figures 10 and 11, the third active layer A3 can include multiple sub-active layers A31, A32, A33, A34, A35, A36, and A37. The third active layer A3 shown in Figures 10 and 11 corresponds to the active layer 130 shown in Figure 1, and the multiple sub-active layers A31, A32, A33, A34, A35, and A36 correspond to the multiple active layers 131, 132, 133, 134, 135, and 136 shown in Figure 1.

[0177] A gate insulating film 140 is placed on the active layers A1, A2, and A3. The gate insulating film 140 has insulating properties and separates the active layers A1, A2, and A3 from the gate electrodes G1, G2, and G3. The gate insulating film 140 can cover the entire upper surface of the active layers A1, A2, and A3.

[0178] Gate gates G1, G2, and G3 are placed on the gate insulating film 140. An interlayer insulating film 160 is placed on the gate gates G1, G2, and G3.

[0179] Source electrodes S1, S2, S4 and drain electrodes D1, D2, D4 are arranged on the interlayer insulating film 160.

[0180] The first gate electrode G1 can be connected to the first light-shielding layer LS1 via a connecting electrode. As a result, the same voltage as that applied to the first gate electrode G1 can be applied to the first light-shielding layer LS1. Therefore, the first thin-film transistor T1 shown in Figure 10 can be said to have a double-gate structure.

[0181] The first thin-film transistor T1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first thin-film transistor T1 can also function as a switching transistor that controls the data voltage Vdata applied to the pixel drive unit.

[0182] The second thin-film transistor T2 may include a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second thin-film transistor T2 acts as a drive transistor that controls the drive voltage applied to the display element 710.

[0183] A passivation layer 170 is placed on the source electrodes S1, S2, S4 and the drain electrodes D1, D2, D4, and a first planarization layer 180 is placed on the passivation layer 170. The first planarization layer 180 planarizes the tops of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4.

[0184] A connecting electrode 185 may be placed on the first planarization layer 180. The connecting electrode 185 can serve to connect the second source electrode S2 and the pixel electrode 711.

[0185] A second flattening layer 190 is placed on the first flattening layer 180 and the connecting electrode 185. The upper surface of the pixel driving unit is flattened by the second flattening layer 190.

[0186] The pixel electrodes 711 of the display element 710 are placed on the second planarization layer 190. A bank layer 730 is placed around the edge of the pixel electrodes 711. The bank layer 730 defines the light-emitting region of the display element 710.

[0187] An organic light-emitting layer 712 is placed on the pixel electrode 711, and a common electrode 713 is placed on the organic light-emitting layer 712.

[0188] The common electrode 713 is placed on the organic light-emitting layer 712, and the common electrode 713 may also be placed on the bank layer 730.

[0189] A display element 710 is formed by a pixel electrode 711, an organic light-emitting layer 712, and a common electrode 713. The display element 710 shown in Figure 10 is an organic light-emitting diode (OLED). Therefore, the display device 1000 according to one embodiment of the present invention is an organic light-emitting display device.

[0190] A capping layer may be placed on the common electrode 713. The capping layer protects the display element 710. The capping layer may be insulating.

[0191] Referring to Figure 10, the first sealing layer 751 is placed on the common electrode 713. The first sealing layer 751 can protect the upper part of the display element 710.

[0192] A second sealing layer 752 is placed on the first sealing layer 751. The second sealing layer 752 can also be called a particle cover layer (PCL).

[0193] The second sealing layer 752 prevents unevenness from occurring on the surface of the display device 1000 due to particles generated during the manufacturing process of the display device 1000.

[0194] A third sealing layer 753 may be placed on the second sealing layer 752. The third sealing layer 753 may consist of an inorganic film with a densely formed thin film. The third sealing layer 753 prevents or inhibits the penetration of moisture or oxygen.

[0195] According to one embodiment of the present invention, the first sealing layer 751, the second sealing layer 752, and the third sealing layer 753 can also be referred to as the sealing portion.

[0196] The present invention, as described above, is not limited by the embodiments and accompanying drawings, and it will be obvious to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the present invention. Therefore, the scope of the present invention is indicated by the claims described below, and all modified or altered forms derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention. [Explanation of Symbols]

[0197] 110 Base board 120 buffer layers 125 Photoresist Patterns 126 Trench 130 Multiple active tiers 131, 132, 133, 134, 135, 136 Active layers 1, 2, 3, 4, 5 and 6 P1, P2, P3, P4, P5 1st, 2nd, 3rd, 4th and 5th flat area T1, T2, T3, T4: First, second, third, and fourth inclined regions SS slope TS1, TS2 First and second flat surfaces 140 Gate Insulator 150 Guard signals 160 Interlayer insulating film 171 Source electrode 172 Drain electrode

Claims

1. A display device including a thin-film transistor substrate, wherein the thin-film transistor substrate is A buffer layer placed on the base substrate, and The buffer layer includes a plurality of thin-film transistors, The plurality of thin-film transistors include a plurality of active layers and a gate electrode superimposed on at least a portion of each of the plurality of active layers. The buffer layer includes alternately arranged flat regions and inclined regions. A display device in which the plurality of active layers are spaced apart from each other and arranged in the flat region.

2. The display device according to claim 1, wherein the plurality of active layers are separated from each other by the inclined regions and arranged in the flat region.

3. The plurality of active layers are arranged spaced apart from each other along the first direction, The flat region and the inclined region are arranged to extend along a second direction perpendicular to the first direction. The display device according to claim 1, wherein the flat region and the inclined region are arranged parallel to each other along the first direction.

4. The display device according to claim 3, wherein the plurality of active layers are arranged to extend along the second direction.

5. The flat region includes a first flat surface and a second flat surface, Each of the aforementioned inclined regions includes an inclined surface, The aforementioned multiple active layers are not arranged on the inclined surface, Optionally, the buffer layer includes trenches. The inclined surfaces are arranged on both sides of the trench. The first flat surface is positioned between the inclined surfaces, The display device according to claim 1, wherein each inclined surface optionally has a taper angle of 45 to 90°.

6. The flat region includes a first flat surface and a second flat surface, Each of the aforementioned inclined regions includes an inclined surface, The display device according to claim 1, wherein the plurality of active layers include regions located at both ends of the inclined surface.

7. The plurality of active layers are arranged parallel to each other and spaced apart along the first direction. The flat region and the inclined region are each arranged to extend along a second direction perpendicular to the first direction. The display device according to claim 6, wherein the regions located at both ends are arranged to extend along the second direction.

8. The first flat surface, the inclined surface, and the second flat surface extend along the first direction, The inclined surface is positioned between the first flat surface and the second flat surface. The display device according to claim 5, wherein the shortest distance between the first flat surface and the base substrate is shorter than the shortest distance between the second flat surface and the base substrate.

9. The plurality of active layers include an oxide semiconductor material and have a crystalline structure. The display device according to claim 1, optionally wherein the plurality of active layers are spaced 0.5 μm or less apart on a plane.

10. The aforementioned multiple active layers are A lower active layer disposed on the first flat surface, and Includes an upper active layer disposed on the second flat surface, The lower active layer and the upper active layer are arranged alternately along the first direction. The display device according to claim 6, wherein the shortest distance between the upper surface of the lower active layer and the base substrate is shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

11. The display device according to claim 1, wherein the gate electrode extends across the plurality of active layers along a first direction and is arranged on the flat region and the inclined region.

12. The buffer layer further includes a gate insulating film disposed on the buffer layer, In the aforementioned flat region, the plurality of active layers are arranged between the buffer layer and the gate insulating film. The display device according to claim 1, wherein the gate insulating film is in contact with the buffer layer in the inclined region.

13. The system further includes source electrodes and drain electrodes, each connected to the plurality of active layers and arranged at a distance from one another. The display device according to claim 1, wherein optionally, the source electrode is integrally formed and the drain electrode is integrally formed.

14. The display device according to claim 1, wherein the plurality of thin-film transistors are driven simultaneously.

15. Steps include forming a buffer layer on a base substrate, The step of forming a photoresist pattern on the buffer layer, The steps include etching the buffer layer using the aforementioned photoresist pattern as a mask to form alternately arranged flat regions and sloped regions, The step of forming an active material layer on the buffer layer, The steps of annealing the active material layer, A method for manufacturing a thin-film transistor substrate for a display device, comprising the step of wet etching and removing a portion of the active material layer disposed in the gradient region.

16. The active material layer disposed in the flat region is crystallized by the annealing step, Optionally, in the inclined region, the buffer layer has a taper angle of 45 to 90°. Optionally, the thickness of the active material layer located in the inclined region is 10% to 60% of the thickness of the active material layer located in the flat region. The manufacturing method according to claim 15, wherein the thickness of the active material layer is measured in a direction perpendicular to the surface of the buffer layer.

17. A display device, A display area, and a non-display area surrounding the display area, A first thin-film transistor disposed in the non-display region, comprising a first active layer having a plurality of sub-active layers separated from each other, and a first gate electrode superimposed on at least a portion of the first active layer, and The second thin-film transistor, disposed in the non-display region, includes a buffer layer disposed on a base substrate, a second active layer disposed on the buffer layer, and a second gate electrode superimposed on at least a portion of the second active layer, The buffer layer includes alternately arranged flat regions and inclined regions. A display device in which the plurality of subactive layers are separated from each other by the inclined regions and arranged in the flat regions.

18. The buffer layer extends from the non-display area to the display area, The buffer layer includes trenches, The display device according to claim 17, wherein at least a portion of the trench is superimposed on the first active layer of the first thin-film transistor.

19. The first thin-film transistor includes an intermediate buffer layer located below the first active layer. The first active layer is positioned on the upper surface of the intermediate buffer layer, The buffer layer has a first taper angle, The display device according to claim 17, wherein the intermediate buffer layer has a second taper angle greater than the first taper angle.

20. The trench is not located in the display area. Optionally, the trench does not overlap with the second active layer of the second thin-film transistor. Optionally, the second active layer includes a low-temperature polycrystalline silicon semiconductor material. Optionally, the first thin-film transistor includes a first light-shielding layer superimposed on the first active layer. The display device according to claim 18, wherein the first light-shielding layer is formed integrally with the second gate electrode.

Images