Method for manufacturing a circuit component with solder bumps and a circuit component with solder bumps

Abstract

To provide a method for manufacturing a circuit component with solder bumps and a circuit component with solder bumps that can ensure a sufficient manufacturing yield for the solder bump component. [Solution] This method for manufacturing a circuit member with solder bumps includes: a deposition step S02 in which a solder layer 11 is deposited in a region including the top surface 3a of a conductive pillar 3 on one surface of a substrate 2 on which a conductive pillar 3 is provided; a reduction step S03 in which the solder layer 11 is reduced in a reducing gas atmosphere to form a solder bump 4 on the top surface 3a of the pillar 3; a removal step S04 in which the excess solder layer 12 remaining on one surface of the substrate 2 after the reduction step is removed; and a re-reduction step S05 in which the solder bump 4 on the top surface 3a of the pillar 3 is re-reduced in a reducing gas atmosphere to form an alloy layer 6 at the interface between the pillar 3 and the solder bump 4, consisting of the constituent material of the pillar 3 and the constituent material of the solder bump 4.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a circuit member with solder bumps and a circuit member with solder bumps.

Background Art

[0002] As one method for mounting electronic components with high density, flip chip mounting is known. In flip chip mounting, for example, solder bumps are formed in advance on electrodes provided on one circuit member, and the electrodes of one circuit member and the electrodes of the other circuit member are joined by melting the solder bumps. Thereby, a connection structure between the circuit members is formed.

[0003] As a technique for forming solder bumps on electrodes, there is, for example, the solder bump forming method described in Patent Document 1. This conventional solder bump forming method includes a step of forming a resist pattern in a conductor groove on a substrate, a step of forming a barrier layer on the substrate using the resist pattern as a mask, a step of forming a solder layer on the substrate using the resist pattern as a mask, and a step of removing the resist pattern from the substrate, and is characterized in that the barrier layer is formed by using a vacuum evaporation method in an inert gas atmosphere.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, miniaturization and precision of electronic components have advanced, and miniaturization of circuit members used in electronic components has advanced. Along with the miniaturization of the circuit members, the electrode size is also advancing in miniaturization. For this reason, even when the electrode size is miniaturized, a technique that can sufficiently ensure the manufacturing yield is required.

[0006] This disclosure was made to solve the above-mentioned problems and aims to provide a method for manufacturing a circuit component with solder bumps and a circuit component with solder bumps that can ensure a sufficient manufacturing yield for the circuit component with solder bumps. [Means for solving the problem]

[0007] The gist of this disclosure is as follows:

[0008] [1] A method for manufacturing a circuit member with solder bumps, comprising: a deposition step of depositing a solder layer in a region including the top surface of a conductive pillar on one surface of a substrate provided with a conductive pillar; a reduction step of reducing the solder layer in a reducing gas atmosphere to form a solder bump on the top surface of the pillar; a removal step of removing the excess solder layer remaining on the surface of the substrate after the reduction step; and a re-reduction step of re-reducing the solder bump on the top surface of the pillar in a reducing gas atmosphere to form an alloy layer of the constituent material of the pillar and the constituent material of the solder bump at the interface between the pillar and the solder bump.

[0009] In this method for manufacturing circuit components with solder bumps, solder bumps are formed on the top surface of the pillar by reducing the solder layer, and then an alloy layer is formed at the interface between the pillar and the solder bump by re-reducing the solder bump. The formation of this alloy layer improves the adhesion between the pillar and the solder bump. Therefore, it is possible to suppress the delamination of the solder bump from the pillar during subsequent cleaning processes, and to ensure a sufficient manufacturing yield for circuit components with solder bumps.

[0010] [2] A method for manufacturing a solder bump circuit member according to [1], comprising a pretreatment step of subjecting the substrate on which the pillars are provided to plasma treatment before the deposition step. In this case, the plasma treatment can sufficiently reduce the wettability of the solder layer on one side of the substrate compared to the wettability of the solder layer on the pillars. As a result, the cohesiveness of the solder layer on one side of the substrate is increased in the reduction step, and the excess solder layer can be easily removed from one side of the substrate in the removal step.

[0011] [3] A method for manufacturing a circuit member with solder bumps according to [2], comprising a cleaning step of ultrasonically cleaning the substrate on which the solder bumps are formed using ultrapure water or methanol after the re-reduction step. This makes it possible to more reliably remove excess solder particles remaining on one surface of the substrate after the excess solder layer has been removed. Furthermore, as described above, the adhesion between the pillars and the solder bumps is improved by the alloy layer, so even when ultrasonic cleaning is performed using ultrapure water or methanol, it is possible to effectively suppress the delamination of the solder bumps from the pillars.

[0012] [4] A method for manufacturing a solder bump circuit member according to any one of [1] to [3], wherein the reduction step alternately creates a vacuum atmosphere and a reducing atmosphere. In this case, during the reduction step, the solder layer on one surface of the substrate can be separated into a solder portion that aggregates toward the pillar and a solder portion that aggregates without adhering toward the pillar. As a result, the shape of the excess solder layer after the reduction step becomes a mesh shape with openings around the pillar, and the excess solder layer can be easily removed from one surface of the substrate during the removal step.

[0013] [5] A method for manufacturing a solder bump circuit member according to any one of [1] to [4], wherein the reduction step is performed at a temperature of ±5°C from the melting point of the solder material constituting the solder layer. In this case, the fluidity of the solder layer in the reduction step can be kept low, and partial integration of the solder layer on one surface of the substrate is promoted. As a result, the shape of the excess solder layer after the reduction step becomes a unified sheet, and the excess solder layer can be easily removed from one surface of the substrate in the removal step.

[0014] [6] A circuit member with solder bumps, comprising a substrate, a conductive pillar provided on one surface of the substrate, and a solder bump provided on the top surface of the pillar, wherein an alloy layer made of the constituent material of the pillar and the constituent material of the solder bump is provided at the interface between the pillar and the solder bump. In this circuit member with solder bumps, the alloy layer at the interface between the pillar and the solder bump improves the adhesion between the pillar and the solder bump. Therefore, it is possible to suppress the delamination of the solder bump from the pillar and ensure a sufficient manufacturing yield.

[0015] [7] The solder bump circuit member according to [6], wherein the thickness of the alloy layer is 0.5% or more and 10% or less of the height of the solder bump from the top surface of the pillar. By making the thickness of the alloy layer 0.5% or more of the height of the solder bump, the adhesion between the pillar and the solder bump can be sufficiently improved. By making the thickness of the alloy layer 10% or less of the height of the solder bump, stress concentration on the alloy layer can be avoided. [Effects of the Invention]

[0016] According to this disclosure, a sufficient manufacturing yield for circuit components with solder bumps can be ensured. [Brief explanation of the drawing]

[0017] [Figure 1] This is a schematic cross-sectional view showing a circuit member with solder bumps according to one embodiment of the present disclosure. [Figure 2] Figure 1 is a flowchart showing an example of a manufacturing method for a circuit component with solder bumps. [Figure 3] This is a schematic cross-sectional view showing the pretreatment process. [Figure 4] (a) and (b) are schematic cross-sectional views showing the subsequent steps in Figure 3. [Figure 5] This is a schematic cross-sectional view illustrating the deposition process. [Figure 6] This is a schematic cross-sectional view showing the reduction process. [Figure 7](a) is a schematic plan view showing the surplus solder layer after the reduction process, and (b) is a schematic cross-sectional view showing the removal process. [Figure 8] It is a schematic cross-sectional view showing the re-reduction process.

Embodiments for Carrying Out the Invention

[0018] Hereinafter, with reference to the drawings, a manufacturing method of a circuit member with solder bumps and a preferred embodiment of the circuit member with solder bumps according to one aspect of the present disclosure will be described in detail.

[0019] In the following description, the numerical range indicated by "~" indicates a range including the numerical values described before and after "~" as the minimum value and the maximum value, respectively. In the numerical ranges described step by step in this specification, the upper limit value or the lower limit value of a certain step's numerical range may be replaced with the upper limit value or the lower limit value of another step's numerical range.

[0020] FIG. 1 is a schematic cross-sectional view showing a circuit member with solder bumps according to an embodiment of the present disclosure. The circuit member 1 with solder bumps shown in FIG. 1 is a member used, for example, for flip-chip mounting between circuit members. The circuit member 1 with solder bumps is electrically connected to another circuit member via the solder bumps 4 to form a connection structure between the circuit members. As shown in FIG. 1, the circuit member 1 with solder bumps includes a substrate 2, a pillar 3, and a solder bump 4.

[0021] The substrate 2 has a first surface (one surface) 2a provided with an electrode region R of a predetermined pattern and a second surface 2b opposite to the first surface 2a. Specific examples of the substrate 2 include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, driver ICs, and rigid package substrates. These substrates generally have a large number of circuit electrodes. Other examples of substrates having a plurality of electrodes on the surface include wiring substrates such as flexible tape substrates having metal wirings, flexible printed wiring boards, and glass substrates on which indium tin oxide (ITO) is deposited.

[0022] Examples of materials that make up the electrode region R include copper, copper / nickel, copper / nickel / gold, copper / nickel / palladium, copper / nickel / palladium / gold, copper / nickel / gold, copper / palladium, copper / palladium / gold, copper / tin, copper / silver, and indium tin oxide. The electrodes can be formed, for example, by electroless plating, electrolytic plating, sputtering, or etching of metal foil.

[0023] A resist layer 5 is provided on the surface of the substrate 2, excluding the electrode region R. Examples of materials used for the resist layer 5 include silicon nitride (SiN). The thickness of the resist layer 5 from the first surface 2a of the substrate 2 is approximately the same as the thickness of the electrode region R from the first surface 2a of the substrate 2. The thickness of the resist layer 5 from the first surface 2a of the substrate 2 is preferably sufficient to withstand plasma processing, and can be, for example, several tens of nanometers or more.

[0024] Pillar 3 is provided on the first surface 2a of the substrate 2, corresponding to the electrode region R. The constituent material of pillar 3 can be the same as that used for the electrode region R described above. In this embodiment, pillar 3 is made of copper (Cu). Pillar 3 is, for example, cylindrical. If the diameter of pillar 3 is r, the height of pillar 3 may be 1 / 4 × r or greater, or 1 / 2 × r or greater, from the viewpoint of ensuring the reliability of the connection structure and utilizing the interlayer sealing material.

[0025] Furthermore, if the diameter of pillar 3 is r, the pitch between adjacent pillars 3, 3 may be 1 / 2 × r or greater, and may be r or greater from the viewpoint of preventing bridging between adjacent pillars 3, 3 when forming solder bumps 4 (a phenomenon in which adjacent pillars 3, 3 become connected by solder). For example, the height of pillar 3 may be 1 μm to 200 μm, or 5 μm to 150 μm. The diameter of pillar 3 may be 0.4 μm to 200 μm, or 1 μm to 100 μm. The pitch between adjacent pillars 3, 3 may be 0.5 μm or greater, or 1 μm.

[0026] The solder bump 4 is composed of a deposit of solder particles and is provided on the top surface 3a of the pillar 3. The solder bump 4 is composed of a tin alloy. Examples of tin alloys include In-Sn alloy, In-Sn-Ag alloy, Sn-Au alloy, Sn-Bi alloy, Sn-Bi-Ag alloy, Sn-Ag-Cu alloy, and Sn-Cu alloy. In this embodiment, the solder bump 4 is formed of a Sn-Bi alloy.

[0027] The particle size of the solder microparticles may be 0.01 μm to 10 μm, or 0.05 μm to 5 μm. The height of the solder bump 4 from the top surface 3a of the pillar 3 may be 0.005 μm to 200 μm, or 0.01 μm to 150 μm. The particle size of the solder microparticles and the height of the solder bump 4 can be measured from images obtained by, for example, an optical microscope or an electron microscope. Specific devices include flow-type particle image analyzers, microtrac, and Coulter counters.

[0028] An alloy layer 6 is provided at the interface between the pillar 3 and the solder bump 4, consisting of the constituent materials of the pillar 3 and the solder bump 4. In this embodiment, as described above, the pillar 3 is made of copper (Cu) and the solder bump 4 is made of a Sn-Bi alloy. Therefore, in this embodiment, the alloy layer at the interface between the pillar 3 and the solder bump 4 is made of a Cu-Sn alloy.

[0029] The thickness T of the alloy layer 6 is 0.5% to 10% of the height H of the solder bump 4 from the top surface 3a of the pillar 3. By setting the thickness T of the alloy layer 6 to 0.5% or more of the height H of the solder bump 4, the adhesion between the pillar 3 and the solder bump 4 can be sufficiently improved. By improving the adhesion between the pillar 3 and the solder bump 4, the joint strength between the pillar 3 and the solder bump 4 is increased, and peeling of the solder bump 4 from the pillar 3 can be suitably suppressed. In addition, by setting the thickness T of the alloy layer 6 to 10% or less of the height H of the solder bump 4, stress concentration on the alloy layer 6 can be avoided. Deformation and damage of the pillar 3 equipped with the solder bump 4 can be suppressed. The thickness T of the alloy layer 6 may be 0.5% to 6% or 4% to 10% of the height H of the solder bump 4 from the top surface 3a of the pillar 3.

[0030] Figure 2 is a flowchart showing an example of a method for manufacturing a circuit component with solder bumps as shown in Figure 1. As shown in Figure 2, the method for manufacturing a circuit component with solder bumps according to this embodiment comprises a pretreatment step (step S01), a deposition step (step S02), a reduction step (step S03), a removal step (step S04), a re-reduction step (step S05), and a cleaning step (step S06).

[0031] The pretreatment step S01 is a step of applying plasma treatment to a substrate 2 on which pillars 3 are provided. In the pretreatment step S01, as shown in Figure 3, a substrate 2 is prepared in which pillars 3 are formed in the electrode region R of the first surface 2a, and a resist layer 5 is formed in the region of the first surface 2a excluding the electrode region R. Next, plasma P is irradiated onto this substrate 2. Plasma P is, for example, H2O plasma. The treatment time with plasma P is, for example, 5 to 30 minutes. Plasma treatment makes it possible to sufficiently reduce the wettability of the solder layer 11 on one side of the substrate 2 (in this case, the resist layer 5) in the subsequent deposition step S02 compared to the wettability of the solder layer 11 on the pillars 3.

[0032] After plasma treatment, as shown in Figure 4(a), the substrate 2 is treated at a temperature of approximately 240°C under a vacuum atmosphere G1 to remove unwanted moisture from the surface of the substrate 2 (the surface of the resist layer 5) and the surface of the pillar 3. Furthermore, as shown in Figure 4(b), the substrate 2 is treated at a temperature of approximately 240°C under a reducing atmosphere G2 with formic acid (CH2O2) to reduce the copper (Cu) that constitutes the pillar 3. The vacuum level in the vacuum atmosphere G1 is, for example, 5.0 × 10⁻⁶. -2 The pressure can be set to approximately hPa. The processing time under the reducing atmosphere G2 can be, for example, about 10 minutes.

[0033] The deposition process S02 is a process of depositing a solder layer 11 on the first surface 2a of the substrate 2, in a region that includes the top surface 3a of the pillar 3. In the deposition process S02, for example, by sputtering, the solder layer 11 is deposited on the top surface 3a of the pillar 3 and on the first surface 2a of the substrate 2 excluding the region of the pillar 3 (i.e., on the resist layer 5), as shown in Figure 5. The solder layer 11 deposited in the region excluding the region of the pillar 3 becomes excess solder layer 12 that is removed in a subsequent removal process.

[0034] In the deposition process S02, for example, Sn42-Bi58 (a solder alloy containing 42% tin and 58% bismuth) can be used as the solder nanoparticles for forming the solder layer 11. For example, Ar gas can be used as the sputtering process gas. The particle size of the solder nanoparticles can be 0.01 μm to 10 μm or 0.05 μm to 5 μm, as described above. The pressure of the Ar gas can be, for example, 1 Pa. The power applied to the target material can be 70 W. The deposition process S02 is not limited to the sputtering method and may be carried out by other methods such as vapor deposition or ion plating.

[0035] The reduction step S03 is a process in which the solder layer 11 is reduced in a reducing gas atmosphere to form solder bumps 4 on the top surface 3a of the pillar 3. In the reduction step S03, the solder spreads to the top surface 3a of the pillar 3 by the reflow of solder fine particles, and as shown in Figure 6, spherical or nearly spherical solder bumps 4 are formed on the top surface 3a of the pillar 3.

[0036] In this embodiment, in the reduction process S03, a vacuum atmosphere G1 and a reducing atmosphere G2 are alternately formed. Here, processing is first carried out under the vacuum atmosphere G1, and then under the reducing atmosphere G2 using formic acid (CH2O2). Under the vacuum atmosphere G1, processing is carried out at a temperature of ±5°C from the melting point of the solder material constituting the solder layer 11, and at a processing tank pressure of 1 Pa or less. In this embodiment, since the melting point of the Sn-Bi alloy, which is the constituent material of the solder layer 11, is approximately 138°C, heating is carried out at 135°C, which is lower than the melting point of the solder layer 11, for 10 minutes under the reducing atmosphere G2. Similarly, under the reducing atmosphere G2, processing is carried out at a temperature of ±5°C from the melting point of the solder material constituting the solder layer 11. In this embodiment, heating is carried out at 135°C, which is lower than the melting point of the solder layer 11, for 10 minutes under the reducing atmosphere G2. In this embodiment, after repeating the processing in the vacuum atmosphere G1 and the reducing atmosphere G2 three times, the temperature is raised to about 150°C and held for about 1 minute.

[0037] In the reduction process S03, as shown in Figure 6, by alternately forming a vacuum atmosphere G1 and a reducing atmosphere G2, the excess solder layer 12 on the first surface 2a of the substrate 2 (on the resist layer 5) can be separated into a solder portion 12a that aggregates toward the pillar 3 and a solder portion 12b that aggregates without adhering toward the pillar 3. The cohesive force of the solder portion 12a is thought to be due to alloying with copper, which is a constituent material of the pillar 3, and the difference in solder wettability between the pillar 3 and the resist layer 5.

[0038] In this embodiment, the pretreatment step S01 described above sufficiently reduces the wettability of the solder layer 11 in the resist layer 5 compared to the wettability of the solder layer 11 in the pillar 3. Furthermore, by setting the temperature under the reducing atmosphere G2 in the reduction step S03 to a temperature of ±5°C of the melting point of the solder material constituting the solder layer 11, the fluidity of the excess solder layer 12 in the reduction step S03 can be kept low. As a result, partial integration of solder portions 12b is promoted, and the separation of solder portions 12b from solder portions 12a proceeds around each pillar 3, so that the shape of the excess solder layer 12 after the reduction step S03 can be made into an integrated sheet shape, as shown in Figure 7(a). In the example in Figure 7(a), the excess solder layer 12 is in the shape of a mesh sheet with openings around each pillar 3 in a plan view of the substrate 2.

[0039] The removal step S04 is a step in which the excess solder layer 12 remaining on the first surface 2a of the substrate 2 after the reduction step S03 is removed. In the removal step S04, as shown in Figure 7(b), the mesh-sheet-like excess solder layer 12 formed in the reduction step S03 is removed from the first surface 2a of the substrate 2 using Kapton tape or tweezers. In the example in Figure 7(b), the corners of the mesh-sheet-like excess solder layer 12 are grasped using tweezers K, and the excess solder layer 12 is peeled off from the first surface 2a of the substrate 2.

[0040] The re-reduction step S05 is a step in which the solder bump 4 on the top surface 3a of the pillar 3 is re-reduction under a reducing gas atmosphere. In this embodiment, heating is performed for 10 minutes at 135°C, which is lower than the melting point of the solder layer 11, under a reducing atmosphere G2 with formic acid (CH2O2). After that, the temperature is raised to about 220°C and held for about 5 seconds. As a result, as shown in Figure 8, an alloy layer 6 is formed at the interface between the pillar 3 and the solder bump 4, consisting of the constituent materials of the pillar 3 and the constituent materials of the solder bump 4. The thickness of the alloy layer 6 formed in the re-reduction step S05 can be controlled by the achieved temperature and heating time.

[0041] The cleaning step S06 is a step in which the substrate on which the solder bumps 4 have been formed is ultrasonically cleaned using ultrapure water or methanol after the re-reduction step S05. Here, for example, ultrasonic cleaning with ultrapure water is performed for about 10 seconds, followed by ultrasonic cleaning with methanol for about 20 seconds. By performing the cleaning step S06, the excess solder particles 12c (see Figure 8) remaining after the removal of the mesh-like excess solder layer 12 are removed from the first surface 2a of the substrate 2, and the circuit member 1 with solder bumps shown in Figure 1 is obtained.

[0042] As explained above, in this method for manufacturing a circuit component with solder bumps, after forming solder bumps 4 on the top surface 3a of the pillar 3 by reducing the solder layer 11, an alloy layer 6 is formed at the interface between the pillar 3 and the solder bumps 4 by re-reducing the solder bumps 4. The formation of this alloy layer 6 improves the adhesion between the pillar 3 and the solder bumps 4. Therefore, it is possible to suppress the delamination of the solder bumps 4 from the pillar 3 in subsequent cleaning steps such as S06, and to ensure a sufficient manufacturing yield for the circuit component with solder bumps 1.

[0043] In this embodiment, a pretreatment step S01 is included in which the substrate 2 on which the pillars 3 are provided is subjected to plasma treatment before the deposition step S02. In this case, the plasma treatment can sufficiently reduce the wettability of the solder layer 11 on the first surface 2a of the substrate 2 compared to the wettability of the solder layer 11 on the pillars 3. As a result, in the reduction step S03, the cohesiveness of the solder layer 11 on the first surface 2a of the substrate 2 is increased, and in the removal step S04, the excess solder layer 12 can be easily removed from the first surface 2a of the substrate 2.

[0044] In this embodiment, after the re-reduction step S05, a cleaning step S06 is included in which the substrate 2 on which the solder bumps 4 are formed is ultrasonically cleaned using ultrapure water or methanol. This makes it possible to more reliably remove excess solder particles 12c remaining on one surface of the substrate 2 after the excess solder layer 12 has been removed. Furthermore, as described above, as the adhesion between the pillar 3 and the solder bump 4 is improved by the alloy layer 6, even when ultrasonic cleaning is performed using ultrapure water or methanol, it is possible to effectively suppress the delamination of the solder bump 4 from the pillar 3.

[0045] In this embodiment, in the reduction step S03, a vacuum atmosphere G1 and a reducing atmosphere G2 are alternately formed. This allows the solder layer 11 on the first surface 2a of the substrate 2 to be separated in the reduction step S03 into a solder portion 12a that aggregates toward the pillar 3 and a solder portion 12b that aggregates without adhering toward the pillar 3. As a result, the excess solder layer 12 after the reduction step S03 takes the shape of a mesh opening around the pillar 3, and the excess solder layer 12 can be easily removed from the first surface 2a of the substrate 2 in the removal step S06.

[0046] In this embodiment, in the reduction step S03, reduction is performed at a temperature of ±5°C from the melting point of the solder material constituting the solder layer 11. This keeps the fluidity of the solder layer 11 low in the reduction step S03, promoting the partial integration of the solder layer 11 on the first surface a of the substrate 2. As a result, the excess solder layer 12 after the reduction step S03 becomes a unified sheet, and in the removal step S06, the excess solder layer 12 can be easily removed from the first surface 2a of the substrate 2.

[0047] In the solder bump-equipped circuit member 1 according to this embodiment, the alloy layer 6 at the interface between the pillar 3 and the solder bump 4 improves the adhesion between the pillar 3 and the solder bump 4. Therefore, it is possible to suppress the delamination of the solder bump 4 from the pillar 3 and ensure a sufficient manufacturing yield. In this embodiment, the thickness T of the alloy layer 6 is 0.5% to 10% of the height H of the solder bump 4 from the top surface 3a of the pillar 3. By setting the thickness T of the alloy layer 6 to 0.5% or more of the height H of the solder bump 4, the adhesion between the pillar 3 and the solder bump 4 can be sufficiently improved. By setting the thickness T of the alloy layer 6 to 10% or less of the height H of the solder bump 4, stress concentration on the alloy layer 6 can be avoided. [Explanation of symbols]

[0048] 1...Circuit component with solder bumps, 2...Substrate, 2a...First surface (one side), 3...Pillar, 3a...Top surface, 4...Solder bump, 6...Alloy layer, 11...Solder layer, 12...Excess solder layer, G1...Vacuum atmosphere, G2...Reducing atmosphere, T...Thickness of alloy layer, H...Height of solder bump.

Claims

1. A deposition step of depositing a solder layer in a region including the top surface of a conductive pillar on one surface of a substrate provided with a conductive pillar, A reduction step is performed to reduce the aforementioned solder layer in a reducing gas atmosphere to form solder bumps on the top surface of the pillar, A removal step to remove the excess solder layer remaining on one surface of the substrate after the reduction step, A method for manufacturing a circuit member with solder bumps, comprising: a re-reduction step of re-reducing the solder bump on the top surface of the pillar in a reducing gas atmosphere to form an alloy layer at the interface between the pillar and the solder bump, consisting of the constituent material of the pillar and the constituent material of the solder bump.

2. A method for manufacturing a circuit member with solder bumps according to claim 1, comprising a pretreatment step of subjecting the substrate on which the pillars are provided to plasma treatment before the deposition step.

3. A method for manufacturing a circuit member with solder bumps according to claim 2, further comprising a cleaning step of ultrasonically cleaning the substrate on which the solder bumps are formed using ultrapure water or methanol after the re-reduction step.

4. The method for manufacturing a solder bump circuit member according to claim 1, wherein the reduction step alternately creates a vacuum atmosphere and a reducing atmosphere.

5. The method for manufacturing a circuit member with solder bumps according to claim 1, wherein the reduction step is performed at a temperature of ±5°C from the melting point of the solder material constituting the solder layer.

6. circuit board and A conductive pillar provided on one surface of the substrate, The pillar comprises a solder bump provided on the top surface of the pillar, A circuit member with a solder bump, wherein an alloy layer made of the constituent material of the pillar and the constituent material of the solder bump is provided at the interface between the pillar and the solder bump.

7. The solder bump circuit member according to claim 6, wherein the thickness of the alloy layer is 0.5% or more and 10% or less of the height of the solder bump from the top surface of the pillar.

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