Semiconductor and display devices

Abstract

To improve the reliability of semiconductor devices containing oxide semiconductors. [Solution] The semiconductor device includes a first oxide semiconductor layer provided on an insulating surface and having a channel portion and a conductive portion with lower resistance than the channel portion; a first insulating layer on the first oxide semiconductor layer; a second insulating layer on the first insulating layer; a first conductive layer between the first insulating layer and the second insulating layer; a first gate electrode on the second insulating layer; a third insulating layer on the first gate electrode; and a second conductive layer provided on the third insulating layer and in contact with the conductive portion via contact holes provided in the first insulating layer, the second insulating layer, and the third insulating layer.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. [Background technology]

[0002] In recent years, oxide semiconductors have attracted attention as materials for semiconductor devices, replacing amorphous silicon, polysilicon, and single-crystal silicon. In particular, development of thin-film transistors using oxide semiconductors as channels is progressing (for example, Patent Documents 1-6). Thin-film transistors using oxide semiconductors as channels can be formed with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon as a channel. Thin-film transistors using oxide semiconductors as channels are known to have higher field-effect mobility than thin-film transistors using amorphous silicon as a channel. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Publication No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Publication No. 2018-006730 [Patent Document 5] Japanese Patent Publication No. 2016-184771 [Patent Document 6] Japanese Patent Publication No. 2021-108405 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Conventionally, various device structures, including top-gate and bottom-gate structures, have been considered for thin-film transistors using oxide semiconductors as channels. However, these thin-film transistors have several reliability issues. For example, in conventional device structures, it is difficult to achieve both the breakdown voltage characteristics of the gate insulating layer (specifically, resistance to high voltages applied between the gate and source, or between the gate and drain) and the suppression of damage to the oxide semiconductor layer. Therefore, there is still room for improvement in the reliability of conventional thin-film transistors using oxide semiconductors as channels.

[0005] One of the objectives of this invention is to improve the reliability of semiconductor devices containing oxide semiconductors. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first oxide semiconductor layer provided on an insulating surface and having a channel portion and a conductive portion with lower resistance than the channel portion; a first insulating layer on the first oxide semiconductor layer; a second insulating layer on the first insulating layer; a first conductive layer between the first insulating layer and the second insulating layer; a first gate electrode on the second insulating layer; a third insulating layer on the first gate electrode; and a second conductive layer provided on the third insulating layer and in contact with the conductive portion via contact holes provided in the first insulating layer, the second insulating layer, and the third insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 2] This is a schematic plan view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 3] This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 19] It is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 20] It is a sequence diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 24] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 25] This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 29] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 30] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 31] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 32] This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. [Figure 33] This is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 34] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 35] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 36] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 37] This is a schematic plan view showing the overall configuration of a display device in one embodiment of the present invention. [Figure 38] Block diagram showing the circuit configuration of a display device in one embodiment of the present invention. [Figure 39] This is a schematic diagram showing the configuration of the pixel circuit of a display device in one embodiment of the present invention. [Figure 40] This is a cross-sectional view showing the pixel configuration of a display device in one embodiment of the present invention. [Figure 41] This figure shows the region where the impurity concentration was evaluated in a semiconductor device according to one embodiment of the present invention. [Figure 42] This figure shows the evaluation results of the impurity concentration for the semiconductor device in one embodiment of the present invention. [Modes for carrying out the invention]

[0008] The embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but for example, the substrate and oxide semiconductor layer may be arranged in the opposite way to what is shown in the figures. In the following description, for example, the expression "oxide semiconductor layer on the substrate" merely describes the upward and downward relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer.

[0010] The term "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, although the embodiments described later will use an organic EL display device including an organic EL layer as an example, the structure in these embodiments can be applied to other display devices including electro-optical layers, such as liquid crystal display devices including a liquid crystal layer.

[0011] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] In this specification, “identical” includes not only perfectly identical but also substantially identical. “Substantially identical” means that the differences are not perfectly identical but are within a range of minor differences that can be considered identical, for example, within an error range of ±5% (preferably ±3%).

[0013] [1. First Embodiment] A semiconductor device according to one embodiment of the present invention will be described using a thin-film transistor as an example. The semiconductor device of the embodiment shown below may be a thin-film transistor used in a display device (for example, an organic EL display device or a liquid crystal display device), or it may be a thin-film transistor used in an integrated circuit (IC) such as a microprocessing unit (MPU), or in a memory circuit.

[0014] [1-1. Semiconductor device configuration] The configuration of the semiconductor device 10 in one embodiment of the present invention will be described. Figure 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 in one embodiment of the present invention. Figure 2 is a schematic plan view showing the configuration of the semiconductor device 10 in one embodiment of the present invention. Specifically, Figure 1 is a cross-sectional view taken along the dashed line shown A-A' in Figure 2.

[0015] First, the cross-sectional structure of the semiconductor device 10 will be described using Figure 1. As shown in Figure 1, the semiconductor device 10 is provided above the substrate 100. The semiconductor device 10 includes a transistor Tr and a capacitive element Cap. The transistor Tr includes a gate electrode 105, a gate insulating layer 110, an oxide semiconductor layer 130, an insulating layer 140, a metal oxide layer 151, an insulating layer 170, a gate electrode 160, an insulating layer 190, and a terminal electrode 181. The capacitive element Cap includes an oxide semiconductor layer 135, conductive layers 162, 203, 204, and terminal electrodes 182 to 185.

[0016] First, let's explain the cross-sectional structure of a transistor (Tr).

[0017] The gate electrode 105 is provided on the substrate 100. The gate electrode 105 functions as the gate of the transistor Tr. Specifically, the gate electrode 105 has the role of applying a gate voltage to the channel portion 131 of the oxide semiconductor layer 130, which will be described later. An insulating layer (not shown) may be provided on the substrate 100. That is, the gate electrode 105 may be placed directly or indirectly on the substrate 100. In other words, the gate electrode 105 is provided on an insulating surface.

[0018] The gate insulating layer 110 is provided on the substrate 100 and the gate electrode 105. The gate insulating layer 110 functions as a barrier film that shields against impurities diffusing from the substrate 100 toward the oxide semiconductor layer 130, and also functions as a base for the oxide semiconductor layer 130 positioned above it.

[0019] Although not shown in the diagram, in this embodiment the gate insulating layer 110 has a two-layer structure. Specifically, a silicon nitride layer is used as the insulating layer on the lower side (closer to the substrate 100) of the gate insulating layer 110, and a silicon oxide layer is used as the insulating layer on the upper side (closer to the oxide semiconductor layer 130) of the gate insulating layer 110. In this embodiment, the thickness of the lower insulating layer (silicon nitride layer) is 200 nm, and the thickness of the upper insulating layer (silicon oxide layer) is 100 nm, so the thickness of the gate insulating layer 110 is 300 nm. That is, in this embodiment, the thickness of the gate insulating layer 110 can be 200 nm or more (preferably 300 nm or more, and even more preferably 400 nm or more). Note that the gate insulating layer 110 may have a single-layer structure or a structure of three or more layers.

[0020] The oxide semiconductor layer 130 is provided on the gate insulating layer 110. In other words, the oxide semiconductor layer 130 is provided on the insulating surface of the gate insulating layer 110. The oxide semiconductor layer 130 has a channel portion 131 and a conductive portion 132 that are continuous in the D1 direction. The channel portion 131 functions as the channel region of the transistor Tr. The conductive portion 132 functions as the source region or drain region of the transistor Tr. The conductive portion 132 is a portion with lower resistance than the channel portion 131 and has the role of transmitting carriers flowing through the channel portion 131 to the terminal electrode 181. As will be described in detail later, the conductive portion 132 contains impurities (phosphorus, boron, argon, etc.) to lower the resistance of the oxide semiconductor layer 130. On the other hand, the channel portion 131 does not contain these impurities. In other words, the amount of impurities contained in the conductive portion 132 is greater than the amount of impurities contained in the channel portion 131.

[0021] Here, "free of impurities" means that impurities have not been intentionally added, not that there are absolutely no impurities present. For example, the expression "free of impurities" means that if SIMS (Secondary Ion Mass Spectrometry) analysis is performed on a certain layer, the impurity concentration calculated by the SIMS analysis in that layer is at the detection limit, or the difference from the detection limit is less than one order of magnitude. For example, in SIMS analysis to detect boron, if the detection limit for boron is 10 16 atoms / cm 3 If the boron concentration calculated by SIMS analysis is 10 17 atoms / cm 3 The following layers can be said to "not contain boron."

[0022] The insulating layer 140 is provided on the oxide semiconductor layer 130. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 is a dielectric layer that electrically insulates the layer on which the gate electrode 160 (described later) or the layer on which the terminal electrode 181 is formed from the layer on which the oxide semiconductor layer 130 is formed. The thickness of the insulating layer 140 is 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 100 nm to 150 nm). The thickness of the insulating layer 140 is thinner than the thickness of the gate insulating layer 110. The advantages of having a thin insulating layer 140 will be described later.

[0023] As shown in Figure 1, the region overlapping with the channel portion 131 in a plan view is called the first region R1, and the region overlapping with the conductive portion 132 in a plan view is called the second region R2. As will be explained in detail later, the insulating layer 140 in the first region R1 does not contain impurities to reduce the resistance of the oxide semiconductor layer 130, while the insulating layer 140 in the second region R2 contains such impurities. On the other hand, the insulating layer 170 in both the first region R1 and the second region R2 does not contain such impurities. In other words, in the second region R2, the insulating layer 140 contains such impurities, but the insulating layer 170 does not. This configuration is due to the timing of impurity addition, as will be explained later.

[0024] The metal oxide layer 151 is provided on top of the insulating layer 140. In this embodiment, the metal oxide layer 151 is composed of a metal oxide mainly composed of aluminum. The metal oxide layer 151 is obtained by processing the metal oxide layer into island shapes by patterning. The metal oxide layer 151 functions as a barrier layer that suppresses hydrogen diffused from above from reaching the channel portion 131 of the oxide semiconductor layer 130. As will be described in detail later, the metal oxide layer 151 is a patterned layer of the metal oxide layer 150 (see Figure 6) used in the manufacturing process of the semiconductor device 10 when performing a heat treatment to supply oxygen to the oxide semiconductor layer 130. The thickness of the metal oxide layer 151 is 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm.

[0025] The metal oxide layer 151 is positioned above the oxide semiconductor layer 130 via the insulating layer 140. In other words, the insulating layer 140 is in contact with both the oxide semiconductor layer 130 and the metal oxide layer 151. The metal oxide layer 151 overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as shown in Figure 1 using the dashed line, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the edge 131a of the channel portion 131 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the boundary between the channel portion 131 and the conductive portion 132 coincide in the vertical direction. The reason why the position of the edge 151a of the metal oxide layer 151 and the position of the edge 131a of the channel portion 131 coincide will be explained later.

[0026] The insulating layer 170 is provided on the insulating layer 140 and the metal oxide layer 151. In this embodiment, a silicon oxide layer is used as the insulating layer 170. The insulating layer 170 is a dielectric layer that electrically insulates the layer on which the gate electrode 160 (described later) or the layer on which the terminal electrode 181 is formed from the layer on which the oxide semiconductor layer 130 is formed. The thickness of the insulating layer 170 is 200 nm or more and 500 nm or less (preferably 350 nm or more and 450 nm or less). The thickness of the insulating layer 170 is greater than the thickness of the insulating layer 140.

[0027] The gate electrode 160 is provided on top of the insulating layer 170. The gate electrode 160 functions as the gate of the transistor Tr, similar to the gate electrode 105. Specifically, the gate electrode 160 has the role of applying a gate voltage to the channel portion 131 of the oxide semiconductor layer 130. The insulating layer 140, metal oxide layer 151, and insulating layer 170 sandwiched between the oxide semiconductor layer 130 and the gate electrode 160 function as a gate insulating layer. The gate insulating layer composed of the insulating layer 140, metal oxide layer 151, and insulating layer 170 is sometimes called the "upper gate insulating layer".

[0028] The insulating layer 190 is provided on top of the insulating layer 170 and the gate electrode 160. Although not shown in the figures, in this embodiment the insulating layer 190 has a two-layer structure. Specifically, a silicon oxide layer is used as the insulating layer on the lower side (closer to the substrate 100) of the insulating layer 190, and a silicon nitride layer is used as the insulating layer on the upper side (further from the substrate 100) of the insulating layer 190. Contact holes 171 reaching the conductive portion 132 are provided in the insulating layers 140, 170, and 190. In this embodiment, the thickness of the lower insulating layer (silicon oxide layer) is 100 nm, and the thickness of the upper insulating layer (silicon nitride layer) is 300 nm, so the thickness of the insulating layer 190 is 400 nm. Note that the insulating layer 190 may have a single-layer structure or a structure of three or more layers.

[0029] The terminal electrode 181 is placed on the insulating layer 190 and is electrically connected to the conductive part 132 via contact holes 171 provided in the insulating layers 140, 170, and 190. The terminal electrode 181 has the role of supplying carriers to the conductive part 132 and extracting carriers from the conductive part 132. In other words, the terminal electrode 181 functions as either the source electrode or the drain electrode of the transistor Tr depending on the role of the conductive part 132. Specifically, the terminal electrode 181 functions as the source electrode when the electrically connected conductive part 132 functions as the source region, and functions as the drain electrode when the electrically connected conductive part 132 functions as the drain region.

[0030] In this embodiment, a dual-gate transistor is exemplified as the transistor Tr, in which a gate electrode 105 is provided below the oxide semiconductor layer 130 and a gate electrode 160 is provided above the oxide semiconductor layer 130, but the embodiment is not limited to this configuration. For example, the transistor Tr may be a bottom-gate transistor in which only the gate electrode 105 is provided, or voltage is applied only to the gate electrode 105, or a top-gate transistor in which only the gate electrode 160 is provided, or voltage is applied only to the gate electrode 160.

[0031] Next, we will describe the cross-sectional structure of the capacitive element Cap.

[0032] The oxide semiconductor layer 135 is provided between the gate insulating layer 110 and the insulating layer 140. In other words, the oxide semiconductor layer 135 is provided between the insulating surface of the gate insulating layer 110 and the insulating layer 140. The oxide semiconductor layer 135, like the conductive portion 132, is a portion with lower resistance than the channel portion 131. The oxide semiconductor layer 135 functions as wiring or an electrode. As will be described in detail later, the oxide semiconductor layer 135 contains impurities (phosphorus, boron, argon, etc.) to lower its resistance. The amount of impurities contained in the oxide semiconductor layer 135 is approximately the same as the amount of impurities contained in the conductive portion 132.

[0033] The conductive layers 203 and 204 are located between the insulating layer 140 and the insulating layer 170, and below the insulating layer 190. As described above, since the insulating layers 140 and 170 function as gate insulating layers between the oxide semiconductor layer 130 and the gate electrode 160, it can be said that the conductive layers 203 and 204 are located between the stacked gate insulating layers. The conductive layer 162 is located between the insulating layer 170 and the insulating layer 190.

[0034] As shown in Figure 2, in a plan view, the conductive layer 204 overlaps with the oxide semiconductor layer 135. Similarly, in a plan view, the conductive layer 162 overlaps with the conductive layer 203. The overlapping portion of conductive layer 162 and conductive layer 203 functions as a capacitive element C1. The overlapping portion of conductive layer 204 and oxide semiconductor layer 135 functions as a capacitive element C2.

[0035] In a plan view, in the region overlapping with the conductive layer 162, a contact hole 172 is provided in the insulating layer 190, and the terminal electrode 182 is connected to the conductive layer 162 via the contact hole 172. In a plan view, in the region overlapping with the conductive layer 203, contact holes 173 are provided in the insulating layers 170 and 190, and the terminal electrode 183 is connected to the conductive layer 203 via the contact hole 173.

[0036] In a plan view, in the region overlapping with the conductive layer 204, contact holes 174 are provided in the insulating layers 170 and 190, and the terminal electrode 184 is connected to the conductive layer 204 via the contact holes 174. In a plan view, in the region overlapping with the oxide semiconductor layer 135, contact holes 175 are provided in the insulating layers 140, 170, and 190, and the terminal electrode 185 is connected to the oxide semiconductor layer 135 via the contact holes 175.

[0037] The oxide semiconductor layer 130 is sometimes referred to as the "first oxide semiconductor layer." The insulating layer 140 is sometimes referred to as the "first insulating layer." The insulating layer 170 is sometimes referred to as the "second insulating layer." The gate electrode 160 is sometimes referred to as the "first gate electrode." The insulating layer 190 is sometimes referred to as the "third insulating layer." The conductive layer 203 or conductive layer 204 is sometimes referred to as the "first conductive layer." The terminal electrode 181 is sometimes referred to as the "second conductive layer."

[0038] The oxide semiconductor layer 135 is sometimes referred to as the "second oxide semiconductor layer." The conductive layer 162 is sometimes referred to as the "third conductive layer." The conductive layer 203 is sometimes called the "first conductive layer," and the conductive layer 204 is sometimes called the "fourth conductive layer." Capacitor element C1 is sometimes referred to as the "first capacitive element." Capacitor element C2 is sometimes referred to as the "second capacitive element."

[0039] Next, the planar structure of the semiconductor device 10 will be described using Figure 2.

[0040] First, let's explain the layout of the transistor (Tr).

[0041] As shown in Figure 2, the D1 direction is the direction connecting the two terminal electrodes 181 to each other (the direction in which the channel portion 131 and the conductive portion 132 are continuous), and corresponds to the direction in which the carriers move. The length of the channel portion 131 in the D1 direction of the oxide semiconductor layer 130 is the channel length (L), and the length of the channel portion 131 in the D2 direction is the channel width (W). The D2 direction is the direction intersecting the D1 direction. In this embodiment, the D2 direction is shown as being perpendicular to the D1 direction, but depending on the layout of the oxide semiconductor layer 130, the D1 direction and the D2 direction may not be perpendicular.

[0042] In this embodiment, in the D1 direction, the width of the gate electrode 105 is greater than the length of the channel portion 131 (channel length). The reason for this configuration is to effectively prevent external light from entering the channel portion 131. However, the example is not limited to this one, and the width of the gate electrode 105 may be the same as the length of the channel portion 131.

[0043] As shown in Figure 2, in a plan view, the metal oxide layer 151 is arranged to overlap with the oxide semiconductor layer 130. Specifically, in a plan view, the metal oxide layer 151 is arranged to intersect with the channel portion 131 of the oxide semiconductor layer 130. Thus, it is desirable that the width of the metal oxide layer 151 in the D2 direction is greater than the width (W) of the oxide semiconductor layer 130 in the D2 direction. Such a configuration is effective in allowing the function of the metal oxide layer 151 described above (the function of suppressing hydrogen diffused from above from reaching the channel portion 131 of the oxide semiconductor layer 130) to work effectively.

[0044] Furthermore, in a plan view, the outer edge of the portion of the metal oxide layer 151 that overlaps with the oxide semiconductor layer 130 coincides with the outer edge of the channel portion 131. In other words, the metal oxide layer 151 intersects with the channel portion 131 and does not overlap with the conductive portion 132. However, the expression "the metal oxide layer 151 intersects with the channel portion 131 and does not overlap with the conductive portion 132" includes cases where the metal oxide layer 151 overlaps with a portion of the conductive portion 132 within an error range. As will be described later, the conductive portion 132 is formed by adding impurities to the oxide semiconductor layer 130 by methods such as ion implantation. Therefore, due to the leakage of impurities to the lower part of the metal oxide layer 151, there may be cases where a small portion of the conductive portion 132 overlaps with the metal oxide layer 151.

[0045] Figure 2 illustrates a configuration in which the terminal electrodes 181 do not overlap with the gate electrode 105 in a plan view, but the configuration is not limited to this. For example, in a plan view, both or one of the two terminal electrodes 181 may overlap with the gate electrode 105.

[0046] Next, we will explain the layout of the capacitive element (Cap).

[0047] Since capacitive elements C1 and C2 have similar layouts, only capacitive element C1 will be described. In a plan view, conductive layer 162 and conductive layer 203 overlap. Contact holes 173 are provided in regions where conductive layer 162 is absent and only conductive layer 203 exists. In Figure 2, conductive layer 162 is provided inside conductive layer 203, but the configuration is not limited to this. For example, conductive layer 162 may be provided in regions where conductive layer 203 is absent. In other words, conductive layer 162 may be provided so as to extend over the edge of conductive layer 203.

[0048] [1-2. Materials of each layer in semiconductor devices] The substrate 100 supports each layer constituting the semiconductor device 10. As the substrate 100, a translucent, rigid substrate such as a glass substrate, quartz substrate, or sapphire substrate may be used. A non-translucent, rigid substrate such as a silicon substrate may also be used. Furthermore, a translucent, flexible substrate such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate may also be used. Impurities may be added to the resin substrate to improve the heat resistance of the substrate 100. As the substrate, a substrate in which a silicon oxide film or silicon nitride film is deposited on the rigid or flexible substrate described above may also be used.

[0049] As described above, the gate electrode 105 has a larger area than the channel portion 131 of the oxide semiconductor layer 130. Therefore, a material that can block ambient light incident on the channel portion 131 from below is used as the gate electrode 105. Examples of materials that can be used as the gate electrode 105 include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof. The gate electrode 105 may have a single-layer structure or a multilayer structure.

[0050] As the gate insulating layer 110, for example, silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) can be used. Here, silicon oxide nitride (SiOxNy) and aluminum oxide nitride (AlOxNy) are silicon compounds and aluminum compounds, respectively, that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). Silicon oxide nitride (SiNxOy) and aluminum oxide nitride (AlNxOy) are silicon compounds and aluminum compounds, respectively, that contain oxygen in a smaller proportion (x>y) than nitrogen. In this embodiment, the gate insulating layer 110 has a two-layer structure, with a silicon nitride layer used as the lower insulating layer and a silicon oxide layer used as the upper insulating layer.

[0051] The oxide semiconductor layers 130 and 135 may have an amorphous structure or a polycrystalline structure.

[0052] The insulating layers 140 and 170 contain an insulating oxide. Specifically, silicon oxide (SiOx), silicon oxide nitride (SiOxNy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), etc., can be used as insulating layers 140 and 170. In this embodiment, a silicon oxide layer with a thickness of 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 100 nm to 150 nm) is used as insulating layer 140. A silicon oxide layer with a thickness of 200 nm to 500 nm (preferably 350 nm to 450 nm) is used as insulating layer 170.

[0053] The metal oxide layer 151 is composed of a metal oxide. In this embodiment, an oxide mainly composed of aluminum (for example, aluminum oxide) is used as the metal oxide constituting the metal oxide layer 151. Since aluminum oxide has high barrier properties against gases, the metal oxide layer 151 has the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. As the metal oxide layer 151, an aluminum oxide layer with a thickness of 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm is used.

[0054] The gate electrode 160 is made of a material that can block ambient light entering the channel portion 131 from above. Examples of materials used for the gate electrode 160 include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof. The gate electrode 160 may be a single-layer structure or a multi-layer structure. The conductive layer 162 is provided in the same layer as the gate electrode 160. Therefore, the same material as the gate electrode 160 is used for the conductive layer 162.

[0055] For example, silicon oxide (SiOx), silicon oxide nitride (SiOxNy), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) can be used as the insulating layer 190. In this embodiment, the insulating layer 190 has a two-layer structure, with a silicon oxide layer used as the lower insulating layer and a silicon nitride layer used as the upper insulating layer.

[0056] The terminal electrodes 181-185 and the conductive layers 203 and 204 are conductive. For example, copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof can be used as terminal electrodes 181-185 and the conductive layers 203 and 204. The terminal electrodes 181-185 and the conductive layers 203 and 204 may be in a single-layer structure or a multi-layer structure.

[0057] [1-3. Method for manufacturing semiconductor devices] Next, a method for manufacturing the semiconductor device 10 in one embodiment of the present invention will be described. Figure 3 is a sequence diagram showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention. Figures 4 to 16 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention.

[0058] As shown in Figures 3 and 4, a gate electrode 105 is formed on the substrate 100, and a gate insulating layer 110 is formed on the gate electrode 105 (step S1001 in Figure 4). For example, a laminated structure of a silicon nitride layer and a silicon oxide layer is formed as the gate insulating layer 110. The gate insulating layer 110 is formed by the CVD (Chemical Vapor Deposition) method. In this specification, the process of forming a film on a substrate by methods such as sputtering or CVD is sometimes expressed as "a thin film is formed," but this expression has the same meaning as "a thin film is deposited."

[0059] If a silicon nitride layer is provided as part of the gate insulating layer 110 on the side closer to the substrate 100, impurities diffusing from the substrate 100 towards the oxide semiconductor layer 130 can be blocked. If a silicon oxide layer is provided as part of the gate insulating layer 110 on the side in contact with the later-formed oxide semiconductor layer 130, the characteristics of the interface between the gate insulating layer 110 and the oxide semiconductor layer 130 are improved.

[0060] By setting the deposition temperature of the silicon oxide layer to a relatively low level, the amount of oxygen contained in the silicon oxide layer can be increased. As described later, by increasing the amount of oxygen contained in the gate insulating layer 110, the amount of hydrogen that diffuses into the oxide semiconductor layer 130 can be reduced. The deposition temperature of the gate insulating layer 110 is set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0061] Next, as shown in Figures 3 and 5, patterned oxide semiconductor layers 130 and 135 are formed on the gate insulating layer 110 (step S1002 in Figure 3). In this embodiment, the process of forming the oxide semiconductor layers 130 and 135 is referred to as "OS pattern formation". In other words, the oxide semiconductor layers 130 and 135 are formed by applying a patterning process to the oxide semiconductor layer deposited on the gate insulating layer 110. In the description of this embodiment, when "oxide semiconductor layer" is written without a reference numeral, it refers to the oxide semiconductor layer in its deposited state (i.e., in its unprocessed state).

[0062] For etching the oxide semiconductor layer, either wet etching or dry etching may be used. For wet etching, for example, an acidic etchant (oxalic acid or hydrofluoric acid) may be used.

[0063] In this embodiment, the oxide semiconductor layer is formed by sputtering. The thickness of the oxide semiconductor layer to be formed is, for example, 10 nm to 100 nm, 10 nm to 70 nm, or 10 nm to 40 nm.

[0064] When a thin film is formed on a substrate by sputtering, ions generated in the plasma and atoms recoiling from the sputtering target collide with the object being formed on (specifically, the structure formed on the substrate 100), causing the temperature of the substrate to rise during the thin film formation process.

[0065] To control the substrate temperature (i.e., film deposition temperature) when forming the oxide semiconductor layer, for example, the thin film is formed while cooling the substrate. For example, the substrate is cooled from the side opposite to the surface to be formed so that the film deposition temperature is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film deposition temperature of the oxide semiconductor layer in this embodiment is preferably 50°C or less. In this embodiment, it is preferable that the difference between the temperature when forming the oxide semiconductor layer and the temperature when performing OS annealing on the oxide semiconductor layers 130 and 135 is 350°C or more.

[0066] After forming oxide semiconductor layers 130 and 135 by patterning, the oxide semiconductor layers 130 and 135 are subjected to heat treatment (OS annealing) (step S1003 in Figure 3). In OS annealing, the oxide semiconductor layers 130 and 135 are heat-treated in an air atmosphere at a temperature of 250°C to 500°C (preferably 300°C to 500°C, and more preferably 350°C to 450°C). The heating atmosphere is not limited to an air atmosphere, but is preferably an oxidizing atmosphere (an atmosphere containing oxygen). The time for heat treatment after reaching the predetermined temperature is 15 minutes to 120 minutes, or 30 minutes to 60 minutes.

[0067] In this embodiment, a substrate on which oxide semiconductor layers 130 and 135 are formed is placed in a heating furnace having a heating medium (e.g., a support plate) maintained at a pre-set temperature (250°C to 500°C). The support plate, acting as the heating medium, serves to support the substrate and to heat the substrate and the coating (including the oxide semiconductor layers 130 and 135) formed on it. When the substrate on which the oxide semiconductor layers 130 and 135 are formed is placed on the support plate, the oxide semiconductor layers 130 and 135 are rapidly heated. When the substrate is placed in the heating furnace, it is desirable that the temperature drop of the support plate be suppressed to within 15%, 10%, or 5% of the set temperature. In other words, it is preferable that the temperature of the support plate be controlled so that the oxide semiconductor layers 130 and 135 reach the set temperature in the shortest possible time.

[0068] Next, as shown in Figures 3 and 6, an insulating layer 140 and a metal oxide layer 150 are formed (step S1004 in Figure 3). For example, a silicon oxide layer is formed as the insulating layer 140. The insulating layer 140 is formed by the CVD method. The thickness of the insulating layer 140 is, for example, 50 nm to 200 nm, 50 nm to 150 nm, or 100 nm to 150 nm. In this embodiment, the thickness of the insulating layer 140 is 100 nm.

[0069] The metal oxide layer 150 is formed by sputtering. By using sputtering to deposit the metal oxide layer 150, oxygen is injected into the insulating layer 140 when the metal oxide layer 150 is formed. Therefore, the insulating layer 140 contains a large amount of oxygen after the metal oxide layer 150 has been formed. The thickness of the metal oxide layer 150 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 150. As mentioned above, aluminum oxide has high barrier properties against gases, so during the heat treatment described later, the upward diffusion of oxygen injected into the insulating layer 140 is suppressed.

[0070] When the metal oxide layer 150 is formed by sputtering, the process gas used in sputtering remains in the metal oxide layer 150 film. For example, if Ar is used as the sputtering process gas, Ar may remain in the metal oxide layer 150 film. The remaining Ar can be detected by SIMS analysis of the metal oxide layer 150. In other words, if Ar is used as the sputtering process gas, Ar will be detected by SIMS analysis of the metal oxide layer 151 obtained by patterning the metal oxide layer 150.

[0071] Next, with the metal oxide layer 150 formed on the insulating layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layers 130 and 135 (step S1005 in Figure 3). During the process between the formation of the oxide semiconductor layers 130 and 135 and the formation of the insulating layer 140 on top of the oxide semiconductor layers 130 and 135, oxygen vacancies may occur on the upper and side surfaces of the oxide semiconductor layers 130 and 135. Oxidation annealing supplies oxygen released from the gate insulating layer 110 and the insulating layer 140 to the oxide semiconductor layers 130 and 135, thereby repairing the oxygen vacancies. Oxidation annealing is performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, and more preferably 350°C to 450°C).

[0072] During oxide annealing, oxygen released from the gate insulating layer 110 and insulating layer 140 is supplied to the oxide semiconductor layers 130 and 135. If a silicon nitride layer is used for part of the gate insulating layer 110, hydrogen may be released from the gate insulating layer 110 during the above oxide annealing. However, most of the released hydrogen is captured by the oxygen contained in the silicon oxide layer located above the silicon nitride layer before it reaches the oxide semiconductor layers 130 and 135.

[0073] As described above, oxygen is supplied to the oxide semiconductor layers 130 and 135 by oxide annealing. During oxide annealing, the upward diffusion of oxygen injected into the insulating layer 140 is blocked by the metal oxide layer 150, thus suppressing the release of diffused oxygen into the atmosphere. Therefore, oxygen is efficiently supplied to the oxide semiconductor layers 130 and 135 during oxide annealing.

[0074] Next, as shown in Figures 3 and 7, a resist mask 210 is formed on the metal oxide layer 150 (step S1006 in Figure 3). The resist mask 210 is positioned to overlap with the oxide semiconductor layer 130. As will be described later, the portion of the oxide semiconductor layer 130 that overlaps with the resist mask 210 corresponds to the portion where the channel portion 131 is formed. As shown in Figure 2, the resist mask 210 is positioned to intersect with the oxide semiconductor layer 130 in the D2 direction.

[0075] Next, as shown in Figures 3 and 8, the metal oxide layer 150 is etched using the resist mask 210 as a mask to form a metal oxide layer 151 (step S1007 in Figure 3). The etching of the metal oxide layer 150 may be wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0076] Next, as shown in Figures 3 and 9, impurities are added to the oxide semiconductor layers 130 and 135 by ion implantation from above the resist mask 210 (step S1008 in Figure 3). Phosphorus, boron, argon, etc., are used as impurities. The purpose of adding impurities is to improve conductivity by forming oxygen vacancies in a part of the oxide semiconductor layer 130 and the oxide semiconductor layer 135. Therefore, it is preferable to use elements with a large atomic radius as impurities. In this embodiment, an example of impurities being added by ion implantation is shown, but impurities may also be added by ion doping. In this embodiment, boron is added by ion implantation. The ion implantation conditions in this embodiment are an acceleration voltage of 30 keV and a dose of 1 × 10⁻⁶. 15 / cm 2 However, this is not the only example.

[0077] As shown in Figure 9, when impurities are ion-implanted into the oxide semiconductor layer 130, conductive portions 132 are formed in the oxide semiconductor layer 130. At this time, the regions where impurities are not implanted and the original state is maintained function as channel portions 131. That is, in a cross-sectional view, the positions of the edges of the resist mask 210 and the metal oxide layer 151 coincide with the positions of the edges of the channel portions 131 in the vertical direction.

[0078] Impurities are added to the conductive portion 132 via the insulating layer 140 by ion implantation. As described above, the conductive portion 132 functions as either the source region or the drain region of the transistor Tr.

[0079] On the other hand, since the same amount of impurities added to the oxide semiconductor layer 135 as are added to the conductive portion 132, the entire oxide semiconductor layer 135 becomes as low-resistance as the conductive portion 132.

[0080] In this embodiment, the upper gate insulating layer between the oxide semiconductor layer 130 and the gate electrode 160 is composed of an insulating layer 140, a metal oxide layer 151, and an insulating layer 170. In other words, since it is not necessary to achieve the breakdown voltage characteristics required for a gate insulating layer of a transistor Tr with only the insulating layer 140, the thickness of the insulating layer 140 can be set to 50 nm to 200 nm (preferably 50 nm to 150 nm, and more preferably 100 nm to 150 nm). In areas other than directly beneath the resist mask 210, the metal oxide layer 150 is removed, so the insulating layer 140 is exposed. In other words, impurities can be added to the oxide semiconductor layer 130 without going through a metal oxide layer with high barrier properties against gases. Thus, in this embodiment, the thickness of the insulating layer 140 can be reduced, and since impurities do not need to pass through a dense metal oxide layer, the dose of impurities can be increased even at a relatively low acceleration voltage. In other words, since a sufficient amount of impurities are added to the oxide semiconductor layer 130 without placing an excessive burden on the manufacturing equipment used for impurity addition, the resistance value of the conductive part 132 can be sufficiently reduced.

[0081] Next, as shown in Figures 3 and 10, the resist mask 210 is removed (step S1009 in Figure 3). By removing the resist mask 210, a metal oxide layer 151, composed of metal oxides, remains on top of the insulating layer 140.

[0082] Next, as shown in Figures 3 and 11, a conductive layer is formed on the insulating layer 140, and conductive layers 203 and 204 are formed by etching the conductive layer using a mask, similar to the metal oxide layer 151 (step S1010 in Figure 3).

[0083] Next, as shown in Figures 3 and 12, an insulating layer 170 is formed on the insulating layer 140, the metal oxide layer 151, and the conductive layers 203 and 204 (step S1011 in Figure 3). As the material constituting the insulating layer 170, any material can be selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon nitride (SiOxNy), or resin, as described above.

[0084] In this embodiment, a silicon oxide layer is formed as the insulating layer 170 using the CVD method. The thickness of the insulating layer 170 is, for example, 200 nm to 500 nm (preferably 350 nm to 450 nm). In this embodiment, a 400 nm silicon oxide layer is formed as the insulating layer 170.

[0085] The film formation temperature for the insulating layer 170 is preferably set to 250°C or more and 500°C or less (preferably 300°C or more and 450°C or less, and more preferably 325°C or more and 400°C or less).

[0086] Next, as shown in Figures 3 and 13, a gate electrode 160 and a conductive layer 162 are formed on the insulating layer 170 (step S1012 in Figure 3). As described above, any material can be selected from aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof, as the gate electrode 160 and the conductive layer 162. The gate electrode 160 and the conductive layer 162 may be a single-layer structure or a laminated structure. In this embodiment, a laminated structure composed of titanium and a molybdenum-tungsten alloy is formed as the gate electrode 160 and the conductive layer 162 using a sputtering method.

[0087] Next, as shown in Figures 3 and 14, an insulating layer 190 is formed on the insulating layer 170, on the gate electrode 160, and on the conductive layer 162 (step S1013 in Figure 3). As the material constituting the insulating layer 190, any material can be selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxide nitride (SiOxNy), or resin, as described above.

[0088] In this embodiment, a laminated structure consisting of a silicon oxide layer and a silicon nitride layer is formed as the insulating layer 190 using the CVD method. In this embodiment, the thickness of the silicon oxide layer formed on the lower side of the insulating layer 190 is 100 nm, and the thickness of the silicon nitride layer formed on the upper side of the insulating layer 190 is 300 nm. That is, the thickness of the insulating layer 190 in this embodiment is 400 nm. However, the thickness of the insulating layer 190 is not limited to this example and may be thicker or thinner than the above thickness.

[0089] The film formation temperature for the insulating layer 190 is set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0090] The insulating layer 190 functions as a passivation layer (protective layer) to prevent gas and moisture from entering from the outside. As described above, the insulating layer 190 also plays a role in insulating and separating the terminal electrode 181 from the conductive portion 132 of the oxide semiconductor layer 130. Furthermore, in this embodiment, since a silicon nitride layer is used in part of the insulating layer 190, the insulating layer 190 helps to reduce the resistance of the conductive portion 132.

[0091] When a silicon nitride layer is formed by the CVD method, ammonia is used as the raw material gas, so the silicon nitride layer contains a large amount of hydrogen. Therefore, when the insulating layer 190 is formed and after the insulating layer 190 is formed, hydrogen diffuses from the silicon nitride layer when the insulating layer 190 is heated. The diffused hydrogen reaches the conductive portion 132 and oxide semiconductor layer 135 via the silicon oxide layer and insulating layers 140 and 170 on the lower side of the insulating layer 190. At this time, the hydrogen is trapped in the oxygen vacancies formed inside the conductive portion 132 and oxide semiconductor layer 135 by the ion implantation described above, and a donor level is formed. This promotes the reduction of resistance of the conductive portion 132 and oxide semiconductor layer 135. In this case, the metal oxide layer 151 functions as a barrier layer that suppresses the movement of hydrogen diffusing from the insulating layer 190 toward the channel portion 131 of the oxide semiconductor layer 130.

[0092] Next, as shown in Figures 3 and 15, contact holes 171 to 175 are formed in the insulating layers 140, 170, and 190 (step S1014 in Figure 3). Contact hole 171 exposes a portion of the conductive portion 132. In this embodiment, since the metal oxide layer 150 located directly above the conductive portion 132 is removed, there is an advantage in that the formation of contact hole 171 is easy. Contact hole 172 is formed in the insulating layer 190 and exposes a portion of the conductive layer 162. Contact holes 173 and 174 are formed in the insulating layers 190 and 170 and expose portions of the conductive layers 203 and 204, respectively. Contact hole 175 is formed in the insulating layers 190, 170, and 140 and exposes a portion of the oxide semiconductor layer 135.

[0093] Finally, as shown in Figures 3 and 16, a terminal electrode 181 is formed on the conductive portion 132 exposed by the contact hole 171 (step S1015 in Figure 3). Similarly, a terminal electrode 182 is formed on the conductive layer 162 exposed by the contact hole 172. Terminal electrodes 183 and 184 are formed on the conductive layers 203 and 204 exposed by the contact holes 173 and 174, respectively. A terminal electrode 185 is formed on the oxide semiconductor layer 135 exposed by the contact hole 175. The semiconductor device 10 shown in Figure 1 is completed by the process described above.

[0094] As described above, impurities are added to the oxide semiconductor layer 130 via the insulating layer 140, and after the impurities are added, the insulating layer 170 is formed on top of the insulating layer 140. Therefore, in the second region R2, the insulating layer 140 contains the impurities, but the insulating layer 170 does not. Here, the profiles of the impurities contained in the insulating layer 140 and the insulating layer 170 will be explained using Figures 41 and 42. Figure 41 is a diagram showing the region in which the impurity concentration of a semiconductor device in one embodiment of the present invention was evaluated. Figure 41 is an enlarged view of a part of Figure 1. Figure 42 is a diagram showing the evaluation results of the impurity concentration of a semiconductor device in one embodiment of the present invention. If SIMS analysis is performed in the direction of the dashed arrow in Figure 41, a SIMS profile as shown in Figure 42 is obtained. The horizontal axis of Figure 42 shows the layer in which the impurity concentration was calculated by SIMS analysis. The vertical axis of Figure 42 is the concentration of the impurities calculated by SIMS analysis. The impurities shown in Figure 42 are impurities added to the oxide semiconductor layer 130 to reduce its resistance.

[0095] As shown in Figure 42, near the boundary between insulating layer 140 and insulating layer 170 in the second region R2, the concentration of impurities in insulating layer 140 is more than 100 times that of insulating layer 170. In other words, the average concentration of impurities in the thickness direction of insulating layer 140 is more than 100 times that of insulating layer 170 in the thickness direction.

[0096] In this embodiment, the transistor Tr can use an insulating layer with a thickness of 200 nm or more (preferably 300 nm or more) as the gate insulating layer 110, and an insulating layer with a thickness of 250 nm or more (preferably 350 nm or more) can be used as the upper gate insulating layer (insulating layer 140, metal oxide layer 151, and insulating layer 170), thereby ensuring sufficient breakdown voltage characteristics of the gate insulating layers above and below the oxide semiconductor layer 130. When the conductive portion 132 is formed on the oxide semiconductor layer 130, the oxide semiconductor layer 130 becomes less resistive by adding impurities via the insulating layer 140, thereby suppressing damage to the oxide semiconductor layer 130 (especially damage to the channel portion 131). At this time, since the thickness of the insulating layer 140 is 200 nm or less (preferably 150 nm or less), the resistance value of the conductive portion 132 can be sufficiently reduced by adding a sufficient amount of impurities while suppressing the load on the equipment used for impurity addition. As described above, according to this embodiment, the reliability of the transistor Tr containing an oxide semiconductor can be improved.

[0097] In this embodiment, since the gate insulating layer of the transistor Tr is composed of a stack of insulating layers 140 and 170, conductive layers 203 and 204 can be formed between the oxide semiconductor layer 130 and the gate electrode 160. By using these conductive layers 203 and 204 as electrodes for capacitive elements C1 and C2, a large capacitance can be secured even in a small area. In this embodiment, a configuration in which conductive layers 203 and 204 are used as electrodes for capacitive elements C1 and C2 is illustrated, but the embodiment is not limited to this configuration. For example, conductive layers 203 and 204 may be used as wiring.

[0098] [1-4. Transistor Mobility] In this specification, "field-effect mobility" refers to the field-effect mobility in the saturation region of a transistor Tr, and means the maximum value of the field-effect mobility in the region where the potential difference between the source and drain (Vd) is greater than the value obtained by subtracting the threshold voltage of the transistor Tr (Vth) from the voltage supplied to the gate (Vg) (Vg-Vth).

[0099] [1-5. Modification 1 of the First Embodiment] In the semiconductor device 10 described above, an example was shown in which the metal oxide layer 150 is etched to form a patterned metal oxide layer 151, but the metal oxide layer 150 may remain unpatterned.

[0100] Figure 17 is a schematic cross-sectional view showing the configuration of a semiconductor device 10a in a modified example of one embodiment of the present invention. In this modified semiconductor device 10a, the metal oxide layer 150 remains on top of the insulating layer 140 without being patterned. That is, in a plan view, the metal oxide layer 150 is superimposed not only on the channel portion 131 of the oxide semiconductor layer 130 but also on the conductive portion 132. In other words, the metal oxide layer 150 is provided in both the first region R1 and the second region R2.

[0101] As shown in Figure 17, in semiconductor device 10a, conductive layers 203 and 204 are provided on top of the metal oxide layer 150.

[0102] In the semiconductor device 10a of this modified example, the metal oxide layer 150 functions as a barrier layer that suppresses hydrogen diffused from above from reaching the oxide semiconductor layer 130, similar to the metal oxide layer 151 shown in Figure 1.

[0103] [1-6. Modification 2 of the First Embodiment] In the semiconductor device 10 described above, an example was shown in which a patterned metal oxide layer 151 is formed by etching the metal oxide layer 150. However, the metal oxide layer 150 may be removed by etching without being patterned.

[0104] Figure 18 is a schematic cross-sectional view showing the configuration of a semiconductor device 10b in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 10b includes a step in which, after the oxide annealing shown in step S1005 of Figure 3, the metal oxide layer 150 formed on the insulating layer 140 is completely removed by etching. In other words, in this modified example, neither the metal oxide layer 151 shown in Figure 1 nor the metal oxide layer 150 shown in Figure 17 exists on the insulating layer 140.

[0105] According to this modified example, in the impurity addition process to the oxide semiconductor layer 130 shown in S1008 of Figure 3, even if the acceleration voltage is set to a low level, a sufficiently large dose of impurities can be added. According to this modified example, the formation of contact holes 171-175 in the insulating layers 140, 170, and 190 shown in S1014 of Figure 3 can be easily performed.

[0106] [2. Second Embodiment] In this embodiment, a semiconductor device 20 with a different oxide semiconductor layer 130 configuration from the semiconductor device 10 of the first embodiment will be described. In the description of this embodiment, elements identical to those in the first embodiment will be indicated in the drawings using the same reference numerals and their descriptions may be omitted.

[0107] In this embodiment, the configuration and manufacturing method of the capacitive element Cap are the same as in Figures 1 and 3. Therefore, in the following description and drawings, the capacitive element Cap is omitted, and only the transistor Tr is shown.

[0108] [2-1. Semiconductor device configuration] Figure 19 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 in one embodiment of the present invention. The difference from the semiconductor device 10 shown in Figure 1 is that an LDD portion 134 is provided in the oxide semiconductor layer 130. "LDD" is an abbreviation for "Light Doped Drain". In other words, the LDD portion 134 refers to a portion that has a lower resistance value than the channel portion 131 and a higher resistance value than the conductive portion 132. As shown in Figure 19, the LDD portion 134 is arranged between the channel portion 131 and the conductive portion 132. In other words, the oxide semiconductor layer 130 of this embodiment has a structure in which the channel portion 131, the LDD portion 134, and the conductive portion 132 are continuous in the D1 direction.

[0109] The metal oxide layer 151, composed of a metal oxide, is superimposed on the channel portion 131 and the LDD portion 134. In this embodiment, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the edge 134a of the LDD portion 134 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the boundary between the LDD portion 134 and the conductive portion 132 coincide in the vertical direction. Thus, in this embodiment, in the D1 direction, the width of the metal oxide layer 151 is wider than the width of the channel portion 131, which is effective in effectively enabling the function of the metal oxide layer 151 described above (the function of suppressing hydrogen diffused from above from reaching the channel portion 131 of the oxide semiconductor layer 130). However, the embodiment is not limited to this configuration, and the metal oxide layer 151 does not have to be superimposed on the LDD portion 134.

[0110] Other effects of the semiconductor device 20 of this embodiment are the same as those of the semiconductor device 10 of the first embodiment.

[0111] [2-2. Method for Manufacturing Semiconductor Devices] Next, a method for manufacturing the semiconductor device 20 in one embodiment of the present invention will be described. Figure 20 is a sequence diagram showing the method for manufacturing the semiconductor device 20 in one embodiment of the present invention. Figures 21 to 22 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 20 in one embodiment of the present invention.

[0112] In the manufacturing method of the semiconductor device 20 of this embodiment, steps S1001 to S1008 shown in Figure 20 are the same as steps S1001 to S1008 shown in Figure 3 of the first embodiment. The manufacturing method of this embodiment differs from the manufacturing method of the first embodiment in that steps S1201 and S1202 shown in Figure 20 are added between steps S1008 and S1009 shown in Figure 3.

[0113] First, similar to the first embodiment, the conductive portion 132 is formed by adding impurities to the oxide semiconductor layer 130 in steps S1001 to S1008 of Figure 3. Next, as shown in Figures 21 and 22, the resist mask 210 is subjected to an ashing process in an oxidizing atmosphere (step S1201 in Figure 20). As a result of the ashing process, the width of the resist mask 210 in the D1 direction is narrowed, and a portion of the upper surface of the metal oxide layer 151 is exposed.

[0114] Next, as shown in Figures 20 and 22, ion implantation is performed from above the resist mask 210, and a second impurity is added to the oxide semiconductor layer 130 (step S1202 in Figure 20). The impurities added are the same as those added in step S1008 of Figure 20 (phosphorus, boron, argon, etc.).

[0115] The ion implantation conditions may be the same as or different from those in step S1008 in Figure 20. In this embodiment, similar to step S1008, the acceleration voltage is 30 keV and the dose is 1 × 10⁻⁶ 13 / cm 2 As shown in Figure 22, in this embodiment, the LDD portion 134 is formed at the end of the channel portion 131 in the D1 direction (the portion that does not overlap with the resist mask 210) by the second impurity addition. At this time, since the impurity is added to the LDD portion 134 via the metal oxide layer 151 and the insulating layer 140, even if the impurity is added under the same conditions as in step S1008, the amount of impurity added will be less than that of the conductive portion 132. In other words, the resistance value of the LDD portion 134 will be higher than the resistance value of the conductive portion 132. However, the dose amount in step S1202 may be less than the dose amount in step S1008.

[0116] Here, as shown in Figure 8, since the metal oxide layer 151 is not formed on the oxide semiconductor layer 135, the same amount of impurities as in the conductive portion 132 are added to the oxide semiconductor layer 135.

[0117] After the LDD section 134 is formed through the above process, the semiconductor device 20 shown in Figure 19 is completed by following steps S1009 to S1015 shown in Figure 20. Steps S1009 to S1015 shown in Figure 20 are the same as steps S1009 to S1015 shown in Figure 3 of the first embodiment.

[0118] [2-3. Modified Examples of the Second Embodiment] In the semiconductor device 20 described above, an example was shown in which the process shown in Figure 22 is performed without processing the metal oxide layer 151 after the resist mask 210 has been subjected to an ashing process. However, a portion of the metal oxide layer 151 may be removed using the resist mask 210 as a mask. That is, in Figure 21, the portion exposed from the resist mask 210 may be removed by etching the edge of the metal oxide layer 151 using the resist mask 210 as a mask.

[0119] In this modified example, in the process shown in Figure 22, impurities are added to the LDD section 134 via the insulating layer 140. In other words, since the metal oxide layer 151 is not superimposed on the LDD section 134, if impurities are added under the same conditions as in S1008 of Figure 20, the LDD section 134 will not be formed. Therefore, in this modified example, during the second impurity addition (step S1202 in Figure 20), the amount of impurities added to the LDD section 134 is adjusted by lowering the acceleration voltage and dose amount compared to the first impurity addition process (step S1008 in Figure 20).

[0120] [3. Third Embodiment] In the first embodiment, an example was shown in which the oxide semiconductor layer 130 was provided in contact with the gate insulating layer 110. However, in this embodiment, a metal oxide layer is provided between the gate insulating layer 110 and the oxide semiconductor layer 130. In the description of this embodiment, elements identical to those in the first embodiment may be indicated in the drawings using the same reference numerals and their descriptions may be omitted.

[0121] Figure 23 is a schematic cross-sectional view showing the configuration of a semiconductor device 30 in one embodiment of the present invention. The basic structure is the same as that of the semiconductor device 10 shown in Figure 1, but in the semiconductor device 30 of this embodiment, a metal oxide layer 120 is arranged between the gate insulating layer 110 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 120 is made of a metal oxide mainly composed of aluminum (specifically, an aluminum oxide layer). The metal oxide layer 120 is formed, for example, by a sputtering method.

[0122] As shown in Figure 23, in this embodiment, the metal oxide layer 120 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, after step S1001 in Figure 3 is performed, the metal oxide layer 120 and the oxide semiconductor layer 130 are continuously deposited. Then, the processes in steps S1002 and S1003 in Figure 3 are performed to form the oxide semiconductor layer 130. Furthermore, by etching the oxide semiconductor layer 130 and the metal oxide layer 120, a metal oxide layer 120 having the same pattern shape as the oxide semiconductor layer 130 is formed.

[0123] The thickness of the metal oxide layer 120 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 120 is 3 nm. In this embodiment, the aluminum oxide layer used as the metal oxide layer 120 has high barrier properties against gas even with a thickness of 1 nm to 10 nm. Therefore, the metal oxide layer 120 in this embodiment blocks hydrogen and oxygen released from the gate insulating layer 110 and suppresses hydrogen and oxygen released from below from reaching the oxide semiconductor layer 130. By blocking hydrogen released from the gate insulating layer 110 with the metal oxide layer 120, the reduction reaction of the oxide semiconductor layer 130 is suppressed.

[0124] After the oxide semiconductor layer 130 is formed, during various manufacturing processes (such as patterning), more oxygen vacancies are formed on the upper side of the oxide semiconductor layer 130 than on the lower side. In other words, the oxygen vacancies in the oxide semiconductor layer 130 are distributed non-uniformly in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen vacancies formed on the upper side of the oxide semiconductor layer 130, an excess of oxygen will be supplied to the lower side of the oxide semiconductor layer 130. As a result, the excess oxygen may form defect levels different from oxygen vacancies, which may cause phenomena such as characteristic fluctuations in reliability tests or a decrease in field-effect mobility. Therefore, by blocking the oxygen released from the gate insulating layer 110 with the metal oxide layer 120, the excess oxygen supply to the lower side of the oxide semiconductor layer 130 is suppressed.

[0125] Thus, in this embodiment, when performing the oxide annealing shown in step S1005 of Figure 3, the supply of oxygen to the lower surface of the oxide semiconductor layer 130, which has a small amount of oxygen vacancy, is suppressed, while oxygen is supplied to the upper and side surfaces of the oxide semiconductor layer 130, which has a relatively large amount of oxygen vacancy. Therefore, during oxide annealing, oxygen is efficiently supplied to the oxide semiconductor layer 130, improving the reliability of the semiconductor device 30.

[0126] In this embodiment, an example in which the metal oxide layer 120 is applied to the semiconductor device 10 shown in Figure 1 of the first embodiment has been described, but the metal oxide layer 120 may be applied to other semiconductor devices.

[0127] [4. Fourth Embodiment] In this embodiment, a semiconductor device 40 with a different layer structure from the semiconductor device 10 of the first embodiment will be described. In the description of this embodiment, elements identical to those in the first embodiment may be indicated in the drawings using the same reference numerals and their descriptions may be omitted.

[0128] [4-1. Semiconductor device configuration] Figure 24 is a schematic cross-sectional view showing the configuration of a semiconductor device 40 in one embodiment of the present invention. The difference between the semiconductor device 40 shown in Figure 24 and the semiconductor device 10 shown in Figure 1 is that a patterned insulating layer 155 is provided on the metal oxide layer 151.

[0129] The insulating layer 155 is provided on top of the metal oxide layer 151. In other words, the metal oxide layer 151 is provided between the insulating layer 140 and the insulating layer 155. The insulating layer 155 is processed into island shapes by patterning an insulating layer such as silicon oxide. The insulating layer 155 functions as a barrier layer that suppresses impurity ions implanted from above from reaching the channel portion 131 of the oxide semiconductor layer 130. For example, if an insulating layer containing a large amount of oxygen or an insulating layer containing a large amount of defects is used as the insulating layer constituting the insulating layer 155, the oxygen or defects will function as hydrogen traps.

[0130] In this embodiment, the metal oxide layer 151 is formed using a resist mask 210 (see Figure 27) used when patterning the insulating layer 155, so the metal oxide layer 151 and the insulating layer 155 have the same pattern shape. In other words, the insulating layer 155, like the metal oxide layer 151, overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as shown by the dashed line in Figure 24, in a cross-sectional view, the position of the edge 155a of the insulating layer 155 and the position of the edge 131a of the channel portion 131 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 155a of the insulating layer 155 and the position of the boundary between the channel portion 131 and the conductive portion 132 coincide in the vertical direction. The insulating layer 155 is sometimes referred to as the "fourth insulating layer". As will be described in detail later, impurities are ion-implanted after the insulating layer 155 is patterned, so the insulating layer 155 contains these impurities.

[0131] The insulating layer 155 contains an insulating oxide. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), etc., can be used as the insulating layer 155. In this embodiment, a silicon oxide layer with a thickness of 100 nm to 400 nm (preferably 100 nm to 300 nm, and more preferably 150 nm to 250 nm) is used as the insulating layer 155. The insulating layer 155 functions as a blocking layer that suppresses the injection of impurities into the channel portion 131 when impurities are added to the oxide semiconductor layer 130.

[0132] In this embodiment, the configuration of the capacitive element Cap is the same as in Figure 1. Therefore, the explanation of the capacitive element Cap is omitted.

[0133] Other effects of the semiconductor device 40 of this embodiment are the same as those of the semiconductor device 10 of the first embodiment.

[0134] [4-2. Method for Manufacturing Semiconductor Devices] Next, a method for manufacturing the semiconductor device 40 in one embodiment of the present invention will be described. Figure 25 is a sequence diagram showing the method for manufacturing the semiconductor device 40 in one embodiment of the present invention. Figures 26 to 29 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 40 in one embodiment of the present invention.

[0135] In the manufacturing method of the semiconductor device 40 of this embodiment, steps S1001 to S1005 shown in Figure 25 are the same as steps S1001 to S1005 shown in Figure 3 of the first embodiment. The manufacturing method of this embodiment differs from the manufacturing method of the first embodiment in that steps S1401 to S1404 shown in Figure 25 are performed instead of steps S1006 to S1009 shown in Figure 3.

[0136] First, as in the first embodiment, oxygen is supplied to the oxide semiconductor layer 130 in the state in which the metal oxide layer 150 has been formed by steps S1001 to S1005 in Figure 3. Next, as shown in Figures 25 and 26, an insulating layer 154 is formed on the metal oxide layer 150, and then a resist mask 210 is formed on the insulating layer 154 (step S1401 in Figure 25). In this embodiment, a silicon oxynitride (SiOxNy) layer is used as the insulating layer 154.

[0137] Since the insulating layer 154 is a silicon oxidizide layer, setting the film deposition temperature relatively low allows the insulating layer 154 to contain a relatively large amount of oxygen. This increase in oxygen content in the insulating layer 154 allows for a sufficient supply of oxygen to the oxide semiconductor layer 130 during the oxide annealing process, and effectively suppresses hydrogen diffusion from above into the oxide semiconductor layer 130. The film deposition temperature for the insulating layer 154 is set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0138] The resist mask 210 is positioned to overlap with the oxide semiconductor layer 130. As will be described later, the portion of the oxide semiconductor layer 130 that overlaps with the resist mask 210 corresponds to the portion where the channel portion 131 is formed. As shown in Figure 2, the resist mask 210 is positioned to intersect with the oxide semiconductor layer 130 in the second direction.

[0139] Next, as shown in Figures 25 and 27, the metal oxide layer 151 and the insulating layer 155 are formed by etching the metal oxide layer 150 and the insulating layer 154 using the resist mask 210 as a mask (step S1402 in Figure 25). The etching of the metal oxide layer 150 and the insulating layer 154 may be wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0140] When the insulating layer 154 is etched, it is preferable that the selectivity between the metal oxide layer 150 and the insulating layer 154 is large. If the selectivity is large, the metal oxide layer 150 can be used as an etching stopper in the etching of the insulating layer 154. In this case, after the insulating layer 154 is etched, the etchant or etching gas is changed and the metal oxide layer 150 is etched. It is preferable that the selectivity between the insulating layer 140 and the metal oxide layer 150 is large with respect to the etching conditions for the metal oxide layer 150.

[0141] Next, as shown in FIGS. 25 and 28, the resist mask 210 is removed (step S1403 in FIG. 25). By removing the resist mask 210, the metal oxide layer 15 and the insulating layer 155 remain on the insulating layer 140.

[0142] Next, as shown in FIGS. 25 and 29, ion implantation is performed from above the insulating layer 155, and impurities are added to the oxide semiconductor layers 130 and 135 (step S1404 in FIG. 25). As the impurities, phosphorus, boron, argon, etc. are used. The purpose of adding the impurities is to increase the conductivity by forming oxygen deficiencies in a part of the region of the oxide semiconductor layer 130 and the oxide semiconductor layer 135. Therefore, it is preferable that an element having a large atomic radius is used as the impurity. In this embodiment, an example in which impurities are added by ion implantation is shown, but impurities may be added by ion doping. In this embodiment, boron is added by ion implantation. The conditions for ion implantation in this embodiment are that the acceleration voltage is 30 keV and the dose amount is 1×10 15 / cm 2 However, it is not limited to this example.

[0143] After forming the conductive portion 132 and the low-resistance oxide semiconductor layer 135 through the above process, the semiconductor device 40 shown in FIG. 24 is completed through steps S1010 to S1015 shown in FIG. 25. Steps S1010 to S1015 shown in FIG. 25 are the same as steps S1010 to S1015 shown in FIG. 3 of the first embodiment.

[0144] [4-3. Modification 1 of the fourth embodiment] In the semiconductor device 40 described above, an example was shown in which the metal oxide layer 150 is etched to form a patterned metal oxide layer 151, but the metal oxide layer 150 may remain unpatterned.

[0145] Figure 30 is a schematic cross-sectional view showing the configuration of a semiconductor device 40a in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 40a has a metal oxide layer 150 remaining on top of the insulating layer 140 without being patterned. That is, in a plan view, the metal oxide layer 150 is superimposed not only on the channel portion 131 of the oxide semiconductor layer 130 but also on the conductive portion 132. In other words, the metal oxide layer 150 is provided not only between the insulating layer 140 and the insulating layer 155 in the first region R1, but also between the insulating layer 140 and the insulating layer 170 in the second region R2.

[0146] As shown in Figure 30, in semiconductor device 40a, conductive layers 203 and 204 are provided on top of the metal oxide layer 150.

[0147] In the semiconductor device 40a of this modified example, the metal oxide layer 150 functions as a barrier layer that suppresses hydrogen diffused from above from reaching the oxide semiconductor layer 130, similar to the metal oxide layer 151 shown in Figure 24.

[0148] [4-4. Modification 2 of the fourth embodiment] In the semiconductor device 40 described above, an example was shown in which a patterned metal oxide layer 151 is formed by etching the metal oxide layer 150. However, the metal oxide layer 150 may be removed by etching without being patterned.

[0149] Figure 31 is a schematic cross-sectional view showing the configuration of a semiconductor device 40b in a modified example of one embodiment of the present invention. In this modified example, the semiconductor device 40b includes a step in which, after the annealing shown in step S1005 of Figure 25, the metal oxide layer 150 formed on the insulating layer 140 is completely removed by etching. In other words, in this modified example, neither the metal oxide layer 151 shown in Figure 24 nor the metal oxide layer 150 shown in Figure 30 exists on the insulating layer 140.

[0150] According to this modified example, in the impurity addition process to the oxide semiconductor layer 130 shown in S1404 of Figure 25, even if the acceleration voltage is set to a low level, a sufficiently large dose of impurities can be added. According to this modified example, the formation of contact holes 171-175 in the insulating layers 140, 170, and 190 shown in S1014 of Figure 24 can be easily performed.

[0151] [5. Fifth Embodiment] In this embodiment, a semiconductor device 50 with a different oxide semiconductor layer 130 configuration from the semiconductor device 40 of the fourth embodiment will be described. In the description of this embodiment, elements identical to those in the fourth embodiment may be indicated in the drawings using the same reference numerals and their descriptions may be omitted.

[0152] In this embodiment, the configuration and manufacturing method of the capacitive element Cap are the same as in Figures 24 and 25. Therefore, in the following description and drawings, the capacitive element Cap is omitted, and only the transistor Tr is shown.

[0153] [5-1. Semiconductor device configuration] Figure 32 is a schematic cross-sectional view showing the configuration of a semiconductor device 50 in one embodiment of the present invention. The difference from the semiconductor device 40 shown in Figure 24 is that an LDD portion 134 is provided in the oxide semiconductor layer 130. As shown in Figure 32, the LDD portion 134 is arranged between the channel portion 131 and the conductive portion 132. In other words, the oxide semiconductor layer 130 of this embodiment has a structure in which the channel portion 131, the LDD portion 134 and the conductive portion 132 are continuous in the D1 direction.

[0154] The metal oxide layer 151, composed of a metal oxide, is superimposed on the channel portion 131 and the LDD portion 134. In this embodiment, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the edge 134a of the LDD portion 134 coincide in the vertical direction. In other words, in a cross-sectional view, the position of the edge 151a of the metal oxide layer 151 and the position of the boundary between the LDD portion 134 and the conductive portion 132 coincide in the vertical direction. Thus, in this embodiment, in the D1 direction, the width of the metal oxide layer 151 is wider than the width of the channel portion 131, which is effective in effectively enabling the function of the metal oxide layer 151 described above (the function of suppressing hydrogen diffused from above from reaching the channel portion 131 of the oxide semiconductor layer 130). However, the embodiment is not limited to this configuration, and the metal oxide layer 151 does not have to be superimposed on the LDD portion 134.

[0155] Other effects of the semiconductor device 50 of this embodiment are the same as those of the semiconductor device 40 of the fourth embodiment.

[0156] [5-2. Method for Manufacturing Semiconductor Devices] Next, a method for manufacturing the semiconductor device 50 in one embodiment of the present invention will be described. Figure 33 is a sequence diagram showing the method for manufacturing the semiconductor device 50 in one embodiment of the present invention. Figures 34 to 36 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 50 in one embodiment of the present invention.

[0157] In the manufacturing method of the semiconductor device 50 of this embodiment, steps S1001 to S1005 and steps S1401 to S1402 shown in Figure 33 are the same as steps S1001 to S1005 and steps S1401 to S1402 shown in Figure 25 of the fourth embodiment. The manufacturing method of this embodiment differs from the manufacturing method of the fourth embodiment in that steps S1501 to S1504 shown in Figure 33 are performed instead of steps S1403 to S1404 shown in Figure 25.

[0158] First, similar to the fourth embodiment, as shown in Figure 27, the metal oxide layer 151 and the insulating layer 155 are formed by etching the metal oxide layer 150 and the insulating layer 154 using the resist mask 210 as a mask in steps S1001 to S1005 and steps S1401 to S1402 of Figure 25. In this embodiment, the conductive portion 132 is formed by adding impurities to the oxide semiconductor layer 130 in this state (step S1501 in Figure 33). The ion implantation conditions in step S1501 may be the same as or different from those in step S1404 of Figure 25. In this embodiment, similar to step S1404, the acceleration voltage is 30 keV and the dose is 1 × 10⁻⁶ 15 / cm 2 That is the case.

[0159] After the conductive portion 132 is formed, the resist mask 210 is subjected to an ashing process in an oxidizing atmosphere, as shown in Figures 33 and 34 (step S1502 in Figure 33). The ashing process narrows the width of the resist mask 210 in the D1 direction.

[0160] Next, as shown in Figures 33 and 35, the insulating layer 155 is etched through the resist mask 210. The etching of the insulating layer 155 may be wet etching or dry etching. By etching the insulating layer 155, a portion of the upper surface of the metal oxide layer 151 is exposed.

[0161] Next, as shown in Figures 33 and 36, ion implantation is performed from above the resist mask 210 to add impurities to the oxide semiconductor layer 130 for the second time (step S1503 in Figure 33). The impurities added are the same as those added in step S1501 in Figure 33 (phosphorus, boron, argon, etc.).

[0162] The ion implantation conditions may be the same as or different from those in step S1501 in Figure 33. In this embodiment, similar to step S1501, the acceleration voltage is 30 keV and the dose is 1 × 10⁻⁶15 / cm 2 As shown in Figure 36, in this embodiment, the LDD portion 134 is formed at the end of the channel portion 131 in the D1 direction (the portion that does not overlap with the resist mask 210) by the second impurity addition. At this time, since the impurities are added to the LDD portion 134 via the metal oxide layer 151 and the insulating layer 140, even if the impurities are added under the same conditions as in step S1501, the amount of impurities added will be less than that of the conductive portion 132. In other words, the resistance value of the LDD portion 134 will be higher than the resistance value of the conductive portion 132.

[0163] Here, as shown in Figure 29, since the metal oxide layer 151 is not formed on the oxide semiconductor layer 135, the same amount of impurities as in the conductive portion 132 are added to the oxide semiconductor layer 135.

[0164] After forming the LDD section 134 through the above process, the semiconductor device 50 shown in Figure 32 is completed by following steps S1010 to S1015 shown in Figure 33. Steps S1010 to S1015 shown in Figure 33 are the same as steps S1010 to S1015 shown in Figure 25 of the fourth embodiment.

[0165] [6. Sixth Embodiment] This embodiment describes a display device 500 using a semiconductor device 10 according to one embodiment of the present invention. In the embodiments described below, a configuration in which the semiconductor device 10 described in the first embodiment is used as an element constituting the circuit of a liquid crystal display device will be described. However, the invention is not limited to this example, and semiconductor devices described in the second to fifth embodiments may be used as elements constituting the circuit of a liquid crystal display device. The semiconductor device may also be used as an element constituting the circuit of another display device, such as an organic EL display device, instead of as an element constituting the circuit of a liquid crystal display device.

[0166] [6-1. Overview of Display Devices] Figure 37 is a schematic plan view showing the overall configuration of a display device 500 in one embodiment of the present invention. As shown in Figure 37, the display device 500 has an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. Multiple pixels 51 are arranged in a matrix in the liquid crystal area 52 surrounded by the sealing portion 310. That is, the display area is formed by multiple pixels 51 arranged side by side in the X and Y directions, respectively. The liquid crystal area 52 is the area that overlaps with the liquid crystal element 311, which will be described later, in a plan view. With respect to the pixels 51, the letters "R", "G", and "B" indicate that they correspond to pixels for red display, pixels for green display, and pixels for blue display, respectively.

[0167] The sealing region 54, where the sealing portion 310 is provided, is the area surrounding the liquid crystal region 52. The flexible printed circuit board 330 is provided in the terminal region 56. The terminal region 56 is the area of ​​the array substrate 300 that is exposed from the opposing substrate 320 and is provided outside the sealing region 54. The area outside the sealing region 54 means the area outside where the sealing portion 310 is provided and the area enclosed by the sealing portion 310. The IC chip 340 is provided on the flexible printed circuit board 330. The IC chip 340 supplies signals to drive each pixel circuit 301 (see Figure 38) arranged in each pixel 51.

[0168] [6-2. Circuit Configuration of Display Devices] Figure 38 is a block diagram showing the circuit configuration of a display device 500 in one embodiment of the present invention. As shown in Figure 38, a plurality of pixel circuits 301 are arranged in a matrix corresponding to each pixel 51 shown in Figure 37. A source driver circuit 302 is provided at a position adjacent to the liquid crystal area 52 in the Y direction (column direction) with respect to the liquid crystal area 52 where the pixel circuits 301 are arranged. A gate driver circuit 303 is provided at a position adjacent to the liquid crystal area 52 in the X direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the seal area 54. However, the area in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the seal area 54, but can be anywhere outside the area in which the pixel circuits 301 are provided.

[0169] A data signal line 304 extends from the source driver circuit 302 in the Y direction and is connected to multiple pixel circuits 301 arranged in the Y direction. A scan signal line 305 extends from the gate driver circuit 303 in the X direction and is connected to multiple pixel circuits 301 arranged in the X direction.

[0170] A terminal section 306 is provided in the terminal area 56. The terminal section 306 and the source driver circuit 302 are connected by a connecting wire 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connecting wire 308. By connecting the flexible printed circuit board 330 to the terminal section 306, the display device 500 is connected to an external device via the flexible printed circuit board 330. Each pixel circuit 301 provided in the display device 500 is driven by a signal from an external device input via the flexible printed circuit board 330.

[0171] The transistor Tr shown in the first embodiment is used as a switching element or current control element included in the pixel circuit 301, source driver circuit 302, and gate driver circuit 303. The capacitive element Cap is used as a capacitive element included in the above circuit.

[0172] [6-3. Pixel Circuits of Display Devices] Figure 39 is a circuit diagram showing the configuration of a pixel circuit 301 of a display device 500 in one embodiment of the present invention. As shown in Figure 39, the pixel circuit 301 includes elements such as a switching element 410, a holding capacitor 420, and a liquid crystal element 311.

[0173] The switching element 410 is composed of a transistor Tr according to the first embodiment. The switching element 410 has a gate electrode 411, a source electrode 412, and a drain electrode 413. The gate electrode 411 is connected to the scan signal line 305. However, the gate electrode 411 and the scan signal line 305 may be formed from a single conductive layer. The source electrode 412 is connected to the data signal line 304. However, the source electrode 412 and the data signal line 304 may be formed from a single conductive layer.

[0174] The drain electrode 413 is connected to the holding capacitor 420 and the liquid crystal element 311. The roles of the source electrode 412 and the drain electrode 413 may be reversed depending on the relationship between the voltage supplied to the data signal line 304 and the voltage stored in the holding capacitor 420. That is, the source electrode 412 may function as the drain electrode, and the drain electrode 413 may function as the source electrode.

[0175] The retaining capacitance 420 is composed of the capacitive element Cap of the first embodiment. The retaining capacitance 420 may consist only of the capacitive element C1, or only of the capacitive element C2, or of both the capacitive elements C1 and C2.

[0176] [6-4. Pixel structure of display devices] Figure 40 is a cross-sectional view showing the pixel structure of a display device 500 in one embodiment of the present invention. In the display device 500, the transistor Tr described in the first embodiment is used as the switching element 410 included in the pixel circuit 301. In the following description, the configuration of the transistor Tr is the same as that of the transistor Tr shown in Figure 1, so a detailed explanation will be omitted.

[0177] An insulating layer 360 is provided on the terminal electrode 181 of the transistor Tr. For example, acrylic resin is used as the insulating layer 360. A common electrode 370, which is provided in common to multiple pixels, is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. For example, a silicon nitride layer is used as the insulating layer 380. Contact holes 381 are provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380, which is connected to the terminal electrode 181 via the contact hole 381.

[0178] A transparent conductive layer is used as the common electrode 370 and the pixel electrode 390. In this embodiment, ITO (Indium Tin Oxide) is used as the material for the transparent conductive layer constituting the common electrode 370 and the pixel electrode 390, but other metal oxide layers may be used. The common electrode 370 is composed of a flat transparent conductive layer. Although not shown in Figure 40, the pixel electrode 390 is composed of a comb-shaped transparent conductive layer that combines a portion extending in the D1 direction and a portion extending in the D2 direction. The portion extending in the D2 direction is composed of multiple linear electrodes, each connected to an electrode corresponding to a trunk extending in the D1 direction.

[0179] A liquid crystal layer 311a is sealed between the active matrix substrate, on which the pixel electrodes 390 are formed on the substrate 100, and the opposing substrate 320. The liquid crystal layer 311a is arranged across multiple pixels 51. The region where the liquid crystal layer 311a is arranged corresponds to the liquid crystal region 52 shown in Figure 37.

[0180] As shown in Figure 40, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This transverse electric field causes the liquid crystal molecules contained in the liquid crystal layer 311a to act, thereby determining the gradation of light passing through the pixel 51.

[0181] The embodiments described above (including variations of each embodiment) can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on each embodiment, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0182] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0183] 10, 20, 30, 40, 50: Semiconductor device, 51: Pixel, 52: Liquid crystal area, 54: Seal area, 56: Terminal area, 100: Substrate, 105: Gate electrode, 110: Gate insulating layer, 120: Metal oxide layer, 130, 135: Oxide semiconductor layer, 131: Channel area, 131a, 134a: Edge, 132: Conductive area, 134: LDD area, 140: Insulating layer, 150, 151: Metal oxide layer, 151a, 155a: Edge, 154, 155: Insulating layer, 160: Gate electrode, 162: Conductive layer, 170: Insulating layer, 171~175: Contact hole, 181~185: Terminal electrode, 190: Insulating layer, 203, 204: Conductive layer, 210: Resist mask, 300: Array substrate, 301: Pixel circuit, 302: Source driver circuit, 303: Gate driver circuit, 304: Data signal line, 305: Scan signal line, 306: Terminal section, 307, 308: Connection wiring, 310: Seal section, 311: Liquid crystal element, 311a: Liquid crystal layer, 320: Opposing substrate, 330: Substrate, 330: Flexible printed circuit board, 340: Chip, 360: Insulating layer, 370: Common electrode, 380: Insulating layer, 381: Contact hole, 390: Pixel electrode, 410: Switching element, 411: Gate electrode, 412: Source electrode, 413: Drain electrode, 420: Holding capacitance, 500: Display device, C1, C2: Capacitor elements

Claims

1. A first oxide semiconductor layer provided on an insulating surface, having a channel portion and a conductive portion with lower resistance than the channel portion, A first insulating layer on the first oxide semiconductor layer, A second insulating layer on the first insulating layer, A first conductive layer between the first insulating layer and the second insulating layer, The first gate electrode on the second insulating layer, The third insulating layer on the first gate electrode, A second conductive layer is provided on the third insulating layer and is in contact with the conductive portion via contact holes provided in the first insulating layer, the second insulating layer, and the third insulating layer, Semiconductor equipment including

2. The present invention further includes a second oxide semiconductor layer provided between the insulating surface and the first insulating layer, which has a lower resistance than the channel portion. The semiconductor device according to claim 1, wherein a capacitive element is formed by the first conductive layer and the second oxide semiconductor layer.

3. The third conductive layer between the second insulating layer and the third insulating layer is further included. The semiconductor device according to claim 1, wherein a capacitive element is formed by the first conductive layer and the third conductive layer.

4. A second oxide semiconductor layer is provided between the insulating surface and the first insulating layer, and has a lower resistance than the channel portion. A third conductive layer between the second insulating layer and the third insulating layer, The present invention further includes a fourth conductive layer between the first insulating layer and the second insulating layer, The first conductive layer and the second oxide semiconductor layer constitute the first capacitive element. The semiconductor device according to claim 1, wherein the third conductive layer and the fourth conductive layer constitute a second capacitance element.

5. The semiconductor device according to claim 1, further comprising a metal oxide layer mainly composed of aluminum, provided between the first insulating layer and the second insulating layer.

6. If the region overlapping with the channel portion in a plan view is designated as the first region, and the region overlapping with the conductive portion in a plan view is designated as the second region, The semiconductor device according to claim 5, wherein the metal oxide layer is provided in both the first region and the second region.

7. The semiconductor device according to claim 5, wherein, in a cross-sectional view, the position of the edge of the metal oxide layer and the position of the edge of the channel portion coincide in the vertical direction.

8. The fifth insulating layer beneath the first oxide semiconductor layer, The semiconductor device according to claim 1, further comprising a second gate electrode below the fifth insulating layer.

9. The material further includes a fourth insulating layer provided between the first insulating layer and the second insulating layer, The semiconductor device according to claim 1, wherein, in a cross-sectional view, the position of the edge of the fourth insulating layer and the position of the edge of the channel portion coincide in the vertical direction.

10. The amount of impurities contained in the conductive portion is greater than the amount of impurities contained in the channel portion. The semiconductor device according to claim 9, wherein the fourth insulating layer contains the impurity.

11. If the region overlapping with the channel portion in a plan view is designated as the first region, and the region overlapping with the conductive portion in a plan view is designated as the second region, The semiconductor device according to claim 9, further comprising a metal oxide layer mainly composed of aluminum, provided between the first insulating layer and the fourth insulating layer in the first region.

12. The semiconductor device according to claim 11, wherein the metal oxide layer is also provided between the first insulating layer and the second insulating layer in the second region.

13. The fifth insulating layer beneath the first oxide semiconductor layer, The semiconductor device according to claim 9, further comprising a second gate electrode below the fifth insulating layer.

14. A display device comprising a semiconductor device according to any one of claims 1 to 13 for each pixel.

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