Semiconductor equipment

Abstract

To provide semiconductor devices with excellent electrical performance. [Solution] The semiconductor device according to the present invention has a bit line disposed on a substrate and extending in a first horizontal direction, a mold structure disposed on the bit line and extending in a second horizontal direction intersecting the first horizontal direction and including a metal layer, an active semiconductor layer extending vertically from the side wall of the mold structure and including an oxide semiconductor, and a word line disposed on the side wall of the active semiconductor layer and extending in the second horizontal direction, wherein at least a portion of the side wall of the active semiconductor layer is in contact with the metal layer.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a vertical channel transistor. [Background technology]

[0002] The downscaling of semiconductor devices is also reducing the size of DRAM devices. In DRAM devices with a 1T-1C structure, where one capacitor is connected to one transistor, there is a problem in that leakage current through the channel region increases as the device becomes smaller. To reduce leakage current, a vertical channel transistor using an oxide semiconductor material as the channel layer has been proposed. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] The present invention has been made in view of the problems of the above-mentioned conventional semiconductor devices, and the object of the present invention is to provide a semiconductor device with excellent electrical performance. [Means for solving the problem]

[0004] To achieve the above objective, the semiconductor device according to the present invention comprises: a bit line disposed on a substrate and extending in a first horizontal direction; a mold structure disposed on the bit line and extending in a second horizontal direction intersecting the first horizontal direction, and including a metal layer; an active semiconductor layer extending vertically from the side wall of the mold structure and including an oxide semiconductor; and a word line disposed on the side wall of the active semiconductor layer and extending in the second horizontal direction, wherein at least a portion of the side wall of the active semiconductor layer is in contact with the metal layer.

[0005] Furthermore, the semiconductor device according to the present invention, made to achieve the above objective, is characterized by comprising: a bit line disposed on a substrate and extending in a first horizontal direction; a mold structure disposed on the bit line, extending in a second horizontal direction intersecting the first horizontal direction, and including a first insulating layer, a metal layer, and a second insulating layer stacked vertically; an active semiconductor layer extending vertically from the side wall of the mold structure, containing an oxide semiconductor, and in contact with the side wall of the metal layer; a word line disposed on the side wall of the active semiconductor layer and extending in the second horizontal direction; and a cell capacitor disposed on the active semiconductor layer.

[0006] Furthermore, the semiconductor device according to the present invention, made to achieve the above objective, comprises: a peripheral circuit region disposed on a substrate; a plurality of bit lines disposed on the peripheral circuit region and extending in a first horizontal direction; a plurality of mold structures disposed on the plurality of bit lines and extending in a second horizontal direction intersecting the first horizontal direction, each including a first insulating layer, a metal layer, and a second insulating layer stacked vertically; a plurality of active semiconductor layers disposed between two adjacent mold structures among the plurality of mold structures and disposed on the side walls of the two mold structures and on the upper surfaces of each of the plurality of bit lines, each having a U-shaped vertical cross-section; a first word line and a second word line disposed between the two mold structures and extending in the second horizontal direction and spaced apart from each other; and a plurality of cell capacitors disposed on the plurality of active semiconductor layers, wherein at least a portion of each of the plurality of active semiconductor layers is in contact with the metal layer. [Effects of the Invention]

[0007] According to the semiconductor device of the present invention, the molded structure includes a metal layer, and a conductive region is formed within a portion of the active semiconductor layer that is in contact with the sidewall of the metal layer. The conductive region contains a relatively large amount of free electrons, and these free electrons fill the trap sites in the active semiconductor layer, resulting in the active semiconductor layer having a reduced trap density. Therefore, the semiconductor device has a relatively high on-current and excellent electrical performance.

Brief Description of the Drawings

[0008] [Figure 1] It is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2] It is an enlarged layout view of the cell array region portion of FIG. 1. [Figure 3] It is a cross-sectional view taken along the line A1 - A1' of FIG. 2. [Figure 4] It is a cross-sectional view taken along the line A2 - A2' of FIG. 2. [Figure 5] It is an enlarged view of the CX1 portion of FIG. 3. [Figure 6] It is a graph showing a schematic oxygen content according to the line S1 - S2 of FIG. 5. [Figure 7] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 8] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 9] It is a cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 10A] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 10B] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 10C] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 11A] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 11B] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 11C] It is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 12A]This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19A]This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0009] Figure 1 is a perspective view showing a schematic configuration of a semiconductor device 100 according to an embodiment of the present invention; Figure 2 is an enlarged layout view of the cell array region MCA portion of Figure 1; Figure 3 is a cross-sectional view of Figure 2 along the line A1-A1'; Figure 4 is a cross-sectional view of Figure 2 along the line A2-A2'; Figure 5 is an enlarged view of the CX1 portion of Figure 3; and Figure 6 is a graph showing the approximate oxygen content along the line S1-S2 of Figure 5.

[0010] Referring to Figures 1 to 6, the semiconductor device 100 includes a peripheral circuit area PCA and a cell array area MCA located at a vertical level higher than the peripheral circuit area PCA. In one embodiment, the cell array region MCA is the memory cell region of the DRAM device, and the peripheral circuit region PCA is the core region or peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA includes peripheral circuit transistors PTR for transmitting signals and / or power to the memory cell array contained in the cell array region MCA. In one embodiment, the peripheral circuit transistor PTR can constitute a variety of circuits, such as a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, and data input / output circuit.

[0011] Referring to Figure 2, the cell array region MCA contains multiple word lines WL extending along the first horizontal direction X and multiple bit lines BL extending along the second horizontal direction Y. Multiple cell transistors CTR are placed at the intersections of multiple word lines WL and multiple bit lines BL. Multiple cell transistors CTR are each topped with multiple cell capacitors CAP. Multiple word lines WL include a first word line WL1 and a second word line WL2 arranged alternately along a second horizontal direction Y, and multiple cell transistors CTR include a first cell transistor CTR1 and a second cell transistor CTR2 arranged alternately along a second horizontal direction Y. A first cell transistor CTR1 is positioned adjacent to the first word line WL1, and a second cell transistor CTR2 is positioned adjacent to the second word line WL2. The first cell transistor CTR1 and the second cell transistor CTR2 have a mirror-symmetry structure with respect to each other. For example, the first cell transistor CTR1 and the second cell transistor CTR2 have a mirror-symmetry structure with respect to the center line between the first cell transistor CTR1 and the second cell transistor CTR2 that extends along the first horizontal direction X.

[0012] In one embodiment, the pitch of multiple bit lines BL (for example, the sum of the width of one bit line BL and the distance between two adjacent bit lines BL) is 2F, the pitch of the first word line WL1 is 2F (or the pitch of the second word line WL2 is 2F), and the unit area for forming one cell transistor CTR is 4F. 2 That is the case. Therefore, since the cell transistor CTR has a cross-point type which requires a relatively small unit area, it is effective in improving the integration density of the semiconductor device 100. Although not shown in the diagram, edge regions are located around the cell array region (MCA). The edge region is the region where electrical connection members for the word line WL and / or for the bit line BL are arranged, and where electrical connection members that enable electrical connection between the cell array region MCA and the peripheral circuit region PCA are arranged.

[0013] The following describes the case where the cell array region MCA is positioned at a higher vertical level than the peripheral circuit region PCA, as shown in Figures 3 and 4 (for example, when the cell array region MCA is positioned on top of the peripheral circuit region PCA). However, if the semiconductor device 100 is positioned upside down such that the cell array region MCA is located at a higher vertical level than the peripheral circuit region PCA, then in the following description, the "top surface" or "bottom surface" of a component should be understood to mean the "bottom surface" or "top surface" of that component, a component described as being located "above" or "below" another component should be understood as being located "below" or "above" another component, and a component described as being "located at an even higher vertical level" should be understood as being "located at an even lower vertical level."

[0014] The substrate 110 may include silicon, for example, single-crystal silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In one embodiment, the substrate 110 includes conductive regions, such as impurity-doped wells or impurity-doped structures. In the peripheral circuit region PCA, an active region AC is defined on the substrate 110, and peripheral circuit transistors PTR are arranged on the active region AC of the substrate 110. The peripheral circuit transistor PTR includes a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS. A peripheral circuit wiring structure 120 that covers the peripheral circuit transistor PTR is placed on the substrate 110.

[0015] The peripheral circuit wiring structure 120 includes peripheral circuit wiring 122, peripheral circuit contacts 124, and a peripheral circuit insulating layer 126. The peripheral circuit wiring 122 and peripheral circuit contacts 124 are electrically connected to the peripheral circuit transistor PTR and / or the substrate 110, and the peripheral circuit insulating layer 126 covers the peripheral circuit transistor PTR, peripheral circuit wiring 122, and peripheral circuit contacts 124 on the substrate 110. The peripheral circuit insulating layer 126 may include an oxide film, a nitride film, a low dielectric film, or a combination thereof, and consists of a laminated structure of multiple insulating layers. Multiple bit lines BL are arranged on the peripheral circuit region PCA, cell transistors CTR are arranged on the multiple bit lines BL, and cell capacitors CAP are arranged on the cell transistors CTR.

[0016] In one embodiment, a plurality of bit lines BL are extended in the second horizontal direction Y, and a bit line insulating layer 152 and a shielding metal layer SS are arranged in the space between the plurality of bit lines BL. In one embodiment, a shield metal layer SS is placed between two adjacent bit lines BL, and the top surface, bottom surface, and side walls of the shield metal layer SS are covered by a bit line insulating layer 152. In one embodiment, bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or combinations thereof. In one embodiment, the shield metal layer SS may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, Cu, Al, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, or a combination thereof.

[0017] A bit line contact 156 is positioned between the bottom surface of the bit line BL and the peripheral circuit wiring 122, and the side walls of the bit line contact 156 are surrounded by a bit line contact spacer 158. In one embodiment, the bit line contact spacer 158 may be omitted. Multiple molded structures 130 and multiple cell transistors CTR are arranged on the upper surface of bit line BL. For example, multiple molded structures 130 are each extended in a first horizontal direction X, and multiple cell transistors CTR are arranged on both side walls of each molded structure 130. Each of the multiple molded structures 130 includes a first insulating layer 132, a metal layer 134, a second insulating layer 136, and a capping layer 138, all arranged along the vertical direction Z.

[0018] In one embodiment, the first insulating layer 132 and the second insulating layer 136 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant dielectric material. In one embodiment, the capping layer 138 may contain at least one of silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the metal layer 134 may contain at least one of aluminum, titanium, tungsten, copper, molybdenum, ruthenium, tantalum, and cobalt. In one embodiment, the metal layer 134 may further include at least one of titanium nitride, tungsten nitride, molybdenum nitride, ruthenium nitride, tantalum nitride, and cobalt nitride.

[0019] In one embodiment, the cell transistor CTR includes an active semiconductor layer AP, a gate insulating layer GI, and a word line WL, which are sequentially arranged on the side wall of the molded structure 130. In one embodiment, the active semiconductor layer AP includes a portion extending vertically Z from the side wall of the mold structure 130 and a portion extending horizontally Y from the upper surface of the bit line BL. In one embodiment, the active semiconductor layer AP has a U-shaped vertical cross-sectional shape. In one embodiment, the active semiconductor layer AP is made of zinc tin oxide (Zn x Sn y O), Indium zinc oxide (In x Zn y O), zinc oxide (ZnO) x) Indium gallium zinc oxide (In x Ga y Zn z O), indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In x W y O), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc nitride oxide (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr x Zn y Sn z O) and may contain at least one of them. In one embodiment, the active semiconductor layer AP further contains n-type impurity ions. For example, the n-type impurity ions are doped into the active semiconductor layer AP through an ion implantation process or the like.

[0020] As shown in Figure 5, at least a portion of the sidewall of the active semiconductor layer AP is positioned in contact with the sidewall of the metal layer 134 of the mold structure 130. For example, the sidewall of the active semiconductor layer AP is in contact with the sidewall of the first insulating layer 132, the sidewall of the metal layer 134, and the sidewall of the second insulating layer 136. A portion of the active semiconductor layer AP that is in contact with the sidewall of the metal layer 134 is called the conductive region (AP_i). In one embodiment, the conductive region (AP_i) is a region having a lower oxygen content than other regions of the active semiconductor layer AP (e.g., the bulk region of the active semiconductor layer AP). As shown in Figure 5, a portion of the metal layer 134 adjacent to the conductive region (AP_i) of the active semiconductor layer AP is a region where oxygen atoms have migrated or diffused from the conductive region (AP_i) of the active semiconductor layer AP. A portion of the metal layer 134 adjacent to the conductive region (AP_i) of the active semiconductor layer AP is referred to as the insulating region ((134_i)).

[0021] As schematically shown in Figure 6, the bulk region of the metal layer 134 has a primary oxygen content (C_10), which is substantially zero. A first oxygen content (C_10) of substantially zero means that the oxygen content is within the range of oxygen content that inevitably penetrates into the metal layer 134 during the manufacturing process, or within the range of oxygen content that naturally exists inside the metal layer 134, and that no oxygen atoms are intentionally injected or added to such a component. As schematically shown in Figure 6, the insulating region (134_i) of the metal layer 134 has a second oxygen content (C_1m) that is greater than the first oxygen content (C_10). In one embodiment, the second oxygen content (C_1m) is greater than 0 at%, less than 50 at%, or equal to 50 at%. In one embodiment, the second oxygen content (C_1m) is greater than 0 at% and less than or equal to 30 at%, and in other embodiments, the second oxygen content (C_1m) is greater than 0 at% and less than or equal to 20 at%.

[0022] In one embodiment, when the metal layer 134 contains a first metal and the first metal has a chemical formula represented by M, at least a part of the insulating region (134_i) of the metal layer 134 is MO x is represented by a chemical formula of (0 < x ≤ 0.5). The second oxygen content (C_1m) of the insulating region (134_i) varies depending on the selection of the material type of the metal layer 134 and the material type of the active semiconductor layer AP. For example, it can vary depending on the difference in the relative magnitudes of the oxygen bonding strength of the metal layer 134 and the oxygen bonding strength of the active semiconductor layer AP. In one embodiment, the bulk region of the active semiconductor layer AP has a third oxygen content (C_20), and the conductive region (AP_i) of the active semiconductor layer AP has a fourth oxygen content (C_2m) that is less than the third oxygen content (C_20).

[0023] In one embodiment, the metal layer 134 contained in the mold structure 130 functions as a scavenging region that captures oxygen atoms from the active semiconductor layer AP. In a partial region of the active semiconductor layer AP adjacent to the contact interface between the active semiconductor layer AP and the metal layer 134, oxygen atoms move or diffuse into the metal layer 134, whereby the conductive region (AP_i) of the active semiconductor layer AP and the insulating region (134_i) of the metal layer 134 are arranged adjacent to each other. In one embodiment, the upper surface of the metal layer 134 is disposed at a lower vertical level than the upper surface of the active semiconductor layer AP, and the upper surfaces of the metal layer 134, the insulating region (134_i), and the conductive region (AP_i) are all disposed at the same vertical level. For example, the upper surface of the conductive region (AP_i) is separated from the upper surface of the active semiconductor layer AP in the vertical direction Z. In one embodiment, the bottom surface of the metal layer 134 is positioned at a higher vertical level than the bottom surface of the active semiconductor layer AP, and the bottom surface of the metal layer 134, the bottom surface of the insulating region (134_i), and the bottom surface of the conductive region (AP_i) are all positioned at the same vertical level. For example, the bottom surface of the conductive region (AP_i) is separated from the bottom surface of the active semiconductor layer AP in the vertical direction Z.

[0024] A gate insulating layer GI is placed on the sidewall of the active semiconductor layer AP. In one embodiment, the gate insulating layer GI consists of at least one selected from high-k dielectric materials and ferroelectric materials having a higher dielectric constant than silicon oxide. In one embodiment, the gate insulating layer GI is made of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide ( It may contain at least one substance selected from among TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (StTsBiP), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0025] Word lines WL are positioned on the sidewalls of the gate insulation layer GI. In one embodiment, the wordline WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. For example, between two adjacent mold structures 130, two ward lines WL are separated from each other and extended in a first horizontal direction X. For example, between two adjacent mold structures 130, the first word line WL1 and the second word line WL2 are arranged spaced apart from each other. The wordline WL has a rectangular vertical cross-sectional shape. An insulating liner 142 and an embedded insulating layer 144 are placed between the first word line WL1 and the second word line WL2. The insulating liner 142 is conformally arranged on the side walls and top surfaces of the first word line WL1 and the second word line WL2, and is interposed between the word line WL and the embedded insulating layer 144.

[0026] Multiple landing pads (LPs) are placed on each of the multiple cell transistors (CTRs), and a cell capacitor (CAP) is placed on each of the landing pads (LPs). Multiple landing pads (LPs) may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or combinations thereof. As shown in Figure 5, each landing pad LP includes a lower LPb positioned between the molded structure 130 and the active semiconductor layer AP, and an upper LPu positioned at a vertical level higher than the upper surface of the molded structure 130 and the active semiconductor layer AP, and connected to the lower LPb. Cell capacitors (CAPs) have a metal-insulator-metal type capacitor structure. For example, a cell capacitor CAP includes a first electrode, a second electrode, and a capacitor dielectric layer interposed between the first electrode and the second electrode. An insulating layer 176 is placed on the upper surface of the landing pad LP and on at least a portion of the cell capacitor CAP.

[0027] In a comparative example semiconductor device containing an oxide semiconductor channel, the molded structure is made of an insulating material, and an active semiconductor layer is arranged on the sidewall of the molded structure. Because there is a relatively high density of trap sites within the active semiconductor layer, there is a problem in that the on-current of the cell transistor is relatively low. On the other hand, according to an embodiment of the present invention, the molded structure 130 includes a metal layer 134, and a conductive region (AP_i) is formed within a portion of the active semiconductor layer AP that is in contact with the side wall of the metal layer 134. The conductive region (AP_i) contains a relatively large amount of free electrons, and these free electrons fill the trap sites within the active semiconductor layer AP, resulting in the active semiconductor layer AP having a reduced trap density compared to the comparative example. Therefore, the semiconductor device 100 has a relatively high on-current and excellent electrical performance.

[0028] Figure 7 is a cross-sectional view showing a schematic configuration of a semiconductor device 100A according to an embodiment of the present invention. Referring to Figure 7, the molded structure 130 includes a first insulating layer 132, a first metal layer 134a, a second metal layer 134b, a third metal layer 134c, a second insulating layer 136, and a capping layer 138. In one embodiment, the first metal layer 134a and the third metal layer 134c contain the same metallic substance, for example, the first metal, while the second metal layer 134b contains a different metallic substance from the first metal layer 134a and the third metal layer 134c, for example, the second metal. In other embodiments, the first metal layer 134a contains a first metal, the second metal layer 134b contains a second metal different from the first metal, and the third metal layer 134c contains a third metal different from the first and second metals. The constituent materials and thicknesses of the first metal layer 134a, the second metal layer 134b, and the third metal layer 134c vary depending on the required oxygen content profile of the conductive region (AP_i) (see Figure 5) contained within the active semiconductor layer AP.

[0029] In one embodiment, the first metal layer 134a and the third metal layer 134c contain a first metal, the second metal layer 134b contains a second metal, and the first metal contains a substance having even stronger oxygen bonding strength than the second metal. As a result, the oxygen content in the conductive region of the active semiconductor layer AP adjacent to the second metal layer 134b is even lower than the oxygen content in the conductive region of the active semiconductor layer AP adjacent to the first metal layer 134a and the third metal layer 134c, and the conductivity of the conductive region of the active semiconductor layer AP adjacent to the second metal layer 134b is even higher than the conductivity of the conductive region of the active semiconductor layer AP adjacent to the first metal layer 134a and the third metal layer 134c. In other embodiments, the molded structure 130 includes a first metal layer 134a containing a first metal and a second metal layer 134b containing a second metal, and the third metal layer 134c may be omitted. In other embodiments, the molded structure 130 may further include additional metal layers in addition to the first to third metal layers (134a, 134b, 134c).

[0030] Figures 8 and 9 are cross-sectional views showing a schematic configuration of a semiconductor device 100B according to an embodiment of the present invention. Referring to Figures 8 and 9, the peripheral circuit region PCA is attached to the cell array region MCA by a bonding method. In one embodiment, the boundary between the peripheral circuit region PCA and the cell array region MCA is referred to as the bonding interface BIF. For example, a portion of the semiconductor device 100B located at a vertical level lower than the bonding interface BIF shown in Figure 8 is referred to as the peripheral circuit region PCA, and a portion of the semiconductor device 100B located at a vertical level higher than the bonding interface BIF is referred to as the cell array region MCA. In one embodiment, the peripheral circuit wiring structure 120 and the cell wiring structure 160 are in contact with each other via the bonding interface BIF. The cell wiring structure 160 includes a cell wiring layer 162, a cell contact 164, and a cell insulation layer 166.

[0031] A bonding pad BP is placed at the interface between the cell wiring structure 160 and the peripheral circuit wiring structure 120 (for example, at the bonding interface BIF). The bonding pad BP includes a first bonding pad BP1 and a second bonding pad BP2. The upper surface of the first bonding pad BP1 is positioned at the same level as the upper surface of the peripheral circuit insulating layer 126, the lower surface of the second bonding pad BP2 is positioned at the same level as the lower surface of the cell insulating layer 166, and the upper surface of the first bonding pad BP1 is in contact with the lower surface of the second bonding pad BP2. In one embodiment, the cell wiring structure 160 and the peripheral circuit wiring structure 120 are bonded to each other by a metal-oxide hybrid bonding method, in which case the interface between the peripheral circuit insulating layer 126 and the cell insulating layer 166 is coplanar with the interface between the first bonding pad BP1 and the second bonding pad BP2 (for example, the interface between the peripheral circuit insulating layer 126 and the cell insulating layer 166 and the interface between the first bonding pad BP1 and the second bonding pad BP2 are aligned along the bonding interface BIF). In other embodiments, the cell wiring structure 160 and the peripheral circuit wiring structure 120 may be bonded together by oxide bonding, in which case the bonding pad BP may be omitted.

[0032] In one embodiment, the bit line BL is positioned closer to the bonding interface BIF than the cell transistor CTR or the cell capacitor CAP. As a result, the vertical distance between the bit line BL and the peripheral circuit transistor PTR is even smaller than the vertical distance between the cell capacitor CAP and the peripheral circuit transistor PTR. A portion of the shield metal layer SS is positioned to extend in the second horizontal direction Y, filling the space between multiple bit lines BL. The other portion of the shield metal layer SS is positioned between the bottom surface of the multiple bit lines BL and the top surface of the cell wiring structure 160. The side walls and bottom surface of the bit line BL are covered by a first bit line insulating layer 152 and a second bit line insulating layer 154, and the first bit line insulating layer 152 and the second bit line insulating layer 154 are interposed between the side walls of the bit line BL and the shield metal layer SS, and between the bottom surface of the bit line BL and the shield metal layer SS.

[0033] The molded structure 130 and the cell transistor CTR are positioned on the bit line BL. The molded structure 130 includes a capping layer 138, a second insulating layer 136, a metal layer 134, and a first insulating layer 132, which are sequentially arranged on the bit line BL. The active semiconductor layer AP is positioned on the side wall of the mold structure 130 and has a rectangular vertical cross-section. The upper surface of the active semiconductor layer AP is positioned on the same plane as the upper surface of the mold structure 130, and the bit line pad BP is positioned between the bottom surface of the active semiconductor layer AP and the bit line BL. The landing pad LP is positioned on the upper surface of the active semiconductor layer AP and on the upper surface of the molded structure 130.

[0034] In one embodiment, a cell capacitor CAP is formed on a carrier substrate, then a molded structure 130 and a cell transistor CTR are formed on the cell capacitor CAP, and a bit line BL, a shielding metal layer SS, and a cell wiring structure 160 are formed on the molded structure 130 and the cell transistor CTR. Subsequently, peripheral circuit transistors PTR and peripheral circuit wiring structures 120 are formed on the substrate 110, and the carrier substrate and substrate 110 are bonded to each other to form the semiconductor device 100B.

[0035] Figures 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, 17B, 18A, 18B, 19A, and 19B are cross-sectional views illustrating a method for manufacturing a semiconductor device 100 according to an embodiment of the present invention. Figures 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, and 19A are cross-sectional views obtained by cutting along the line A1-A1' in Figure 2; Figures 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, and 19B are cross-sectional views obtained by cutting along the line A2-A2' in Figure 2; and Figures 10C, 11C, 13C, and 15C are plan views corresponding to the cross-sectional views of Figures 10A, 11A, 13A, and 15A, respectively.

[0036] Referring to Figures 10A to 10C, an active region AC is formed on the substrate 110, and peripheral circuit transistors PTR are formed on the active region AC. For example, a peripheral circuit transistor PTR includes a gate electrode PTG, a gate insulating layer PTI, and a source / drain region PTS. Subsequently, peripheral circuit wiring 122 and peripheral circuit contacts 124 that are electrically connected to the substrate 110 and peripheral circuit transistor PTR are formed, and a peripheral circuit insulating layer 126 that covers the peripheral circuit wiring 122 and peripheral circuit contacts 124 is formed on the substrate 110. The peripheral circuit insulating layer 126 is formed using an oxide film, a nitride film, a low dielectric film, or a combination thereof. Subsequently, a bit line BL and a shield metal layer SS are formed on the peripheral circuit insulating layer 126. In one embodiment, a bit line BL is formed extending in the second horizontal direction Y, a first portion of the bit line insulating layer 152 is conformally formed in the space between the bit lines BL, and a shield metal layer SS is formed on the first portion of the bit line insulating layer 152. Subsequently, a second portion of the bit line insulating layer 152 is formed on the upper surface of the shield metal layer SS.

[0037] Referring to Figures 11A to 11C, a plurality of molded structures 130 extending in the first horizontal direction X are formed on the upper surface of the bit line BL and the bit line insulating layer 152. Each of the multiple molded structures 130 includes a first insulating layer 132, a metal layer 134, a second insulating layer 136, and a capping layer 138, which are sequentially arranged on the bit line BL and the bit line insulating layer 152. In one embodiment, the metal layer 134 may contain at least one of aluminum, titanium, tungsten, copper, molybdenum, ruthenium, tantalum, and cobalt. In one embodiment, the metal layer 134 may further include at least one of titanium nitride, tungsten nitride, molybdenum nitride, ruthenium nitride, tantalum nitride, and cobalt nitride. In one embodiment, a cell space 130H extending in a first horizontal direction X is defined between two adjacent mold structures 130 among a plurality of mold structures 130.

[0038] Referring to Figures 12A and 12B, a preliminary active semiconductor layer APL is formed on the side wall of the cell space 130H between two adjacent mold structures 130. The preliminary active semiconductor layer APL is conformally arranged on the side walls and top surface of the mold structure 130, and on the top surface of the bit line BL and the top surface of the bit line insulating layer 152. For example, the thickness of the pre-active semiconductor layer APL placed on the side wall of the mold structure 130 is the same as or approximately the thickness of the pre-active semiconductor layer APL placed on the upper surface of the mold structure 130, and on the upper surface of the bit line BL and the upper surface of the bit line insulating layer 152.

[0039] Referring to Figures 13A to 13C, an anisotropic etching process or an etch-back process is performed on the preliminary active semiconductor layer APL to remove a portion of the preliminary active semiconductor layer APL that is placed on the upper surface of the mold structure 130, leaving only a portion of the preliminary active semiconductor layer APL that is placed on the side walls of the mold structure 130, the upper surface of the bit line BL, and the upper surface of the bit line insulating layer 152. The upper surface of the molded structure 130 (for example, the upper surface of the capping layer 138) is exposed again by an anisotropic etching process or an etch-back process. The upper surface of the mold structure 130 (for example, the upper surface of the capping layer 138) is positioned at the same level as the upper surface of the preliminary active semiconductor layer APL. Furthermore, as shown in Figure 13A, the bottom surface of the preliminary active semiconductor layer APL is in contact with the top surface of the bit line BL.

[0040] Thereafter, a mask pattern extending in the second horizontal direction Y is formed on the mold structure 130 and the preliminary active semiconductor layer APL, and a portion of the preliminary active semiconductor layer APL not covered by the mask pattern is removed. The remaining portion of the preliminary active semiconductor layer APL covered by the mask pattern is not removed and is referred to as the active semiconductor layer AP. Between two adjacent mold structures 130, the active semiconductor layers AP are spaced apart in the first horizontal direction X, and each active semiconductor layer AP has a U-shaped vertical cross-section. In one embodiment, a portion of the active semiconductor layer AP is positioned in contact with the side wall of the metal layer 134 of the molded structure 130.

[0041] During the formation process of the active semiconductor layer AP, or in a subsequent process, oxygen atoms move or diffuse into the metal layer 134 in a portion of the active semiconductor layer AP adjacent to the contact interface between the active semiconductor layer AP and the metal layer 134. As a result, a portion of the active semiconductor layer AP that is in contact with the sidewall of the metal layer 134 has a lower oxygen content than other regions of the active semiconductor layer AP (e.g., the bulk region of the active semiconductor layer AP), and such a region is referred to as the conductive region (AP_i). Furthermore, a portion of the metal layer 134 adjacent to the conductive region (AP_i) of the active semiconductor layer AP has a higher oxygen content than other regions of the metal layer 134 (for example, the bulk region of the metal layer 134), and such a region is referred to as the insulating region (134_i). In one embodiment, a heat treatment or annealing step for diffusing oxygen atoms contained in the active semiconductor layer AP into the metal layer 134 may be selectively performed after or in a subsequent step following the formation step of the active semiconductor layer AP.

[0042] Referring to Figures 14A and 14B, a gate insulating layer GI and a word line metal layer WLP are formed on the sidewall of the active semiconductor layer AP. In one embodiment, the gate insulating layer GI is conformally formed on the upper surface of the molded structure 130 and on the side wall of the active semiconductor layer AP. The wordline metal layer (WLP) is conformally formed on the gate insulating layer (GI) on the upper surface of the molded structure (130) and on the sidewall of the active semiconductor layer (AP).

[0043] Referring to Figures 15A to 15C, an anisotropic etching process or recess process is performed on the upper side of the word line metal layer (WLP) to form the word line (WL). In the anisotropic etching process or recess process, the height of the word line WL is reduced such that the word line WL has an upper surface that is positioned at a lower level than the upper surface of the molded structure 130. As illustrated in Figure 15A, between two adjacent mold structures 130, a first word line WL1 is placed on the side wall of the left mold structure 130, and a second word line WL2 is placed on the side wall of the right mold structure 130.

[0044] Referring to Figures 16A and 16B, an insulating liner 142 and an embedded insulating layer 144 are sequentially formed on the word line WL. In one embodiment, a portion of the insulating liner 142, which is placed on the upper surface of the molded structure 130, is removed, thereby exposing the upper surface of the molded structure 130 and the upper surface of the active semiconductor layer AP again. The process for removing a portion of the insulating liner 142 is a grinding or chemical mechanical polishing (CMP) process. After the grinding or CMP process, the upper surface of the embedded insulating layer 144, the upper surface of the active semiconductor layer AP, and the upper surface of the molded structure 130 are arranged on the same plane.

[0045] Referring to Figures 17A and 17B, a portion of the active semiconductor layer AP is removed to form the landing pad recess LPH. The formation of the landing pad recess LPH causes the upper surface of the active semiconductor layer AP to be positioned at a lower vertical level than the upper surface of the molded structure 130.

[0046] Referring to Figures 18A and 18B, a conductive layer is formed on the molded structure 130 to fill the landing pad recess LPH, and the upper side of the conductive layer is patterned to form the landing pad LP. The landing pad LP includes a lower LPb (see Figure 5) that fills the interior of the landing pad recess LPH, and an upper LPa (see Figure 5) that is connected to the lower LPb and positioned on the upper surface of the molded structure 130.

[0047] Referring to Figures 19A and 19B, a cell capacitor CAP is formed on the landing pad LP. After performing the above-described process, the semiconductor device 100 is completed. According to embodiments of the present invention, the molded structure 130 includes a metal layer 134, and a conductive region (AP_i) is formed within a portion of the active semiconductor layer AP that is in contact with the sidewall of the metal layer 134. The conductive region (AP_i) contains a relatively large amount of free electrons, and these free electrons fill the trap sites within the active semiconductor layer AP, resulting in the active semiconductor layer AP having a reduced trap density compared to the comparative example. Therefore, the semiconductor device 100 can have a relatively high on-current and excellent electrical performance. According to the present invention, an oxygen-deficient conductive region is formed in the active semiconductor layer adjacent to the mold structure containing a metallic material, thereby reducing the trap density in the active semiconductor layer and increasing the on-current of the transistor. Therefore, the semiconductor device can have excellent electrical performance.

[0048] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0049] 100 Semiconductor Equipment 110 circuit boards 120 Peripheral circuit wiring structure 122 Peripheral Circuit Wiring 124 Peripheral Circuit Contacts 126 Peripheral circuit insulating layer 130 Molded Structures 132 First insulating layer 134 Metal layer 136 Second insulating layer 138 Capping layer 142 Insulating Liner 144 Embedded insulating layer 156-bit line contacts 158-bit line contact spacer 176 Insulating layer AC active area AP Active Semiconductor Layer BL Bitline CAP Cell Capacitor CTR Cell Transistor CTR1 First Cell Transistor CTR2 Second Cell Transistor GI gate insulating layer LP Landing Pad MCA Cell Array Region PCA Peripheral Circuit Area PTG Terminal PTI gate insulation layer PTR Peripheral Circuit Transistor PTS Source / Drain Area SS Shield Metal Layer WL Wardline WL1 1st Wardline WL2 2nd Wardline

Claims

1. A bit line is arranged on the substrate and extends in the first horizontal direction, Arranged on the aforementioned bit line, extending in a second horizontal direction intersecting the first horizontal direction, and comprising a molded structure including a metal layer, An active semiconductor layer containing an oxide semiconductor is extended vertically from the side wall of the mold structure, The active semiconductor layer has a word line disposed on the side wall of the active semiconductor layer and extending in the second horizontal direction, A semiconductor device characterized in that at least a portion of the side wall of the active semiconductor layer is in contact with the metal layer.

2. The aforementioned molded structure is A first insulating layer disposed on the bit line, The metal layer disposed on the first insulating layer, The semiconductor device according to claim 1, further comprising a second insulating layer disposed on the metal layer.

3. The semiconductor device according to claim 2, characterized in that the sidewall of the active semiconductor layer is in contact with the sidewall of the first insulating layer, the sidewall of the metal layer, and the sidewall of the second insulating layer.

4. The upper surface of the metal layer is positioned between the upper surface of the active semiconductor layer and the substrate. The semiconductor device according to claim 1, characterized in that the bottom surface of the active semiconductor layer is disposed between the bottom surface of the metal layer and the substrate.

5. A conductive region is arranged within a portion of the active semiconductor layer that is in contact with the metal layer. The semiconductor device according to claim 1, characterized in that an insulating region is disposed within a portion of the metal layer that is in contact with the active semiconductor layer.

6. The semiconductor device according to claim 5, characterized in that the oxygen content in the conductive region is smaller than the oxygen content in the bulk region of the active semiconductor layer.

7. The semiconductor device according to claim 5, characterized in that the oxygen content in the insulating region is greater than the oxygen content in the bulk region of the metal layer.

8. The bottom surface of the conductive region is positioned vertically away from the bottom surface of the active semiconductor layer. The semiconductor device according to claim 5, characterized in that the upper surface of the conductive region is arranged to be separated from the upper surface of the active semiconductor layer in the vertical direction.

9. The active semiconductor layer is zinc tin oxide (Zn ｘ , ｚ Sn ｙ O), indium zinc oxide (In ｘ Zn ｙ O), zinc oxide (ZnO ｘ ), indium gallium zinc oxide (In ｘ Ga ｙ Zn ｚ O), indium gallium silicon oxide (In ｘ Ga ｙ Su ｚ O), indium tungsten oxide (In ｘ W ｙ O), indium oxide (In ｘ O), tin oxide (Sn ｘ O), titanium oxide (Ti ｘ O), zinc oxynitride (Zn ｘ ON ｚ ), magnesium zinc oxide (Mg ｘ Zn ｙ O), zirconium indium zinc oxide (Zr ｘ In ｙ Zn ｚ O), hafnium indium zinc oxide (Hf ｘ In ｙ Zn ｚ O), tin indium zinc oxide (Sn ｘ In ｙ Zn ｚ O), aluminum tin indium zinc oxide (Al ｘ Sn ｙ In ｚ Zn ａ O), silicon indium zinc oxide (Si ｘ In ｙ Zn ｚ O), aluminum zinc tin oxide (Al ｘ Zn ｙ Sn ｚ O), gallium zinc tin oxide (Ga ｘ An ｙ Sn ｚ O), zirconium zinc tin oxide (Zr ｘ Zn ｙ Sn ｚ The semiconductor device according to claim 8, characterized by including at least one of O).

10. The semiconductor device according to claim 1, characterized in that the metal layer includes at least one of aluminum, titanium, tungsten, copper, molybdenum, ruthenium, tantalum, cobalt, titanium nitride, tungsten nitride, molybdenum nitride, ruthenium nitride, tantalum nitride, and cobalt nitride.

11. A peripheral circuit region arranged on the substrate, The system further comprises a cell capacitor disposed on the active semiconductor layer, The semiconductor device according to claim 1, characterized in that the peripheral circuit region is arranged between the bit line and the substrate.

12. A bit line is arranged on the substrate and extends in the first horizontal direction, A molded structure comprising a first insulating layer, a metal layer, and a second insulating layer arranged on the bit line, extending in a second horizontal direction intersecting the first horizontal direction, and stacked vertically, An active semiconductor layer extending vertically from the side wall of the mold structure, containing an oxide semiconductor, and in contact with the side wall of the metal layer, A word line is arranged on the side wall of the active semiconductor layer and extends in the second horizontal direction, A semiconductor device characterized by having a cell capacitor disposed on the active semiconductor layer.

13. A conductive region is arranged within a portion of the active semiconductor layer that is in contact with the metal layer. The semiconductor device according to claim 12, characterized in that an insulating region is disposed within a portion of the metal layer that is in contact with the active semiconductor layer.

14. The oxygen content within the conductive region is less than the oxygen content in the bulk region of the active semiconductor layer. The semiconductor device according to claim 13, characterized in that the oxygen content in the insulating region is greater than the oxygen content in the bulk region of the metal layer.

15. The upper surface of the metal layer is positioned between the upper surface of the active semiconductor layer and the substrate. The semiconductor device according to claim 13, characterized in that the bottom surface of the active semiconductor layer is disposed between the bottom surface of the metal layer and the substrate.

16. The bottom surface of the conductive region is positioned so as to be separated vertically from the bottom surface of the active semiconductor layer. The semiconductor device according to claim 13, characterized in that the upper surface of the conductive region is arranged to be separated vertically from the upper surface of the active semiconductor layer.

17. The active semiconductor layer is zinc tin oxide (Zn ｘ Sn ｙ O), indium zinc oxide (In ｘ Zn ｙ O), zinc oxide (ZnO ｘ ), indium gallium zinc oxide (In ｘ Ga ｙ Zn ｚ O), indium gallium silicon oxide (In[[ID=…]] ｘ Ga ｙ Su ｚ O), indium tungsten oxide (In ｘ W ｙ O), indium oxide (In ｘ O), tin oxide (Sn ｘ O), titanium oxide (Ti ｘ O), zinc oxynitride (Zn ｘ ON ｚ ), magnesium zinc oxide (Mg ｘ Zn ｙ O), zirconium indium zinc oxide (Zr ｘ … In ｙ Zn ｚ O), hafnium indium zinc oxide (Hf ｘ In ｙ Zn ｚ O), tin indium zinc oxide (Sn ｘ In ｙ Zn ｚ O), aluminum tin indium zinc oxide (Al ｘ Sn ｙ In ｚ Zn ａ O), silicon indium zinc oxide (Si ｘ In ｙ Zn<…… ｚ O), aluminum zinc tin oxide (Al ｘ Zn ｙ Sn ｚ O), gallium zinc tin oxide (Ga ｘ An ｙ Sn ｚ O), zirconium zinc tin oxide (Zr ｘ Zn ｙ Sn ｚ and includes at least one of them, The semiconductor device according to claim 12, characterized in that the metal layer includes at least one of aluminum, titanium, tungsten, copper, molybdenum, ruthenium, tantalum, cobalt, titanium nitride, tungsten nitride, molybdenum nitride, ruthenium nitride, tantalum nitride, and cobalt nitride.

18. Peripheral circuit areas arranged on the substrate, A plurality of bit lines are arranged on the peripheral circuit region and extend in the first horizontal direction, A plurality of molded structures including a first insulating layer, a metal layer, and a second insulating layer, which are arranged on the plurality of bit lines, extend in a second horizontal direction intersecting the first horizontal direction, and each is stacked vertically, A plurality of active semiconductor layers having a U-shaped vertical cross-section are arranged between two adjacent mold structures among the plurality of mold structures, on the side walls of the two mold structures, and on the upper surface of each of the plurality of bit lines, A first word line and a second word line are positioned between the two molded structures, extending horizontally and spaced apart from each other, The system comprises a plurality of cell capacitors arranged on the plurality of active semiconductor layers, A semiconductor device characterized in that at least a portion of each of the plurality of active semiconductor layers is in contact with the metal layer.

19. A conductive region is arranged within a portion of the active semiconductor layer that is in contact with the metal layer. The semiconductor device according to claim 18, characterized in that the oxygen content in the conductive region is smaller than the oxygen content in the bulk region of the active semiconductor layer.

20. An insulating region is disposed within a portion of the metal layer that is in contact with the active semiconductor layer. The semiconductor device according to claim 18, characterized in that the oxygen content in the insulating region is greater than the oxygen content in the bulk region of the metal layer.

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