Memory device

Abstract

To provide a storage device with a smaller area. [Solution] A plurality of first conductors are arranged apart from each other along a first axis. A memory pillar extends along the first axis, faces the plurality of first conductors, and includes a semiconductor and a film surrounding the semiconductor. A plurality of contact plugs extend along the first axis and each includes a second conductor and a first insulator surrounding the second conductor. The first insulator is located between the plurality of first conductors and the second conductors. Each of the plurality of contact plugs is in contact with the upper surface of one of the plurality of first conductors, which does not overlap, at its lower surface. The plurality of contact plugs include first to third contact plugs. The first and second contact plugs are arranged adjacent to each other along a second axis intersecting the first axis. The third contact plug is located between the first and second contact plugs on the second axis and is located at a different position on the third axis which is perpendicular to the first and second axes.

Description

Technical Field

[0001] Embodiments generally relate to a memory device.

Background Art

[0002] A memory device in which memory cells are arranged three-dimensionally is known. The memory device is required to have a smaller area.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An attempt is made to provide a memory device having a smaller area.

Means for Solving the Problems

[0005] A memory device according to one embodiment comprises a plurality of first conductors, a memory pillar, and a plurality of contact plugs. The plurality of first conductors are spaced apart from each other and arranged along a first axis. The memory pillar extends along the first axis, faces the plurality of first conductors, and includes a semiconductor and a film surrounding the semiconductor. The plurality of contact plugs extend along the first axis. Each of the plurality of contact plugs includes a second conductor and a first insulator surrounding the second conductor. The first insulator is located between the plurality of first conductors and the second conductor. Each of the plurality of contact plugs is in contact with the upper surface of one of the plurality of first conductors at its lower surface. The plurality of contact plugs includes a first contact plug, a second contact plug, and a third contact plug. The first contact plug and the second contact plug are arranged adjacent to each other along a second axis intersecting the first axis. The third contact plug is located between the first contact plug and the second contact plug on the second axis, and is positioned at different locations on the third axis which is orthogonal to the first and second axes. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing the components of a storage device according to the first embodiment and an example of how the components are connected. [Figure 2] A diagram showing the components of one block of the storage device according to the first embodiment and the connections between the components. [Figure 3] A figure showing an example of a planar layout of a portion of the memory cell array of a storage device according to the first embodiment. [Figure 4] A figure showing an example of a planar layout of a portion of the memory area of ​​the storage device according to the first embodiment. [Figure 5] A diagram showing the structure of a cross-section of a portion of the memory area of ​​the storage device according to the first embodiment. [Figure 6] A diagram showing an example of the cross-sectional structure of a memory pillar of a storage device according to the first embodiment. [Figure 7] A diagram showing an example of a partial planar layout of the drawer area of ​​the storage device according to the first embodiment. [Figure 8] A diagram showing the structure of a portion of the memory area and the drawer area of ​​the storage device according to the first embodiment. [Figure 9] A diagram showing the structure of a portion of the memory area and the drawer area of ​​the storage device according to the first embodiment. [Figure 10] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 11] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 12] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 13] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 14] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 15] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 16] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 17] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 18] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 19] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 20] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 21] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 22] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the first embodiment of the memory device. [Figure 23]A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the memory device according to the first embodiment. [Figure 24] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the memory device according to the first embodiment. [Figure 25] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the memory device according to the first embodiment. [Figure 26] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the memory device according to the first embodiment. [Figure 27] A diagram showing an example of the cross-sectional structure during one step in the manufacturing process of the memory device according to the first embodiment. [Figure 28] A diagram showing an example of a partial planar layout of the lead-out area of the reference memory device. [Figure 29] A diagram showing an example of a partial planar layout of the lead-out area of the memory device according to the second embodiment. [Figure 30] A diagram showing an example of a partial planar layout of the lead-out area of the memory device according to the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] In the following description, in embodiments following a described embodiment, differences from the described embodiment are mainly described. All descriptions of an embodiment apply as descriptions of another embodiment as well, unless explicitly or implicitly excluded. Thus, descriptions of an embodiment generally do not include the same content as descriptions of a preceding embodiment, except when necessary. For a plurality of components having substantially the same functions and configurations within an embodiment or across different embodiments, additional numbers or characters may be added to the end of the reference signs in order to distinguish them from each other.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may differ from reality. There may also be differences in dimensional relationships and ratios between drawings. In plan drawings, hatching may be added to improve the visibility of the drawing. Hatching added to plan drawings is not necessarily related to the material and / or properties of the components to which the hatching is added.

[0009] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or temporarily conductive.

[0010] The following descriptions of the embodiments use the xyz Cartesian coordinate system. In the figures, the positive direction on the vertical axis is sometimes referred to as the upper side, and the negative direction as the lower side. In the figures, the positive direction on the horizontal axis is sometimes referred to as the right side, and the negative direction as the left side.

[0011] 1. First Embodiment 1.1.Configuration (Structure) 1.1.1. Storage device Figure 1 shows an example of the components of a storage device according to the first embodiment and the connections of those components. Storage device 1 is a device that stores data using memory cells. Storage device 1 is controlled by an external memory controller. Storage device 1 operates based on commands CMD and address information ADD received from the memory controller, for example. Storage device 1 receives data DAT to be written and outputs the data stored in storage device 1. Storage device 1 is configured, for example, as a single semiconductor chip.

[0012] The storage device 1 includes components such as a memory cell array 10, a row decoder 11, a register 12, a sequencer 13, a driver 14, and a sense amplifier 15.

[0013] The memory cell array 10 is a set of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK (BLK_0, BLK_1, ...). Each block BLK includes a plurality of memory cell transistors MT (not shown). The memory cell array 10 also includes wiring such as word lines WL (not shown) and bit lines BL (not shown), and wiring connected to the memory cell transistors MT.

[0014] The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transfers the voltage supplied from the driver 14 to one block BLK that is selected based on the block address received from the register 12.

[0015] Register 12 is a circuit that holds the command CMD and address information ADD received by the storage device 1. The command CMD instructs the sequencer 13 to perform various operations, including data read, data write, and data erase. The address information ADD specifies the target of access in the memory cell array 10.

[0016] The sequencer 13 is a circuit that controls the operation of the entire storage device 1. Based on the command CMD received from the register 12, the sequencer 13 controls the row decoder 11, the driver 14, and the sense amplifier 15 to perform various operations, including data reading, data writing, and data erasure.

[0017] The driver 14 is a circuit that generates multiple voltages of different magnitudes and applies various voltages necessary for the operation of the memory device 1 to several components. Of the multiple voltages generated, the one selected based on control by the sequencer 13 and address information ADD is supplied to the row decoder 11.

[0018] The sense amplifier 15 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 15 senses the state of the memory cell transistor MT and generates read data or transfers write data to the memory cell transistor MT based on the sensed state.

[0019] 1.1.2. Circuit configuration of memory cell array Figure 2 shows the components and connections of one block BLK of the storage device in the first embodiment. Multiple block BLKs, for example, all block BLKs, include the components and connections shown in Figure 2.

[0020] A single block BLK contains multiple string units SU. Figure 2 shows an example of four string units SU_0 to SU_3.

[0021] Each of the m bit lines BL_0 to BL_m-1 is connected in each block BLK to one NAND string NS from each of the string units SU_0 to SU_3, where m is a positive integer.

[0022] Each NAND string NS includes one selection gate transistor ST, multiple memory cell transistors MT, and one selection gate transistor DT (DT0, DT1, DT2, or DT3). Figure 2 is based on an example of eight memory cell transistors MT0 to MT7. Each memory cell transistor MT includes a control gate electrode and a charge storage film isolated from the surroundings, and is an element that non-volatilely stores data based on the amount of charge in the charge storage film. The selection gate transistor ST, memory cell transistor MT, and selection gate transistor DT are connected in this order in series between the source line SL and one bit line BL.

[0023] Multiple NAND strings NS, each connected to a different bit line BL, constitute a single string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. A set of memory cell transistors MT sharing a word line WL within a single string unit SU is referred to as a cell unit CU.

[0024] The selection gate transistors DT0 to DT3 belong to string units SU_0 to SU_3, respectively. In Figure 2, selection gate transistors DT2 and DT3 are not shown. The gates of each selection gate transistor DT0 in the multiple NAND strings NS of string unit SU_0 are connected to the selection gate line SGDL0. Similarly, the gates of each selection gate transistor DT1, DT2, and DT3 in the multiple NAND strings NS of string units SU_1, SU_2, and SU_3 are connected to the selection gate lines SGDL1, SGDL2, and SGDL3, respectively.

[0025] The gate of the selection gate transistor ST is connected to the selection gate line SGSL.

[0026] 1.1.3. Planar layout of memory cell array Figure 3 shows an example of a partial planar layout of the memory cell array of the first embodiment of the storage device. Figure 3 shows the region where four blocks BLK_0 to BLK_3 are formed, along the xy plane. The structure shown in Figure 3 is repeated along the y axis.

[0027] As shown in Figure 3, the memory cell array 10 includes a memory area MA and extraction areas HA1 and HA2. The extraction area HA1, memory area MA, and extraction area HA2 are arranged in this order along the x-axis. The memory cell array 10 is provided with a plurality of members SLT and SHE.

[0028] The memory region MA is a region containing multiple NAND strings NS. The extraction region HA is a region where contact plugs are provided that connect to a stacked structure in which memory cell transistors are formed.

[0029] Multiple member SLTs extend along the x-axis and are aligned along the y-axis. Each member SLT is located at the boundary between adjacent blocks BLK. Member SLTs traverse the memory area MA and the draw-out areas HA1 and HA2. Each member SLT has a structure in which, for example, an insulator and / or plate-shaped contacts are embedded. Each member SLT separates adjacent stacked structures through itself.

[0030] Multiple members SHE extend along the x-axis and are aligned along the y-axis. Multiple members SHE are located between every two adjacent members SLT. Figure 4 shows an example of four members SHE. Each member SHE crosses the memory region MA along the x-axis. Both ends of each member SHE are located in the draw-out regions HA1 and HA2, respectively. Each member SHE includes, for example, an insulator. Each member SHE separates adjacent selection gate lines SGDL through itself. Each region separated by members SLT and SHE is a region where one string unit SU is formed.

[0031] 1.1.4. Planar layout of the memory area Figure 4 shows an example of a partial planar layout of the memory area of ​​the storage device of the first embodiment. Figure 4 shows one block BLK, i.e., an area containing string units SU0 to SU4, and two members SLT flanking this block. As shown in Figure 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contact plugs CV, and a plurality of conductors 25 in the memory area MA. Each member SLT includes a contact LI and a spacer SP.

[0032] A memory pillar MP is a structure in which memory cell transistors MT are formed inside. A memory pillar MP contains one or more semiconductors, conductors, and insulators. Each memory pillar MP functions as a single NAND string NS. Multiple memory pillar MPs are distributed in a staggered arrangement in the region between two member SLTs. That is, the multiple memory pillar MPs are arranged in multiple columns along the y-axis, and each column of memory pillar MPs is arranged in a zigzag pattern along the y-axis. In other words, each column contains two sub-columns. The y-axis coordinate of each memory pillar MP in one sub-column corresponds to the y-axis coordinate between two adjacent memory pillar MPs in the other sub-column. Each column contains, for example, 24 memory pillar MPs.

[0033] For example, component SHE overlaps with the 5th, 10th, 15th, and 20th memory pillars MP, counting from the top in Figure 4.

[0034] Each conductor 25 functions as a single bit line BL. The conductors 25 extend along the y-axis and are aligned along the x-axis. Each conductor 25 is positioned to overlap with at least one memory pillar MP for each string unit SU. Figure 4 shows an example where two conductors 25 are positioned to overlap with one memory pillar MP. Each memory pillar MP is electrically connected to one of the multiple conductors 25 that overlap with this memory pillar MP via a contact plug CV.

[0035] The contact LI is made of a conductor. The contact LI extends along the xz plane and has a plate-like shape. The spacer SP is an insulator and is located on the side surface of the contact LI, for example, covering the side surface of the contact LI.

[0036] 1.1.5. Cross-sectional structure of the memory area Figure 5 shows the structure of a portion of the memory area of ​​the storage device of the first embodiment. Specifically, Figure 5 shows a cross-section along the VV line in Figure 4.

[0037] As shown in Figure 5, the memory cell array 10 further includes a substrate 20, conductors 21 and 22, a plurality of conductors 23, conductors 24 and 25, and insulators 30-37. Figure 5 shows eight examples of conductors 23. The insulators 30-37, with the exception of insulator 31, include, for example, silicon oxide.

[0038] The substrate 20 is, for example, a p-type semiconductor substrate. An insulator 30 is located on the upper surface of the substrate 20. Circuits (not shown) are formed in the semiconductor substrate 20 and the insulator 30. The circuits include, for example, a raw decoder 11, a driver 14, and / or a sense amplifier 15, and include transistors (not shown).

[0039] The insulator 31 is located on the upper surface of the insulator 30. The insulator 31, for example, from the structure above the insulator 31, suppresses the intrusion of hydrogen into the transistors contained in the substrate 20 and the insulator 30. The insulator 31 includes, for example, silicon nitride.

[0040] The insulator 32 is located on the upper surface of the insulator 31.

[0041] The conductor 21 is located on the upper surface of the insulator 32. The conductor 21 extends along the xy plane and has a plate-like shape. The conductor 21 functions as at least part of the source wire SL. The conductor 21 includes, for example, phosphorus-doped silicon.

[0042] The insulator 33 is located on the upper surface of the conductor 21.

[0043] The conductor 22 is located on the upper surface of the insulator 33. The conductor 22 extends along the xy plane and has a plate-like shape. The conductor 22 functions as at least part of the selected gate line SGSL. The conductor 22 includes, for example, tungsten.

[0044] Multiple insulators 34 and multiple conductors 23 are positioned alternately one by one along the z-axis on the upper surface of the conductor 22. Thus, the conductors 23 are arranged along the z-axis, separated from each other or with gaps between them. The insulators 34 and conductors 23 extend along the xy-plane and have a plate-like shape. The multiple conductors 23 function as word lines WL0 to WL7, respectively, starting from the side of the substrate 20. The conductors 23 include, for example, tungsten.

[0045] The insulator 35 is located on the upper surface of the top conductor 23.

[0046] The conductor 24 is located on the upper surface of the insulator 35. The conductor 24 extends along the xy plane and has a plate-like shape. The conductor 24 functions as at least part of the selected gate line SGDL. The conductor 24 includes, for example, tungsten.

[0047] The insulator 36 is located on the upper surface of the conductor 24.

[0048] The conductor 25 is located on the upper surface of the insulator 36. The conductor 25 has a linear shape and extends along the y-axis. The conductor 25 functions as at least part of one bit line BL. The conductor 25 is also provided in a yz plane different from the yz plane shown in Figure 5, so that the conductors 25 are spaced apart along the x-axis. The conductor 25 includes, for example, copper.

[0049] The insulator 37 is located on the upper surface of the conductor 25.

[0050] The memory pillar MP extends along the z-axis and has a columnar shape. The memory pillar MP is located in a laminated structure consisting of insulators 33-35 and conductors 22-24, and penetrates or passes through the insulators 33-35 and conductors 22-24. The upper surface of the memory pillar MP is located above the conductor 24. The lower surface of the memory pillar MP is located within the conductor 21. The portion where the memory pillar MP contacts the conductor 22 functions as a selection gate transistor ST. The portion where the memory pillar MP contacts one conductor 23 functions as one memory cell transistor MT. The portion where the memory pillar MP contacts the conductor 24 functions as a selection gate transistor DT.

[0051] The memory pillar MP includes, for example, a core 50, a semiconductor 51, and a laminate 52. The core 50 is made of an insulator, for example, silicon oxide. The core 50 extends along the z-axis and has a columnar shape. The semiconductor 51 includes, for example, silicon. The semiconductor 51 covers the surface of the core 50. The laminate 52 covers the sides and bottom of the semiconductor 51. The laminate 52 is open in the conductor 21, which is partially located within the opening. Within the opening, the conductor 21 and the semiconductor 51 are in contact.

[0052] As described above, one memory pillar MP and one conductor 25 are connected by a contact plug CV.

[0053] Component SLT separates conductors 22-24. The upper surface of component SLT is located above the upper surface of memory pillar MP. The lower surface of contact LI is in contact with conductor 21. Spacer SP is located between contact LI and conductors 22-24, insulating contact LI from conductors 22-24. Contact LI functions as part of source wire SL.

[0054] Component SHE divides the conductor 24. The lower surface of component SHE is located within the insulator 35. Component SHE includes an insulator such as silicon oxide.

[0055] Figure 6 shows an example of the cross-sectional structure of a memory pillar of a storage device according to the first embodiment. Specifically, Figure 6 shows a cross-section along the line VI-VI in Figure 5. As shown in Figure 6, the laminate 52 includes, for example, a tunnel insulator 53, a charge storage film 54, and a block insulator 55.

[0056] The tunnel insulator 53 surrounds the side surface of the semiconductor 51. The charge storage film 54 surrounds the side surface of the tunnel insulator 53. The block insulator 55 surrounds the side surface of the charge storage film 54. The conductor 23 surrounds the side surface of the block insulator 55.

[0057] The semiconductor 51 functions as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection gate transistors DT and ST. Each of the tunnel insulator 53 and the block insulator 55 contains, for example, silicon oxide. The charge storage film 54 stores charge. The charge storage film 54 contains, for example, silicon nitride.

[0058] 1.1.6. Structure of the drawer area Figure 7 shows an example of a planar layout of a portion of the drawer area of ​​the storage device according to the first embodiment. Figure 7 shows a portion of the area between the two member SLTs along the xy plane. Figure 7 shows the layout of the layer containing the conductor 24 as viewed from above on the z axis.

[0059] As shown in Figure 7, the extension region HA1 includes a plurality of support pillars HR and a plurality of contact plugs CC.

[0060] The support pillars HR are distributed throughout the entire extraction region HA1. The support pillars HR are made of an insulator, such as silicon oxide. The support pillars HR have a columnar shape and extend along the z-axis. The support pillars HR extend from the layer of insulator 36 to the layer of conductor 22, as will be described later with reference to Figure 8. Some of the support pillars HR overlap the contact plugs CC, at least partially. The portion of the support pillars HR that overlaps the contact plugs CC is in contact with the contact plugs CC on its upper surface and is not located in the insulator 36. The support pillars HR are not located at the center of one or more contact plugs CC, for example, but are located in a region off-center from the center.

[0061] A contact plug CC has a shape, for example, that of a rectangle. A contact plug CC constitutes multiple rows along the x-axis. Figure 7 shows three rows of contact plug CCs as an example. Rows of contact plug CCs are sometimes referred to as contact plug sets. Contact plug CCs are distributed in a staggered arrangement, meaning that the positions of two adjacent rows of contact plug CCs are offset from each other. Specifically, this is as follows: Two contact plug CCs belonging to two adjacent rows are located at different coordinates on the x-axis. For example, the x-axis coordinate of each contact plug CC in one row of two rows of contact plug CCs is the same as the x-axis coordinate of the area between two adjacent contact plug CCs in the other row of the two rows of contact plug CCs. For example, the x-axis coordinate of each contact plug CC in one row is substantially the same as the x-axis coordinate of the center of the area between two adjacent contact plug CCs in the other row. On the other hand, the x-axis coordinates of two rows of contact plug CCs separated by another row are substantially the same. In other words, the x-axis coordinates of each contact plug CC in one row of two rows separated by another row are substantially the same as the x-axis coordinates of each contact plug CC in the other row. In this specification and the claims, “substantially the same” means that they are intended to be the same, but allow for errors resulting from limitations of the manufacturing and / or measurement techniques.

[0062] In other words, the two rows contain contact plugs CC arranged in a zigzag pattern along the x-axis.

[0063] The arrangement of contact plugs CC described using rows also applies to descriptions using columns. The description using columns is equivalent to the above description with "rows" replaced by "columns" and "x-axis" replaced by "y-axis".

[0064] Each contact plug CC makes contact with the upper surface of a different conductor 23 on its lower surface. A specific example is as follows:

[0065] The contact plugs CC in the bottom row are designated CC0, CC3, and CC6 from left to right. The lower surface of contact plug CC0 is in contact with the upper surface of conductor 23, which functions as word line WL0. The lower surface of contact plug CC3 is in contact with the upper surface of conductor 23, which functions as word line WL3. The lower surface of contact plug CC6 is in contact with the upper surface of conductor 23, which functions as word line WL6.

[0066] The contact plugs CC in the second row from the bottom are designated CC1, CC4, and CC7 from left to right. The lower surface of contact plug CC1 is in contact with the upper surface of conductor 23, which functions as word line WL1. The lower surface of contact plug CC4 is in contact with the upper surface of conductor 23, which functions as word line WL4. The lower surface of contact plug CC7 is in contact with the upper surface of conductor 23, which functions as word line WL7.

[0067] The contact plugs CC in the top row are designated CC2, CC5, and CC8 from left to right. The lower surface of contact plug CC2 is in contact with the upper surface of conductor 23, which functions as word line WL2. The lower surface of contact plug CC5 is in contact with the upper surface of conductor 23, which functions as word line WL5. The lower surface of contact plug CC8 is in contact with the upper surface of conductor 23, which functions as word line WL8.

[0068] As described with reference to Figure 5, the conductors 23, which function as different word lines WL, are located at different heights or in different layers. Thus, the contact plug CC has a lower surface at a position based on the position of the conductor 23 with which the contact plug CC is in contact.

[0069] As described above with reference to Figure 7, the upper surface of the portion of the support pillar HR that overlaps with the contact plug CC, at least partially, is in contact with the lower surface of the contact plug CC. Therefore, the support pillar HR has an upper surface based on the position of the contact plug CC that partially overlaps it.

[0070] Figures 8 and 9 show the structure of a portion of the memory area and the extraction area of ​​the storage device according to the first embodiment. Specifically, Figure 8 shows a cross-section of the extraction area HA1 along the line VIII-VIII in Figure 7, and also shows a portion of the memory area MA shown in Figure 5. Figure 9 shows a cross-section along the line IX-IX in Figure 7.

[0071] As shown in Figures 8 and 9, each contact plug CC penetrates the conductor 24 and the insulator 35. Some contact plug CCs further penetrate one or more conductors 23, and one or more insulators 34. Each contact plug CC includes a conductor 61 and a spacer 62.

[0072] The conductor 61 has a projection on its lower surface that points downward along the z-axis. The lower surface of the projection is in contact with the upper surface of one conductor 23. The lower surface of the projection may also be in contact with the upper surfaces of one or more support pillars HR. The sides of the contact plug CC are covered by spacers 62. The spacers 62 are made of, for example, silicon oxide. The sides of the spacers 62 are in contact with the conductors 24 and the insulators 35. The spacers 62 of some contact plug CCs are further in contact with one or more conductors 23 and one or more insulators 34. The spacers 62 insulate the conductor 61 from conductors 23 other than the conductor 23 in contact with its lower surface.

[0073] As described with reference to Figure 7, the different contact plugs CC contact the different conductors 23 on their lower surfaces. The lower surface of contact plug CC0 contacts the upper surface of conductor 23 which functions as word line WL0. The lower surface of contact plug CC1 contacts the upper surface of conductor 23 which functions as word line WL1. The lower surface of contact plug CC2 contacts the upper surface of conductor 23 which functions as word line WL2. The lower surface of contact plug CC3 contacts the upper surface of conductor 23 which functions as word line WL3. The lower surface of contact plug CC6 contacts the upper surface of conductor 23 which functions as word line WL6.

[0074] A conductor 60 is provided on the upper surface of the contact plug CC.

[0075] Refer to Figures 7 to 9 to describe the lead-out region HA1, and in particular, the contact plugs CC0 to CC8. The other contact plugs CC and lead-out region HA2 are similar to the lead-out region HA1 and contact plugs CC0 to CC8 described with reference to Figures 7 to 9. That is, the lead-out region HA2 has a planar layout inverted along the y-axis from the planar layout of the lead-out region HA1. Contact plugs CC other than contact plugs CC0 to CC8 contact a different conductor 23 on their lower surface than the conductor 23 that the other contact plugs CC contact.

[0076] 1.2. Manufacturing method Figures 10 to 26 each show examples of cross-sectional structures at one step in the manufacturing process of the memory device of the first embodiment. Figures 10 to 12, 14 to 16, 18, 20, and 22 to 27 sequentially show the structures during the manufacturing process. Figures 10 to 12, 14 to 16, 18, 20, and 22 to 27 show cross-sections of the same region as the cross-sectional region shown in Figure 8. Figures 13, 17, 19, and 21 show the same steps as Figures 12, 16, 18, and 20, respectively. Figures 12, 16, 18, and 20 show cross-sections of the same region as the cross-sectional region shown in Figure 9.

[0077] As shown in Figure 10, after a circuit (not shown) is formed on the substrate 20, insulators 31 and 32, conductor 61, insulators 62, 63, and 64, and conductor 65 are deposited on the upper surface of the substrate 20 in this order. The set of conductor 61, insulators 62, 63, and 64, and conductor 65 occupies the area where conductor 21 is to be formed.

[0078] An insulator 33 is formed on the upper surface of the conductor 65.

[0079] Multiple insulators SM and multiple insulators 34 are deposited alternately, one at a time, on the upper surface of the insulator 33. The bottommost insulator SM occupies the area where the conductor 22 is to be formed. The remaining insulators SM are located in the area where the conductor 23 is to be formed. The insulators SM include, for example, silicon nitride.

[0080] Insulator 35, insulator SM2, and insulator 71 are deposited in this order on the upper surface of the top insulator SM. Insulator SM2 is located in the region where the conductor 24 is to be formed. Insulator 71 constitutes part of insulator 36. Insulator SM2 contains, for example, silicon nitride.

[0081] As shown in Figure 11, a memory pillar MP is formed. However, the laminate 52 of the memory pillar MP does not have an opening at this stage. Specifically, it is as follows: Memory holes are formed by photolithography and anisotropic etching. The memory holes are located in the region where the memory pillar MP is to be formed. The memory holes penetrate the insulators 71, SM2, 35, SM, 34, 33, conductor 65, insulators 64, 63, and 62. The bottom of the memory hole is located in the conductor 61. The laminate 52, i.e., the tunnel insulator 53, charge storage film 54, and block insulator 55, is formed on the surface of the memory hole. A semiconductor 51 is formed on the surface of the laminate 52. The center of the memory hole is filled by the core 50 when the core 50 is formed on the surface of the semiconductor 51. Subsequently, the top of the core 50 is removed, and the semiconductor 51 is formed in the removed portion. In this way, the memory pillar MP is formed, and then an insulator is formed on the upper surface of the memory pillar MP. In Figure 11, this insulator is depicted as part of the insulator 71.

[0082] Support pillars HR are formed. Each support pillar HR penetrates insulators 71, SM2, 35, SM, and 34. Each support pillar HR extends from the upper surface of insulator 71 to the upper surface of insulator 33.

[0083] In the steps shown in Figures 12 and 13, and in subsequent steps, contact holes CH for contact plugs CC are formed. As described with reference to Figures 7 to 9, contact plugs CC have bottoms located at different heights based on the position of the conductor 23 with which they are in contact. Therefore, contact holes CH also have bottoms located at different depths before being filled with the conductor 61. For this purpose, contact holes CH with bottoms at deeper positions are further etched in steps following the steps shown in Figure 14. The steps starting from the steps in Figures 12 and 13 are performed so that each contact hole CH has its own target depth. Contact holes CH that should have a deeper target depth are repeatedly etched. Meanwhile, contact holes CH that have reached their target depth are filled with the filler material NG described later while other contact holes CH are further etched.

[0084] As shown in Figures 12 and 13, a portion of the contact hole CH is formed. The contact hole CH is the region where the contact plug CC is formed. Specifically, the formation is as follows:

[0085] A mask is formed on the upper surface of the insulator 71 by photolithography. The mask has an opening above the area where contact plugs CC0 to CC8 are to be formed. Contact holes CH0 to CH8 are formed by anisotropic etching through the mask. The contact holes CH0 to CH8 penetrate the insulator 71 and SM2 and reach the upper surface of the insulator 35.

[0086] As shown in Figure 14, the bottoms of contact holes CH7 and CH8 (not shown) are lowered to the desired depth by the steps described with reference to Figure 14 and thereafter. At this time, contact holes CH having a shallower desired depth than the desired depth of contact hole CH are filled with filler material NG (not shown). On the other hand, the bottoms of contact holes CH with a deeper desired depth than contact holes CH7 and CH8, i.e., contact holes CH0 to CH5, are etched to a deeper position. As a result, contact holes CH0 to CH6 reach the upper surface of insulator 34 on the upper surface of insulator SM located in the region where the conductor 23, which functions as a word line WL6, is to be formed.

[0087] As shown in Figure 15, the contact hole CH6 is filled with a filler material NG. The filler material NG is, for example, a negative resist. Specifically, the negative resist is applied to the upper surface of the structure obtained by the steps up to this point. Next, a mask is formed on the upper surface of the structure, having an opening in the area where the filler material NG is to be filled, i.e., above the contact hole CH6. The negative resist is exposed to light through the opening in the mask. As a result, the portion of the negative resist below the opening in the mask, i.e., the portion inside the contact hole CH6, hardens. After that, the unhardened portion of the negative resist is removed.

[0088] As shown in Figures 16 and 17, anisotropic etching is performed on the structure obtained in the steps up to this point. The etching is carried out under conditions that have a high selectivity ratio between the insulator SM and 34 pair and the filler material NG. As a result, the bottoms of the contact holes CH0 to CH5 that are not filled with the filler material NG are etched. Through etching, the bottoms of the contact holes CH0 to CH5 reach the upper surface of the insulator 34 on the upper surface of the insulator SM located in the region where the conductor 23, which will function as the word line WL5, is to be formed.

[0089] As shown in Figures 18 and 19, the bottoms of contact holes CH0 to CH4 are etched by repeating steps similar to those described with reference to Figures 15 to 17. During this process, contact hole CH4 is filled with filler material NG after reaching the desired depth. As the contact holes CH are etched and filled, the bottoms of contact holes CH0 to CH3 reach the upper surface of insulator 34 on the upper surface of insulator SM, which is located in the region where the conductor 23, which will function as a word line WL3, is to be formed.

[0090] As shown in Figures 20 and 21, the bottoms of contact holes CH0 to CH2 are etched by etching, while the contact holes CH reach the desired depth, through a repetition of steps similar to those described with reference to Figures 15 to 17, with the CHs being filled as they are etched. As a result, the bottoms of contact holes CH0 to CH2 reach the upper surface of the insulator 34 on the upper surface of the insulator SM, which is located in the region where the conductors 23, which will function as word lines WL0, WL1, and WL2, will be formed, respectively.

[0091] As shown in Figure 22, the filler material NG in each contact hole CH is removed. Removal can be performed by wet etching or ashing. An insulator 62 is deposited over the entire upper surface of the structure obtained in the steps up to this point. The insulator 62 covers the sides and bottom of each contact hole CH. The insulator 62 further covers the upper surface of the insulator 71 and the upper surface of the support pillar HR that does not overlap with the contact hole CH.

[0092] The contact hole CH is filled with an embedding material 72. The embedding material 72 is, for example, amorphous silicon.

[0093] As shown in Figure 23, a slit SLI is formed by photolithography and anisotropic etching. The slit SLI is located in the region where the member SLT is to be formed. At the bottom, the slit SLI reaches the upper surface of the insulator 64. An insulator 75 is formed on the surface of the slit SLI. The bottom portion of the insulator 75 and the portion of the insulator 64 below the slit SLI are removed. As a result, the insulator 63 is exposed at the bottom of the slit SLI.

[0094] As shown in Figure 24, the bottom of the slit SLI, i.e., the insulator 63, is exposed to the chemical solution by wet etching. The insulator 63 is removed by the chemical solution. At this time, the portion of the memory pillar MP laminate 52 located in the layer of insulator 63 is removed, and the semiconductor 51 is exposed in the removed portion.

[0095] As shown in Figure 25, wet etching allows the chemical solution to advance from the space where the insulator 63 at the bottom of the slit SLI was located. The chemical solution removes the insulators 62 and 64. Conductors 21 are formed by filling the spaces where insulators 62 and 64 were located with conductors.

[0096] The insulator 75 is removed. With the removal of the insulator 75, the insulators SM and SM2 are exposed in the slit SLI. The exposed portions of the insulators SM and SM2 are exposed to the chemical solution by wet etching. As the chemical solution progresses, the insulators SM and SM2 are removed, and the region where the insulators SM and SM2 were located in the slit SLI becomes open. During this time, a space is formed in the region where the insulators SM and SM2 were located. This weakens the structure of the memory device 1 during manufacturing, and in particular destabilizes the high aspect ratio portion of the structure. In contrast, the provision of numerous support pillars HR suppresses the collapse of the structural shape.

[0097] Conductors 22, 23, and 24 are formed by embedding a conductor in the region where insulators SM and SM2 were located through an opening in the slit SLI.

[0098] As shown in Figure 26, the side surface of the slit SLI is covered by the spacer SP. The slit SLI is filled with a conductor to form the component SLT.

[0099] The embedding material 72 is removed. The portion of the insulator 62 that does not overlap with the upper surface of insulator 71 and the upper surface of support pillar HR is removed. As a result, insulator 62 remains on the sides and bottom of the contact hole CH. Anisotropic etching is performed on the bottom surface of the contact hole CH. This removes the portion of insulator 62 that is on the bottom surface of the contact hole CH. As a result, insulator 34 is partially exposed on the bottom surface of each contact hole CH.

[0100] Further anisotropic etching is performed on the bottom of each contact hole CH. This removes the portion of each insulator 34 below each contact hole CH. As a result, the conductor 23 is exposed at the bottom of each contact hole CH. During this etching, the support pillar HR overlapping the contact hole CH is also partially removed. The partially removed upper surface of the support pillar HR aligns with the upper surface of one of the conductors 23.

[0101] As described with reference to Figure 7, the support pillar HR is not located in the center of the contact plug CC. Therefore, when etching the bottom of the contact hole CH to connect it to the conductor 23, the contact area between the bottom of the contact hole CH and the support pillar HR is suppressed.

[0102] As shown in Figure 27, the contact hole CH is filled with a conductor. This forms the contact plug CC.

[0103] The remaining portion of the insulator 36, the conductor 60, the contact plug CV, the conductor 25, and the insulator 37 are formed to complete the structure shown in Figures 8 and 9.

[0104] 1.3. Advantages (Effects) According to the first embodiment, a storage device including a drawer area having a small area can be provided, as described below.

[0105] Figure 28 shows a reference access area 101 of a storage device. In the access area 101, the contact plugs 103 that contact the conductor 102, which corresponds to the conductor 23 of the first embodiment, are thought to be arranged in a matrix. However, if many conductors are provided for the purpose of increasing the storage capacity, many contact plugs will be required to match the number of conductors. For this reason, the access area needs to have a large surface area.

[0106] According to the first embodiment, the contact plugs CC are distributed in a staggered arrangement. Therefore, the contact plugs CC are more densely arranged than the contact plugs 103. Thus, if the dimensions of the contact plugs 103 and CC, particularly the cross-sectional area along the x and y planes, are the same, the area of ​​the required drawout region HA1 for the arrangement of the same number of contact plugs 103 or CC is smaller than the area of ​​the required drawout region 101.

[0107] According to the first embodiment, the support pillar HR is not located in the center of the contact plug CC. Therefore, when etching the bottom of the contact hole CH to connect it to the conductor 23, the area in contact between the bottom of the contact hole CH and the support pillar HR is suppressed. Thus, the area of ​​the surface along the xy plane of the bottom of the contact hole CH that is in contact with the conductor 23 is suppressed. This reduces the resistance between the contact plug CC and the conductor 23.

[0108] 2. Second Embodiment The second embodiment differs from the first embodiment in that the shape of the contact plug CC along the xy plane is different.

[0109] Figure 29 shows an example of a planar layout of a portion of the drawer area of ​​the storage device according to the second embodiment. Figure 29 shows the same area as in Figure 7, i.e., a portion of the area between the two member SLTs, shown along the xy plane. Figure 29 shows the layout of the layer containing the conductor 24 as viewed from above along the z axis.

[0110] As shown in Figure 29, each contact plug CC has a hexagonal shape. For example, two opposing (substantially parallel) sides of each contact plug CC extend along the x-axis. The remaining four sides intersect both the x-axis and the y-axis. In other words, each contact plug CC has a shape in which the four corners of the square contact plug CC in the first embodiment have been cut off. Therefore, the position of the vertices of each contact plug CC is closer to the center than the position of the vertices of the square contact plug CC. Based on this shape, the minimum distance between adjacent contact plug CCs is large. The minimum distance between adjacent contact plug CCs is the length of the shortest virtual line among a plurality of virtual lines connecting the respective edges of two adjacent contact plug CCs. In the second embodiment, the minimum distance between two contact plug CCs is the distance between the opposing vertices of the two contact plugs, based on the fact that the contact plug CCs are arranged in the same configuration as in the first embodiment and have a hexagonal shape.

[0111] The arrangement of the contact plugs CC is the same as in the first embodiment, that is, they are distributed in a staggered pattern.

[0112] Support pillars HR include support pillars HR located in the neighborhood of four vertices VX of one or more contact plugs CC. The four vertices VX are two vertices VX formed by one edge and the other edge of two edges extending along the x-axis of the contact plug CC, and two vertices VX formed by the other edge and the other edge of two edges extending along the x-axis of the contact plug CC. Support pillars HR are located, for example, in the neighborhood of four vertices VX of each contact plug CC.

[0113] The support pillar HR is located in a region that does not overlap with the contact plug CC, for example, in the vicinity of vertices VX 1 to 4 of the four vertices VX when viewed along the xy-plane. Alternatively, the support pillar HR is located so as to include vertices VX 1 to 4 of the four vertices VX when viewed along the xy-plane. Figure 29 shows this example. Alternatively, the support pillar HR is located in a region that completely overlaps with the contact plug CC, in the vicinity of vertices VX 1 to 4 of the four vertices VX when viewed along the xy-plane.

[0114] The support pillar HR is not located in the center of one or more contact plugs CC, for example, each contact plug CC.

[0115] The arrangement of support pillars HR includes support pillars HR located in the vicinity of one or more of the four vertices VX of one or more contact plugs CC, and also in any other region of one or more contact plugs CC, for example, not located in the center of each contact plug CC. Figure 29 shows an example in which the support pillars HR are arranged in a matrix.

[0116] According to the second embodiment, the contact plug CC is arranged in the same manner as in the first embodiment. Also, according to the second embodiment, as in the first embodiment, the support pillar HR is not located in the center of the contact plug CC. Therefore, the same advantages as in the first embodiment can be obtained.

[0117] Furthermore, according to the second embodiment, it is possible to provide a memory device having a structure in which the differences from the designed and assumed structure are suppressed, as described below. When contact holes CH are formed in the manner described with reference to Figures 12 to 21 of the first embodiment, a state in which a part of the structure of the insulators 34, SM, and SM2 (hereinafter sometimes referred to as the "layered structure") has a high aspect ratio may occur during the formation process. For example, the state in Figure 19 is an example, and the aspect ratio is higher when more conductors 23 are provided for the purpose of increasing the capacity of the memory device. The aspect ratio depends on the distance between adjacent contact holes CH.

[0118] According to the second embodiment, each contact plug CC has a hexagonal shape. The minimum spacing between contact plugs CC is the distance between the vertex VX of one contact plug CC and the vertex VX of the other contact plug CC. Therefore, the minimum spacing between adjacent contact plugs CC is wide, wider than the minimum spacing between adjacent contact plugs CC when the contact plugs CC have a square shape. As a result, the aspect ratio of a portion of the stacked structure that occurs during the formation of the contact holes CH is smaller than the aspect ratio of a portion of the stacked structure when the contact plugs CC have a square shape. Thus, a portion of the stacked structure is stable, at least more stable than when the contact plugs CC have a square shape. This prevents the structure from collapsing during the manufacturing process of the memory device 1, and as a result, prevents the structure of the completed memory device 1 from differing from the designed and assumed structure.

[0119] As described above, according to the second embodiment, based on the fact that the contact plugs CC are arranged in the same way as in the first embodiment, the minimum spacing of the contact plugs CC is the distance between the opposing vertices of two diagonally aligned contact plugs. For this reason, the distance between two adjacent rows of contact plugs CC is smaller than the distance between two adjacent rows in the reference storage device. Here, the distance between two adjacent rows of contact plugs is the difference between the coordinate of the center of one row of contact plug CC on the y-axis and the coordinate of the center of the other row of contact plug CC on the y-axis. Based on the fact that the minimum spacing of the contact plugs CC is diagonally aligned, even if the distance between two adjacent rows of two contact plugs CC is smaller than the distance between adjacent rows of contact plugs 103 in the reference storage device, it is possible to maintain the same minimum spacing as the minimum spacing of the contact plugs 103 in the reference storage device. Thus, according to the second embodiment, the contact plugs CC can have the same minimum spacing as the minimum spacing of the contact plugs 103 in the reference storage device, and can be arranged more densely than the contact plugs 103 in the reference storage device. In other words, according to the second embodiment, it is possible to achieve both structural strength equivalent to that of the reference storage device and an extraction area HA having a smaller area than the extraction area 101 of the reference storage device.

[0120] The contact plug CC of the second embodiment may be circular along the xy plane, as shown in Figure 30.

[0121] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0122] 1...Memory device, 10...Memory cell array, 11...Row decoder, 12...Register, 13...Sequencer, 14...Driver, 15...Sense amplifier, BLK...Block, WL...Word line, BL...Bit line, MT...Memory cell transistor, MA...Memory area, HA1...Draw-out area, HA2...Draw-out area, SLT...Component, SHE...Component, MP...Memory pillar, CV...Contact plug, 22...Conductor, 23...Conductor, 24...Conductor

Claims

1. Multiple first conductors, spaced apart from each other and aligned along the first axis, A memory pillar extending along the first axis, facing the plurality of first conductors, and including a semiconductor and a film surrounding the semiconductor, Multiple contact plugs extending along the first axis, Equipped with, Each of the plurality of contact plugs includes a second conductor and a first insulator surrounding the second conductor. The first insulator is located between the plurality of first conductors and the second conductor, Each of the plurality of contact plugs is in contact with the upper surface of one of the plurality of first conductors, which does not overlap, at its lower surface. The plurality of contact plugs include a first contact plug, a second contact plug, and a third contact plug. The first contact plug and the second contact plug are arranged adjacent to each other along a second axis that intersects the first axis. The third contact plug is located between the first and second contact plugs on the second axis, and is positioned at a different location on the third axis which is perpendicular to the first and second axes. storage device.

2. The plurality of contact plugs further include a fourth contact plug, The third contact plug and the fourth contact plug are arranged adjacent to each other along the second axis. The second contact plug is located on the second shaft between the third contact plug and the fourth contact plug. The storage device according to claim 1.

3. Each of the plurality of contact plugs has a hexagonal shape along the first surface consisting of the second axis and the third axis. The storage device according to claim 1.

4. Each of the plurality of contact plugs has a circular shape along the first surface consisting of the second axis and the third axis. The storage device according to claim 1.

5. The present invention further comprises a plurality of insulators extending along the first axis and penetrating the plurality of first conductors, wherein the plurality of insulators are located in regions offset from the center of the shape of each of the plurality of contact plugs. The storage device according to claim 1.

6. The film of the memory pillar is A second insulator is provided between the semiconductor and the first conductor, A charge storage film is provided between the second insulator and the first conductor, A third insulator is provided between the charge storage film and the first conductor, Equipped with, The storage device according to claim 1.

7. A fourth insulator extending along the first axis, with its upper end located above the conductor provided in the uppermost layer among the plurality of first conductors, and its lower end in contact with the conductor provided in the lowermost layer among the plurality of first conductors, A plurality of fifth insulators extending along the first axis, with their upper ends in contact with the lower surfaces of each of the plurality of contact plugs and their lower ends in contact with the lowest layer of the plurality of first conductors, Furthermore, The plurality of fifth insulators are located in regions offset from the center of the shape of each of the plurality of contact plugs. The storage device according to claim 1.

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