Printed circuit board and method for manufacturing the same

Abstract

The present invention provides a printed circuit board and a method for manufacturing the same that improve die bonding reliability and underfill formation stability. [Solution] The present invention relates to a printed circuit board comprising an insulating layer, a conductive pad disposed on the insulating layer, a conductive bump disposed on the insulating layer and spaced apart from the insulating layer to cover at least a portion of the conductive pad, and a solder resist layer disposed on the insulating layer and covering at least a portion of the conductive pad and the conductive bump, wherein the conductive bump has a maximum width wider than the conductive pad, and a method for manufacturing the same.

Description

Technical Field

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[0001] The present invention relates to a printed circuit board and a method for manufacturing the same.

Background Art

[0002] The pitch of the bumps on the substrate connected to the flip chip die is continuously decreasing, and risks such as solder ball mounting and bonding reliability may occur at a fine pitch. Therefore, it is considered to apply conductive bumps. However, the conductive bumps have limitations in height, and further, there may be limitations in the resolution of the width. In addition, the size of the conductive bumps may be affected by the size of the conductive pads. At this time, when formed to be below a certain size due to the influence of the conductive pads, the bonding reliability with the die may become vulnerable. Furthermore, when the pitch is reduced, such risks may increase.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to increase the height and / or size of the conductive bumps separately from the design rules of the conductive pads, that is, separately from the design rules of the conductive pads, thereby providing a printed circuit board with improved die bonding reliability and underfill formation stability.

[0004] Another object of the present invention is to reduce the size of the conductive pads, thereby providing a printed circuit board with improved circuit density and circuit design freedom.

Means for Solving the Problems

[0005] A printed circuit board according to one aspect of the present invention, made to achieve the above objective, includes an insulating layer, a conductive pad disposed on the insulating layer, a conductive bump disposed on the insulating layer and separated from the insulating layer and covering at least a portion of the conductive pad, and a solder resist layer disposed on the insulating layer and covering at least a portion of the conductive pad and the conductive bump, wherein the conductive bump has a maximum width even wider than the conductive pad.

[0006] A method for manufacturing a printed circuit board according to one aspect of the present invention, made to achieve the above objective, is characterized by comprising the steps of: forming a conductive pad on an insulating layer; forming a first solder resist layer on the insulating layer to cover the conductive pad; reducing the thickness of the first solder resist layer to expose a portion of the conductive pad from the first solder resist layer; forming a conductive bump on the first solder resist layer to cover the exposed portion of the conductive pad; forming a second solder resist layer on the first solder resist layer to cover the conductive bump; and reducing the thickness of the second solder resist layer to expose a portion of the conductive bump from the second solder resist layer. [Effects of the Invention]

[0007] According to the present invention, the height and / or size of conductive bumps can be increased separately from the design rules of conductive pads, thereby providing a printed circuit board with improved die bonding reliability and underfill formation stability.

[0008] Furthermore, according to the present invention, the size of the conductive pads can be reduced, thereby providing a printed circuit board with improved circuit density and design flexibility. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a perspective view illustrating a typical example of an electronic device. [Figure 3]This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 4] Figure 3 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 5] This is a schematic cross-sectional view showing another example of a printed circuit board. [Figure 6] Figure 5 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 7] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 8] Figure 7 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 9] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 10] Figure 9 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 11] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 12] Figure 11 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 13] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 14] Figure 13 is a schematic process diagram illustrating an example of the manufacturing process of a printed circuit board. [Figure 15] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 16] Figure 15 is a schematic process diagram illustrating an example of the manufacturing process of a printed circuit board. [Figure 17] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 18] Figure 17 is a schematic process diagram illustrating an example of the manufacturing process of a printed circuit board. [Figure 19] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 20] Figure 19 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 21] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 22] It is a process diagram schematically showing an example of manufacturing the printed circuit board of FIG. 21. [Figure 23] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 24] It is a plan view schematically showing a top view of the printed circuit board of FIG. 23. [Figure 25] It is a cross-sectional view schematically showing another example of a printed circuit board.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, the present invention will be described with reference to the drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

[0011] FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0012] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also combined with other electronic components described later to form various signal lines 1090.

[0013] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package containing the aforementioned chips and electronic components.

[0014] The network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi® (IEEE 802.11 family, etc.), WiMAX® (IEEE 802.16 family, etc.), IEEE 802.20, LTE® (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It may also include any other diverse wireless or wired standards and protocols. Furthermore, the network-related component 1030 may be combined with the chip-related component 1020.

[0015] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks) (registered trademarks), DVDs (digital versatile disks), etc. In addition to these, depending on the type of electronic device 1000, other electronic components used for various purposes may also be included.

[0017] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and may be any other electronic device that processes data.

[0018] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0019] Referring to the drawings, the electronic device is, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the chip-related components described above, and may, for example, be a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with the active and / or passive components built-in. On the other hand, the electronic device is not necessarily limited to a smartphone 1100, but may be other electronic devices as described above.

[0020] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board.

[0021] Referring to the drawings, an example printed circuit board 100A includes an insulating layer 110, a first conductive pattern 120 disposed within the insulating layer 110, a second conductive pattern 130 and a conductive pad 140 disposed on the insulating layer 110, conductive bumps 150 disposed on the insulating layer 110 and spaced apart from the insulating layer 110, covering at least a portion of the conductive pad 140, and a solder resist layer 160 disposed on the insulating layer 110 and covering at least a portion of the second conductive pattern 130, the conductive pad 140, and the conductive bumps 150. The conductive bumps 150 have a greater maximum width than the conductive pads 140. The maximum width is measured on a cross-section, for example, as described later.

[0022] Thus, in one example, the printed circuit board 100A has conductive bumps 150 placed on an insulating layer 110, separated from the insulating layer 110 and covering at least a portion of the conductive pad 140. Both the conductive pad 140 and the conductive bumps 150 are at least partially covered by a solder resist layer 160, and in this case, the conductive bumps 150 are formed to be larger in size than the conductive pads 140. Conductive pads 140 and conductive bumps 150 with such a structure can be easily applied to the mounting of high-performance dies that require high-density input / output terminals. For example, the height of the conductive bumps 150 can be increased. This is advantageous in ensuring the standoff height between the die and the substrate, thereby further improving connection reliability with the die and the stability of underfill formation. In addition, the size of the conductive bumps 150 can be increased separately from the design rules of the conductive pads 140, thereby further advantageous in ensuring the connection strength of the die. Furthermore, the size of the conductive pad 140 can be reduced, thereby improving the circuit density and design flexibility of the second conductive pattern 130 formed in the same layer. In addition, this structure eliminates the need for the open process of the solder resist layer 160, preventing interfacial residues and feet that may occur during the open process of the solder resist layer 160, and as a result, the reliability of the conductive bump 150 can be further improved.

[0023] On the other hand, at least a portion of the solder resist layer 160 is positioned between the upper surface of the insulating layer 110 and the lower surface of the conductive bump 150, and the lower surface of the conductive bump 150 is in direct contact with the solder resist layer 160. Furthermore, the solder resist layer 160 covers a portion of the side surface of the conductive pad 140, and the conductive bump 150 covers the other portion of the side surface and the upper surface of the conductive pad 140. Additionally, the solder resist layer 160 covers a portion of the side surface of the conductive bump 150, and the other portion of the side surface and the upper surface of the conductive bump 150 protrude above the upper surface of the solder resist layer 160. With this arrangement and structure, the height of the conductive bump 150 can be increased more easily. Furthermore, the size of the conductive bump 150 can be increased more easily by separating it from the design rules of the conductive pad 140. Furthermore, the size of the conductive pad 140 can be reduced more easily. Therefore, the above-mentioned technical effects can be achieved more easily.

[0024] The conductive pad 140 has a first side surface S1 and a second side surface S2 that face each other, and the conductive bump 150 has a third side surface S3 and a fourth side surface S4 that face each other, with the third side surface S1 and the fourth side surface S4 of the conductive bump 150 protruding outward from the first side surface S1 and the second side surface S2 of the conductive pad 140, respectively. For example, the third side surface S3 of the conductive bump 150 protrudes perpendicular to the first side surface S1 of the conductive pad 140, and the fourth side surface S4 of the conductive bump 150 protrudes perpendicular to the second side surface S2 of the conductive pad 140. In this case, the length L1 of the protrusion of the third side surface S3 of the conductive bump 150 from the first side surface S1 of the conductive pad 140 and the length L2 of the protrusion of the fourth side surface S4 of the conductive bump 150 from the second side surface S2 of the conductive pad 140 are substantially the same. However, this is not limited to this, and the protruding lengths L1 and L2 may be different as needed. For example, the protruding length L1 may be longer than the protruding length L2, or conversely, the protruding length L2 may be longer than the protruding length L1. On the other hand, such a protruding structure makes it easier to increase the size of the conductive bump 150 separately from the design rules of the conductive pad 140, and furthermore, makes it easier to reduce the size of the conductive pad 140. Therefore, the above-mentioned technical effects can be achieved more easily.

[0025] On the other hand, the conductive bump 150 includes a seed layer M1 and a metal layer M2 disposed on the seed layer M1. The seed layer M1 is in direct contact with at least a portion of the conductive pad 140 and the solder resist layer 160, respectively. For example, the seed layer M1 covers the upper end of the conductive pad 140 and extends around it. The seed layer M1 can be formed by electroless plating and may include, for example, chemical copper. The metal layer M2 can be formed by electroplating and may include, for example, electrolytic copper. However, it is not limited to these. In this way, by forming the conductive bump 150 in a plating process using circuit lithography, the size of the conductive bump 150 can be set more easily, separate from the design rules of the conductive pad 140. Also, in connection with the conductive pad 140, it becomes possible to join the same metals, for example, copper (Cu) to copper (Cu), thus providing higher bonding strength. On the other hand, at least a portion of the side surface of the seed layer M1 may be recessed inward from the side surface of the metal layer M2. In this case, the solder resist layer 160 can fill the recessed space, thereby further improving bonding reliability. However, this is not limited to this, and the sides of the seed layer M1 may be left unrecessed if necessary. For example, the sides of the seed layer M1 and the sides of the metal layer M2 may be made substantially coplane.

[0026] The solder resist layer 160 includes first and second solder resist layers 161 and 162. The first solder resist layer 161 is placed on the insulating layer 110 and covers a portion of the sides of the second conductive pattern 130 and the conductive pad 140. The second solder resist layer 162 is placed on the first solder resist layer 161 and covers the other portion of the sides and the top surface of the second conductive pattern 130, and also covers a portion of the sides of the conductive bump 150. The first solder resist layer 161 is thinner than the second conductive pattern 130 and / or the conductive pad 140. Therefore, a portion of the second conductive pattern 130 and / or the conductive pad 140 protrudes above the top surface of the first solder resist layer 161. The second solder resist layer 162 is thinner than the conductive bump 150. Therefore, a portion of the conductive bump 150 protrudes above the top surface of the second solder resist layer 162. If the solder resist layer 160 includes first and second solder resist layers 161 and 162 having such a structure and arrangement, the conductive pad 140 and conductive bump 150 can be more easily realized as described above. Therefore, the above technical effects can be more easily realized. On the other hand, the first and second solder resist layers 161 and 162 contain substantially the same insulating material and can be integrated with each other without boundary separation, but are not limited to this, and may contain different insulating materials or be separated from each other by boundaries for other reasons.

[0027] On the other hand, conductive vias may be formed in the insulating layer 110 as needed, connected to at least a portion of the first conductive pattern 120, and even in this case, the conductive pad 140 does not have to be directly connected to the conductive vias formed in the insulating layer 110. For example, the conductive pad 140 has a via-less pad structure. For example, the lower surface of the conductive pad 140 is in contact with the insulating layer 110 overall. In this case, the size of the conductive pad 140 can be further reduced. If the size of the conductive pad 140 can be further reduced in this way, the line width of the conductive lines that pass around the conductive pad 140 among the conductive lines included in the second conductive pattern 130 can be further increased. Therefore, the degree of freedom in circuit design of the second conductive pattern 130 can be increased. Also, when multiple conductive pads 140 and corresponding conductive bumps 150 are formed, the pitch of the conductive bumps 150 can be made finer.

[0028] The components of a printed circuit board 100A will be described in more detail below, with reference to the drawings.

[0029] The insulating layer 110 contains an insulating material. The insulating material may include, but is not limited to, thermosetting resins such as epoxy resin, thermoplastic resins such as polyimide, or materials obtained by mixing these insulating resins with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber. Examples include prepregs, ABF (Ajinomoto Build-up Film), PID (Photo Image-able Dielectric), and RCC (Resin Coated Copper). The insulating layer 110 may consist of multiple layers as needed. The multiple layers may contain substantially the same insulating material, and the boundaries between them may be indistinct, or they may be clearly defined. Furthermore, the multiple layers may contain different insulating materials.

[0030] The first and second conductive patterns 120 and 130 each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second conductive patterns 120 and 130 may each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer, but are not limited to this. If necessary, sputtered titanium and / or sputtered copper formed by sputtering may be included as seed layers, or these may be further included together with chemical copper. The first and second conductive patterns 120 and 130 can each perform various functions depending on the design. For example, the first and second conductive patterns 120 and 130 may each include a signal transmission pattern, a power transmission pattern, a ground transmission pattern, and so on. On the other hand, these patterns can have various pattern forms such as line, trace, plane, pad, and land.

[0031] The conductive pad 140 contains a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the conductive pad 140 may include, but is not limited to, chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. If necessary, it may also include sputtered titanium and / or sputtered copper formed by sputtering as a seed layer, or further include these together with chemical copper. The conductive pad 140 can perform various functions depending on the design. For example, the conductive pad 140 may include a signal transmission pad, a power transmission pad, a ground transmission pad, and so on. The conductive pad 140 may have a circular or elliptical shape on a plane, but is not limited to these, and may have various kinds of polygonal shapes. The conductive pad 140 may be connected to at least a portion of the second conductive pattern 130, for example, to the conductive lines of the second conductive pattern 130. The conductive pad 140 may, but is not limited to, have sides that are substantially vertical. There may be multiple conductive pads 140.

[0032] The conductive bump 150 contains a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the conductive bump 150 may include, but is not limited to, chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. If necessary, it may also include sputtered titanium and / or sputtered copper formed by sputtering as a seed layer, or further include these together with chemical copper. The conductive bump 150 can perform various functions depending on the design. For example, the conductive bump 150 may include signal transmission bumps, power transmission bumps, ground transmission bumps, etc. The conductive bump 150 may have a circular or elliptical shape on a plane, but is not limited to these, and may have various kinds of polygonal shapes. The conductive bump 150 may, but is not limited to, have sides that are substantially vertical. The conductive bump 150 may, but is not limited to, substantially cover the upper end of the conductive pad 140 in a cap-like manner. The corners and edges of the upper surface of the conductive bump 150 may, but is not limited to, have a substantially vertical shape, and may also have a substantially rounded shape. If there are multiple conductive pads 140, there may be multiple conductive bumps 150 corresponding to them.

[0033] The first and second solder resist layers 161 and 162 each contain an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain inorganic and / or organic fillers together with the resin. For example, the first and second solder resist layers 161 and 162 may contain, but are not limited to, ABF (Ajinomoto Build-up Film) and SR (Solder resist), respectively. The first and second solder resist layers 161 and 162 may be of liquid type or film type, but are not limited to these. The first and second solder resist layers 161 and 162 may contain substantially the same insulating material, but are not limited to this, and may contain different insulating materials.

[0034] Figure 4 is a schematic process diagram showing an example of the manufacturing process for the printed circuit board shown in Figure 3.

[0035] Referring to the drawings, an example of a method for manufacturing a printed circuit board 100A includes the steps of: forming a first conductive pattern 120 in an insulating layer 110; forming a second conductive pattern 130 and a conductive pad 140 on the insulating layer 110; forming a first solder resist layer 161 on the insulating layer 110 to cover the conductive pad 140; reducing the thickness of the first solder resist layer 161 to expose a portion of the conductive pad 140 from the first solder resist layer 161; forming a conductive bump 150 on the first solder resist layer 161 to cover the exposed portion of the conductive pad 140; forming a second solder resist layer 162 on the first solder resist layer 161 to cover the conductive bump 150; and reducing the thickness of the second solder resist layer 162 to expose a portion of the conductive bump 150 from the second solder resist layer 162. The step of forming the conductive bump 150 involves forming the conductive bump 150 such that its maximum width is even wider than that of the conductive pad 140. The formed first and second solder resist layers 161 and 162 constitute the solder resist layer 160. The maximum width is measured on a cross-section, for example, as will be described later.

[0036] Thus, in this example of a printed circuit board manufacturing method, a first solder resist layer 161 covering the conductive pad 140 is formed on the insulating layer 110, then the thickness of the first solder resist layer 161 is reduced to expose a portion of the conductive pad 140, and the exposed portion of the conductive pad 140 is covered with a larger conductive pad 150. Furthermore, after forming a second solder resist layer 162 covering the conductive pad 150, the thickness of the second solder resist layer 162 is reduced to expose a portion of the conductive bump 150. Therefore, the height of the conductive bump 150 can be easily increased, which is advantageous in securing the standoff height between the die and the substrate, thereby improving the reliability of the connection with the die and the stability of underfill formation. In addition, the size of the conductive bump 150 can be increased separately from the design rules of the conductive pad 140, which is advantageous in securing the connection strength of the die. Furthermore, the size of the conductive pad 140 can be reduced, thereby improving the circuit density of the second conductive pattern 130 formed on the same layer and the freedom of circuit design.

[0037] On the other hand, the step of forming the conductive bump 150 includes the steps of forming a seed layer M1 on the upper surface of the first solder resist layer 161, and on the exposed upper and side surfaces of the second conductive pattern 130 and conductive pad 140, respectively; forming a plating layer M2 on the seed layer M1 in the region corresponding to the conductive pad 140 by circuit lithography and electroplating, etc.; and removing the seed layer M1 from the region of the upper surface of the first solder resist layer 161 where the plating layer M2 has not been formed by etching. The seed layer M1 can be formed by electroless plating and may include, for example, chemical copper. The metal layer M2 can be formed by electroplating and may include, for example, electrolytic copper. However, it is not necessarily limited to these. In this way, by forming the conductive bump 150 in a plating process using circuit lithography, the size of the conductive bump 150 can be set more easily, separate from the design rules of the conductive pad 140. Furthermore, in connection with the conductive pad 140, bonding between the same metals, such as copper (Cu) to copper (Cu), becomes possible, resulting in higher bonding strength. On the other hand, in the step of removing the seed layer M1 by etching, at least a portion of the side surface of the seed layer M1 beneath the plating layer M2 can be removed by flash etching or the like, resulting in the formation of a recessed space. In this case, the solder resist layer 160 can fill the recessed space, further improving bonding reliability. However, this is not limited to this, and the side surface of the seed layer M1 may be left unrecessed as needed. For example, the side surface of the seed layer M1 and the side surface of the metal layer M2 may be made substantially coplane. Also, in the step of removing the seed layer M1 by etching, at least a portion of the second conductive pattern 130 may be removed as needed. Therefore, the thickness of the conductive pad 140 may be greater than the thickness of the second conductive pattern 130.

[0038] On the other hand, the step of forming the second conductive pattern 130 and the conductive pad 140 may further include, if necessary, the step of forming conductive vias that penetrate at least a portion of the insulating layer 110 and are connected to at least a portion of the first conductive pattern 120. For example, after processing via holes in the insulating layer 110, at least a portion of the via holes is filled with plating to form conductive vias. In this case, the conductive pad 140 does not have to be directly connected to the conductive vias formed in the insulating layer 110. For example, the conductive pad 140 may be formed as a via-unconnected pad structure. In this case, the size of the conductive pad 140 can be further reduced. In this way, if the size of the conductive pad 140 can be further reduced, the line width of the conductive lines that pass around the conductive pad 140 among the conductive lines included in the second conductive pattern 130 can be further increased. Therefore, the degree of freedom in circuit design of the second conductive pattern 130 can be increased. Also, when multiple conductive pads 140 and corresponding conductive bumps 150 are formed, the pitch of the conductive bumps 150 can be made finer.

[0039] The other explanations are substantially the same as those given for printed circuit board 100A above, so we will omit any redundant explanations.

[0040] Figure 5 is a schematic cross-sectional view showing another example of a printed circuit board.

[0041] Referring to the drawings, another example of a printed circuit board 100B includes an insulating layer 110, a first conductive pattern 120 disposed within the insulating layer 110, a second conductive pattern 130 and a conductive pad 145 disposed on the insulating layer 110, a conductive bump 155 disposed on the insulating layer 110 and spaced apart from the insulating layer 110, covering at least a portion of the conductive pad 145, a solder resist layer 160 disposed on the insulating layer 110 and covering at least a portion of the second conductive pattern 130, the conductive pad 145, and the conductive bump 155, and conductive vias 170 penetrating at least a portion of the insulating layer 110 and connecting the first conductive pattern 120 and the conductive pad 145 to each other. The conductive bump 155 may have a maximum width even wider than the conductive pad 145. The maximum width is measured on a cross-section, for example, as described later.

[0042] Thus, in another example, the printed circuit board 100B has conductive bumps 155 placed on an insulating layer 110, separated from the insulating layer 110 and covering at least a portion of the conductive pad 145. Both the conductive pad 145 and the conductive bump 155 are at least partially covered by a solder resist layer 160, and in this case, the conductive bump 155 is formed to be larger in size than the conductive pad 145. Conductive pads 145 and conductive bumps 155 with such a structure can be easily applied to the mounting of high-performance dies that require high-density input / output terminals. For example, the height of the conductive bump 155 can be increased, which is advantageous in ensuring the standoff height between the die and the substrate, thereby improving connection reliability with the die and the stability of underfill formation. Also, the size of the conductive bump 155 can be increased separately from the design rules of the conductive pad 145, which is advantageous in ensuring the connection strength of the die. Furthermore, the size of the conductive pad 145 can be reduced, thereby improving the circuit density of the second conductive pattern 130 formed on the same layer and the freedom of circuit design. Furthermore, since this structure eliminates the need for the solder resist layer 160 opening process, it is possible to prevent interfacial residues and feet that may occur during the solder resist layer 160 opening process, and as a result, the reliability of the conductive bumps 155 can be further improved.

[0043] On the other hand, at least a portion of the solder resist layer 160 is positioned between the upper surface of the insulating layer 110 and the lower surface of the conductive bump 155, and the lower surface of the conductive bump 155 is in direct contact with the solder resist layer 160. Furthermore, the solder resist layer 160 covers a portion of the side surface of the conductive pad 145, and the conductive bump 155 covers the other portion of the side surface and the upper surface of the conductive pad 145. Additionally, the solder resist layer 160 covers a portion of the side surface of the conductive bump 155, and the other portion of the side surface and the upper surface of the conductive bump 155 protrude above the upper surface of the solder resist layer 160. With this arrangement and structure, the height of the conductive bump 155 can be increased more easily. Furthermore, the size of the conductive bump 155 can be increased more easily by separating it from the design rules of the conductive pad 145. Furthermore, the size of the conductive pad 145 can be reduced more easily. Therefore, the above-mentioned technical effects can be achieved more easily.

[0044] The conductive pad 145 has a first side surface S1' and a second side surface S2' that face each other, and the conductive bump 155 has a third side surface S3' and a fourth side surface S4' that face each other, with the third side surface S3' and the fourth side surface S4' of the conductive bump 155 protruding outward from the first side surface S1' and the second side surface S2' of the conductive pad 145, respectively. For example, the third side surface S3' of the conductive bump 155 protrudes perpendicular to the first side surface S1' of the conductive pad 145, and the fourth side surface S4' of the conductive bump 155 protrudes perpendicular to the second side surface S2' of the conductive pad 145. In this case, the protruding length L1' of the third side surface S3' of the conductive bump 155 from the first side surface S1' of the conductive pad 145 and the protruding length L2' of the fourth side surface S4' of the conductive bump 155 from the second side surface S2' of the conductive pad 145 are substantially the same. However, this is not limited to this, and the protruding lengths L1' and L2' may be different as needed. For example, the protruding length L1' may be longer than the protruding length L2', or conversely, the protruding length L2' may be longer than the protruding length L1'. On the other hand, such a protruding structure makes it easier to increase the size of the conductive bump 155 separately from the design rules of the conductive pad 145, and to reduce the size of the conductive pad 145. Therefore, the above-mentioned technical effects can be achieved more easily.

[0045] On the other hand, the conductive bump 155 includes a seed layer M1' and a metal layer M2' disposed on the seed layer M1'. The seed layer M1' is in direct contact with at least a portion of the conductive pad 145 and the solder resist layer 160, respectively. For example, the seed layer M1' covers the upper end of the conductive pad 145 and extends around it. The seed layer M1' can be formed by electroless plating and may include, for example, chemical copper. The metal layer M2' can be formed by electroplating and may include, for example, electrolytic copper. However, it is not limited to these. In this way, by forming the conductive bump 155 in a plating process using circuit lithography, the size of the conductive bump 155 can be set more easily, separate from the design rules of the conductive pad 145. Also, in connection with the conductive pad 145, it becomes possible to join the same metals, for example, copper (Cu) to copper (Cu), thus providing higher bonding strength. On the other hand, at least a portion of the side surface of the seed layer M1' may be recessed inward from the side surface of the metal layer M2. In this case, the solder resist layer 160 can fill the recessed space, thereby further improving bonding reliability. However, this is not limited to this, and the side surface of the seed layer M1' may be left unrecessed if necessary. For example, the side surface of the seed layer M1' and the side surface of the metal layer M2 may be made substantially coplane.

[0046] The solder resist layer 160 includes first and second solder resist layers 161 and 162. The first solder resist layer 161 is placed on the insulating layer 110 and covers a portion of the sides of the second conductive pattern 130 and the conductive pad 145. The second solder resist layer 162 is placed on the first solder resist layer 161 and covers the other portion of the sides and the top surface of the second conductive pattern 130, and further covers a portion of the sides of the conductive bump 155. The first solder resist layer 161 is thinner than the second conductive pattern 130 and / or the conductive pad 145. Therefore, a portion of the second conductive pattern 130 and / or the conductive pad 145 protrudes above the top surface of the first solder resist layer 161. The second solder resist layer 162 is thinner than the conductive bump 155. Therefore, a portion of the conductive bump 155 protrudes above the top surface of the second solder resist layer 162. If the solder resist layer 160 includes first and second solder resist layers 161 and 162 having such a structure and arrangement, the conductive pad 145 and conductive bump 155 can be more easily realized with the above-described structure. Therefore, the above-described technical effects can be more easily realized. On the other hand, the first and second solder resist layers 161 and 162 contain substantially the same insulating material and can be integrated with each other without boundary division, but are not limited to this, and may contain different insulating materials or be separated from each other by boundaries for other reasons.

[0047] On the other hand, the conductive via 170 is directly connected to the conductive pad 145. For example, the conductive pad 145 may have a via-connected pad structure. For example, at least a portion of the lower surface of the conductive pad 145 is in contact with the insulating layer 110, and at least another portion of the lower surface is in contact with the conductive via 170. In this case, the size of the conductive pad 145 is increased, resulting in better adhesion with the conductive pad 155. On the other hand, multiple conductive pads 145, and their corresponding conductive bumps 150 and conductive vias 170, may be arranged.

[0048] The components of printed circuit board 100B, as shown in the diagrams below, will be described in more detail using another example.

[0049] The insulating layer 110 contains an insulating material. The insulating material may include, but is not limited to, thermosetting resins such as epoxy resin, thermoplastic resins such as polyimide, or materials obtained by mixing these insulating resins with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber. Examples include prepregs, ABF (Ajinomoto Build-up Film), PID (Photo Image-able Dielectric), and RCC (Resin Coated Copper). The insulating layer 110 may consist of multiple layers as needed. The multiple layers may contain substantially the same insulating material, and the boundaries between them may be indistinct, or they may be clearly defined. Furthermore, the multiple layers may contain different insulating materials.

[0050] The first and second conductive patterns 120 and 130 each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second conductive patterns 120 and 130 may each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer, but are not limited to this. If necessary, sputtered titanium and / or sputtered copper formed by sputtering may be included as seed layers, or these may be further included together with chemical copper. The first and second conductive patterns 120 and 130 can each perform various functions depending on the design. For example, the first and second conductive patterns 120 and 130 may each include a signal transmission pattern, a power transmission pattern, a ground transmission pattern, and so on. On the other hand, these patterns can have various pattern forms such as line, trace, plane, pad, and land.

[0051] The conductive pad 145 contains a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the conductive pad 145 may include, but is not limited to, chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. If necessary, it may also include sputtered titanium and / or sputtered copper formed by sputtering as a seed layer, or further include these together with chemical copper. The conductive pad 145 can perform various functions depending on the design. For example, the conductive pad 145 may include a signal transmission pad, a power transmission pad, a ground transmission pad, and so on. The conductive pad 145 may have a circular or elliptical shape on a plane, but is not limited to these, and may have various kinds of polygonal shapes. The conductive pad 145 may be connected to at least a portion of the second conductive pattern 130, for example, to the conductive lines of the second conductive pattern 130. The conductive pad 145 may, but is not limited to, have sides that are substantially vertical. There may be multiple conductive pads 145.

[0052] The conductive bump 155 contains a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the conductive bump 155 may include, but is not limited to, chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. If necessary, sputtered titanium and / or sputtered copper formed by sputtering may be included as a seed layer, or these may be further included together with chemical copper. The conductive bump 155 can perform various functions depending on the design. For example, the conductive bump 155 may include signal transmission bumps, power transmission bumps, ground transmission bumps, etc. The conductive bump 155 may have a circular or elliptical shape on a plane, but is not limited to these, and may have various kinds of polygonal shapes. The conductive bump 155 may, but is not limited to, have sides that are substantially vertical. The conductive bump 155 may, but is not limited to, substantially cover the upper end of the conductive pad 145 in a cap-like manner. The corners and edges of the upper surface of the conductive bump 155 may, but is not limited to, have a substantially vertical shape, and may also have a substantially rounded shape. If there are multiple conductive pads 145, there may be multiple conductive bumps 155 corresponding to them.

[0053] The first and second solder resist layers 161 and 162 each contain an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler and / or organic filler together with the resin. For example, the first and second solder resist layers 161 and 162 may, but are not limited to, ABF (Ajinomoto Build-up Film) and SR (Solder resist), respectively. The first and second solder resist layers 161 and 162 may, but are not limited to, be of liquid type or film type. The first and second solder resist layers 161 and 162 may, but are not limited to, contain substantially the same insulating material, and may also contain different insulating materials.

[0054] The conductive via 170 contains a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the conductive via 170 may include, but is not limited to, chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. If necessary, it may also include sputtered titanium and / or sputtered copper formed by sputtering as a seed layer, or further include these together with chemical copper. The conductive via 170 may include signal transmission vias, power transmission vias, ground transmission vias, etc. The conductive via 170 has substantially tapered sides, with the width of the upper end being wider than the width of the lower end. The conductive via 170 has a fill-plated via structure. There may be multiple conductive vias 170, and if necessary, at least some of them may be connected to at least some of the second conductive pattern 130.

[0055] Figure 6 is a schematic process diagram showing an example of the manufacturing process of the printed circuit board shown in Figure 5.

[0056] Referring to the drawings, another example of a method for manufacturing a printed circuit board 100B includes the steps of: forming a first conductive pattern 120 in an insulating layer 110; forming a second conductive pattern 130 and a conductive pad 145 on the insulating layer 110; forming conductive vias 170 that penetrate at least a portion of the insulating layer 110 and connect the first conductive pattern 120 and the conductive pad 145 to each other; forming a first solder resist layer 161 on the insulating layer 110 that covers the conductive pad 145; reducing the thickness of the first solder resist layer 161 to expose a portion of the conductive pad 145 from the first solder resist layer 161; forming a conductive bump 155 on the first solder resist layer 161 that covers the exposed portion of the conductive pad 145; forming a second solder resist layer 162 on the first solder resist layer 161 that covers the conductive bump 155; and reducing the thickness of the second solder resist layer 162 to expose a portion of the conductive bump 155 from the second solder resist layer 162. The step of forming the conductive bump 155 involves forming the conductive bump 155 such that its maximum width is even wider than that of the conductive pad 145. The formed first and second solder resist layers 161 and 162 constitute the solder resist layer 160. The maximum width is measured on a cross-section, for example, as will be described later.

[0057] Thus, in the manufacturing method of a printed circuit board according to another example, a first solder resist layer 161 covering the conductive pad 145 is formed on the insulating layer 110, then the thickness of the first solder resist layer 161 is reduced to expose a portion of the conductive pad 145, and the exposed portion of the conductive pad 145 is covered with a larger conductive pad 155. Alternatively, a second solder resist layer 162 covering the conductive pad 155 is formed, and then the thickness of the second solder resist layer 162 is reduced to expose a portion of the conductive bump 155. Therefore, the height of the conductive bump 155 can be easily increased, which is advantageous in securing the standoff height between the die and the substrate, thereby improving the reliability of the connection with the die and the stability of underfill formation. In addition, the size of the conductive bump 155 can be increased separately from the design rules of the conductive pad 145, which is advantageous in securing the connection strength of the die. Furthermore, the size of the conductive pad 145 can be reduced, thereby improving the circuit density of the second conductive pattern 130 formed on the same layer and the freedom of circuit design.

[0058] On the other hand, the step of forming the conductive bump 155 includes the steps of forming a seed layer M1' on the upper surface of the first solder resist layer 161, and on the exposed upper and side surfaces of the second conductive pattern 130 and conductive pad 145, respectively; forming a plating layer 2' on the seed layer M1' in the region corresponding to the conductive pad 145 by circuit lithography and electroplating, etc.; and removing the seed layer M1' from the upper surface of the first solder resist layer 161 in the region where the plating layer M2' has not been formed by etching. The seed layer M1' can be formed by electroless plating and includes, for example, chemical copper. The metal layer M2' can be formed by electroplating and includes, for example, electrolytic copper. However, it is not necessarily limited to these. In this way, by forming the conductive bump 155 in a plating process using circuit lithography, the size of the conductive bump 155 can be set more easily, separate from the design rules of the conductive pad 145. Furthermore, in connection with the conductive pad 145, bonding between the same metals, such as copper (Cu) to copper (Cu), becomes possible, resulting in higher bonding strength. On the other hand, at the stage of removing the seed layer M1' by etching, at least a portion of the side surface of the seed layer M1' beneath the plating layer M2' can be removed by flash etching or the like, resulting in the formation of a recessed space. In this case, the solder resist layer 160 can fill the recessed space, further improving bonding reliability. However, this is not limited to this, and the side surface of the seed layer M1' may be left unrecessed as needed. For example, the side surface of the seed layer M1' and the side surface of the metal layer M2' may be made substantially coplane. Also, at the stage of removing the seed layer M1' by etching, at least a portion of the second conductive pattern 130 may be removed as needed. Therefore, the thickness of the conductive pad 145 may be greater than the thickness of the second conductive pattern 130.

[0059] Furthermore, during the stage of forming the conductive via 170, the conductive via 170 is directly connected to the conductive pad 145. For example, the conductive pad 145 may be formed in a via-connected pad structure. In this case, the size of the conductive pad 145 increases, resulting in excellent adhesion with the conductive pad 155. On the other hand, multiple conductive pads 145, and their corresponding conductive bumps 155 and conductive vias 170, may be formed.

[0060] The other explanations are substantially the same as those given for printed circuit board 100B above, so we will omit any redundant explanations.

[0061] Figure 7 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 8 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 7.

[0062] Referring to the drawings, another example of a printed circuit board 100C is that, in the printed circuit board 100A of the above-described example, the seed layer M1 of the conductive bump 150 includes a plurality of seed layers M1-1 and M1-2. Furthermore, the manufacturing method of the printed circuit board 100C of yet another example is that, in the manufacturing method of the printed circuit board 100A of the above-described example, the step of forming the seed layer M1 includes the step of forming a plurality of seed layers M1-1 and M1-2. At least one of the plurality of seed layers M1-1 and M1-2 may contain a different metal from the metal layer M2. For example, the plurality of seed layers M1-1 and M2-2 can be formed by sputtering, in which case the first seed layer M1-1 of the plurality of seed layers M1-1 and M1-2 may contain sputtered titanium, and the second seed layer M2-2 of the plurality of seed layers M1-1 and M1-2 may contain sputtered copper. Also, since the metal layer M2 can be formed by electroplating as described above, the metal layer M2 may contain electroplated copper. In this way, the adhesion strength can be improved by applying a first seed layer M1-1 containing a metal different from copper, such as sputtered titanium, to the etched surface of the first solder resist layer 161. If necessary, electroless plating can be further applied to the second seed layer M1-2, for example, further chemical copper can be formed on sputtered copper.

[0063] The remaining explanations are substantially the same as those described above for the printed circuit board 100A and its manufacturing method, so redundant explanations will be omitted.

[0064] Figure 9 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 10 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 9.

[0065] Referring to the drawings, the printed circuit board 100D according to yet another example is the printed circuit board 100B according to yet another example described above, in which the seed layer M1' of the conductive bump 155 includes a plurality of seed layers M1'-1 and M1'-2. Furthermore, the manufacturing method of the printed circuit board 100D according to yet another example is the manufacturing method of the printed circuit board 100B according to yet another example described above, in which the step of forming the seed layer M1' includes the step of forming a plurality of seed layers M1'-1 and M1'-2. At least one of the plurality of seed layers M1'-1 and M1'-2 may contain a different metal from the metal layer M2'. For example, the plurality of seed layers M1'-1 and M1'-2 can be formed by sputtering, in which case the first seed layer M1'-1 of the plurality of seed layers M1'-1 and M1'-2 contains sputtered titanium, and the second seed layer M2'-2 of the plurality of seed layers M1'-1 and M1'-2 contains sputtered copper. Furthermore, since the metal layer M2' can be formed by electroplating as described above, the metal layer M2' can contain electroplated copper. In this way, the adhesion strength can be improved by applying a first seed layer M1'-1 containing a metal different from copper, such as sputtered titanium, to the etched surface of the first solder resist layer 161. If necessary, electroless plating can be further applied to the second seed layer M1'-2, for example, further forming chemical copper on sputtered copper.

[0066] The remaining explanations are substantially the same as those described above for the printed circuit board 100B and its manufacturing method, so redundant explanations will be omitted.

[0067] Figure 11 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 12 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 11.

[0068] Referring to the drawings, in yet another example, printed circuit board 100E is formed on the upper surface of the solder resist layer 160 and on the lower surface of the conductive bump 150, in the printed circuit board 100A described above. Furthermore, the manufacturing method of printed circuit board 100E in yet another example further includes the steps of forming a rough surface on the upper surface of the solder resist layer 160 and forming a rough surface on the lower surface of the solder resist layer 160 and on the lower surface of the conductive bump 150, in the manufacturing method of printed circuit board 100A described above. For example, the upper surface of the solder resist layer 160 has a greater surface roughness than the surface of the solder resist layer 160 that contacts the side surface of the conductive pad 140 and / or the surface of the solder resist layer 160 that contacts the side surface of the conductive bump 150. In this case, the underfill flowability and adhesion can be improved during the package assembly process. Furthermore, the surface of the solder resist layer 160 that contacts the underside of the conductive bump 150 has a rougher surface than the surface of the solder resist layer 160 that contacts the side surface of the conductive pad 140 and / or the surface of the solder resist layer 160 that contacts the side surface of the conductive bump 150. In this case, it is more effective in ensuring adhesion between the conductive bump 150 and the solder resist layer 160.

[0069] On the other hand, a rough surface may also be formed at the boundary between the first and second solder resist layers 161 and 162. For example, the upper surface of the first solder resist layer 161 may have a rougher surface than the surface of the first solder resist layer 161 that contacts the side surface of the conductive pad 140. In this case, the adhesion between the first and second solder resist layers 161 and 162 can be improved. On the other hand, even if the first and second solder resist layers 161 and 162 contain substantially the same insulating material, such a rough surface may create a boundary between the first and second solder resist layers 161 and 162, but this is not limited to this, and the boundary may not be created depending on the degree of roughness, material properties, etc. Also, the upper surface of the second solder resist layer 162 that provides the upper surface of the solder resist layer 160 may have a rougher surface than the surface of the second solder resist layer 162 that contacts the side surface of the conductive bump 150. In this case, as described above, the underfill flowability and adhesion can be improved during the package assembly process.

[0070] The step of thinning the thickness of the first solder resist layer 161 includes the step of thinning the first solder resist layer 161 by etching. Similarly, the step of thinning the thickness of the second solder resist layer 162 includes the step of thinning the second solder resist layer 162 by etching. Here, the etching may be wet etching, but is not limited to this, and may also be dry etching. In this case, the surfaces of the first and second solder resist layers that have been thinned by etching will have the rough surfaces described above. For example, the upper surface of the first solder resist layer 161 has a rougher surface than the surface of the first solder resist layer 161 that contacts the side surface of the conductive pad 140. In this case, as described above, the adhesion between the first and second solder resist layers 161 and 162 can be improved. Also, the upper surface of the second solder resist layer 162 may have a rougher surface than the surface of the second solder resist layer 162 that contacts the side surface of the conductive bump 150. In this case, as mentioned above, the flowability and adhesion of the underfill can be improved during the package assembly process.

[0071] On the other hand, surface roughness refers to average roughness (Ra), which is typically a few microns to tens of microns, but is not limited to this range.

[0072] The remaining explanations are substantially the same as those described above for the printed circuit board 100A and its manufacturing method, so redundant explanations will be omitted.

[0073] Figure 13 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 14 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 13.

[0074] Referring to the drawings, the printed circuit board 100F according to yet another example is the printed circuit board 100B according to yet another example described above, in which a rough surface is formed on the upper surface of the solder resist layer 160 and a rough surface is formed at the boundary between the solder resist layer 160 and the lower surface of the conductive bump 155. Furthermore, the manufacturing method of the printed circuit board 100F according to yet another example further includes the steps of forming a rough surface on the upper surface of the solder resist layer 160 and forming a rough surface at the boundary between the solder resist layer 160 and the lower surface of the conductive bump 155, in the manufacturing method of the printed circuit board 100B according to yet another example described above. For example, the upper surface of the solder resist layer 160 has a greater surface roughness than the surface of the solder resist layer 160 that contacts the side surface of the conductive pad 145 and / or the surface of the solder resist layer 160 that contacts the side surface of the conductive bump 155. In this case, the underfill flowability and adhesion can be improved during the package assembly process. Furthermore, the surface of the solder resist layer 160 that contacts the underside of the conductive bumps 155 has a rougher surface than the surface of the solder resist layer 160 that contacts the side surface of the conductive pads 145 and / or the surface of the solder resist layer 160 that contacts the side surface of the conductive bumps 155. In this case, it is more effective in ensuring adhesion between the conductive bumps 155 and the solder resist layer 160.

[0075] On the other hand, a rough surface is also formed at the boundary between the first and second solder resist layers 161 and 162. For example, the upper surface of the first solder resist layer 161 has a rougher surface than the surface of the first solder resist layer 161 that contacts the side surface of the conductive pad 145. In this case, the adhesion between the first and second solder resist layers 161 and 162 can be improved. It should be noted that even if the first and second solder resist layers 161 and 162 contain substantially the same insulating material, such a rough surface can distinguish the boundary between the first and second solder resist layers 161 and 162, but this is not limited to this, and the boundary may not be distinguished depending on the degree of roughness, material properties, etc. Also, the upper surface of the second solder resist layer 162 that provides the upper surface of the solder resist layer 160 has a rougher surface than the surface of the second solder resist layer 162 that contacts the side surface of the conductive bump 155. In this case, as described above, the underfill flowability and adhesion can be improved during the package assembly process.

[0076] The step of thinning the thickness of the first solder resist layer 161 includes the step of thinning the first solder resist layer 161 by etching. Similarly, the step of thinning the thickness of the second solder resist layer 162 includes the step of thinning the second solder resist layer 162 by etching. Here, the etching may be wet etching, but is not limited to this, and may also be dry etching. In this case, a rough surface is formed on the thinned surfaces of the first and second solder resist layers by etching, as will be described later. For example, the upper surface of the first solder resist layer 161 has a rougher surface than the surface of the first solder resist layer 161 that contacts the side surface of the conductive pad 145. In this case, as described above, the adhesion between the first and second solder resist layers 161 and 162 can be improved. Also, the upper surface of the second solder resist layer 162 has a rougher surface than the surface of the second solder resist layer 162 that contacts the side surface of the conductive bump 155. In this case, as described above, the underfill flowability and adhesion can be improved during the package assembly process.

[0077] On the other hand, surface roughness refers to average roughness (Ra), which is typically a few microns to tens of microns, but is not limited to this range.

[0078] The remaining explanations are substantially the same as those described above for the printed circuit board 100B and its manufacturing method, so redundant explanations will be omitted.

[0079] Figure 15 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 16 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 15.

[0080] Referring to the drawings, another example of a printed circuit board 100G is a printed circuit board 100A in which a surface treatment layer 180 is placed on a portion of the conductive bumps 150 exposed from the solder resist layer 160, for example, the second solder resist layer 162. Furthermore, a method for manufacturing the printed circuit board 100G in yet another example further includes the step of forming the surface treatment layer 180 on a portion of the conductive bumps 150 exposed from the solder resist layer 160, for example, the second solder resist layer 162, in the method for manufacturing the printed circuit board 100A in which the solder resist layer 160 is placed. The surface treatment layer 180 includes a first surface treatment layer 181 placed on the exposed portion of the conductive bumps 150, and a second surface treatment layer 182 placed on the first surface treatment layer 181. The first surface treatment layer 181 contains nickel (Ni) and the second surface treatment layer 182 contains gold (Au), but is not limited to these, and various other materials can be used. The step of forming the surface treatment layer 180 includes, for example, ENIG (Electroless Nickel / Immersion Gold), ENEPIG (Electroless Nickel / Electroless Palladium / Immersion Gold), and / or ENGP (Electrolytic Nickel / Gold Plating) steps, but is not limited thereto. It may also include HASL (Hot Air Solder Leveling), ImAg (Immersion Silver), and / or ImSn (Immersion Tin) steps, as well as OSP (Organic Solderability Preservative) steps, as needed. Forming the surface treatment layer 180 in this way ensures reliability during die bonding in the packaging stage. It also prevents copper consumption.

[0081] The remaining explanations are substantially the same as those described above for the printed circuit board 100A and its manufacturing method, so redundant explanations will be omitted.

[0082] Figure 17 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 18 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 17.

[0083] Referring to the drawings, another example of a printed circuit board 100H is the printed circuit board 100B of the other example described above, in which a surface treatment layer 180 is placed on a portion of the conductive bumps 155 exposed from the solder resist layer 160, for example, the second solder resist layer 162. Furthermore, the manufacturing method of the printed circuit board 100H of the yet another example further includes the step of forming the surface treatment layer 180 on a portion of the conductive bumps 155 exposed from the solder resist layer 160, for example, the second solder resist layer 162, in the manufacturing method of the printed circuit board 100B of the other example described above. The surface treatment layer 180 includes a first surface treatment layer 181 placed on the exposed portion of the conductive bumps 155, and a second surface treatment layer 182 placed on the first surface treatment layer 181. The first and second surface treatment layers 181 and 182 may include, but are not limited to, nickel (Ni) and gold (Au), respectively, and various other materials can be used. For example, the step of forming the surface treatment layer 180 may include, but is not limited to, ENIG (Electroless Nickel / Immersion Gold), ENEPIG (Electroless Nickel / Electroless Palladium / Immersion Gold), and / or ENGP (Electrolytic Nickel / Gold Plating) steps, and may also include HASL (Hot Air Solder Leveling), ImAg (Immersion Silver), and / or ImSn (Immersion Tin) steps, as well as OSP (Organic Solderability Preservative) steps, as needed. Forming the surface treatment layer 180 in this way ensures reliability during die bonding in the packaging stage. It also prevents copper consumption.

[0084] Other explanations are substantially the same as those described above for the printed circuit board 100B and its manufacturing method, so redundant explanations will be omitted.

[0085] Figure 19 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 20 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 19.

[0086] Referring to the drawings, another example of a printed circuit board 100I is a printed circuit board 100A in the above example, in which the solder resist layer 160, for example, the second solder resist layer 162, has a cavity C that exposes a portion of each of the plurality of conductive bumps 150 from the solder resist layer 160, for example, the second solder resist layer 162, and the upper surface of the solder resist layer 160, for example, the second solder resist layer 162 has a step due to the cavity C. Furthermore, a method for manufacturing a printed circuit board 100I in another example is a method for manufacturing a printed circuit board 100A in the above example, in which the step of thinning the thickness of the second solder resist layer 162 includes a step of forming a cavity C in the second solder resist layer 162 that exposes a portion of each of the plurality of conductive bumps 150 from the second solder resist layer 162, and the upper surface of the second solder resist layer 162 has a step due to the cavity C. The cavity C may be in the form of a blind cavity having a bottom surface. The cavity C allows the solder resist layer 160, for example, the second solder resist layer 162, to have a two-tiered stepped structure.

[0087] On the other hand, the multiple conductive bumps 150 and the corresponding multiple conductive pads 140 are arranged in a region that overlaps with the cavity C. The region that overlaps with the cavity C is located within the cavity C when viewed through from a top view and / or a side view. Such a cavity C can be formed, for example, by curing the outer region 162-2 of the solder resist layer 160, for example, the second solder resist layer 162, with ultraviolet light, and etching the remaining uncured region 162-1. If necessary after etching, the uncured region 162-1 in which the cavity C has been formed can be further cured. In this case, the upper surface of the solder resist layer 160 in the region where the cavity C is formed, for example, the upper surface of the second solder resist layer 162, is formed as described above, while the upper surface of the solder resist layer 160 in the region where the cavity C is not formed, for example, the upper surface of the second solder resist layer 162, has a smooth surface. For example, the upper surface of the solder resist layer 160 in the region where cavity C is formed, for example, the upper surface of the second solder resist layer 162, has a greater surface roughness than the upper surface of the solder resist layer 160 in the region where cavity C is not formed, for example, the upper surface of the second solder resist layer 162. Surface roughness refers to the average roughness (Ra), which is several microns to several tens of microns, but is not limited to this.

[0088] In this way, the height of the solder resist layer 160, for example, the second solder resist layer 162, can be selectively reduced only in the area where the die is mounted, and a rough surface can be applied to the surface. Therefore, die mounting can be performed more effectively during the packaging stage, and reliability can be improved.

[0089] The remaining explanations are substantially the same as those described above for the printed circuit board 100A and its manufacturing method, so redundant explanations will be omitted.

[0090] Figure 21 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 22 is a schematic process diagram showing an example of the manufacturing of the printed circuit board shown in Figure 21.

[0091] Referring to the drawings, the printed circuit board 100J according to yet another example is the printed circuit board 100B according to yet another example described above, wherein the solder resist layer 160, for example, the second solder resist layer 162, has a cavity C that exposes a portion of each of the plurality of conductive bumps 155 from the solder resist layer 160, for example, the second solder resist layer 162, and the upper surface of the solder resist layer 160, for example, the second solder resist layer 162 has a step due to the cavity C. Furthermore, the manufacturing method of the printed circuit board 100J according to yet another example is the manufacturing method of the printed circuit board 100B according to yet another example described above, wherein the step of thinning the thickness of the second solder resist layer 162 includes a step of forming a cavity C in the second solder resist layer 162 that exposes a portion of each of the plurality of conductive bumps 155 from the second solder resist layer 162, and the upper surface of the second solder resist layer 162 has a step due to the cavity C. The cavity C may be in the form of a blind cavity having a bottom surface. The cavity C allows the solder resist layer 160, for example, the second solder resist layer 162, to have a two-tiered stepped structure.

[0092] On the other hand, the multiple conductive bumps 155 and the corresponding multiple conductive pads 145 are arranged in a region that overlaps with the cavity C. The region that overlaps with the cavity C is located within the cavity C when viewed through from a top view and / or a side view. Such a cavity C can be formed, for example, by curing the outer region 162-2 of the solder resist layer 160, for example, the second solder resist layer 162, with ultraviolet light, and etching the remaining uncured region 162-1. If necessary after etching, the uncured region 162-1 in which the cavity C has been formed can be further cured. In this case, the upper surface of the solder resist layer 160 in the region where the cavity C is formed, for example, the upper surface of the second solder resist layer 162, is formed as described above, while the upper surface of the solder resist layer 160 in the region where the cavity C is not formed, for example, the upper surface of the second solder resist layer 162, has a smooth surface. For example, the upper surface of the solder resist layer 160 in the region where cavity C is formed, for example, the upper surface of the second solder resist layer 162, has a greater surface roughness than the upper surface of the solder resist layer 160 in the region where cavity C is not formed, for example, the upper surface of the second solder resist layer 162. Surface roughness refers to the average roughness (Ra), which is several microns to several tens of microns, but is not limited to this.

[0093] In this way, the height of the solder resist layer 160, for example, the second solder resist layer 162, can be selectively reduced only in the area where the die is mounted, and a rough surface can be applied to the surface. Therefore, die mounting can be performed more effectively during the packaging stage, and reliability can be improved.

[0094] The remaining explanations are substantially the same as those described above for the printed circuit board 100B and its manufacturing method, so redundant explanations will be omitted.

[0095] On the other hand, the structures of the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above can be combined with each other as long as they do not contradict each other. Furthermore, the manufacturing methods of the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above can also be combined with each other as long as they do not contradict each other.

[0096] Figure 23 is a schematic cross-sectional view showing yet another example of a printed circuit board, and Figure 24 is a schematic plan view showing a top view of the printed circuit board of Figure 23.

[0097] Referring to the drawings, another example of the printed circuit board 100K may include a multilayer substrate structure comprising a plurality of insulating layers 211, 212, 213, a plurality of wiring layers 221, 222, and a plurality of via layers 231, 232, 233. The multilayer substrate structure may also be a core-type multilayer substrate structure. For example, the plurality of insulating layers 211, 212, 213 may include a core insulating layer 211, and the core insulating layer 211 may be thicker than each of the remaining insulating layers 212, 213. However, it is not limited thereto, and the multilayer substrate structure may be a coreless type multilayer substrate structure as needed. Thus, the printed circuit board 100K, having a multilayer substrate structure, can be easily used as a package substrate and / or interposer substrate on which dies are mounted. A first passivation layer 241 is placed above the multiple insulating layers 211, 212, and 213, and a second passivation layer 242 is placed below the multiple insulating layers 211, 212, and 213.

[0098] On the other hand, the uppermost insulating layer 212 among the multiple insulating layers 211, 212, and 213 may include the insulating layer 110 described in the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above. Also, the uppermost wiring layer 221 among the multiple wiring layers 221 and 222 may include the second conductive pattern 130 and conductive pads 140 and 145 described in the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above, and conductive bumps 150 and 155 may be placed on the conductive pads 140 and 145, respectively. In this case, the conductive pad 145 has a larger maximum width than the conductive pad 140, and the conductive bump 155 has a larger maximum width than the conductive bump 145. The wiring layer 221 located directly below the uppermost wiring layer 221 of the multiple wiring layers 221 and 222 includes the first conductive pattern 120 described in the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above. The uppermost via layer 232 of the multiple via layers 231, 232, and 233 includes a conductive via (not shown) or conductive via 170 described in the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above. Furthermore, the first passivation layer 241 includes the solder resist layer 160 described above in printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J, for example, the first and second solder resist layers 161 and 162.

[0099] Furthermore, the second conductive pattern 130 included in the uppermost wiring layer 221 of the multiple wiring layers 221, 222 includes multiple conductive lines 131. The multiple conductive lines 131 are connected to a portion of the multiple conductive pads 140, 145, for example, a relatively smaller conductive pad 140. At least a portion of each of the multiple conductive lines 131 is positioned between at least two of the multiple conductive pads 140, 145 on a plane, for example, between at least two of the relatively smaller conductive pads 140. In this case, conductive bumps 145, 155 can be formed on the multiple conductive pads 140, 145, respectively, thus improving the risk of side effects that may occur when the multiple conductive lines 131 are positioned between the multiple conductive pads 140, 145, for example, between the relatively smaller conductive pads 140.

[0100] On the other hand, the manufacturing methods for the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above may further include the step of forming a multilayer substrate structure of the printed circuit board 100K according to yet another example described above.

[0101] The components of the printed circuit board 100K will be described in more detail below, with reference to the drawings and using another example.

[0102] The multiple insulating layers 211, 212, and 213 include a core insulating layer 211, multiple first build-up insulating layers 212 laminated on the upper surface of the core insulating layer 211, and multiple second build-up insulating layers 213 laminated on the lower surface of the core insulating layer 211. The core insulating layer 211 and the multiple first and second build-up insulating layers 212 and 213 each contain an insulating material. As the insulating material, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated into a core material such as glass fiber together with an inorganic filler can be used. For example, the core insulating layer 211 may include an insulating material of CCL (Copper Clad Laminate) and / or a prepreg. The multiple first and second build-up insulating layers 212, 213 may each include a prepreg, ABF (Ajinomoto Build-up Film), PID (Photo Image-able Dielectric), and / or RCC (Resin Coated Copper). The multiple first and second build-up insulating layers 212, 213 may have a symmetrical structure, for example, having the same number of layers. However, they are not limited to this and may have an asymmetrical structure, for example, having different numbers of layers.

[0103] The plurality of wiring layers 221, 222 each include a plurality of first build-up wiring layers 221, each disposed on or within a plurality of first build-up insulating layers 212, and a plurality of second build-up wiring layers 222, each disposed on or within a plurality of second build-up insulating layers. The plurality of first and second build-up wiring layers 221, 222 each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The plurality of first and second build-up wiring layers 221, 222 each may include chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer, but is not limited thereto. If necessary, sputtered titanium and / or sputtered copper formed by sputtering may be included as seed layers, or these may be further included together with chemical copper. Multiple first and second build-up wiring layers 221, 222 can each perform various functions depending on the design. For example, multiple first and second build-up wiring layers 221, 222 may each include signal transmission patterns, power transmission patterns, ground transmission patterns, etc. On the other hand, these patterns can have various pattern forms such as lines, traces, planes, pads, and lands. Multiple first and second build-up wiring layers 221, 222 may have the same number of layers, but are not limited to this, and may have different numbers of layers.

[0104] The multiple via layers 231, 232, and 233 include a core via layer 231 penetrating the core insulating layer 211, multiple first build-up via layers 232 each penetrating at least a portion of the multiple first build-up insulating layers 212, and multiple second build-up via layers 233 each penetrating at least a portion of the multiple second build-up insulating layers 213. The multiple first and second build-up wiring layers 221 and 222 are electrically connected to each other via the core via layer 231 and the multiple first and second build-up via layers 232 and 233. The core via layer 231 and the multiple first and second build-up via layers 232 and 233 each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the core via layer 231 and the multiple first and second build-up via layers 232, 233 may each include chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer, but are not limited thereto. If necessary, sputtered titanium and / or sputtered copper formed by sputtering may be included as seed layers, or these may be further included together with the chemical copper. The core via layer 231 and the multiple first and second build-up via layers 232, 233 can each perform various functions depending on the design. For example, the core via layer 231 and the multiple first and second build-up via layers 232, 233 may each include signal transmission vias, power transmission vias, ground transmission vias, etc. The through vias included in the core via layer 231 have a substantially hourglass shape or cylindrical shape. The connecting vias included in the multiple first build-up via layers 232 each have a substantially tapered shape in opposite directions to each of the connecting vias included in the multiple second build-up via layers 233. The multiple first and second build-up via layers 232, 233 may have the same number of layers as each other, but are not limited to this, and may have different numbers of layers as each other.

[0105] The first and second passivation layers 241 and 242 each contain an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may include inorganic and / or organic fillers together with the resin. For example, the first and second passivation layers 241 and 242 may, but are not limited to, ABF (Ajinomoto Build-up Film) and SR (Solder resist), respectively. The first and second passivation layers 241 and 242 may, but are not limited to, be liquid or film types. The first passivation layer 241 has blind cavities C that expose a portion of each of the plurality of conductive bumps 150. The second passivation layer 242 has a plurality of openings h that expose at least a portion of the bottommost second build-up wiring layer 222. The patterns exposed to multiple apertures h may each be of the SMD (Solder Mask Defined) and / or NSMD (Non-Solder Mask Defined) type.

[0106] Other explanations are substantially the same as those described in the manufacturing methods for the printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, and 100J described above, so redundant explanations are omitted.

[0107] Figure 25 is a schematic cross-sectional view showing yet another example of a printed circuit board.

[0108] Referring to the drawings, the printed circuit board 100L according to yet another example further includes a semiconductor chip 310 mounted on the first passivation layer 241, as in the printed circuit board 100K according to yet another example described above. The semiconductor chip 310 has a plurality of electrodes 311 on its mounting surface, and each of the electrodes 311 is connected to a plurality of bumps 150 via a plurality of connecting members 320. An underfill 330 is placed between the first passivation layer 241 and the semiconductor chip 310. The underfill 330 covers at least a portion of each of the plurality of electrodes 311 and the plurality of connecting members 320. The underfill 330 can improve the bonding reliability of the semiconductor chip 310. A plurality of electrically connecting metals 350 are placed on each of the plurality of openings h of the second passivation layer 242. Thus, the printed circuit board 100L according to yet another example has a semiconductor package structure.

[0109] The components of the printed circuit board 100L will be described in more detail below, with reference to the drawings and using another example.

[0110] Each semiconductor chip 310 includes an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may be, but is not limited to, logic chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, application processor (e.g., AP), analog-to-digital converter, or ASIC (application-specific IC). It may also be other types such as memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, HBM (High Bandwidth Memory), or PMIC (Power Management IC). Multiple semiconductor chips 310 may be mounted, in which case the multiple semiconductor chips 310 may be identical or different from each other.

[0111] Multiple electrodes 311 are arranged on the active surface of the semiconductor chip 310, for example, on the active surface of the die. The multiple electrodes 311 include metals, and the metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Each of the multiple electrodes 311 may have a structure consisting of a pad, a bump, a post, or a combination thereof.

[0112] The multiple connecting members 320 and the multiple electrical connecting metals 350 are each formed of a low-melting-point metal, such as solder made of tin (Sn)-aluminum (Al)-copper (Cu), but this is merely an example and the material is not particularly limited thereto. The multiple connecting members 320 and the multiple electrical connecting metals 350 may each include solder balls or solder bumps. The multiple connecting members 320 and the multiple electrical connecting metals 350 may each be formed in multiple layers or single layers, but are not limited thereto.

[0113] Underfill 330 is formed from an epoxy resin base and may contain inorganic fillers due to its low coefficient of thermal expansion (CTE), but the material is not necessarily limited to this. Underfill 330 possesses high adhesive strength, low viscosity, excellent thermal conductivity, and mechanical strength. Therefore, it can improve the reliability of the semiconductor chip 310.

[0114] Other explanations are substantially the same as those described in the manufacturing methods for printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, and printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, so redundant explanations are omitted.

[0115] In this invention, the expression "cover" includes not only cases of covering the entire object but also cases of covering at least a part of it, and includes not only cases of direct covering but also cases of indirect covering. Furthermore, the expression "fill" includes not only cases of complete filling but also cases of at least a part of it, and cases of general filling. For example, this includes cases where some gaps or voids exist. Furthermore, the expression "enclose" includes not only cases of complete enclosure but also cases of partial enclosure and general enclosure. In addition, "expose" includes not only cases of complete exposure but also cases of partial exposure, and "exposure" means that the component is exposed from what is embedded in it. For example, when an opening exposes a pad, it means that the pad is exposed from the outermost insulating layer, and a surface treatment layer or the like is further placed on the exposed pad.

[0116] In this invention, the determination includes process errors, positional deviations, and measurement errors that substantially occur during the manufacturing process. For example, "placed at substantially the same level" includes not only cases where they are placed in exactly the same position, but also cases where they are placed in approximately the same position. Furthermore, "having substantially a specific shape" includes not only cases where they have exactly that shape, but also cases where they have approximately that shape. For example, it is determined by the overall shape. Also, "substantially the same insulating material" means not only cases where the insulating material is completely identical, but also cases where it is the same type of insulating material. Therefore, although the composition of the insulating material is substantially the same, the specific composition ratios may differ slightly.

[0117] In this invention, "on a cross-section" refers to the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" refers to the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0118] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and the technical scope of this invention is not particularly limited by such descriptions of direction, and the concepts of up / down can be changed at any time.

[0119] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where physically connected and cases where not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component.

[0120] In this invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc., can be measured using a scanning microscope or optical microscope, etc., based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points.

[0121] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0122] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0123] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Component Package 1130 Camera Module 1140 speaker 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L Printed Circuit Board 110 Insulating layer 120, 130 conductive patterns 140, 145 conductive pads 150, 155 conductive bumps 160, 161, 162 Solder resist layer 170 conductive vias 180, 181, 182 Surface treatment layer 211, 212, 213 Insulating layer (core insulating layer, build-up insulating layer) 221, 222 wiring layers (build-up wiring layers) 231, 232, 233 via layers (through-beam layers, build-up via layers) 241, 242 Passivation Layer 310 semiconductor chips 311 Electrode 320 Connecting Member 330 Underfill M1, M1-1, M1-2 seed layers M2 Metal layer (plating layer) C Cavity h aperture

Claims

1. Insulating layer and, A conductive pad disposed on the insulating layer, A conductive bump is disposed on the insulating layer and covers at least a portion of the conductive pad, separated from the insulating layer. The solder resist layer is disposed on the insulating layer and covers at least a portion of the conductive pad and the conductive bump, The conductive bump is characterized in that it has a wider maximum width than the conductive pad.

2. At least a portion of the solder resist layer is disposed between the upper surface of the insulating layer and the lower surface of the conductive bump. The printed circuit board according to claim 1, characterized in that the lower surface of the conductive bump is in direct contact with the solder resist layer.

3. The solder resist layer covers a portion of the side surface of the conductive pad. The printed circuit board according to claim 1, characterized in that the conductive bump covers another portion of the side surface and the top surface of the conductive pad.

4. The solder resist layer covers a portion of the side surface of the conductive bump. The printed circuit board according to claim 1, characterized in that the other parts of the sides and the top surface of the conductive bump protrude above the top surface of the solder resist layer.

5. The conductive pad has first and second sides facing each other, The conductive bump has third and fourth sides facing each other, The printed circuit board according to claim 1, characterized in that the third and fourth sides of the conductive bump each protrude outward more than the first and second sides of the conductive pad each.

6. The printed circuit board according to claim 5, characterized in that the protruding length from the first side surface to the third side surface is different from the protruding length from the second side surface to the fourth side surface.

7. The conductive bump includes a seed layer and a metal layer disposed on the seed layer. The printed circuit board according to claim 1, characterized in that the seed layer is in direct contact with at least a portion of the conductive pad and the solder resist layer, respectively.

8. The printed circuit board according to claim 7, characterized in that at least a portion of the side surface of the seed layer is recessed inward from the side surface of the metal layer.

9. The aforementioned seed layer includes multiple seed layers, The printed circuit board according to claim 7, characterized in that one or more of the plurality of seed layers contain a metal different from the metal layer.

10. The aforementioned plurality of seed layers include sputtered titanium and sputtered copper. The printed circuit board according to claim 9, characterized in that the metal layer contains electrolytic copper.

11. The printed circuit board according to claim 1, characterized in that at least a portion of the upper surface of the solder resist layer has a surface roughness greater than one or more of the surfaces of the solder resist layer that contact the side surface of the conductive pad and the surfaces of the solder resist layer that contact the side surface of the conductive bump.

12. The printed circuit board according to claim 1, characterized in that the surface of the solder resist layer that contacts the lower surface of the conductive bump has a surface roughness greater than one or more of the surfaces of the solder resist layer that contacts the side surface of the conductive pad and the surfaces of the solder resist layer that contact the side surface of the conductive bump.

13. A portion of the conductive bump is exposed from the solder resist layer. The printed circuit board according to claim 1, characterized in that a surface treatment layer is disposed on a portion of the exposed conductive bump.

14. The surface treatment layer includes a first surface treatment layer disposed on an exposed portion of the conductive bump, and a second surface treatment layer disposed on the first surface treatment layer. The first surface treatment layer contains nickel (Ni), The printed circuit board according to claim 13, characterized in that the second surface treatment layer contains gold (Au).

15. The solder resist layer has a cavity that exposes a portion of the conductive bump from the solder resist layer. The printed circuit board according to claim 1, characterized in that the upper surface of the solder resist layer has a step due to the cavity.

16. The solder resist layer includes a first solder resist layer disposed on the insulating layer and covering a portion of the side surface of the conductive pad, and a second solder resist layer disposed on the first solder resist layer and covering a portion of the side surface of the conductive bump. The first solder resist layer is thinner than the conductive pad. The printed circuit board according to claim 1, characterized in that the second solder resist layer is thinner than the conductive bumps.

17. At least a portion of the upper surface of the first solder resist layer has a surface roughness greater than the surface of the first solder resist layer that is in contact with the side surface of the conductive pad. The printed circuit board according to claim 16, characterized in that at least a portion of the upper surface of the second solder resist layer has a surface roughness greater than the surface of the second solder resist layer that is in contact with the side surface of the conductive bump.

18. The printed circuit board according to claim 16, characterized in that the first and second solder resist layers are integrated with each other without boundary divisions.

19. A conductive pattern arranged within the insulating layer, The printed circuit board according to claim 1, further comprising conductive vias that penetrate at least a portion of the insulating layer and are connected to the conductive pattern.

20. The lower surface of the conductive pad is in overall contact with the insulating layer. The printed circuit board according to claim 19, characterized in that the conductive pad is not directly connected to the conductive via.

21. At least a portion of the lower surface of the conductive pad is in contact with the insulating layer, and at least another portion of the lower surface is in contact with the conductive via. The printed circuit board according to claim 19, characterized in that the conductive pad is directly connected to the conductive via.

22. The printed circuit board includes a multilayer substrate structure comprising a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers. The uppermost insulating layer among the plurality of insulating layers includes the insulating layer, The printed circuit board according to claim 1, characterized in that the uppermost wiring layer among the plurality of wiring layers includes the conductive pad.

23. The plurality of insulating layers include a core insulating layer, a plurality of first build-up insulating layers disposed on the upper surface of the core insulating layer, and a plurality of second build-up insulating layers disposed on the lower surface of the core insulating layer. The plurality of wiring layers include a plurality of first build-up wiring layers, each disposed on or within the plurality of first build-up insulating layers, and a plurality of second build-up wiring layers, each disposed on or within the plurality of second build-up insulating layers. The plurality of via layers include a through-via layer penetrating the core insulating layer, a plurality of first build-up via layers each penetrating at least a portion of the plurality of first build-up insulating layers, and a plurality of second build-up via layers each penetrating at least a portion of the plurality of second build-up insulating layers. The printed circuit board according to claim 22, characterized in that the core insulating layer is thicker than each of the plurality of first and second build-up insulating layers.

24. Multiple conductive pads and conductive bumps are arranged, The uppermost wiring layer further includes a plurality of conductive lines, The printed circuit board according to claim 22, characterized in that each of the plurality of conductive lines is arranged in a plane at least in part between at least two of the plurality of conductive pads.

25. The uppermost via layer among the plurality of via layers includes one or more conductive vias connected to one or more of the plurality of pads. The printed circuit board according to claim 24, characterized in that one or more conductive pads among the plurality of pads that are connected to one or more conductive vias have a maximum width greater than each of the one or more conductive pads among the plurality of pads that are not connected to one or more conductive vias.

26. The steps include forming a conductive pad on an insulating layer, The steps include forming a first solder resist layer on the insulating layer to cover the conductive pad, The steps include reducing the thickness of the first solder resist layer to expose a portion of the conductive pad from the first solder resist layer, The steps include forming conductive bumps on the first solder resist layer to cover an exposed portion of the conductive pad, The steps include forming a second solder resist layer on the first solder resist layer to cover the conductive bumps, A method for manufacturing a printed circuit board, characterized by including the step of reducing the thickness of the second solder resist layer to expose a portion of the conductive bump from the second solder resist layer.

27. The method for manufacturing a printed circuit board according to claim 26, characterized in that the step of forming the conductive bump is characterized in that the conductive bump is formed such that the maximum width of the conductive bump is even wider than that of the conductive pad.

28. The method for manufacturing a printed circuit board according to claim 26, characterized in that the step of forming the conductive bumps includes the steps of forming a seed layer on the upper surface of the first solder resist layer and on the exposed upper and side surfaces of the conductive pad, forming a plating layer on the seed layer, and removing the seed layer by etching in the area of ​​the upper surface of the first solder resist layer on which the plating layer has not been formed.

29. The step of forming the seed layer includes the step of forming a plurality of seed layers. The method for manufacturing a printed circuit board according to claim 28, characterized in that one or more of the plurality of seed layers contain a metal different from the plating layer.

30. The step of reducing the thickness of the first solder resist layer includes the step of thinning the first solder resist layer by etching. The step of reducing the thickness of the second solder resist layer includes the step of thinning the second solder resist layer by etching, The method for manufacturing a printed circuit board according to claim 26, characterized in that a rough surface is formed on the thinned surface of the first and second solder resist layers by etching.

31. The process further includes the step of forming a surface treatment layer on an exposed portion of the conductive bump, The method for manufacturing a printed circuit board according to claim 26, characterized in that the step of forming the surface treatment layer includes one or more steps from among ENIG (Electroless Nickel / Immersion Gold), ENEPIG (Electroless Nickel / Electroless Palladium / Immersion Gold), and ENGP (Electrolytic Nickel / Gold Plating).

32. The step of reducing the thickness of the second solder resist layer includes the step of forming a cavity in the second solder resist layer that exposes a portion of the conductive bumps, The method for manufacturing a printed circuit board according to claim 26, characterized in that a step is formed on the upper surface of the second solder resist layer by the cavity.

33. The steps include forming a conductive pattern within the insulating layer, The method for manufacturing a printed circuit board according to claim 26, further comprising the step of forming a conductive via that penetrates at least a portion of the insulating layer and is connected to the conductive pattern.

34. The method for manufacturing the printed circuit board includes manufacturing a multilayer substrate structure comprising a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers. The uppermost insulating layer among the plurality of insulating layers includes the insulating layer, The method for manufacturing a printed circuit board according to claim 26, characterized in that the uppermost wiring layer among the plurality of wiring layers includes the conductive pad.

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