Image sensor and imaging device

Abstract

This suppresses the superposition of noise on the pixel signal caused by increases and decreases in charge during charge transfer in the image sensor. [Solution] An image sensor comprising a first semiconductor chip having a first block, a second block, and a third block, and a second semiconductor chip having a first circuit section, a second circuit section, and a third circuit section, wherein the first circuit section is positioned to overlap with the first block in the stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked, the second circuit section is positioned to overlap with the second block in the stacking direction, and the third circuit section is positioned to overlap with the third block in the stacking direction.

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] In an imaging device in which pixels are arranged in a matrix, there is a device that electronically realizes a global shutter by transferring charges simultaneously using a memory circuit composed of a transistor and a storage capacitor (see, for example, Patent Document 1). Patent Document 1: JP-A-2011-119950

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, after the charges are transferred simultaneously, pixel signals based on the charges are sequentially read. Therefore, as the number of pixels increases, the time from when the charges are transferred until the pixel signals are read becomes longer, and the charges increase or decrease, making it easy for noise to be added to the pixel signals.

Means for Solving the Problems

[0004] In a first embodiment of the present invention, an image sensor comprises a first block having a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and a third photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit, and a block arranged in the column direction alongside the first block having a fourth photoelectric conversion unit that converts light into electric charge, and a fifth photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the fourth photoelectric conversion unit A first semiconductor chip having a second block having a photoelectric conversion unit that converts light into electric charge and a sixth photoelectric conversion unit arranged in the row direction alongside a fourth photoelectric conversion unit; a third block having a seventh photoelectric conversion unit that converts light into electric charge, an eighth photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside a seventh photoelectric conversion unit; and a ninth photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside a seventh photoelectric conversion unit; and stacked with the first semiconductor chip A semiconductor chip comprising: a first circuit section including a first signal processing unit that performs signal processing on a first signal based on a charge converted by a first photoelectric conversion unit and a second signal based on a charge converted by a second photoelectric conversion unit; a second circuit section including a third signal processing unit that performs signal processing on a third signal based on a charge converted by a third photoelectric conversion unit; a second circuit section including a third signal processing unit that performs signal processing on a fourth signal based on a charge converted by a fourth photoelectric conversion unit and a fifth signal based on a charge converted by a fifth photoelectric conversion unit; and a fourth signal processing unit that performs signal processing on a sixth signal based on a charge converted by a sixth photoelectric conversion unit; and a seventh photoelectric conversion unit The second semiconductor chip includes a third circuit section which includes a fifth signal processing unit that performs signal processing on a seventh signal based on the charge converted by the first photoelectric conversion unit and an eighth signal based on the charge converted by the eighth photoelectric conversion unit, and a sixth signal processing unit that performs signal processing on a ninth signal based on the charge converted by the ninth photoelectric conversion unit. The first circuit section is positioned to overlap with the first block in the stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked, the second circuit section is positioned to overlap with the second block in the stacking direction, and the third circuit section is positioned to overlap with the third block in the stacking direction.

[0005] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of a back-illuminated image sensor according to this embodiment. [Figure 2] This diagram illustrates the pixel arrangement and unit blocks of the imaging chip. [Figure 3] This is a circuit diagram corresponding to a pixel. [Figure 4] This shows a schematic representation of the unit block, its surrounding circuits, and their connection relationships. [Figure 5] This shows a general overview of the connections between peripheral circuits and other components. [Figure 6] This is a block diagram showing the configuration of the imaging device according to this embodiment. [Figure 7] This is a block diagram showing the specific configuration of the drive unit. [Figure 8] This chart shows the timing of operations such as charge accumulation and transfer in pixels. [Figure 9] This shows the timing chart for the operation of reading out the pixel signal from each pixel. [Figure 10] This is a timing chart showing the readout timing of multiple pixels included in the imaging unit. [Figure 11] Another example of the connection relationships of peripheral circuits, etc., is shown. [Modes for carrying out the invention]

[0007] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] Figure 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. These imaging chip 113, signal processing chip 111, and memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like.

[0009] As shown in the figure, the incident light mainly enters in the Z-axis positive direction, indicated by the white arrow. In this embodiment, the side of the imaging chip 113 that the incident light enters is referred to as the back surface. Also, as shown in the coordinate axes, the direction to the right of the paper perpendicular to the Z-axis is the X-axis positive direction, and the direction towards the front of the paper perpendicular to the Z-axis and X-axis is the Y-axis positive direction. In some of the following figures, the coordinate axes are displayed with the coordinate axes of Figure 1 as the reference point, so that the orientation of each figure can be seen.

[0010] An example of an imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is located on the back side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged in two dimensions, and transistors 105 provided corresponding to the PDs 104.

[0011] A color filter 102 is provided on the incident light side of the PD layer 106 via a passivation film 103. The color filter 102 has multiple types that transmit different wavelength regions and has a specific arrangement corresponding to each PD 104. The arrangement of the color filter 102 will be described later. A set of color filter 102, PD 104, and transistor 105 forms one pixel.

[0012] Microlenses 101 are provided on the incident light side of the color filter 102, corresponding to each pixel. The microlenses 101 focus the incident light toward the corresponding PD 104.

[0013] The wiring layer 108 has a wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and passive elements and active elements may be provided.

[0014] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with a plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and when the imaging chip 113 and the signal processing chip 111 are pressed together, etc., the aligned bumps 109 are joined to each other and electrically connected.

[0015] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps are aligned with each other, and when the signal processing chip 111 and the memory chip 112 are pressed together, etc., the aligned bumps 109 are joined to each other and electrically connected.

[0016] Note that for the joining between the bumps 109, not only Cu bump joining by solid-phase diffusion but also micro bump bonding by solder melting may be adopted. Also, for example, about one bump 109 may be provided for one output wiring described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Also, in the peripheral region outside the pixel region where the pixels are arranged, bumps larger than the bumps 109 corresponding to the pixel region may be provided together.

[0017] The signal processing chip 111 has TSVs (through-silicon vias) 110 that connect the circuits provided on the front and back surfaces to each other. The TSVs 110 are preferably provided in the peripheral region. Also, the TSVs 110 may be provided in the peripheral region of the imaging chip 113 and the memory chip 112.

[0018] FIG. 2 is a diagram for explaining the pixel array of the imaging chip 113 and the unit block 131. In particular, it shows how the imaging chip 113 is observed from the back side. The imaging chip 113 has an imaging unit in which more than 20 million pixels are arranged in a matrix. In the example of FIG. 2, 16 adjacent pixels of 4 pixels × 4 pixels form one unit block 131. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form the unit block 131.

[0019] As shown in the partial enlarged view of the imaging unit, the unit block 131 includes four so-called Bayer arrays each consisting of 4 pixels of green pixels Gb, Gr, blue pixel B, and red pixel R, in the up, down, left, and right directions. The green pixels Gb, Gr have green filters as the color filters 102 and receive light in the green wavelength band of the incident light. Similarly, the blue pixel B has a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band.

[0020] In FIG. 2, for the sake of simplicity of explanation, an example in which the unit block 131 consists of 16 pixels of 4 pixels × 4 pixels has been described. Hereinafter, an example in which the unit block 131 has pixels arranged in L rows and P columns for a total of (L × P) pixels will be described. There is no particular limitation on the number of rows and columns, but when the entire number of pixels in the imaging unit is about 20 million pixels, for example, it is 64 rows and 32 columns. Also, an example in which the unit block 131 is arranged in m rows and n columns for a total of (m × n) to form the imaging unit will be described.

[0021] FIG. 3 is a circuit diagram corresponding to the pixel 150. In FIG. 3, a rectangle typically surrounded by a dotted line represents a circuit corresponding to one pixel 150. At least a part of each transistor described below corresponds to the transistor 105 in FIG. 1.

[0022] PD104 is connected to transfer transistor 154, and the gate of transfer transistor 154 is connected to wiring Tx_i_j, which supplies the transfer pulse. The subscript i is a sequential number for the entire imaging unit that identifies unit block 131. The subscript j is a sequential number within unit block 131 that identifies the row number within unit block 131.

[0023] The drain of the transfer transistor 154 is connected to the source of the reset transistor 152. This forms a so-called floating diffusion (FD) 156 between the drain of the transfer transistor 154 and the source of the reset transistor 152. The drain of the reset transistor 152 is connected to the wiring Vdd to which the power supply voltage is supplied, and its gate is connected to the wiring Rst_i_j to which the reset pulse is supplied.

[0024] One end of FD156 is further connected to the source of pass transistor 158. The gate of pass transistor 158 is connected to the wiring Wrt_i_j to which the pass pulse is supplied, and its drain is connected to one end of storage capacitor 160. These pass transistor 158 and storage capacitor 160 form a so-called memory circuit.

[0025] One end of the storage capacitor 160 is further connected to the gate of the amplification transistor 162. The drain of the amplification transistor 162 is connected to the wiring Vdd to which the power supply voltage is supplied. The source of the amplification transistor 162 is connected to the drain of the corresponding selection transistor 164. The gate of the selection transistor 164 is connected to the wiring Sel_i_j to which the selection pulse is supplied.

[0026] The source of the selection transistor 164 is connected to the column transmission line 170. The load current source 166 supplies current to the column transmission line 170. In other words, the column transmission line 170 to the selection transistor 164 is formed by a source follower.

[0027] Figure 4 shows a schematic of the unit block 131 and its peripheral circuits 133, as well as their connection relationships. In the unit block 131 in Figure 4, pixels 150 are arranged in a row of L x P columns, totaling (P x L) pixels.

[0028] The wiring Rst_i_l (where l is an integer from 1 to L) is connected to the row control unit 200 and is also commonly connected to the P pixels 150 in the lth row within the unit block 131. Similarly, the wiring Tx_i_l, Wrt_i_l, and Sel_i_l are also connected to the row control unit 200 and are also commonly connected to the P pixels 150 in the lth row within the unit block 131.

[0029] The row control unit 200 is sometimes called a row selection unit, vertical scanning circuit, etc. A row control unit 200 is provided for each unit block 131. The row control unit 200 may also be provided on the signal processing chip 111 side.

[0030] A column transmission path 170 is provided for each pixel 150 in the same column. These column transmission paths 170_p (where p is an integer from 1 to P) are commonly connected to the L pixels 150 in the p-th column within the unit block 131. As a result, the column transmission paths 170 are shared by the pixels 150 in the same column within the unit block 131 and transmit signals from the pixels 150 included in that column.

[0031] These column transmission lines 170_p are connected from the imaging chip 113 side to peripheral circuits 133 located on the signal processing chip 111 side via bumps 109. Peripheral circuits 133 are provided for each unit block 131 and are arranged to overlap with the unit blocks 131 on the imaging chip 113 when viewed from the stacking direction.

[0032] The peripheral circuit 133 has CDS circuits 202 and A / D conversion circuits 204 connected in series for each column transmission line 170_p. In the example shown in Figure 4, there are P pairs of CDS circuits 202 and A / D conversion circuits 204 provided per unit block 131.

[0033] The peripheral circuit 133 further includes a shift register 206 located on the output side of the P A / D conversion circuits 204. In the example in Figure 4, one shift register 206 is provided for each unit block 131. The output of the shift register 206 is connected to a shift register 210 via a column bus line 172.

[0034] Figure 5 shows a schematic diagram of the connection relationships of peripheral circuits 133, etc. Corresponding to the arrangement of unit blocks 131 in m rows and n columns, the peripheral circuits 133 are also arranged in m rows and n columns.

[0035] A column bus line 172 is provided for each peripheral circuit 133 in the same column. This column bus line 172_u (where u is an integer from 1 to n) is commonly connected to the m peripheral circuits 133 in the u-th column. As a result, the column bus line 172 is shared by the unit block 131 in the same column and transmits signals from the unit block 131 included in that column.

[0036] Furthermore, since the row bus line 172 is shared by peripheral circuits 133 in the same row, the output of each peripheral circuit 133 is configured to be controlled by an output selection circuit (not shown). For example, the output of 172 in Figure 4 is enabled or disabled. When disabled, it is controlled by setting it to high impedance, etc.

[0037] A shift register 210 is placed on the output side of the n column bus lines 172 described above. In the example in Figure 5, one shift register 210 is placed on the entire image sensor 100. The shift register 210 holds the signals transmitted from the n column bus lines 172 and outputs them sequentially. Note that the shift registers 206 and 210 are sometimes called horizontal scanning circuits, multiplexers, etc.

[0038] Figure 6 is a block diagram showing the configuration of the imaging device according to this embodiment. The imaging device 500 includes an imaging lens 520 as an imaging optical system, which guides the subject light beam incident along the optical axis OA to the image sensor 100. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. The imaging device 500 mainly comprises an image sensor 100, a system control unit 501, a drive unit 502, a photometering unit 503, a work memory 504, a recording unit 505, and a display unit 506.

[0039] The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. In Figure 6, it is represented by a single virtual lens positioned near the pupil. The drive unit 502 performs charge accumulation control of the image sensor 100, pixel signal readout control, etc., according to instructions from the system control unit 501.

[0040] The image sensor 100 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to perform various image processing operations and generate image data. For example, when generating image data in JPEG file format, it performs white balance processing, gamma processing, etc., followed by compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.

[0041] The photometering unit 503 detects the brightness distribution of the scene prior to a series of shooting sequences that generate image data. The photometering unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each area of ​​the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. Note that the pixels used in the AE sensor may be provided within the image sensor 100, in which case it is not necessary to provide a separate photometering unit 503 from the image sensor 100.

[0042] Figure 7 is a block diagram showing the specific configuration of the drive unit 502. The drive unit 502 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, a signal control unit 444, a pixel memory 414, and an arithmetic circuit 415, which are assigned control functions, and a drive control unit 420 that comprehensively controls each of these control units. The drive unit 502 further includes an I / F circuit 418 between the drive control unit 420 and the system control unit 501 of the imaging device 500 main body.

[0043] The drive control unit 420 refers to the timing memory 430 and converts the instructions from the system control unit 501 into control signals that can be executed by each control unit and passes them on to each unit. The timing memory 430 is formed by flash RAM or the like.

[0044] The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel, which are sent to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation of target pixels by sending reset pulses, transfer pulses, and pass pulses to the row control units 200 of each unit block 131, and outputs pixel signals to the column transmission path 170 by sending selection pulses to readout pixels.

[0045] The block control unit 442 sends a specific pulse to the imaging chip 113 that identifies the unit block 131 to be controlled. The transfer pulses that each pixel receives via wiring Tx_i_j etc. are the logical AND of each pulse sent by the sensor control unit 441 and the specific pulse sent by the block control unit 442. In this way, each region can be controlled as an independent block. When synchronized pulses are used for multiple unit blocks 131, or when operations are performed that span multiple unit blocks 131, the block control unit 442 simultaneously sends a specific pulse that identifies each of these multiple unit blocks.

[0046] The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, decimation control, etc., can be realized, which controls only specific pixels belonging to the same unit block 131. The signal control unit 444 is also responsible for timing control of the CDS circuit 202, A / D conversion circuit 204, shift registers 206 and 210.

[0047] The arithmetic circuit 415 calculates AE evaluation values ​​and the like based on the pixel values ​​stored in the pixel memory 414. The arithmetic circuit 415 outputs the calculation results to the drive control unit 420.

[0048] The pixel memory 414 has a memory space capable of storing pixel values ​​from the pixels 150 of the imaging unit, and stores the respective pixel values ​​that have been read out and digitized from each pixel. The pixel memory 414 is provided with a data transfer interface that transmits pixel signals according to a handover request. The data transfer interface is connected to a data transfer line that is connected to the image processing unit 511. The data transfer line is configured, for example, as a data bus within a bus line. In this case, the handover request from the system control unit 501 to the drive control unit 420 is executed by address specification using the address bus.

[0049] The transmission of pixel signals via a data transfer interface can employ various methods, not limited to address-based methods. For example, a double data rate method can be used, which utilizes both the rising and falling edges of the clock signal used for synchronization of each circuit during data transfer. Alternatively, a burst transfer method can be employed to transfer data all at once by omitting some steps such as addressing, thereby increasing speed. Furthermore, a combination of methods such as a bus system using a line connecting the control unit, memory unit, and input / output unit in parallel, or a serial system that transfers data one bit at a time in series, can also be employed.

[0050] With this configuration, the image processing unit 511 can receive only the necessary pixel values, allowing for high-speed image processing, especially when forming low-resolution images. The drive unit 502, the row control unit 200 in Figure 4, the peripheral circuit 133, and the shift register 210 in Figure 5 function as a readout unit that sequentially reads the pixel signals of the pixels 150 included in the imaging unit across multiple unit blocks 131.

[0051] Figure 8 shows the timing chart for operations such as charge accumulation and transfer in pixel 150. The following explanation of charge accumulation and transfer operations in pixel 150 in Figure 3 will use Figure 8 to describe the process.

[0052] As an initial state, at time t0, the drive unit 502 turns on the reset transistor 152, the transfer transistor 154, and the pass transistor 158 by setting the voltages of the wiring Rst_i_j, Tx_i_j, and Wrt_i_j high via the row control unit 200. This resets PD104, FD156, and the storage capacitor 160.

[0053] At time t1, when an input to start imaging is received, such as by pressing the release button, the drive unit 502 turns off the transfer transistor 154 by setting the wiring Tx_i_j low. As a result, the light incident on PD104 is converted into photoelectric charge and begins to accumulate.

[0054] At time t2, immediately before the set charge accumulation end time t3, the drive unit 502 turns off the reset transistor 152 and pass transistor 158 by setting the voltages of wiring Rst_i_j and Wrt_i_j low, and then sends a transfer pulse that sets wiring Tx_i_j high from the end time t3 to time t4. As a result, the charge converted photoelectrically by PD104 is accumulated in FD156.

[0055] After time t4, the drive unit 502 sends a transfer pulse that sets wiring Wrt_i_j high from time t5 to time t6. As a result, the charge accumulated in FD156 is transferred to the storage capacitor 160, and the charge is held, isolated from subsequent charge accumulation in PD104. At the following time t7, wiring Rst_i_j is set high, ending the charge accumulation and transfer operation.

[0056] The operation of one pixel 150 in Figure 3 has been explained above. However, as shown in Figure 4, within the unit block 131, the wiring Rst_i_j etc. are commonly connected to P pixels 150 in the same row. Therefore, the operation in Figure 8 above is executed simultaneously at least for pixels 150 in the same row within the unit block 131.

[0057] Furthermore, during global shutter operation, the operation shown in Figure 8 is simultaneously performed on the pixels 150 in row L of the m x n unit block 131. That is, for wiring Rst_i_j etc., where the subscript i ranges from 1 to m x n and the subscript j ranges from 1 to L, the high and low states are simultaneously switched according to Figure 8. This allows the image light incident on each pixel 150 at the same time to be photoelectrically converted and the charge to be retained. Unless otherwise specified, the following explanation assumes that global shutter operation has been performed.

[0058] Figure 9 shows the timing chart for the operation of reading out the pixel signal of pixel 150. The operation of reading out the pixel signal of pixel 150 to the column transmission path 170 will be explained below using Figure 9.

[0059] At time t8, which is later than time t7, the drive unit 502 turns on the selection transistor 164 by setting the wiring Sel_i_j high. As a result, a voltage as a pixel signal corresponding to the voltage generated by the charge stored in the storage capacitor 160 is output to the column transmission line 170. Furthermore, with the wiring Sel_i_j high, the drive unit 502 sends a pass pulse that sets the wiring Wrt_i_j high. As a result, a voltage as a reset signal at the node between the storage capacitor 160 and the amplification transistor 162 is output to the column transmission line 170. At the following time t9, the drive unit 502 ends the readout for the pixel 150 by setting the wiring Sel_i_j low.

[0060] The CDS circuit 202 removes noise based on the pixel signal and reset signal. The A / D conversion circuit 204 converts the pixel signal, from which noise has been removed by the CDS circuit 202, into a digital signal and outputs it.

[0061] Figure 10 is a timing chart showing the readout timings of multiple pixels 150 included in the imaging unit. As explained in Figure 9, the pass pulse for wiring Wrt_i_j is sent with wiring Sel_i_j set to high, so for the sake of simplicity, only the timing chart for wiring Sel_i_j is shown in Figure 9.

[0062] In the readout of the entire imaging unit, first, the first row of pixels 150 in the entire imaging unit is selected. That is, the first row of pixels 150 in the first row of the unit block 131 is selected. In the example in Figure 5, the first row of unit block 131 corresponds to subscript i from 1 to n. Therefore, the drive unit 502 sends a selection pulse that simultaneously sets the wiring Sel_i_1 (where i is from 1 to n) high to the row control unit 200 of the corresponding unit block 131.

[0063] As described above, within the unit block 131, the wiring Sel_i_1 is commonly connected at the first row of pixels 150. Furthermore, a selection pulse is sent to the first row of unit block 131. Therefore, the pixel signals of the first row of pixels 150 are read out to the respective column transmission lines 170 across multiple unit blocks 131.

[0064] Each column transmission path 170 transmits the pixel signal from the pixel 150 selected by the row control unit 200 to the CDS circuit 202 of the corresponding column within the unit block 131. The pixel signal is denoised in the CDS circuit 202, converted into a digital signal in the A / D conversion circuit 204, and input to the shift register 206. Through this read operation, the shift register 206 receives the P digital signals of the first row in the unit block 131 via each of the column transmission paths 170 and temporarily holds them.

[0065] The shift register 206 sequentially outputs P digital signals to the shift register 210 via the column bus line 172. In this case, it is preferable that the signals are transmitted synchronously among the unit blocks 131 of the first row. Through this read operation, the shift register 210 receives the pixels 150 of the first row of the entire imaging unit, i.e., P × n digital signals.

[0066] The shift register 210 sequentially outputs P × n digital signals to the pixel memory 414, and the pixel memory 414 stores these digital signals as pixel values. In this case, it is preferable that the shift register 210 outputs the digital signals in the order in which the pixels 150 are arranged in the entire imaging unit. In the example shown in Figures 4 and 5, the digital signals of the first row of pixels 150 in the first unit block 131 (i=1) are output P times from left to right, then the digital signals of the first row of pixels 150 in the second unit block 131 (i=2) are output P times from left to right, and so on.

[0067] With the above steps, the reading of the first row of pixels 150 in the entire imaging unit is completed. Next, the second row of pixels 150 in the entire imaging unit is selected. That is, the second row of pixels 150 in the first row of unit block 131 is selected. The drive unit 502 sends a selection pulse that simultaneously sets the wiring Sel_i_2 (where i is from 1 to n) high to the row control unit 200 of the corresponding unit block 131. As a result, the pixel signal of the second row of pixels 150 is read out, similar to the first row of pixels 150, and output as a pixel value to the pixel memory 414.

[0068] From the third line onward, the above operation is repeated until the last line (line L) within the unit block 131. This completes the reading of the pixels 150 contained in the first line of the unit block 131.

[0069] Next, the pixel 150 of the (L+1)th row in the entire imaging unit is selected. That is, the pixel 150 of the first row in the second row unit block 131 is selected. The drive unit 502 sends a selection pulse to the row control unit 200 of the corresponding unit block 131, which simultaneously sets the wiring Sel_i_1 (where i is from (n+1) to 2n) high. As a result, similar to the case of the first row unit block 131, the pixel signal of the pixel 150 of the first row in the second row unit block 131 is read out and output as a pixel value to the pixel memory 414. Similarly, rows (L+2) through 2L in the entire imaging unit, that is, rows 2 through L of the second row unit block 131, are read out sequentially. This completes the reading out of the pixels 150 included in the second row unit block 131.

[0070] Subsequently, rows (2L+1) through L×m of the entire imaging unit, that is, from row 1 of the 3rd row unit block 131 to row L of the mth row unit block 131, are read out sequentially. This completes the reading of (L×P)×(n×m) pixels 150 contained in the entire imaging unit, i.e., the m x n column unit block 131.

[0071] In the above embodiment, the pixel signal is converted to a digital signal by the peripheral circuit 133 before being input to the shift register 210, which sequentially outputs pixels to the pixel memory 414. Therefore, it is possible to suppress the superposition of noise while the signal is held in the shift register 210. Furthermore, since the pixel signal is converted to a digital signal before being input to the shift register 206 by the peripheral circuit 133, it is possible to suppress the superposition of noise while the signal is held in the shift register 206.

[0072] Furthermore, by dividing the imaging unit into multiple unit blocks 131 and arranging the peripheral circuits 133 corresponding to each unit block 131 on the signal processing chip 111 side, A / D conversion can be performed before input to the shift registers 206 and 210 without reducing the area of ​​the PD 104. Moreover, even if the unit blocks 131 are arranged in a matrix, and the pixels 150 within each unit block 131 are also arranged in a matrix, the pixel signal corresponding to the matrix arrangement of the pixels 150 in the entire imaging unit can be output. As a result, the pixel memory 414, image processing unit 511, etc., do not need to use additional circuits or processing due to the division of the imaging unit into unit blocks 131.

[0073] Figure 11 shows another example of the connection relationships of peripheral circuits 133, etc. In Figure 11, components identical to those in Figure 5 are given the same numbers and their explanations are omitted.

[0074] Matrix switches 220 are connected to the output sides of n column bus lines 172. The output sides of the matrix switches 220 are connected to shift registers 206_1 through 206_k.

[0075] The matrix switch 220 inputs the digital signals transmitted to the column bus line 172 to one of several shift registers 206, for each unit block 131 included in the corresponding column. For example, the digital signals from column bus lines 172_1 and 172_2 are input to shift register 206_1, and the digital signals from column bus lines 172_3 and 172_4 are input to shift register 206_2.

[0076] Furthermore, the matrix switch 220 may dynamically change the combination of the column bus line 172 and the shift register 206_1, etc. For example, when reading from a portion of the unit blocks 131 of the imaging unit during video recording, live view (also called through-image display, etc.), crop shooting, etc., the combination of the column bus line 172 of the unit block 131 to be read and the shift register 206_1, etc. may be set. For example, when reading n / 2 unit blocks 131, these unit blocks 131 may be allocated from the shift register 206_1 to the shift register 206_k as evenly as possible. This allows the pixel signal to be transmitted at the preset maximum transmission frequency whether the pixel signal is output from m x n unit blocks 131 or from a smaller number of unit blocks 131.

[0077] Although the above embodiment describes an example in which a global shutter is used, it is not necessary to use a global shutter. In this case, charge accumulation and transfer may occur simultaneously within a unit block 131, and these may occur in a temporal order between multiple unit blocks 131. Alternatively, charge accumulation and transfer may occur in a temporal order between pixels 150 within a unit block 131. Whether or not to use a global shutter may be selected by the user or automatically set based on the shooting conditions.

[0078] Although a memory circuit is used at pixel 150 in Figure 3, this memory circuit is not required. In that case, a mechanical shutter, for example, may be used as the global shutter.

[0079] The peripheral circuit 133 in Figure 4 has a CDS circuit 202 and an A / D conversion circuit 204 for each column. The number of CDS circuit 202 and A / D conversion circuit 204 pairs may be more or less than this. For example, a pair of CDS circuit 202 and A / D conversion circuit 204 may be provided for one pixel 150. In this case, the pair of CDS circuit 202 and A / D conversion circuit 204 is provided on the signal processing chip 111 side, the output lines for each pixel 150 are connected via bumps 109, and a column transmission path may be provided on the signal processing chip 111 side to transmit the output of the A / D conversion circuit 204 for each column.

[0080] In Figure 4, the peripheral circuit 133 sequentially inputs P digital signals for one row into the shift register 210 via the shift register 206. Alternatively, P column bus lines 172 may be provided for each column, and the peripheral circuit 133 may simultaneously input P digital data to the shift register 210 via these column bus lines 172. Furthermore, the number of column bus lines 172 may correspond to the number of bits in each column, transmitting the digital signals simultaneously in terms of the number of bits, or fewer lines may be provided per column, transmitting the signals sequentially in terms of the number of bits.

[0081] In Figure 10, selection pulses are sent sequentially for each row of the unit block 131. Alternatively, selection pulses may be sent simultaneously to all m rows and n columns of the unit block 131. That is, transfer pulses may be sent simultaneously to all i values ​​from 1 to m × n in the wiring Sel_i_j. In this case, the drive unit 502 controls the timing of each shift register 206 of the unit block 131 in the same column, so that P digital signals are sent from the shift register 206 corresponding to one unit block 131, and then P digital signals are sent from the shift register 206 corresponding to the next unit block 131, according to the order of the column.

[0082] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0083] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0084] 100 Image sensor, 101 Microlens, 102 Color filter, 103 Passivation film, 104 PD, 105 Transistor, 106 PD layer, 107 Wiring, 108 Wiring layer, 109 Bump, 110 TSV, 111 Signal processing chip, 112 Memory chip, 113 Imaging chip, 131 Unit block, 133 Peripheral circuitry, 150 Pixel, 152 Reset transistor, 154 Transfer transistor, 156 FD, 158 Pass transistor, 160 Storage capacitor, 162 Amplifier transistor, 164 Selection transistor, 166 Load current source, 170 Column transmission line, 172 Column bus line, 200 Row control unit, 202 CDS circuit, 204 A / D conversion circuit, 206 Shift register, 210 Shift register, 220 Matrix switch, 414 Pixel memory, 415 418 I / F circuit, 420 drive control unit, 430 timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 500 imaging device, 520 imaging lens, 501 system control unit, 502 drive unit, 503 photometering unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit, 512 calculation unit

Claims

[Claim 1] A first block having a first photoelectric conversion unit that converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, and a third photoelectric conversion unit that converts light into electric charge and is arranged in the row direction alongside the first photoelectric conversion unit, a block arranged in the column direction alongside the first block having a fourth photoelectric conversion unit that converts light into electric charge, a fifth photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the fourth photoelectric conversion unit, and A first semiconductor chip comprising: a second block having a photoelectric conversion unit for conversion, a sixth photoelectric conversion unit arranged in the row direction alongside the fourth photoelectric conversion unit; a third block arranged in the row direction alongside the first block, having a seventh photoelectric conversion unit for converting light into electric charge; an eighth photoelectric conversion unit for converting light into electric charge, arranged in the column direction alongside the seventh photoelectric conversion unit; and a ninth photoelectric conversion unit for converting light into electric charge, arranged in the row direction alongside the seventh photoelectric conversion unit; A semiconductor chip stacked with the first semiconductor chip, the second semiconductor chip having a first circuit section including a first signal processing unit that performs signal processing on a first signal based on a charge converted by the first photoelectric conversion unit and a second signal based on a charge converted by the second photoelectric conversion unit, and a second signal processing unit that performs signal processing on a third signal based on a charge converted by the third photoelectric conversion unit; a second circuit section including a third signal processing unit that performs signal processing on a fourth signal based on a charge converted by the fourth photoelectric conversion unit and a fifth signal based on a charge converted by the fifth photoelectric conversion unit, and a fourth signal processing unit that performs signal processing on a sixth signal based on a charge converted by the sixth photoelectric conversion unit; a third circuit section including a fifth signal processing unit that performs signal processing on a seventh signal based on a charge converted by the seventh photoelectric conversion unit and an eighth signal based on a charge converted by the eighth photoelectric conversion unit, and a sixth signal processing unit that performs signal processing on a ninth signal based on a charge converted by the ninth photoelectric conversion unit. Equipped with, The first circuit section is positioned in a location that overlaps with the first block in the stacking direction in which the first semiconductor chip and the second semiconductor chip are stacked. The second circuit section is positioned in a location that overlaps with the second block in the stacking direction. The third circuit section is an image sensor positioned to overlap with the third block in the stacking direction.

Images