Wiring board and method for manufacturing a wiring board

Abstract

Suppression of delamination of the conductor layer from the insulating layer in a wiring board. [Solution] The wiring board of the embodiment comprises an insulating layer 11 and a conductor layer formed in contact with the upper surface of the insulating layer. The conductor layer includes a gas vent hole DGH that penetrates the conductor layer and exposes the upper surface of the insulating layer 11, and the gas vent hole DGH has a substantially rectangular planar shape.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] In the wiring board disclosed in Patent Document 1, a metal layer composed of a seed layer and a metal plating film is formed on an insulating layer. The metal layer has circular degassing holes (degas holes). The formation of the degas holes includes the formation of a metal plating layer in an opening of a plating resist layer formed on the seed layer, and the removal of the plating resist layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the wiring board disclosed in Patent Document 1, the planar shape of the degas holes formed in the metal layer is circular. In the removal of the plating resist layer in the formation of the degas holes, it is considered that peeling failure of the plating resist layer may occur.

Means for Solving the Problems

[0005] The wiring board of the present invention includes an insulating layer and a conductor layer formed in contact with the upper surface of the insulating layer. The conductor layer includes degassing holes that penetrate the conductor layer and expose the upper surface of the insulating layer, and the degassing holes have a substantially rectangular planar shape.

[0006] The present invention provides a method for manufacturing a wiring substrate, comprising: forming a metal film layer on the upper surface of an insulating layer; forming a plating resist on the metal film layer; forming an opening pattern in the plating resist; forming a plating film layer within the opening pattern; exposing the upper surface of the metal film layer by removing the plating resist; and removing the exposed metal film layer. The formation of the opening pattern includes forming a gas venting hole resist with a substantially rectangular planar shape.

[0007] According to embodiments of the present invention, the occurrence of peeling defects of the plating resist can be suppressed, and peeling (lifting) of the conductor layer from the insulating layer can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2] A diagram showing the planar shape of a gas vent hole in a wiring board according to one embodiment of the present invention. [Figure 3A] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3B] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3C] A plan view illustrating one step in the manufacturing method of a wiring board according to one embodiment of the present invention. [Figure 3D] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3E] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3F] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3G] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3H] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3I]A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Figure 3J] A cross-sectional view illustrating one step in the manufacturing process of a wiring board according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Next, a wiring board according to one embodiment of the present invention will be described with reference to the drawings. Note that the drawings referenced below are not intended to show the exact proportions of each component, but are drawn in a way that facilitates understanding of the features of the present invention. Figure 1 shows a cross-section of a wiring board 1, which is an example of a wiring board according to this embodiment. The illustrated wiring board 1 has a laminate 100 having one surface 100A and the other surface 100B which is the opposite surface of the first surface 100A. A first build-up portion 10 is formed on the first surface 100A. A second build-up portion 20 is formed on the other surface 100B. In the following description, the laminate 100 will also be referred to as the core substrate 100. The core substrate 100 has an insulating layer (core insulating layer) 101 and a conductor layer (core conductor layer) 102.

[0010] In the following description of the wiring board, the side furthest from the core insulating layer 101 will be referred to as "top," "upper side," "outside," or "outer," while the side closer to the core insulating layer 101 will be referred to as "bottom," "lower side," "inside," or "inner." Furthermore, in each insulating layer and conductor layer, the surface facing away from the core insulating layer 101 will be referred to as the "top surface," and the surface facing the core insulating layer 101 will be referred to as the "bottom surface." Therefore, for example, in the description of each element constituting the core substrate 100, the first build-up section 10, and the second build-up section 20, the side furthest from the core insulating layer 101 will be referred to as "top," "upper side," "upper layer side," "outside," or simply "top" or "outer," while the side closer to the core insulating layer 101 will be referred to as "bottom," "lower side," "lower layer side," "inside," or simply "bottom" or "inner."

[0011] The core conductor layer 102 that constitutes one surface 100A of the core substrate 100 and the core conductor layer 102 that constitutes the other surface 100B are connected by a through-conductor 103 that penetrates the core insulating layer 101 in the thickness direction. The hollow portion inside the through-conductor 103 is filled with a filler 103f.

[0012] The first build-up portion 10 is composed of an insulating layer 11 and a conductor layer 12 that are alternately laminated on one surface 100A of the core substrate 100. The second build-up portion 20 is composed of an insulating layer 21 and a conductor layer 22 that are alternately laminated on the other surface 100B of the core substrate 100. The insulating layer 11 that constitutes the first build-up portion 10 and the insulating layer 21 that constitutes the second build-up portion 20 each include via conductors 13 and 23 that connect conductor layers formed in contact with two opposite surfaces in the thickness direction.

[0013] A solder resist layer SR1 is formed on the first build-up portion 10. A solder resist layer SR2 is formed on the second build-up portion 20. An opening SR1o is formed in the solder resist layer SR1, and a conductor pad 12p of the outermost conductor layer 12 in the first build-up portion 10 is exposed from the opening SR1o. An opening SR2o is formed in the solder resist layer SR2, and a conductor pad 22p of the outermost conductor layer 22 in the second build-up portion 20 is exposed from the opening SR2o.

[0014] The core insulating layer 101, the insulating layer 11 that constitutes the first build-up portion 10, and the insulating layer 21 that constitutes the second build-up portion 20 are each formed using an insulating resin such as, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin. Each of the insulating layers 101, 11, 21 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. In the illustrated example, the insulating layer 101 contains a core material, and the other insulating layers 11, 21 do not contain a core material.

[0015] The conductor layers 102, 12, 22, through-conductor 103, and via conductors 13, 23 can be formed using any metal such as copper or nickel. For example, the conductor layers 102, 12, 22 can be formed by a metal foil such as a copper foil and / or a metal film formed by plating or sputtering. The conductor layers 102, 12, 22, through-conductor 103, and via conductors 13, 23 are shown in a single-layer structure in FIG. 1 for ease of viewing, but may have a multilayer structure of two or more layers. The conductor layer 102 can have a five-layer structure including a metal foil, a metal film layer (e.g., electroless copper plating film), and a plating film layer (e.g., electrolytic copper plating film). The conductor layers 12, 22, through-conductor 103, and via conductors 13, 23 can have a two-layer structure including, for example, a metal film layer (e.g., electroless copper plating film) and a plating film layer (e.g., electrolytic copper plating film).

[0016] Each of the conductor layers 102, 12, 22 included in the wiring substrate 1 is patterned to have a predetermined conductor pattern. In the wiring substrate of the embodiment, the conductor layer formed on the upper surface of the insulating layer is formed in a pattern including degassing holes (degas holes). In the illustrated example, the conductor layers 12, 22 are formed to include a so-called solid pattern, and degassing holes are formed in each solid pattern. Specifically, the conductor layer 12 is formed to include a solid pattern 12PL that extends over a predetermined range in contact with the upper surface of the insulating layer 11 as shown in the region II surrounded by the dashed-dotted line, and a plurality of degassing holes DGH are formed in the solid pattern 12PL. The degassing holes DGH penetrate the conductor layer 12 in the thickness direction, and the insulating layer 11 is exposed at the bottom of the degassing holes DGH.

[0017] Gas can be generated from each insulating layer that makes up a wiring board. If the gas generated from the insulating layer accumulates inside the wiring board, it can cause blistering of the wiring board and impair the flatness of the wiring board surface. In particular, if gas accumulates at the interface between the conductor layer and the inner insulating layer, the conductor layer may peel off from the insulating layer, causing the conductor layer to lift. By forming the conductor layer of the wiring board in a pattern with gas vents, the possibility of gas generated from the insulating layer remaining inside the conductor layer is reduced, and the gas is more easily released to the outside of the wiring board. Therefore, blistering of the wiring board and peeling of the conductor layer from the insulating layer can be suppressed.

[0018] The gas vents DGH formed in the solid pattern 12PL of the illustrated wiring board 1 are formed as gas discharge paths that move gas generated from the inner insulating layer 11 and insulating layer 101 toward the outside of the wiring board 1. As will be described later with reference to Figure 2, the gas vents DGH included in the wiring board of the embodiment have a substantially rectangular planar shape. Here, "planar shape" means the shape that can be recognized when the wiring board is viewed from a line of sight parallel to its thickness direction (i.e., viewed from above).

[0019] Next, Figure 2, a top view of the solid pattern 12PL contained in the conductor layer 12 in region II enclosed by the dashed line in Figure 1, is shown in plan view, and the configuration of the gas vent holes DGH formed in the solid pattern 12PL is described in detail. In Figure 2, a top view is shown of the solid pattern 12PL in region II of the wiring board 1 with the upper components removed. Therefore, in Figure 2, the upper surface of the solid pattern 12PL and the upper surface of the insulating layer 11 below the solid pattern 12PL are exposed.

[0020] The solid pattern 12PL shown in the illustration has multiple gas vents DGH with a roughly rectangular planar shape. As shown in the illustration, the multiple gas vents DGH are arranged in a grid pattern. Here, grid pattern means that the multiple gas vents DGH are regularly arranged in at least one of two perpendicular directions in a plan view. Because the multiple gas vents DGH are arranged in a grid pattern and formed over a relatively wide area, local gas accumulation on the lower surface of the solid pattern 12PL can be suppressed. Gas can be discharged to the outside more effectively. Each gas vent DGH has a roughly rectangular planar shape, and the area of ​​each gas vent DGH in a plan view is relatively small, for example, 8000 μm². 2 The above, and 30,000 μm 2 The following applies:

[0021] Because the planar shape of the gas vent hole DGH is approximately rectangular, peeling (lifting) of the solid pattern 12PL from the insulating layer 11 can be effectively suppressed, as will be described in more detail later in the manufacturing method of the wiring board. Regarding the planar shape of the gas vent hole DGH, "approximately rectangular" means a shape in which two approximately parallel long sides and two approximately parallel short sides are connected approximately perpendicularly via four corners. For example, this may include shapes in which the four corners have shapes other than strict right angles (e.g., R-shaped corners).

[0022] The dimensions and area of ​​each of the multiple vent holes DGH that can be formed in the solid pattern 12PL may differ from one another. From the viewpoint of effectively suppressing delamination (lifting) of the solid pattern 12PL from the insulating layer 11, the ratio of the longer side to the shorter side in the substantially rectangular shape of the vent hole DGH is preferably, for example, 1.2 or more and 5.0 or less.

[0023] Next, using the case where the wiring board 1 shown in Figure 1 is manufactured as an example, an example of a manufacturing method for a wiring board according to one embodiment will be explained with reference to Figures 3A to 3J. In Figures 3A to 3B and 3I to 3J, cross-sections of the area corresponding to Figure 1 are shown, and each conductor layer is shown as a single layer. In Figures 3C to 3H, the area corresponding to region II in Figure 1 is shown, and each of the multiple layers constituting the conductor layer (metal film layer and plating film layer) is shown.

[0024] First, as shown in Figure 3A, a core substrate 100 is prepared. For example, a double-sided copper-clad laminate is prepared in which a metal foil (copper foil) is provided on the surface of the core insulating layer 101. Through holes 103o are formed in the double-sided copper-clad laminate, for example by drilling, and a metal film layer, for example an electroless copper plating film, is formed on the inner wall of the through holes 103o and the upper surface of the metal foil. On the metal film layer, a plating film layer, for example an electrolytic copper plating film, is formed by electrolytic plating using this metal film layer as a power supply layer.

[0025] The inside of the through-conductor 103 formed on the inner wall of the through-hole 103o is filled with filler 103f, for example by injecting epoxy resin. After the filler 103f has solidified, a metal film layer and a plating film layer are further formed on the upper surface of the filler 103f and the plating film layer. As a result, although shown as a single layer in the figure, a core conductor layer 102 having a five-layer structure of metal foil, metal film layer, plating film, metal film layer, and plating film layer is formed on both sides of the core insulating layer 101. Then, by patterning the core conductor layer 102 using a subtractive method, a core substrate 100 having a predetermined conductor pattern is obtained.

[0026] Next, as shown in Figure 3B, a first build-up section 10 is formed by alternately stacking a plurality of insulating layers 11 and conductive layers 12 on one surface 100A of the core substrate 100. On the other surface 100B, a second build-up section 20 is formed by alternately stacking a plurality of insulating layers 21 and conductive layers 22. For example, each insulating layer 11, 21 can be formed by thermocompression bonding a film-like insulating resin, such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, onto the core substrate 100. The conductive layers 12, 22 are formed using a semi-additive method simultaneously with via conductors 13, 23 that fill openings in the insulating layers 11, 21, for example, by laser light. The manufacturing method of the wiring board of this embodiment includes forming vent holes in the formation of the conductive layers.

[0027] Next, with reference to Figures 3C to 3H, the formation of region C in Figure 3B, which corresponds to region II in Figure 1 (specifically, the formation of the solid pattern 12PL having gas vents DGH), will be explained. Figure 3C shows the stage in the process of forming the conductive layer 12 (solid pattern 12PL) shown in region C in Figure 3B, where a metal film layer 12a is formed on the upper surface of the insulating layer 11. The metal film layer 12a is formed, for example, as an electroless copper plating film layer by electroless plating. The metal film layer 12a may also be formed by sputtering.

[0028] Next, as shown in Figure 3D, a plating resist DFR is formed on the metal film layer 12a. The plating resist DFR is formed by, for example, forming a resin layer containing a photosensitive polyhydroxyether resin, epoxy resin, phenol resin, or polyimide resin using a laminating roll, and then exposure and development using a mask having an appropriate aperture pattern. The plating resist DFR is formed to have an aperture DFRo corresponding to the pattern that the conductive layer 12 (see Figure 3H) in contact with the upper surface of the insulating layer 11 should have (i.e., a solid pattern 12PL with gas vents DGH).

[0029] Figure 3E shows a top view of the state shown in Figure 3D. Multiple substantially rectangular partial DFRh of the plating resist DFR formed on the metal film layer 12a correspond to the positions where vent holes DGH are formed in a later process (see Figure 2). Therefore, partial DFRh are also called vent hole resist DFRh. Opening DFRo of the plating resist DFR, where the metal film 12a is exposed at the bottom, correspond to the positions where a solid pattern 12PL is formed in a later process (see Figure 2). That is, forming a pattern of opening DFRo on the plating resist DFR includes forming vent hole resist DFRh having a substantially rectangular planar shape. In the illustrated example, multiple substantially rectangular vent hole resist DFRh are formed during the formation of the opening DFRo. The opening DFRo can be formed such that multiple vent hole resist DFRh are arranged in a grid pattern in a planar view.

[0030] Each of the multiple roughly rectangular DFRh portions of the plating resist DFR is, for example, 8000 μm. 2 The above, and 30,000 μm 2 It may be formed to have the following areas. Furthermore, each of the multiple portions DFRh of the roughly rectangular shape may be formed such that the ratio of the longer side to the shorter side is, for example, 1.2 or more and 5.0 or less.

[0031] Next, as shown in Figure 3F, for example, the interior of the opening DFRo of the plating resist DFR is filled with the plating film layer 12b by electroplating using the metal film layer 12a as a power supply layer.

[0032] Next, the plating resist DFR is removed, and the upper surface of the metal film layer 12a is exposed, as shown in Figure 3G. In removing the plating resist DFR, a chemical solution such as a sodium hydroxide solution is used to peel the plating resist DFR from the metal film layer 12a and the plating film layer 12b. The gas venting hole resist DFRh has a substantially rectangular planar shape, which allows it to be peeled more reliably from the metal film layer 12a and the plating film layer 12b. Specifically, because the gas venting hole resist DFRh has a substantially rectangular planar shape, strain due to stress caused by swelling of the gas venting hole resist DFRh when using the chemical solution is more likely to occur locally (for example, in the shorter direction), allowing it to be removed more easily from the metal film layer 12a and the plating film layer 12b. In particular, by forming the resist DFRh for gas venting holes such that the ratio of the longer side to the shorter side of the roughly rectangular shape is, for example, 1.2 or more and 5.0 or less, the resist DFRh for gas venting holes can be more reliably removed from the metal film layer 12a and the plating film layer 12b.

[0033] Next, the metal film layer 12a exposed from the plating film layer 12b is removed by etching, exposing the upper surface of the insulating layer 11 as shown in Figure 3H. The formation of the solid pattern 12PL with gas vents DGH is completed.

[0034] As described above, in the manufacturing method of the wiring board of the embodiment, the resist DFRh for the gas venting holes can be removed more reliably because its planar shape is formed to be substantially rectangular. Therefore, the remaining residue of the resist DFRh for the gas venting holes is suppressed, and the metal film layer 12a in the portion corresponding to the gas venting hole DGH can be removed more reliably. The gas venting hole DGH can be formed more reliably. Gas generated from the insulating layer during the manufacturing process of the wiring board can be more reliably discharged to the outside of the wiring board, and the occurrence of delamination of the conductor layer from the insulating layer can be suppressed.

[0035] After the manufacturing process, which includes the steps shown in Figures 3C to 3H, has resulted in the state shown in Figure 3B, a solder resist layer SR1 is formed on the first build-up section 10 and a solder resist layer SR2 is formed on the second build-up section 20, as shown in Figure 3I. The solder resist layers SR1 and SR2 are composed of, for example, a photosensitive epoxy resin or polyimide resin and can be formed by spray coating, curtain coating, or lamination.

[0036] Next, as shown in Figure 3J, an opening SR1o is formed in the solder resist layer SR1 to expose the conductor pad 12p, and an opening SR2o is formed in the solder resist layer SR2 to expose the conductor pad 22p. The openings SR1o and SR2o are formed by exposure and development using a mask having an appropriate opening pattern. A surface protective film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, or heat-resistant preflux may be formed on the exposed surfaces of the conductor pads 12p and 22p by electroless plating, solder leveling, or spray coating. The wiring board 1 is completed by going through the above steps.

[0037] The wiring boards of the embodiments are not limited to those having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. The wiring boards of the embodiments may have a conductive layer formed on an insulating layer, having a substantially rectangular gas vent hole in its planar shape. The wiring boards are not limited to those having a core substrate, and may be coreless substrates.

[0038] The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to Figures 3A to 3J. In the method for manufacturing the wiring board of the embodiment, a conductive layer having gas vents can be formed by forming openings in the plating resist formed on the metal film layer covering the surface of the insulating layer, such that a gas vent resist with a substantially rectangular planar shape is formed. Any additional steps may be added in addition to the steps described above, and any part of the steps described above may be omitted. [Explanation of Symbols]

[0039] 1 Wiring board 101 Insulating layer (core insulating layer) 102 Conductor layer (core conductor layer) 10. First Build-up Department 20. Second Build-up Department 13, 23 via conductors 100-layer structure (core substrate) 103 Through conductor 11, 21 Insulating layer 12, 22 Conductor layers DFR Plating Resist 12PL Beta Pattern DGH gas vent hole SR1, SR2 Solder Resist Layer

Claims

1. Insulating layer and, A conductive layer formed in contact with the upper surface of the insulating layer, A wiring board comprising, The conductor layer includes a gas vent hole that penetrates the conductor layer and exposes the upper surface of the insulating layer. The aforementioned gas vent hole has a roughly rectangular planar shape.

2. A wiring board according to claim 1, wherein the conductor layer includes a plurality of gas vents, and the plurality of gas vents are arranged in a grid pattern.

3. The wiring board according to claim 1, wherein the area of ​​the planar shape of the gas vent hole is 8000 μm². 2 Above, and 30,000 μm 2 The following applies:

4. The wiring board according to claim 1, wherein the substantially rectangular planar shape has a ratio of the longer side to the shorter side of 1.2 or more and 5.0 or less.

5. Forming a metal film layer on the upper surface of the insulating layer, Forming a plating resist on the aforementioned metal film layer, Forming an opening pattern in the aforementioned plating resist, Forming a plating film layer within the aforementioned opening pattern, By removing the aforementioned plating resist, the upper surface of the metal film layer is exposed. Removing the exposed metal film layer, A method for manufacturing a wiring board, including, Forming the aforementioned opening pattern involves forming a resist for gas venting holes with a substantially rectangular planar shape.

6. A method for manufacturing a wiring board according to claim 5, wherein the aperture pattern is formed by 8000 μm 2 Above, and 30,000 μm 2 This includes forming the gas venting hole resist having the following area.

7. A method for manufacturing a wiring board according to claim 5, wherein forming the opening pattern includes forming a gas venting hole resist having a ratio of the long side to the short side of 1.2 or more and 5.0 or less.

8. A method for manufacturing a wiring board according to claim 5, wherein forming the opening pattern includes forming a plurality of gas venting hole resists in a grid pattern.

9. A method for manufacturing a wiring substrate according to claim 5, wherein removing the plating resist includes using a chemical solution to peel the plating resist from the metal film layer.

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