Semiconductor device and method for manufacturing the same

Abstract

To improve the voltage resistance and reliability of semiconductor devices. [Solution] Multiple semiconductor elements are formed in the cell region CA. The termination region TA surrounds the cell region CA in a plan view. A p-type resurf region RS1 is formed in the semiconductor substrate SUB of the termination region TA so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The resurf region RS1 is formed in a ring shape in the termination region TA so as to surround the cell region CA in a plan view. The resurf region RS1 contains boron as an impurity.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device using a semiconductor substrate made of silicon carbide and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices equipped with semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used. Silicon carbide (SiC) has an electric field strength at breakdown approximately one order of magnitude higher than that of silicon (Si). Therefore, in a power MOSFET using an SiC substrate, the drift region for maintaining the breakdown voltage can be made approximately 1 / 10 as thin, and the impurity concentration can be increased to approximately 100 times, thereby theoretically reducing the element resistance by three orders of magnitude or more. In addition, since the bandgap of SiC is approximately three times larger than the bandgap of Si, a power MOSFET using an SiC substrate can operate at high temperatures.

[0003] Such a semiconductor device for high breakdown voltage products includes a cell region in which a plurality of semiconductor elements are formed and a termination region surrounding the cell region in a plan view. A source voltage, such as 0V, is applied to the innermost circumference of the termination region, and a drain voltage, such as 1000V or more, is applied to the outermost circumference of the termination region. Therefore, it is necessary to maintain the breakdown voltage of the semiconductor device in the termination region.

[0004] For example, in Patent Document 1, a RESURF region, which is a p-type impurity region, is formed in the semiconductor substrate of the termination region. The RESURF region is formed in an annular shape so as to surround the cell region in a plan view.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] In order to improve the breakdown voltage of a semiconductor device in the terminal region, it is preferable to make the shape of the corner portion of the resurface region in a cross-sectional view gentler and to mitigate the electric field in the corner portion.

[0007] However, when forming p-type impurity regions in SiC substrates, ion implantation using aluminum (Al) is usually performed. In SiC substrates, aluminum is known to be activated by heat treatment but does not diffuse. Therefore, the cross-sectional shape of the corners of the resurfaced region becomes almost the same as the cross-sectional shape during ion implantation, resulting in sharp corners. Consequently, electric fields tend to concentrate in the corners, making it difficult to improve the breakdown voltage and reliability of semiconductor devices, for example, in high-temperature reverse bias tests.

[0008] To create a gentler shape in the corners of the p-type resurf region, one possible approach is to prepare multiple masks with different aperture widths and perform multiple ion implantations with varying implantation energies. For example, ion implantation with a high implantation energy is performed with masks with small aperture widths, and the implantation energy is decreased as the aperture width increases. This makes the corners of the resurf region appear stepped, thus creating a gentler shape.

[0009] However, forming a resurf region using this method requires a large number of masks and ion implantation cycles. For example, seven or more masks and seven or more ion implantations may be necessary. In other words, the gentler the shape of the corners and the greater the voltage resistance of the semiconductor device, the higher the manufacturing cost becomes.

[0010] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0011] A semiconductor device in one embodiment comprises a cell region on which a plurality of semiconductor elements are formed, a terminal region surrounding the cell region in a plan view, a semiconductor substrate of a first conductivity type made of silicon carbide having an upper surface and a lower surface, and a first impurity region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate in the terminal region so as to reach a predetermined depth from the upper surface of the semiconductor substrate. The first impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view, the first impurity region contains boron as an impurity, and the virtual curve indicating the junction surface between the first impurity region and the semiconductor substrate has a predetermined radius of curvature.

[0012] A semiconductor device manufacturing method in one embodiment is a method for manufacturing a semiconductor device comprising a cell region on which a plurality of semiconductor elements are formed and a terminal region that surrounds the cell region in a plan view. The method for manufacturing a semiconductor device comprises (a) the step of preparing an n-type semiconductor substrate having an upper surface and a lower surface and made of silicon carbide, and (b) the step of forming a p-type first impurity region in the semiconductor substrate of the terminal region so as to reach a predetermined depth from the upper surface of the semiconductor substrate. The first impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view, and the first impurity region has a central part, an inner end closer to the cell region than the central part, and an outer end further from the cell region than the central part. The (b) step comprises: (b1) ion implantation of boron into the central portion, inner end portion and outer end portion of the semiconductor substrate using a first mask film; (b2) ion implantation of carbon into the inner end portion and outer end portion of the semiconductor substrate using a second mask film; and (b3) diffusing the boron contained in the central portion, inner end portion and outer end portion by performing a heat treatment after the (b1) and (b2) steps. [Effects of the Invention]

[0013] According to one embodiment, the voltage withstand capability and reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] Figure 2 is a plan view showing the semiconductor device in Embodiment 1. [Figure 3] Figure 3 is a cross-sectional view showing the cell region and the termination region in Embodiment 1. [Figure 4] Figure 4 is an enlarged cross-sectional view around the MOSFET in the cell region and the RESURF region in the termination region in Embodiment 1. [Figure 5] Figure 5 is a cross-sectional view showing the details of the RESURF region in the termination region in Embodiment 1. [Figure 6] Figure 6 is a cross-sectional view showing the details of the RESURF region in the termination region in Embodiment 1. [Figure 7] Figure 7 is the impurity profile of the RESURF region in Embodiment 1. [Figure 8] Figure 8 is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 9] Figure 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 8. [Figure 10] Figure 10 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 9. [Figure 11] Figure 11 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 10. [Figure 12] Figure 12 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 11. [Figure 13] Figure 13 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 12. [Figure 14] Figure 14 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 13. [Figure 15] Figure 15 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 14. [Figure 16] Figure 16 is a cross-sectional view showing the manufacturing process of the semiconductor device following Figure 15. [Figure 17]Figure 17 is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 16. [Figure 18] Figure 18 is a cross-sectional view showing a modified semiconductor device. [Modes for carrying out the invention]

[0015] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0016] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is the vertical direction, depth direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) The semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 to 4.

[0018] As shown in Figure 1, the semiconductor device 100 comprises a cell region CA on which multiple semiconductor elements are formed, and a termination region TA that surrounds the cell region CA in a plan view. In Embodiment 1, an n-type MOSFET 1Q, as shown in Figure 4, is given as an example of a semiconductor element.

[0019] As shown in Figure 1, the semiconductor device 100 includes multiple wirings. A source electrode SE is formed as wiring in the cell region CA. Multiple MOSFETs 1Q are formed below the source electrode SE. In the termination region TA, a gate wiring GW, a source wiring SW, and a guard ring wiring GR are formed as wirings, respectively.

[0020] The gate wiring GW surrounds the source electrode SE in a plan view. The source wiring SW is drawn out from the source electrode SE and is formed in a ring shape so as to surround the gate wiring GW in a plan view. The guard ring wiring GR is formed in a ring shape so as to surround the source wiring SW in a plan view.

[0021] Furthermore, as shown in Figure 3, the source electrode SE, gate wiring GW, source wiring SW, and guard ring wiring GR are covered with a protective film PIQ. An opening is provided in a portion of the protective film PIQ. The protective film PIQ is a resin film, such as a polyimide film.

[0022] As shown by the dashed lines in Figure 1, the source pad SP and gate pad GP are the exposed parts of the source electrode SE and gate wiring GW at the openings in the protective film PIQ. By connecting external connection members to the source pad SP and gate pad GP, the semiconductor device 100 can be electrically connected to other semiconductor devices, lead frames, or wiring boards. The external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plates.

[0023] Figure 2 shows p-type resurf regions RS1 and RS2 formed in the semiconductor substrate SUB of the terminal region TA. The hatched region in Figure 2 is resurf region RS1. The location of resurf region RS1 shown in Figure 2 coincides with the location of resurf region RS1 shown by the dashed line in Figure 1.

[0024] Resurf regions RS1 and RS2 are each formed in a ring shape within the terminal region TA, surrounding the cell region CA in a plan view. Furthermore, parts of resurf region RS1 and parts of resurf region RS2 are adjacent to each other and overlap in a plan view.

[0025] The cross-sectional structure of MOSFET1Q formed in the cell region CA and the cross-sectional structure of the termination region TA are described below with reference to Figures 3 and 4. Note that the termination region TA in Figure 4 is a part of Figure 3, showing an enlarged view of the structure around the resurf region RS1. Also, the protective film PIQ shown in Figure 3 is omitted in Figure 4.

[0026] <Structure of MOSFET1Q in the cell region CA> As shown in Figure 4, the semiconductor substrate SUB has an upper surface TS and a lower surface BS and is made of n-type silicon carbide (SiC). The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The drain region ND is formed in the semiconductor substrate SUB with a predetermined thickness, extending from the lower surface BS of the semiconductor substrate SUB toward the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the drain region ND is higher than the impurity concentration in the drift region NV.

[0027] The semiconductor substrate SUB may be, for example, a laminate of an n-type SiC substrate and an n-type SiC layer formed on the n-type SiC substrate by epitaxial growth. In this case, the n-type silicon substrate constitutes the drain region ND, and the n-type SiC layer constitutes the drift region NV.

[0028] A drain electrode DE is formed beneath the lower surface BS of the semiconductor substrate SUB. The drain electrode DE consists of a single layer of metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed across the entire lower surface BS of the semiconductor substrate SUB. The drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0029] A gate electrode GE is formed on the upper surface TS of the semiconductor substrate SUB in the cell region CA via a gate insulating film GI. The gate insulating film GI is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0030] Within the semiconductor substrate SUB of the cell region CA, a p-type body region PB is formed, extending to a predetermined depth from the upper surface TS of the semiconductor substrate SUB. Within the body region PB, an n-type source region NS and a p-type high-concentration diffusion region PR are formed. The impurity concentration in the source region NS is higher than that in the drift region NV. The impurity concentration in the high-concentration diffusion region PR is higher than that in the body region PB.

[0031] Note that the body region PB and the high-concentration diffusion region PR contain aluminum (Al) as an impurity. The source region NS contains nitrogen (N) as an impurity.

[0032] The gate electrode GE is formed to span a portion of each of two adjacent body regions PB and a drift region NV located between the two adjacent body regions PB. Of the body regions PB, the portion located below the gate electrode GE via the gate insulating film GI, and situated between the source region NS and the drift region NV in a plan view, constitutes the channel region of MOSFET1Q.

[0033] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB, covering the MOSFET 1Q. The interlayer insulating film IL is, for example, a silicon oxide film. Pores CH are formed in the interlayer insulating film IL, reaching the source region NS and the high-concentration diffusion region PR.

[0034] A source electrode SE is formed on the interlayer insulating film IL of the cell region CA. The source electrode SE is also formed inside the pore CH and is electrically connected to the source region NS, the high-concentration diffusion region PR, and the body region PB, supplying a source potential to these impurity regions.

[0035] As shown in Figure 3, a lead-out portion GEa is formed in the terminal region TA. The lead-out portion GEa is integrated with a plurality of gate electrodes GE formed in the cell region CA. In the terminal region TA, a hole CH reaching the lead-out portion GEa is formed in the interlayer insulating film IL. Gate wiring GW is formed on the interlayer insulating film IL and inside the hole CH. The gate wiring GW is electrically connected to the lead-out portion GEa and supplies gate potential to the gate electrodes GE. In addition, a hole CH reaching the semiconductor substrate SUB is also formed in the interlayer insulating film IL in the terminal region TA.

[0036] <Structure of the terminal region TA> As shown in Figure 3, a field insulating film IF0 is formed on the upper surface TS of the semiconductor substrate SUB in the termination region TA. The field insulating film IF0 is, for example, a silicon oxide film and has a greater thickness than the gate insulating film GI. An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the field insulating film IF0. Gate wiring GW, source wiring SW, and guard ring wiring GR are formed on the interlayer insulating film IL of the termination region TA.

[0037] The source electrode SE, gate wiring GW, source wiring SW, and guard ring wiring GR each consist of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film. The conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0038] As shown in Figures 3 and 4, in the semiconductor substrate SUB of the termination region TA, a p-type resurf region RS1, a p-type resurf region RS2, and an n-type impurity region NGR are formed to a predetermined depth from the top surface TS of the semiconductor substrate SUB. The impurity concentration in the impurity region NGR is higher than that of the drift region NV. The depth of the resurf region RS1 is, for example, 0.5 μm or more and 1.5 μm or less. The depth of the resurf region RS2 is shallower than the depth of the resurf region RS1.

[0039] Furthermore, a p-type resurfacing region RS3 is formed within resurfacing region RS2. The impurity concentration in resurfacing region RS2 is higher than that in resurfacing region RS1. The impurity concentration in resurfacing region RS3 is higher than that in resurfacing region RS2.

[0040] Resurf region RS2 and RS3 contain aluminum (Al) as an impurity. Resurf region RS1 contains boron (B) and carbon (C) as impurities.

[0041] As shown in Figure 3, a pore CH is formed in the interlayer insulating film IL of the termination region TA, reaching the resurface region RS3, and the source wiring SW is also formed inside this pore CH. The source wiring SW is electrically connected to resurface regions RS3, RS2, and RS1, supplying source potential to these impurity regions.

[0042] Furthermore, a pore CH is formed in the interlayer insulating film IL of the terminal region TA, reaching the impurity region NGR, and the guard ring wiring GR is also formed inside this pore CH. The guard ring wiring GR and the impurity region NGR are electrically connected to the drain electrode DE via the drift region NV and the drain region ND. Therefore, the drain electrode DE supplies the drain potential to the guard ring wiring GR and the impurity region NGR.

[0043] Although not shown in the diagram, a silicide film may be formed on the upper surface of each of the impurity region NGR, resurf region RS3, source region NS, high-concentration diffusion region PR, and extraction region GEa located at the bottom of the pore CH. Such a silicide film may be, for example, nickel silicide or titanium silicide.

[0044] <Detailed configuration of the resurfacing region RS1> As shown in Figure 5, the resurf region RS1 has a central part RS1a, an inner part RS1b that is closer to the cell region CA than the central part RS1a, and an outer part RS1c that is further from the cell region CA than the central part RS1a. The central part RS1a contains boron as an impurity. The inner part RS1b and the outer part RS1c contain boron and carbon as impurities.

[0045] As shown in the manufacturing method described later, boron is ion-implanted into the central part RS1a, the inner end RS1b, and the outer end RS1c, and then carbon is ion-implanted into the inner end RS1b and the outer end RS1c. After that, the boron is diffused by heat treatment. At this time, the diffusion of boron in the inner end RS1b and the outer end RS1c is suppressed by the carbon. As a result, the corner portion of the resurf region RS1 takes on a gently curving shape.

[0046] The virtual curve 10 shown in Figure 6 represents the junction between the resurf region RS1 and the semiconductor substrate SUB (drift region NV). The virtual curve 20 shown in Figure 6 represents the depletion layer extending from the resurf region RS1. At the corner portion of the resurf region RS1, the virtual curve 10 has a predetermined radius of curvature R1. The radius of curvature R1 is, for example, 0.5 μm or more and 1.5 μm or less.

[0047] By increasing the radius of curvature R1, it becomes easier to mitigate electric field concentration at the corners of the resurf region RS1, thereby improving the breakdown voltage of the semiconductor device 100. When the radius of curvature R1 is within the above numerical range, for example, even when 0V is applied to the source wiring SW and 700V to 4000V is applied to the drain electrode DE, the breakdown voltage of the semiconductor device 100 can be ensured.

[0048] However, the radius of curvature R1 is preferably greater than or equal to the depth D1 of the resurf region RS1, and should be less than or equal to the width W1 of the depletion layer extending from the resurf region RS1. In other words, it is preferable that the relationship "D1 ≤ R1 ≤ W1" is satisfied.

[0049] Figure 7 shows the impurity concentration profile in the resurfacing region RS1. As shown in Figure 7, since boron is diffused by heat treatment, the impurity concentration profile in the resurfacing region RS1 is a smooth curve.

[0050] <Manufacturing method for semiconductor devices> The following describes each manufacturing step included in the manufacturing method of the semiconductor device 100 in Embodiment 1, using Figures 8 to 17.

[0051] As shown in Figure 8, an n-type semiconductor substrate SUB made of silicon carbide is prepared, having an upper surface TS and a lower surface BS. As described above, the semiconductor substrate SUB may be a laminate of an n-type SiC substrate and an n-type SiC layer formed on the n-type SiC substrate by epitaxial growth. In that case, the n-type silicon substrate constitutes the drain region ND, and the n-type SiC layer constitutes the drift region NV.

[0052] As shown in Figures 9 and 10, a p-type resurf region RS1 is formed in the semiconductor substrate SUB of the terminal region TA, having a central portion RS1a, an inner end portion RS1b, and an outer end portion RS1c.

[0053] First, as shown in Figure 9, a mask film MK1 is formed on the upper surface TS of the semiconductor substrate SUB, covering the cell region CA and leaving a portion of the termination region TA open. The mask film MK1 is, for example, a photoresist film. Next, boron (B) is ion-implanted into the central part RS1a, the inner end RS1b, and the outer end RS1c of the semiconductor substrate SUB using the mask film MK1. Then, the mask film MK1 is removed, for example, by ashing.

[0054] This ion implantation method involves, for example, setting the implantation energy to between 50 keV and 150 keV, and the dose to 1.0 × 10⁻⁶. 13 cm -2 The above and 3.0 × 10 13 cm -2The procedure will be carried out under the following conditions. Furthermore, the implantation energy and dose may be changed within the range of the above conditions, and the ion implantation may be performed in two separate steps.

[0055] Furthermore, as shown in Figure 9, the mask film MK1 includes an opening pattern OP1 that opens at the central part RS1a, multiple opening patterns OP2 that partially open at the inner end RS1b, and multiple opening patterns OP3 that partially open at the outer end RS1c. The opening width of each of the multiple opening patterns OP2 and OP3 is narrower than the opening width of opening pattern OP1. In addition, the planar shape of each of the multiple opening patterns OP2 and OP3 is either dot-shaped or slit-shaped.

[0056] Narrowing the opening width tends to make it more difficult for ions to reach deeper positions during ion implantation, resulting in a reduction in the amount of ions implanted. Consequently, boron implanted from multiple opening patterns OP2 and OP3 reaches a shallower position than boron implanted from opening pattern OP1. As a result, the depths of the inner end RS1b and outer end RS1c are shallower than the depth of the central part RS1a. Therefore, when boron is diffused by the heat treatment described later, it becomes easier to form a virtual curve 10 with a radius of curvature R1 as shown in Figure 6.

[0057] The opening widths of each of the multiple opening patterns OP2 and OP3 narrow as they move away from the central part RS1a. Consequently, at the inner end RS1b and outer end RS1c, the boron reaches a shallower position and the boron concentration decreases as they move away from the central part RS1a. This makes it easier to form the virtual curve 10 shown in Figure 6.

[0058] Next, as shown in Figure 10, a mask film MK2 is formed on the upper surface TS of the semiconductor substrate SUB, covering the cell region CA and opening the inner end RS1b and outer end RS1c in the termination region TA. The mask film MK2 is, for example, a photoresist film. Next, carbon (C) is ion-implanted into the areas of the semiconductor substrate SUB that will become the inner end RS1b and outer end RS1c using the mask film MK2. Then, the mask film MK2 is removed, for example, by ashing.

[0059] This ion implantation method involves, for example, setting the implantation energy to between 50 keV and 150 keV, and the dose to 1.0 × 10⁻⁶. 13 cm -2 The above and 3.0 × 10 13 cm -2 The procedure will be carried out under the following conditions. Furthermore, the implantation energy and dose may be changed within the range of the above conditions, and the ion implantation may be performed in two separate steps.

[0060] Furthermore, as shown in Figure 10, the mask film MK2 includes a plurality of opening patterns OP4 that partially open at the inner end RS1b and a plurality of opening patterns OP5 that partially open at the outer end RS1c. The opening width of each of the plurality of opening patterns OP4 and the plurality of opening patterns OP5 is narrower than the opening width of the opening pattern OP1 of the mask film MK1. In addition, the planar shape of each of the plurality of opening patterns OP4 and the plurality of opening patterns OP5 is either dot-shaped or slit-shaped.

[0061] The opening widths of each of the multiple opening patterns OP4 and OP5 widen as they move away from the central part RS1a. Consequently, at the inner end RS1b and outer end RS1c, the carbon reaches deeper and the carbon concentration increases as you move away from the central part RS1a. In other words, the diffusion of boron is more easily suppressed as you move away from the central part RS1a, making it easier to form the virtual curve 10 shown in Figure 6.

[0062] As shown in Figure 11, a mask film MK3 is formed on the upper surface TS of the semiconductor substrate SUB, opening a portion of the cell region CA and a portion of the termination region TA. The mask film MK3 is, for example, a photoresist film. Next, by ion implanting aluminum (Al) using the mask film MK3, a p-type body region PB is formed in the semiconductor substrate SUB of the cell region CA, reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB, and a p-type resurf region RS2 is formed in the semiconductor substrate SUB of the termination region TA. The resurf region RS2 is formed so as to be in contact with a portion of the resurf region RS1. Next, the mask film MK3 is removed, for example, by an ashing process.

[0063] As shown in Figure 12, a mask film MK4 is formed on the upper surface TS of the semiconductor substrate SUB, covering the termination region TA and opening a portion of the body region PB in the cell region CA. The mask film MK4 is, for example, a photoresist film. Next, an n-type source region NS is formed in the body region PB by ion implantation of nitrogen (N) using the mask film MK4. Then, the mask film MK4 is removed, for example, by an ashing process.

[0064] As shown in Figure 13, a mask film MK5 is formed on the upper surface TS of the semiconductor substrate SUB, opening a portion of the body region PB in the cell region CA and a portion of the resurf region RS2 in the termination region TA. The mask film MK5 is, for example, a photoresist film. Next, by ion implanting aluminum (Al) using the mask film MK5, a p-type high-concentration diffusion region PR is formed in the body region PB and a p-type resurf region RS3 is formed in the resurf region RS2. Then, the mask film MK5 is removed, for example, by an ashing process.

[0065] Subsequently, although not shown in the diagram, a mask film is formed on the upper surface TS of the semiconductor substrate SUB, covering the cell region CA and opening a portion of the drift region NV in the termination region TA. This mask film is, for example, a photoresist film. Next, nitrogen (N) is ion-implanted using the mask film to form an n-type impurity region NGR in the drift region NV (see Figure 3). Then, the mask film is removed, for example, by an ashing process.

[0066] As shown in Figure 14, heat treatment diffuses the boron contained in the central part RS1a, the inner end RS1b, and the outer end RS1c. This heat treatment also activates the impurities (Al) contained in the body region PB, the high-concentration diffusion region PR, the resurf region RS2, and the resurf region RS3, the impurities (N) contained in the source region NS, and the impurities (B) contained in the central part RS1a, the inner end RS1b, and the outer end RS1c. This heat treatment is carried out in an inert gas atmosphere under conditions such as 1600 degrees Celsius or higher and 1800 degrees Celsius or higher.

[0067] Carbon is ion-implanted in the inner end RS1b and outer end RS1c, but not in the central part RS1a. Therefore, boron diffuses easily in the central part RS1a, but the diffusion of boron is suppressed by carbon in the inner end RS1b and outer end RS1c. In other words, in the above heat treatment, the diffusion of boron in the inner end RS1b and outer end RS1c is smaller than the diffusion of boron in the central part RS1a. As a result, the corner portion of the resurf region RS1 takes on a gently curving shape.

[0068] On the other hand, aluminum and nitrogen do not diffuse due to the heat treatment described above. Therefore, the cross-sectional shapes of the body region PB, the high-concentration diffusion region PR, the resurfacing region RS2, the resurfacing region RS3, and the source region NS are almost the same as the cross-sectional shapes during ion implantation.

[0069] In Embodiment 1, a resurf region RS1 can be formed by performing ion implantation of boron and carbon using two masks (mask film MK1, mask film MK2), thus suppressing an increase in manufacturing costs compared to methods such as those described in the present invention.

[0070] Note that the manufacturing processes shown in Figures 9 and 10 may be performed before the heat treatment shown in Figure 14, or after the manufacturing processes shown in Figures 11, 12, and 13.

[0071] Furthermore, while photoresist films were exemplified as mask films MK1, MK2, MK3, MK4, and MK5, mask films MK1, MK2, MK3, MK4, and MK5 may also be patterned insulating films. For example, silicon oxide films, silicon nitride films, or silicon oxynitride films can be used as such insulating films.

[0072] As shown in Figure 15, a field insulating film IF0 is formed on the upper surface TS of the semiconductor substrate SUB by a film deposition process, for example, using CVD (Chemical Vapor Deposition). Next, the field insulating film IF0 located in the cell region CA is removed by patterning, leaving the field insulating film IF0 in a part of the termination region TA.

[0073] Next, a gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB, for example, by thermal oxidation treatment. Then, a conductive film is formed on the gate insulating film GI by a film deposition process, for example, using CVD. The conductive film is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0074] Next, the conductive film located in the termination region TA is removed by patterning, and multiple gate electrodes GE are formed on the gate insulating film GI located in the cell region CA. The gate electrodes GE are formed so as to span a portion of each of two adjacent body regions PB and a drift region NV located between the two adjacent body regions PB. In this way, multiple MOSFETs 1Q are formed in the cell region CA.

[0075] As shown in Figure 16, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by a film deposition process, for example, using a CVD method, so as to cover the field insulating film IF0 in the terminal region TA and cover multiple MOSFETs 1Q in the cell region CA.

[0076] Next, multiple pores CH are formed in the interlayer insulating film IL using photolithography and etching techniques. In the cell region CA, multiple pores CH are formed that reach multiple source regions NS and multiple high-concentration diffusion regions PR. In the termination region TA, multiple pores CH are formed that reach the extraction region GEa, the resurf region RS3, or the semiconductor substrate SUB (see Figure 3).

[0077] Subsequently, although not shown in the diagram, a silicide film may be formed on the upper surfaces of the semiconductor substrate SUB located at the bottom of the pore CH, the resurf region RS3, the source region NS, the high-concentration diffusion region PR, and the extraction region GEa, respectively, by salicide technology.

[0078] As shown in Figure 17, multiple wirings, including source electrodes SE and source wiring SW, are formed on the interlayer insulating film IL and inside multiple pores CH.

[0079] First, a barrier metal film is formed on the interlayer insulating film IL and inside the multiple pores CH by a film deposition process, for example, using a sputtering method. The barrier metal film is, for example, a titanium-tungsten film. Next, a conductive film is formed on the barrier metal film by a film deposition process, for example, using a sputtering method, so as to fill the inside of the multiple pores CH. The conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0080] Next, multiple wirings are formed by patterning the barrier metal film and the conductive film. Specifically, a source electrode SE is formed as wiring in the cell region CA, and a gate wiring GW, a source wiring SW, and a guard ring wiring GR are formed as wiring in the termination region TA, respectively (see Figure 3).

[0081] Subsequently, the semiconductor device 100 shown in Figures 3 and 4 is manufactured through the following manufacturing process. First, a protective film PIQ is formed to cover the source electrode SE, gate wiring GW, source wiring SW, and guard ring wiring GR by a film deposition process, for example, using a coating method. Next, an opening is formed in a part of the protective film PIQ so as to expose a part of each of the source electrode SE and gate wiring GW. Next, a drain electrode DE is formed under the lower surface BS of the semiconductor substrate SUB by a film deposition process, for example, using a sputtering method.

[0082] (modified version) The semiconductor device in a modified version of Embodiment 1 will be described below with reference to Figure 18. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0083] In Embodiment 1, a planar MOSFET1Q was exemplified as the semiconductor element formed in the cell region CA, but the MOSFET1Q may also have a trench gate structure.

[0084] As shown in Figure 18, trenches TR are formed in the semiconductor substrate SUB so as to extend from the upper surface TS of the semiconductor substrate SUB to a position deeper than the body region PB. The manufacturing process for forming the trenches TR is carried out before the formation of the gate insulating film GI.

[0085] The gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR. The gate electrode GE is formed on the gate insulating film GI so as to fill the inside of the trench TR. The portion of the body region PB that is adjacent to the gate electrode GE via the gate insulating film GI and located between the source NS and the drift region NV becomes the channel region of MOSFET1Q.

[0086] Furthermore, in order to avoid a strong electric field being applied to the bottom of the trench TR closest to the terminal region TA among the multiple trenches TR formed in the cell region CA, it is preferable that the depth of the resurf region RS1 be greater than the depth of the trench TR. The depth of the resurf region RS1 is preferably, for example, 0.1 μm or more and 0.2 μm or less than the depth of the trench TR.

[0087] Although the present invention has been specifically described above based on embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from its essence.

[0088] For example, the semiconductor element formed in the cell region CA is not limited to a MOSFET, but may also be an IGBT or a Schottky barrier diode. [Explanation of Symbols]

[0089] 100 Semiconductor Equipment 10. Virtual curve (joint surface) 20. Virtual curve (depletion layer) 1Q MOSFET BS semiconductor substrate bottom surface CA cell area CH hole DE drain electrode GE Terminal GI gate insulating film GP Gate Pad GR Guard Ring Wiring GW gate wiring IF0 Field Insulation Film IL interlayer film MK1, MK2, MK3, MK4, MK5 Mask Film ND Drain region (Impurity region) NGR impurity region NS source area (impurity area) NV drift region (impurity region) OP1, OP2, OP3, OP4, OP5 Opening Patterns PB body region (impurity region) PIQ protective film PR High concentration diffusion region (impurity region) RS1, RS2, RS3 RESURF region (impurity region) RS1a central part RS1b inner end RS1c outer end SE source electrode SP Source Pad SUB Semiconductor Substrate SW Source Wiring TA termination area TR Trench Top surface of TS semiconductor substrate

Claims

1. A cell region in which multiple semiconductor elements are formed, In a plan view, the terminal region surrounding the cell region, A first-conductivity semiconductor substrate having an upper surface and a lower surface and made of silicon carbide, A first impurity region of a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate in the termination region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, Equipped with, The first impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view. The first impurity region contains boron as an impurity. The virtual curve representing the junction surface between the first impurity region and the semiconductor substrate has a predetermined radius of curvature, in the semiconductor device.

2. In the semiconductor device described in claim 1, A semiconductor device having a radius of curvature of 0.5 μm or more and 1.5 μm or less.

3. In the semiconductor device described in claim 1, A semiconductor device wherein the radius of curvature is greater than or equal to the depth of the first impurity region.

4. In the semiconductor device described in claim 3, A semiconductor device wherein the radius of curvature is less than or equal to the width of the depletion layer extending from the first impurity region.

5. In the semiconductor device described in claim 1, The first impurity region has a central portion, an inner end portion that is closer to the cell region than the central portion, and an outer end portion that is further from the cell region than the central portion. The aforementioned central portion contains boron as an impurity. A semiconductor device in which the inner end and the outer end contain boron and carbon as impurities.

6. In the semiconductor device described in claim 1, The termination region further comprises a second impurity region of the second conductivity type formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate, The depth of the second impurity region is shallower than the depth of the first impurity region. The aforementioned second impurity region contains aluminum as an impurity. The impurity concentration in the second impurity region is higher than the impurity concentration in the first impurity region. The second impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view. The semiconductor device wherein the first impurity region surrounds the second impurity region in a plan view and is in contact with a part of the second impurity region.

7. In the semiconductor device described in claim 6, An interlayer insulating film formed on the upper surface of the semiconductor substrate, A source wiring formed on the interlayer insulating film of the terminal region and electrically connected to the second impurity region, A drain electrode formed below the lower surface of the semiconductor substrate, Furthermore, A semiconductor device in which the first impurity region is electrically connected to the source wiring via the second impurity region.

8. In the semiconductor device described in claim 1, A semiconductor device in which the plurality of semiconductor elements are MOSFETs, IGBTs, or Schottky barrier diodes.

9. A method for manufacturing a semiconductor device comprising a cell region on which multiple semiconductor elements are formed, and a terminal region surrounding the cell region in a plan view, (a) A step of preparing an n-type semiconductor substrate having an upper surface and a lower surface and made of silicon carbide, (b) A step of forming a p-type first impurity region in the semiconductor substrate of the termination region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, Equipped with, The first impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view. The first impurity region has a central portion, an inner end portion that is closer to the cell region than the central portion, and an outer end portion that is further from the cell region than the central portion. The above step (b) is, (b1) A step of ion implanting boron into the central portion, the inner end portion and the outer end portion of the semiconductor substrate using a first mask film, (b2) A step of ion implanting carbon into the inner and outer edges of the semiconductor substrate using a second mask film. (b3) After the steps of (b1) and (b2), a step of diffusing the boron contained in the central portion, the inner end portion and the outer end portion by performing a heat treatment, A method for manufacturing a semiconductor device having the following characteristics.

10. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein in step (b3), the diffusion of boron at the inner end and the outer end is less than the diffusion of boron at the central part.

11. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the virtual curve representing the junction surface between the first impurity region and the semiconductor substrate has a predetermined radius of curvature.

12. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the radius of curvature is 0.5 μm or more and 1.5 μm or less.

13. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the radius of curvature is greater than or equal to the depth of the first impurity region.

14. In the method for manufacturing a semiconductor device according to claim 13, A method for manufacturing a semiconductor device, wherein the radius of curvature is less than or equal to the width of the depletion layer extending from the first impurity region.

15. In the method for manufacturing a semiconductor device according to claim 9, The first mask film includes a first opening pattern that opens at the central portion, a plurality of second opening patterns that partially open at the inner end portion, and a plurality of third opening patterns that partially open at the outer end portion. A method for manufacturing a semiconductor device, wherein the aperture width of each of the plurality of second aperture patterns and the plurality of third aperture patterns is narrower than the aperture width of the first aperture pattern.

16. In the method for manufacturing a semiconductor device according to claim 15, A method for manufacturing a semiconductor device, wherein the aperture width of each of the plurality of second aperture patterns and the plurality of third aperture patterns narrows as it moves away from the central portion.

17. In the method for manufacturing a semiconductor device according to claim 15, The second mask film includes a plurality of fourth opening patterns that partially open the portion that will become the inner end, and a plurality of fifth opening patterns that partially open the portion that will become the outer end. A method for manufacturing a semiconductor device, wherein the aperture width of each of the plurality of fourth aperture patterns and the plurality of fifth aperture patterns is narrower than the aperture width of the first aperture pattern.

18. In the method for manufacturing a semiconductor device according to claim 17, A method for manufacturing a semiconductor device, wherein the aperture width of each of the plurality of fourth aperture patterns and the plurality of fifth aperture patterns widens as it moves away from the central portion.

19. In the method for manufacturing a semiconductor device according to claim 9, (c) A step of forming a p-type second impurity region in the semiconductor substrate of the termination region so as to reach a predetermined depth from the upper surface of the semiconductor substrate. Furthermore, The depth of the second impurity region is shallower than the depth of the first impurity region. The aforementioned second impurity region contains aluminum as an impurity. The impurity concentration in the second impurity region is higher than the impurity concentration in the first impurity region. The second impurity region is formed in an annular shape in the terminal region so as to surround the cell region in a plan view. A method for manufacturing a semiconductor device, wherein the first impurity region surrounds the second impurity region in a plan view and is in contact with a part of the second impurity region.

20. In the method for manufacturing a semiconductor device according to claim 19, (d) A step of forming an interlayer insulating film on the upper surface of the semiconductor substrate, (e) A step of forming a source wiring on the interlayer insulating film of the terminal region that is electrically connected to the second impurity region, (f) A step of forming a drain electrode below the lower surface of the semiconductor substrate, Furthermore, A method for manufacturing a semiconductor device, wherein the first impurity region is electrically connected to the source wiring via the second impurity region.

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