Reservoir calculator and equipment status detection system

Abstract

This approach efficiently implements an echo-state network-based reservoir computer on hardware, eliminating the trade-off between the total number of neurons that can be implemented and processing speed. [Solution] The reservoir layer of the reservoir computer is divided into a plurality of sub-reservoirs, each sub-reservoir having a plurality of reservoir neurons, each reservoir neuron having a selector, a multiplier, an integrator, and an activation function calculator arranged in that order, and the selector sequentially selects either the reservoir input signal or the output signal from the reservoir neuron multiplied by a non-zero weight in the multiplier, according to a selection signal.

Description

[Technical Field]

[0001] The present invention relates to a reservoir calculator and an equipment status detection system. [Background technology]

[0002] In order to maintain and manage social infrastructure and large industrial machinery, there is a need for practical equipment condition detection systems that can detect abnormal conditions in equipment by analyzing time-series signals output by sensors (e.g., vibration sensors) placed on or near the equipment.

[0003] To establish an algorithm for analyzing time-series signals, it is necessary to pre-train the time-series signals. Known methods for this training include deep learning techniques such as RNN (Recurrent Neural Network) and LTSM (Long Short-Term Memory), as well as methods using reservoir computing.

[0004] Methods using deep learning are generally difficult to learn and require a lot of time and effort. Methods using reservoir computation can learn time-series signals more easily than deep learning. In particular, reservoir computation based on Echo State Networks has a wealth of research and has become the standard model for reservoir computation.

[0005] Incidentally, regarding the technology for implementing computers on hardware, for example, Patent Document 1 describes a three-state neural network circuit 200 comprising: a non-zero convolution circuit 21 that receives input values ​​Xi and weights Wi in the intermediate layer and performs a convolution operation; a summation circuit 22 that takes the sum of each convolved operation value and a bias W0; and an activation function circuit 23 that transforms the summed signal Y with an activation function f(u). The non-zero convolution circuit 21 is described as skipping weights with zero (0) weights Wi and performing a convolution operation based on the non-zero weights and the input values ​​Xi corresponding to those non-zero weights. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2019-200553 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] In a reservoir computer based on an echo state network, each neuron is required to be randomly and sparsely connected. Therefore, efficiently implementing such a reservoir computer on hardware is difficult. As a result, in an echo state network-based reservoir computer, there is a trade-off between the total number of neurons and processing speed. Consequently, if such a reservoir computer is used in an equipment status detection system, detecting minor anomalies becomes difficult.

[0008] Although Patent Document 1 describes omitting operations where weights are zero in a convolutional deep neural network (hereinafter referred to as zero skipping), it is not easy to apply the zero skipping described in Patent Document 1 to the echo state network because its configuration, operation, and purpose differ from those of the reservoir computer using the echo state network of the present invention.

[0009] The present invention has been made in view of the above points, and aims to enable the efficient implementation of an echo-state network-based reservoir computer on hardware. [Means for solving the problem]

[0010] This application includes several means to solve at least some of the above problems, and some examples are as follows.

[0011] To solve the above problems, a reservoir computer according to one aspect of the present invention is a reservoir computer based on an echo state network, comprising a reservoir layer into which a time-series signal is input as a reservoir input signal, and a readout layer, wherein the reservoir layer is divided into a plurality of sub-reservoirs, each sub-reservoir has a plurality of reservoir neurons, each reservoir neuron has a selector that sequentially selects either the reservoir input signal or the output signals from the plurality of reservoir neurons, a multiplier that multiplies the selection result by a weight, and the multiplier's multiplication An integrator that accumulates the results and an activation function calculator that calculates the output value of an activation function that takes the accumulated result of the integrator as input are arranged in order. The selector sequentially selects either the reservoir input signal or the output signal from the reservoir neuron that is multiplied by a non-zero weight in the multiplier, according to the selection signal. The readout layer performs a sum-of-products operation using readout weights on the output signals from the multiple reservoir neurons each of the multiple sub-reservoirs, and outputs the calculation result as an output signal from the reservoir calculator. [Effects of the Invention]

[0012] According to the present invention, a reservoir computer based on an echo-state network can be efficiently implemented on hardware, eliminating the trade-off between the total number of neurons that can be implemented and the processing speed.

[0013] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 shows an example of the configuration of a reservoir computer according to the first embodiment of the present invention. [Figure 2] Figure 2 shows a first example configuration of the sub-reservoir. [Figure 3] Figures 3(A) and 3(B) illustrate the difference between performing zero skipping and not performing zero skipping in the sub-reservoir. Figure 3(A) shows the time chart when zero skipping is performed, and Figure 3(B) shows the time chart when zero skipping is not performed. [Figure 4] Figure 4 shows a second example configuration of the sub-reservoir. [Figure 5] Figure 5 shows an example of the values ​​of the selection signals and weights stored in the partitioned memory for weight storage. [Figure 6] Figure 6 shows an example configuration of a reservoir computer according to a second embodiment of the present invention. [Figure 7] Figure 7 shows an example of a processing cycle in a subreservoir. [Figure 8] Figure 8 shows an example of the characteristics of a bandwidth-variable filter. [Figure 9] Figure 9 shows an example configuration of a reservoir computer according to the third embodiment of the present invention. [Figure 10] Figures 10(A) and 10(B) are diagrams illustrating the zero-weighting rate search process. Figure 10(A) is a flowchart illustrating an example of the zero-weighting rate search process, and Figure 10(B) is a timing chart illustrating an example of the zero-weighting rate search process. [Figure 11] Figure 11 shows an example configuration of a reservoir computer according to the fourth embodiment of the present invention. [Figure 12] Figure 12 is a diagram illustrating the operation of a selector using an FPGA. [Figure 13]Figures 13(A) and (B) show examples of selector configurations using FPGAs. Figure 13(A) shows an example configuration using a 6-input LUT (Look Up Table), and Figure 13(B) shows an example configuration using BRAM (Block RAM). [Modes for carrying out the invention]

[0015] Multiple embodiments of the present invention will be described below with reference to the drawings. Each embodiment is an example for illustrating the present invention, and has been omitted and simplified as appropriate for clarity of explanation. The present invention can also be implemented in various other forms. Unless otherwise specified, each component may be singular or plural. The position, size, shape, and range of each component shown in the drawings may not represent the actual position, size, shape, and range in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, and range disclosed in the drawings. Various types of information may be described using expressions such as "table," "list," and "queue," but various types of information may be represented by other data structures. For example, various types of information such as "XX table," "XX list," and "XX queue" may be referred to as "XX information." When describing identification information, expressions such as "identification information," "identifier," "name," "ID," and "number" are used, and these are interchangeable. In all drawings used to describe embodiments, the same reference numeral is generally used for the same component, and repeated explanations are omitted. Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily required unless specifically stated or considered to be clearly essential in principle. Also, when referring to "consisting of A," "being composed of A," "having A," or "including A," other elements are not excluded unless specifically stated to refer only to that element. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., it includes those that are substantially similar or analogous to that shape, etc., unless specifically stated or considered to be clearly not so in principle.

[0016] <Example of the configuration of the reservoir computer 101 according to the first embodiment of the present invention> Figure 1 shows an example configuration of an echo-state network-based reservoir computer 101 according to a first embodiment of the present invention.

[0017] The reservoir computer 101 is used in a condition detection system that detects minor abnormal conditions before any abnormalities occur in the appearance of the equipment 100. The equipment 100 may include, for example, social infrastructure such as water and sewage pipes, bridges, and roads, as well as large industrial machinery equipped with engines, motors, etc.

[0018] The reservoir computer 101 receives time-series sensor signals from equipment 100 or sensors 110 located nearby as reservoir input signals S IN It is accepted as such. In this embodiment, the time-series sensor signal is assumed to be a digital signal. The case where the time-series sensor signal is an analog signal will be described later. In addition, the reservoir computer 101 outputs the abnormal condition detection result as an output signal S OUT Output as: Output signal S OUT This could be, for example, a binary signal indicating the presence or absence of an abnormality, or a signal that represents the abnormal condition in more detail. Sensor 110 includes, for example, a vibration sensor, a sound sensor, a temperature sensor, and the like.

[0019] The reservoir computer 101 comprises a reservoir layer 11, a read layer 13, and a processor 15. The reservoir layer 11, read layer 13, and processor 15 are implemented on hardware such as an FPGA (Field Programmable Gate Array).

[0020] The reservoir layer 11 receives the time-series sensor signal from the sensor 110 as the reservoir input signal S. IN This is the input. The reservoir layer 11 is divided into multiple (3 in the case of Figure 1) sub-reservoirs 121, 122, and 123. Hereafter, when it is not necessary to distinguish between sub-reservoirs 121, 122, and 123 individually, they will be referred to as sub-reservoirs 12. Note that the number of sub-reservoirs 12 into which the reservoir layer 11 is divided is not limited to 3; it may be 2 or 4 or more.

[0021] The sub-reservoir 12 is a zero-skip sub-reservoir configured to perform zero-skip that omits operations when the weight W is zero. The sub-reservoir 12 includes a plurality of reservoir neurons (described in detail later), and outputs the output signal NR from the plurality of reservoir neurons 20 (Fig. 2) to the subsequent readout layer 13.

[0022] The readout layer 13 performs a sum-of-products operation on the output signals NR from the plurality of reservoir neurons 20 input from each sub-reservoir 12 using readout weights, and outputs the result as the output signal S of the reservoir computer 101. OUT Note that at least one of the reservoir input signal S IN , and the output signal S OUT may be a plurality of signals.

[0023] The processor 15 is composed of, for example, a CPU or the like, and controls the entire reservoir computer 101.

[0024] <First Configuration Example of Sub-Reservoir 12> Next, Fig. 2 shows a first configuration example of the sub-reservoir 12. The first configuration example of the sub-reservoir 12 is composed of a plurality of (in the case of Fig. 2, 63) reservoir neurons 201 to 20 63 Hereinafter, the output signals of the reservoir neurons 201, 202, ··· 20 63 are referred to as output signals NR1, NR2, ··· NR63. Also, when there is no need to individually distinguish the reservoir neurons 201 to 20 63 and their output signals NR1 to NR63, they are referred to as reservoir neurons 20 and output signals NR.

[0025] The reservoir neuron 20 has a selector 21 and a reservoir neuron section 22. The selector 21 receives the reservoir input signal S IN , and the output signals NR of all the reservoir neurons 20 that constitute the same sub-reservoir 12 as inputs. <\

[0026] The selector 21 sequentially selects one of the input signals according to the selection signal from the processor 15 and outputs it to the reservoir neuron unit 22. Specifically, the selector 21 first selects the reservoir input signal S IN Selects and outputs to the reservoir neuron section 22. Next, the selector 21 selects the weight W from all the output signals NR of the reservoir neurons 20, which is multiplied by the multiplier 221 in the subsequent reservoir neuron section 22. j,k Only those values ​​where (j=1,2,···63,k=1,2,···63) are not zero are sequentially selected and output to the reservoir neuron section 22. The non-zero weights W are supplied to each reservoir neuron 20 that constitute the sub-reservoir 12. j,k The number is standardized.

[0027] The reservoir neuron section 22 comprises, in order, a multiplier 221, an integrator 222, and an activation function arithmetic unit (af) 223. The multiplier 221 receives the reservoir input signal S from the selector 21. IN In contrast, the weight W supplied from processor 15 j,0 The multiplier 221 multiplies the output signal NR from the reservoir neuron 20, which is sequentially input from the selector 21, by a non-zero weight W supplied from the processor 15. j,k The multiplication is performed, and the result is output to the integrator 222. The integrator 222 accumulates the multiplication results sequentially input from the multiplier 221 and outputs the accumulated result to the activation function calculator 223. The activation function calculator 223 calculates the output value of an activation function using the accumulated result input from the integrator 222 as input, and outputs it to the next stage as the output signal NR of the reservoir neuron 20.

[0028] For example, in the case of reservoir neuron 201 in Figure 2, the selector 21 first receives the reservoir input signal S according to the selection signal 1. IN Selecting this option outputs it to the reservoir neuron unit 22. Next, the selector 21 outputs the weights W of the sum-of-accumulate operation in the reservoir neuron unit 22. j,k W is not zero 1,2 ,W 1,24 ,W 1,59The output signals NR2, NR24, and NR59 from the reservoir neuron 20, which are used for multiplication, are sequentially selected and output to the reservoir neuron unit 22.

[0029] Then, in the reservoir neuron portion 22 of the reservoir neuron 201, the result of the sum-of-accumulate operation is W 1,0 ·S IN +W 1,2 NR2+W 1,24 NR24+W 1,59 The output value of the activation function with NR59 as input is calculated and output to the next stage as the output signal NR1 of the reservoir neuron 201. Note that the reservoir input signal S IN The sum-of-products operation on this can be performed at times or by methods other than those described above.

[0030] For example, in the case of reservoir neuron 202 in Figure 2, the selector 21 first receives the reservoir input signal S according to the selection signal 2. IN Selecting this option outputs it to the reservoir neuron unit 22. Next, the selector 21 outputs the weights W of the sum-of-accumulate operation in the reservoir neuron unit 22. j,k W is not zero 2,1 ,W 2,18 ,W 2,45 The output signals NR1, NR18, and NR45 from the reservoir neuron 20, which are used for multiplication, are sequentially selected and output to the reservoir neuron unit 22.

[0031] Then, in the reservoir neuron portion 22 of the reservoir neuron 202, the result of the sum-of-accumulate operation is W 2,0 ·S IN +W 2,1 NR1+W 2,18 NR18+W 2,45 The output value of the activation function with NR45 as input is calculated and output to the next stage as the output signal NR2 of the reservoir neuron 202. Note that the reservoir input signal S IN The sum-of-products operation on this can be performed at times or by methods other than those described above.

[0032] Note that reservoir neurons 203-20 63The same calculation is performed in this case as well. Therefore, the readout layer 13 receives 63 output signals NR1 to NR63 from each of the three sub-reservoirs 121 to 123.

[0033] Next, we will explain the difference between performing zero skipping and not performing zero skipping in the sub-reservoir 12. Figure 3(A) shows the time chart when zero skipping is performed in the sub-reservoir 12. Figure 3(B) shows the time chart when zero skipping is not performed in the sub-reservoir 12.

[0034] For example, as shown in the sub-reservoir 12 in Figure 2, each reservoir neuron 20 (NR1~NR63) receives the reservoir input signal S IN When a sum-of-accumulate operation is performed on a total of four signals, including the three output signals NR, one cycle in which each reservoir neuron 20 outputs the output signal NR once will consist of four cycles, as shown in Figure 3(A).

[0035] On the other hand, if zero skipping is not performed in sub-reservoir 12, as shown in Figure 3(B), each reservoir neuron 20 (NR1~NR63) receives the reservoir input signal S IN Then, a sum-of-accumulate operation is performed on the 63 output signals NR, for a total of 64 input signals. Therefore, the 11 periods in which each reservoir neuron 20 outputs the output signal NR once consist of 64 cycles.

[0036] Therefore, when zero skipping is performed as in this embodiment (Figure 3(A)), the processing speed required for the sum-of-accumulate operation can be increased by 16 times compared to when zero skipping is not performed (Figure 3(B)).

[0037] Furthermore, in this embodiment, the reservoir layer 11 is divided into multiple sub-reservoirs 12, and the sum-of-products operation is performed only on the reservoir neurons 20 in the same sub-reservoirs 12. Therefore, the target of the sum-of-products operation is limited to the output signals NR of the 63 reservoir neurons 20 that constitute the same sub-reservoirs 12. In addition, the actual sum-of-products operation is performed on the corresponding weights W of the output signals NR of the 63 reservoir neurons 20. j,k This is limited to those values ​​that are not zero. Thus, in this embodiment, the number of input signals used for the multiply-accumulate operation is doubly limited, which significantly reduces the number of multiply-accumulate operations. As a result, the number of cycles required to complete the multiply-accumulate operation can be greatly reduced. Therefore, the reservoir computer 101 can be efficiently implemented on hardware, and the trade-off between the total number of implementable neurons and processing speed can be eliminated.

[0038] Furthermore, if necessary, limited multiply-accumulate operations may be added between different sub-reservoirs 12 (for example, between sub-reservoir 121 and sub-reservoir 122). If these operations are limited, they can be implemented without significantly impairing processing speed.

[0039] As explained above, the reservoir computer 101 offers a faster processing speed (i.e., in this embodiment, the input reservoir input signal S) compared to a conventional reservoir computer that does not perform zero skipping. IN The frequency of processing the reservoir input signal S can be significantly improved. IN The time-series sensor signal can be processed up to the high-frequency component, and as a result, the state of the equipment 100 on which the sensor 110 is installed can be detected with high sensitivity.

[0040] <Second configuration example of Sub-reservoir 12> Next, Figure 4 shows a second configuration example of the sub-reservoir 12. The second configuration example of the sub-reservoir 12 is obtained by adding a weight storage partition memory 41 to the first configuration example (Figure 2). Of the components of this second configuration example, those other than the weight storage partition memory 41 are common to the components of the first configuration example and are given the same reference numerals, so their explanation is omitted.

[0041] The weight storage partition memory 41 stores the selection number as the selection signal for the selector 21 of the reservoir neuron 20, and the weight W for the multiplier 221. j,k The following are pre-stored: the selection number and weight W stored in the weight storage partition memory 41. j,k For example, this is read by the processor 15 and supplied to the selector 21 and multiplier 221 of the reservoir neuron 20.

[0042] Figure 5 shows the selection number and weight W stored in the weight storage partition memory 41. j,k This shows an example. The weight storage partition memory 41 is located at reservoir neurons 201-20 63 It is divided into 63 regions accordingly, and each region contains a non-zero weight W that performs the sum-of-accumulate operation in the reservoir neuron 20. j,k The selection number for selector 21 and the following are stored in order.

[0043] For example, in the region corresponding to the reservoir neuron 201 (NR1) of the weight storage partition memory 41, the reservoir input signal S is first received by the selector 21. IN Selection number 0 and weight W for selecting 1,0 The following is stored: Secondly, selection number 2 for selecting the output signal NR2 with selector 21, and a non-zero weight W. 1,2 The following is stored: thirdly, selection number 24 for selecting the output signal NR24 with selector 21, and a non-zero weight W. 1,24 The following is stored: the fourth is the selection number 59 for selecting the output signal NR59 with selector 21, and a non-zero weight W. 1,59 It is stored there.

[0044] For example, in the region corresponding to the reservoir neuron 202 (NR2) of the weight storage partition memory 41, the first reservoir input signal S is received by the selector 21. IN Selection number 0 and weight W for selecting 2,0 The following is stored: Secondly, selection number 1 for selecting the output signal NR1 with selector 21, and a non-zero weight W. 2,1 The following is stored: thirdly, selection number 18 for selecting the output signal NR18 with selector 21, and a non-zero weight W. 2,18 The following is stored: the fourth is the selection number 45 for selecting the output signal NR45 with selector 21, and a non-zero weight W. 2,45 It is stored there.

[0045] Similarly, reservoir neurons 203(NR3)~20 of the weight storage partition memory 41 63 The area corresponding to (NR63) contains, in order from 1st to 4th, the selection number for selector 21 and the weight W. j,k and are stored there.

[0046] According to the second configuration example of the sub-reservoir 12, by providing a partitioned memory 41 for storing weights, the input signals and weights W required for one cycle of calculation shown in Figure 3(A) are available. j,k The data can be read simultaneously and seamlessly, and the multiplication in each cycle can be executed seamlessly. Therefore, the duration of one cycle can be shortened, resulting in even faster performance compared to the first configuration example.

[0047] <Example of the configuration of the reservoir computer 102 according to the second embodiment of the present invention> Next, Figure 6 shows an example configuration of an echo-state network-based reservoir computer 102 according to a second embodiment of the present invention.

[0048] The reservoir computer 102 is modified from the reservoir computer 101 (Figure 1) by adding a variable bandwidth filter 51, a zero weighting rate control unit 52, and a weight generation unit 53. Note that, among the components of the reservoir computer 102, those other than the variable bandwidth filter 51, the zero weighting rate control unit 52, and the weight generation unit 53 are common to the components of the reservoir computer 101 and are given the same reference numerals; therefore, their explanation is omitted. The reservoir layer 11 in the reservoir computer 102 is assumed to employ a second configuration example (Figure 4) having a weight storage partitioned memory 41.

[0049] The variable bandwidth filter 51 is provided before the reservoir layer 11. The variable bandwidth filter 51 limits the bandwidth of the time-series sensor signal according to the high-frequency cutoff frequency specified by the zero-weighting ratio control unit 52. The time-series sensor signal after bandwidth limiting is the reservoir input signal S IN This is input to reservoir layer 11.

[0050] The zero weighting control unit 52 is implemented, for example, by the processor 15. The zero weighting control unit 52 sets the high-frequency cutoff frequency in the band-variable filter 51 and outputs it to the band-variable filter 51. The zero weighting control unit 52 also sets the non-zero weights W used in the sum-of-accumulate operation in each sub-reservoir 12 of the reservoir layer 11. j,k A variable zero weighting rate p (0 ≤ p ≤ 1) is determined to control the number of weights and output to the weight generation unit 53.

[0051] The weight generation unit 53 is implemented, for example, by the processor 15. The weight generation unit 53 receives the reservoir input signal S IN The weight W multiplied by the weight 1,0 ~W 63,0 For example, these are generated randomly. The weight generation unit 53 also generates a weight W of zero for each reservoir neuron 20 in the reservoir layer 11. j,k Weight W is used to multiply the output signals NR1 to NR63 of each reservoir neuron 20 by a predetermined zero weighting rate p, such that the proportion of zeros equals a predetermined zero weighting rate p. j,k It generates the weight W. Specifically, the weight generation unit 53 generates, for example, the weight W. j,kAfter randomly generating each of its weights W j,k A random number uniformly distributed between 0 and 1 is assigned to it. Then, the weight generation unit 53 generates weights W such that the assigned random number is less than or equal to p. j,k Reset to zero, and assign a weight W greater than p for the assigned random number. j,k For this, we will use a randomly generated value as is.

[0052] Weights W are generated in this way for each reservoir neuron 20. j,k The weight W is not zero. j,k The number of elements is approximately 63*(1-p), which may result in some variation in the number. Therefore, the weight generation unit 53 generates a non-zero weight W. j,k In reservoir neurons 20, which have a large number of units, some weights W are not zero. j,k By resetting to zero, the weight W becomes non-zero. j,k The goal is to reduce the number of non-zero weights W. j,k In reservoir neurons 20, where the number of neurons is small, some weights W are zero. j,k By resetting to a non-zero value, or by leaving it as zero but treating it as a non-zero weight and performing a sum-of-products operation, the non-zero weight W j,k Increase the number of them.

[0053] The generated weight W j,k These are stored in the weight storage partitioned memory 41 of each sub-reservoir 12 of the reservoir layer 11. Thus, non-zero weights W are supplied to each reservoir neuron 20 constituting each sub-reservoir 12 of the reservoir layer 11. j,k With the correct number of elements, the read weights to be used in the read layer 13 are learned and applied.

[0054] Next, Figure 7 shows an example of a processing cycle in the sub-reservoir 12. As shown in the figure, the reservoir input signal S in the sub-reservoir 12 IN The period T that can process the data is the product of the time of one cycle and the number of cycles required (4 cycles in the example in Figure 7). The number of cycles required is a non-zero weight W.j,k Since it is determined by the number of, the larger the zero weight ratio p, the smaller the required number of cycles. In this embodiment, since the zero weight ratio p is variable, the required number of cycles is also variable. Therefore, the reserve input signal S IN The processing period T of is also variable.

[0055] By the way, the processing period T of the reserve input signal S IN is also the period for sampling the reserve input signal S IN . According to the sampling theorem, it is known that for the sampling period T, the signal component of the frequency f exceeding 1 / T / 2 (Nyquist frequency) is converted to a frequency lower than the frequency f (1 / T - f). Therefore, if the reserve input signal S IN contains a signal component of the frequency f exceeding the Nyquist frequency, the signal component of the frequency f will be treated as a signal component of a lower frequency (1 / T - f), and the signal component of the frequency (1 / T - f) originally present in the reserve input signal S IN cannot be distinguished. Therefore, the original signal component is damaged, making it difficult to detect the high-sensitivity state of the equipment 100.

[0056] Therefore, the zero weight ratio control unit 52 controls the passband in the band variable filter 51 based on the setting of the zero weight ratio p for the weight generation unit 53. Specifically, the cut-off frequency on the high-frequency side is controlled.

[0057] FIG. 8 shows the characteristics of the band variable filter 51, where the horizontal axis is the frequency of the reserve input signal S IN and the vertical axis is the gain. As shown in the figure, the zero weight ratio control unit 52 controls the cut-off frequency on the high-frequency side in the band variable filter 51 to the same frequency as the Nyquist frequency.

[0058] As mentioned above, the Nyquist frequency is determined according to the setting of the zero weighting ratio p, so the cutoff frequency of the variable bandwidth filter 51 also changes according to the setting of the zero weighting ratio p. The cutoff frequency does not have to be the same frequency as the Nyquist frequency; it may be a higher or lower frequency than the Nyquist frequency, and should be determined according to the characteristics of the time-series sensor signal output by the sensor 110. When the zero weighting ratio p is high, the sampling period T becomes shorter, so the zero weighting ratio control unit 52 sets the cutoff frequency of the variable bandwidth filter 51 to a higher value. Conversely, when the zero weighting ratio p is low, the zero weighting ratio control unit 52 sets the cutoff frequency to a lower value.

[0059] Furthermore, the higher the zero weighting rate p, the higher the reservoir input signal (time-series sensor signal) S. IN The reservoir computer 102 can process the higher frequency signal components contained within. However, if the zero weighting rate p is too high, the time required for calculation processing increases, and the ability to detect the state decreases. Therefore, in the reservoir computer 102, the zero weighting rate control unit 52 is configured to set an appropriate zero weighting rate p according to the task.

[0060] According to the reservoir computer 102, the same effects as the reservoir computer 101 (Figure 1) can be obtained, and an appropriate zero weighting rate p can be set, making it possible to handle a variety of tasks.

[0061] <Example of the configuration of the reservoir computer 103 according to the third embodiment of the present invention> Next, Figure 9 shows an example configuration of an echo-state network-based reservoir computer 103 according to a third embodiment of the present invention.

[0062] The reservoir computer 103 automatically searches for an appropriate zero weighting rate p during the learning period prior to the inference period (the period during which the reservoir calculation is performed to detect the state of the equipment 100).

[0063] The reservoir computer 103 is obtained by adding a learning unit 61 to the reservoir computer 102 (Fig. 6). Among the components of the reservoir computer 103, those other than the learning unit 61 are common to the components of the reservoir computer 102 and are given the same reference numerals, so their description will be omitted.

[0064] The learning unit 61 is realized by, for example, the processor 15. The learning unit 61 receives the output signal S output from the readout layer 13 OUT , the annotation data (correct answer data) corresponding to the learning reservoir input signal S IN , and the output signal NR (signal path not shown) from each sub-reservoir 12 of the reservoir layer 11. The learning unit 61 updates the readout weights used for the sum-product operation in the readout layer 13 based on the output signal S OUT from the readout layer 13, the annotation data, and the output signal NR from each sub-reservoir 12 of the reservoir layer 11. The learning unit 61 repeatedly updates the readout weights until the difference between the output signal S OUT and the annotation data becomes minimum. After the update of the readout weights is completed with the minimum difference, the learning unit 61 calculates the final minimum difference between the output signal S OUT and the annotation data, and outputs it as the learning error to the zero weight ratio control unit 52.

[0065] Fig. 10 is a diagram for explaining the zero weight ratio search process by the reservoir computer 103. Fig. 10(A) is a flowchart for explaining an example of the zero weight ratio search process, and Fig. 10(B) is a timing chart for explaining an example of the zero weight ratio search process.

[0066] The zero weight ratio search process is executed during the learning period before the inference period. First, the zero weight ratio control unit 52 sets the zero weight ratio p to the initial value of 0 and outputs it to the weight generation unit 53 (step S1). Next, the zero weight ratio control unit 52 sets the cut-off frequency on the high-frequency side of the band variable filter 51 based on the zero weight ratio p and outputs it to the band variable filter 51 in the same manner as the reservoir computer 102 (step S2).

[0067] Next, the weight generation unit 53 generates weights W, similar to the reservoir computer 102. j,k The data is generated and stored in the weight storage partition memory 41. Next, the bandwidth-limited reservoir input signal S for learning is sent to the reservoir layer 11 from the bandwidth-variable filter 51. IN The input is received, and each reservoir neuron 20 constituting each sub-reservoir 12 of the reservoir layer 11 performs calculations for one cycle and outputs the output signal NR, which is the result of the calculation, to the readout layer 13 and the learning unit 61. Then, the readout layer 13 multiplies the output signals NR from each reservoir neuron 20 by the readout weight and integrates them, and outputs the integrated result as the output signal S OUT This is output to the learning unit 61 (step S4).

[0068] Next, the learning unit 61 receives the output signal S from the readout layer 13. OUT The learning reservoir input signal S is input to the reservoir layer 11. IN Based on the corresponding annotation data and the output signal NR from the reservoir layer 11, the read weights used in the sum-of-accumulate operation of the read layer 13 are updated. This update is performed by the output signal S OUT This process is repeated until the difference with the annotation data is minimized. Then, after the learning unit 61 has finished updating the read weights, it outputs the output signal S OUT Then, the smallest final difference between the annotation data and the learning error is output to the zero weighting rate control unit 52 as the learning error (step S5). In this case, for example, let's assume that the learning error was 50%, as shown in Figure 10(B).

[0069] Next, the zero weighting rate control unit 52 determines whether the learning error input from the learning unit 61 has decreased compared to the previously input learning error (step S6). If there is no previous input of a learning error, or if it is determined that the learning error has decreased (YES in step S6), the zero weighting rate control unit 52 proceeds to step S7. Conversely, if it is determined that the learning error has not decreased (NO in step S6), the zero weighting rate control unit 52 then adopts the previous zero weighting rate p (step S8).

[0070] In this case, since there is no previous input for the learning error, the process proceeds to step S7. Next, the zero weighting rate control unit 52 sets the zero weighting rate p to a high value (step S7). In this case, for example, let's assume that the zero weighting rate p is set from 0 to 1 / 2, as shown in Figure 10(B). After this, the process returns to step S2, and steps S2 to S6 are repeated for the second time.

[0071] In the second step S2, for example as shown in Figure 10(B), the zero weighting rate control unit 52 sets the high-frequency cutoff frequency of the variable bandwidth filter 51 to twice the cutoff frequency set in the first step, based on the zero weighting rate p increased to 1 / 2, and outputs it to the variable bandwidth filter 51. After this, the second steps S3 to S5 are executed in the same way as the first step. In the second step S5, for example as shown in Figure 10(B), it is assumed that the learning error was 30%. In this case, in the second step S6, it is determined that the learning error has decreased from the previous step, and the process proceeds to step S7, where the zero weighting rate p is set even higher. In this case, for example as shown in Figure 10(B), it is assumed that the zero weighting rate p has been set from 1 / 2 to 3 / 4. After this, the process returns to step S2, and the third steps S2 to S6 are repeated.

[0072] In the third step S2, for example as shown in Figure 10(B), the zero weighting rate control unit 52 sets the high-frequency cutoff frequency of the band-variable filter 51 to four times the cutoff frequency set in the first step, based on the increased zero weighting rate p to 3 / 4, and outputs it to the band-variable filter 51. After this, the third steps S3 to S5 are executed in the same way as the first step. In the third step S5, for example as shown in Figure 10(B), it is assumed that the learning error was 10%. In this case, in the third step S6, it is determined that the learning error has decreased from the previous step, and the process proceeds to step S7, where the zero weighting rate p is set even higher. In this case, for example as shown in Figure 10(B), it is assumed that the zero weighting rate p has been set from 3 / 4 to 7 / 8. After this, the process returns to step S2, and the fourth steps S2 to S6 are repeated.

[0073] In the fourth step S2, for example as shown in Figure 10(B), the zero weighting rate control unit 52 sets the high-frequency cutoff frequency of the band-variable filter 51 to eight times the cutoff frequency set in the first step, based on the zero weighting rate p increased to 7 / 8, and outputs it to the band-variable filter 51. After this, the fourth steps S3 to S5 are executed in the same way as the first step. In the fourth step S5, for example as shown in Figure 10(B), it is assumed that the learning error was 20%. In this case, in the fourth step S6, it is determined that the learning error has not decreased from the previous step, and the process proceeds to step S8, where the previous zero weighting rate p (=3 / 4) is adopted. Accordingly, the cutoff frequency and weight W are changed. j,k Furthermore, the read weights are also set to values ​​corresponding to the previous zero weighting rate p (=3 / 4). With this, the zero weighting rate search process is completed, and from this point onward, the reservoir computer 103 can transition to the inference period, enabling high-precision detection of the equipment 100's state.

[0074] <Example of the configuration of the reservoir computer 104 according to the fourth embodiment of the present invention> Next, Figure 11 shows an example configuration of an echo-state network-based reservoir computer 104 according to a fourth embodiment of the present invention.

[0075] The reservoir calculator 104 is designed to handle cases where the time-series sensor signal from the sensor 110 is an analog signal.

[0076] The reservoir computer 104 is modified from the reservoir computer 102 (Figure 6) by replacing the band-variable filter 51 with a band-variable analog filter 71, and adding a variable gain amplifier 72 and an analog-to-digital converter (A / D) 73 between the band-variable analog filter 71 and the reservoir layer 11. Note that, of the components of the reservoir computer 104, all components except the band-variable analog filter 71, variable gain amplifier 72, and A / D 73 are common to the components of the reservoir computer 102 and are given the same reference numerals; therefore, their explanation is omitted.

[0077] The variable-band analog filter 71 performs band limiting on the time-series sensor signal, which is an analog signal from the sensor 110, in accordance with the high-frequency-side cut-off frequency input from the zero-weight ratio control unit 52, and outputs it to the variable gain amplifier 72. The variable gain amplifier 72 amplifies the time-series sensor signal after band limiting with an appropriate gain and outputs it to the A / D 73. The A / D 73 converts the amplified time-series sensor signal into a digital signal and outputs it to the reservoir layer 11 as the reservoir input signal S IN for output.

[0078] According to the reservoir computer 104, the same effects as those of the reservoir computer 102 can be obtained. Furthermore, unnecessary components included in the time-series sensor signal from the sensor 110 can be attenuated by the variable-band analog filter 71, and necessary components can be amplified by the variable gain amplifier 72. As a result, it becomes less susceptible to the influence of conversion errors (i.e., quantization errors, thermal noise, distortion, etc.) in the A / D 73 and calculation errors in the reservoir computer 104, enabling highly sensitive state detection.

[0079] <Realization of the selector 21 using an FPGA> As described above, in the reservoir computers 101 to 104, each reservoir neuron 20 requires one selector 21. Therefore, if the selector 21 can be efficiently implemented, the usefulness of the present invention can be further enhanced. The following is an explanation of the method for realizing the selector 21 when implementing the reservoir computers 101 to 104 on an FPGA.

[0080] In an FPGA, it is known that the 6-input LUT, which is a component thereof, can be used as a memory (distributed memory). FIG. 12 shows a method for realizing a selector by using the 6-input LUT as a temporary memory.

[0081] The 6-input LUT used as temporary memory can store 64 single-bit values ​​(0 or 1), and by specifying a 6-bit address signal, any one of the 0th to 63rd single-bit values ​​can be read. Therefore, in this embodiment, the reservoir input signal S IN The output signal NR of each reservoir neuron 20 is stored in the 6-input LUT, one bit at a time, and then read out using the address signal of the 6-input LUT to realize the operation of the selector 21.

[0082] Therefore, the selection signals 1 to 63 for the selector 21 in the 63 reservoir neurons 20 constituting the sub-reservoir 12 are input to the 6-input LUT as 6-bit address signals, as shown in Figure 12. In addition, the reservoir input signal S corresponds to the value of the selection signal shown in Figure 5. IN (One bit of the signal) is stored at address 0, and the output signals NR1 to NR63 (one bit of each signal) from the 63 reservoir neurons 20 are stored at addresses 1 to 63.

[0083] However, as shown in Figure 12, a single 6-input LUT can only store one bit of each signal. Therefore, in order to actually implement the selector 21, it is necessary to operate N 6-input LUTs in parallel, the same number as the number of bits N of the signals input to the selector 21.

[0084] Figure 13(A) shows six input LUTs 811-81, each with the same number of bits N as the signal input to selector 21. N This shows an example configuration for implementing selector 21 by operating the components in parallel.

[0085] The 6-input LUT811 has a reservoir input signal S IN The most significant bit of the output signals NR1 to NR63 from each reservoir neuron 20 is stored. Similarly, the reservoir input signals S are stored in the 6th input LUT812 (not shown) and subsequent inputs. INAnd the output signals NR1~NR63 from each reservoir neuron 20 are stored one bit at a time from the most significant side. The last 6 inputs LUT81 N The reservoir input signal S IN The least significant bit of the output signals NR1 to NR63 from each reservoir neuron 20 is stored.

[0086] And these N 6-input LUT811~81 N By inputting a common 6-bit address signal, the 6-input LUT811~81 N It is possible to read out a total of N bits of signals simultaneously from these, enabling operation as a selector 21.

[0087] Next, Figure 13(B) shows an example configuration in which the BRAM82 provided by the FPGA is used to implement the selector 21.

[0088] Since BRAM82 is memory, it consists of N 6-input LUT811~81 as shown in Figure 13(A) N Similarly, the reservoir input signal S IN After writing the output signals NR1 to NR63 of each reservoir neuron 20 to the BRAM 82, the selector 21 can be activated by reading one of them using a selection signal. Since one BRAM 82 is used to implement one selector 21, the number of BRAM 82s required is equal to the total number of reservoir neurons 20 included in the reservoir layer 11.

[0089] Generally, the storage capacity of each BRAM is equal to the storage capacity required for the operation of selector 21 (i.e., in the case of Figure 2, the reservoir input signal S IN This is larger than the capacity to store the output signals NR1~NR63 from each reservoir neuron 20. Therefore, a selector using BRAM is an inefficient implementation compared to using a 6-input LUT as temporary memory. On the other hand, since it does not require the use of the FPGA's 6-input LUT resources, using BRAM is useful when the 6-input LUT resources are insufficient.

[0090] As described above, by implementing the selector 21 using the FPGA's 6-input LUT or BRAM, the numerous selectors 21 required can be efficiently implemented. Therefore, the reservoir computers 101 to 104 can be implemented even on low-cost FPGAs with limited hardware resources. This significantly improves the processing speed of the reservoir computers 101 to 104 (i.e., the frequency at which the reservoir input signals are processed). Consequently, the time-series sensor signals output by the sensor 110 can be processed up to high-frequency components, resulting in highly sensitive state detection.

[0091] The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace or add to the configurations of one embodiment with those of another embodiment.

[0092] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software by a processor interpreting and executing programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, recording devices such as hard disks and SSDs, or recording media such as IC cards, SD cards, and DVDs. Also, control lines and information lines are shown only if deemed necessary for explanation, and not all control lines and information lines are necessarily shown in the actual product. In practice, it can be assumed that almost all configurations are interconnected. [Explanation of Symbols]

[0093] 101-104...Reservoir computer, 11...Reservoir layer, 12...Sub-reservoir, 13...Readout layer, 15...Processor, 20...Reservoir neuron, 21...Selector, 22...Reservoir neuron section, 221...Multiplier, 222...Integrator, 223...Activation function calculator, 41...Storage partition memory, 51...Variable bandwidth filter, 52...Rate control section, 53...Weight generation section, 61...Learning section, 71...Variable bandwidth analog filter, 72...Variable gain amplifier, 73...Analog-to-digital converter

Claims

1. A reservoir computer based on an echo state network, A reservoir layer into which a time-series signal is input as a reservoir input signal, A readout layer, The reservoir layer is divided into multiple sub-reservoirs, The aforementioned sub-reservoir has multiple reservoir neurons, The reservoir neuron is, A selector that sequentially selects either the reservoir input signal or the output signals from a plurality of reservoir neurons, A multiplier that multiplies the selection result by a weight, An integrator that accumulates the multiplication results of the aforementioned multiplier, An activation function calculator that calculates the output value of an activation function using the integration result of the aforementioned integrator as input is arranged in order: The selector, according to the selection signal, sequentially selects either the reservoir input signal or the output signal from the reservoir neuron, which is multiplied by a non-zero weight in the multiplier. The readout layer performs a sum-of-accumulate operation using readout weights on the output signals from the multiple reservoir neurons, each of the multiple sub-reservoirs, and outputs the result of the operation as an output signal from the reservoir computer. Reservoir calculator.

2. A reservoir calculator according to claim 1, A memory in which the selection number as the selection signal and the non-zero weight are stored in association, Equipped with a processor, The processor reads the selection number from the memory and supplies it to the selector, and reads the non-zero weight and supplies it to the multiplier. Reservoir calculator.

3. A reservoir calculator according to claim 1, A variable bandwidth filter is provided prior to the reservoir layer to limit the bandwidth of the reservoir input signal, Equipped with a processor, The processor controls the zero weighting ratio, which represents the proportion of the non-zero weights supplied to the multiplier, and controls the passband of the variable bandwidth filter according to the zero weighting ratio. Reservoir calculator.

4. A reservoir calculator according to claim 3, During the learning period, the processor learns the read weights in the read layer and calculates the learning error based on the output signals from a plurality of reservoir neurons based on the reservoir input signal for learning, the output signals calculated by the read layer, and annotation data corresponding to the reservoir input signal for learning. Based on the learning error, the processor updates the zero weight ratio. Reservoir calculator.

5. A reservoir calculator according to claim 3, Between the band-variable filter and the reservoir layer, a variable gain amplifier and an analog-to-digital converter are provided. The variable gain amplifier amplifies the reservoir input signal that has been attenuated by the band-variable filter, The analog-to-digital converter converts the reservoir input signal, amplified by the variable gain amplifier, into a digital signal. Reservoir calculator.

6. A reservoir calculator according to claim 1, The selector sequentially selects from the reservoir input signal and the output signals from a plurality of reservoir neurons belonging to the same sub-reservoir, the output signals that are multiplied by the non-zero weight in the multiplier. Reservoir calculator.

7. A reservoir calculator according to claim 1, The aforementioned selector is implemented using a lookup table within an FPGA (Field Programmable Gate Array). The lookup table contains the reservoir input signal and the output signals from the multiple reservoir neurons, and the selection signal is supplied to the selector as the address signal for reading to the lookup table. Reservoir calculator.

8. A reservoir calculator according to claim 1, The selector is implemented by block RAM within the FPGA. The reservoir input signal and the output signals from the plurality of reservoir neurons are written to the block RAM, and the selection signal is supplied to the selector as the address signal for reading to the block RAM. Reservoir calculator.

9. A system for detecting the state of equipment, comprising equipment, sensors located in or near the equipment, and a reservoir computer based on an echo state network, The reservoir calculator is, A reservoir layer to which the time-series sensor signal input from the aforementioned sensor is input as a reservoir input signal, A readout layer, The reservoir layer is divided into multiple sub-reservoirs, The aforementioned sub-reservoir has multiple reservoir neurons, The reservoir neuron is, A selector that sequentially selects either the reservoir input signal or the output signals from a plurality of reservoir neurons, A multiplier that multiplies the selection result by a weight, An integrator that accumulates the multiplication results of the aforementioned multiplier, An activation function calculator that calculates the output value of an activation function using the integration result of the aforementioned integrator as input is arranged in order: The selector, according to the selection signal, sequentially selects either the reservoir input signal or the output signal from the reservoir neuron, which is multiplied by a non-zero weight in the multiplier. The readout layer performs a sum-of-accumulate operation using readout weights on the output signals from the multiple reservoir neurons, each of the multiple sub-reservoirs, and outputs the calculation result as an output signal from the reservoir computer representing the status of the equipment. Equipment status detection system.

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