Semiconductor device, circuit board assembly, and inspection method

Abstract

The present invention provides a semiconductor device, a circuit board assembly, and an inspection method that can accurately evaluate the molten state of solder used for connections. [Solution] The semiconductor device 1 comprises a base material 21 and a package substrate 2 having mounting patterns 22a and 22c formed on the front surface 211 of the base material 21, semiconductor elements 3 mounted on the mounting patterns 22a and 22c via connecting solder 6, and inspection solder 4 arranged on the front side of the package substrate 2. The inspection method inspects the melting state of the connecting solder 6 based on the reflection characteristics when light is irradiated onto the inspection solder 4.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, an integrated substrate device, and an inspection method.

Background Art

[0002] Patent Document 1 discloses a printed wiring board on which a plurality of electronic components are solder-mounted by reflow. In the printed wiring board described in Patent Document 1, an elongated check pattern terminal is provided at a corner thereof, and cream solder is disposed thereon. Further, a scale is provided on the printed wiring board along the longitudinal direction of the check pattern terminal. Hereinafter, the solder on the check pattern terminal is referred to as check solder, and the solder for connecting a plurality of electronic components is referred to as connection solder.

[0003] Patent Document 1 discloses an inspection method for inspecting whether a plurality of connection solders are properly melted by reflow. In this inspection method, first, a printed wiring board in a state where check solder, a plurality of connection solders, and a plurality of electronic components are arranged is reflowed. Then, after reflow, it is confirmed using the scale that the check solder has spread and wet over a predetermined length or more on the check pattern terminal, and it is evaluated that the melting state of the plurality of connection solders is appropriate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the printed circuit board described in Patent Document 1, due to the temperature distribution of the reflow heat source, connection solder may be produced under different temperature conditions during reflow than the test solder. In such cases, the molten state of connection solder may not be properly evaluated. From this perspective, there is room for improvement in the printed circuit board described in Patent Document 1.

[0006] Furthermore, the inspection method described in Patent Document 1 involves accurately placing a test solder in a desired area on a test pattern terminal, and then using a scale to confirm how much the test solder has wetted and spread during reflow. However, if the test solder before reflow is not accurately placed in the desired position on the test pattern terminal, the melting state of multiple connection solders cannot be accurately determined. From this perspective, there is room for improvement in the inspection method described in Patent Document 1.

[0007] The present invention has been made in view of the above circumstances, and aims to provide a semiconductor device, a substrate assembly device, and an inspection method that can accurately evaluate the molten state of connecting solder. [Means for solving the problem]

[0008] To achieve the above objective, the present invention provides a semiconductor device comprising: a base material and a package substrate having a mounting pattern formed on the front surface of the base material; a semiconductor element mounted on the mounting pattern via connecting solder; and an inspection solder arranged on the front surface of the package substrate.

[0009] To achieve the above objective, the present invention provides a substrate assembly apparatus comprising: a substrate divided into a plurality of unit regions by dicing; a substrate assembly having a mounting pattern formed on the front surface of each of the plurality of unit regions; a plurality of semiconductor elements mounted on each of the mounting patterns of the plurality of unit regions via connecting solder; and a plurality of inspection solders arranged on the front side of the substrate assembly and on each of the plurality of unit regions.

[0010] To achieve the above objective, the present invention provides an inspection method for a mounting apparatus comprising a mounting substrate, a semiconductor element mounted on the front side of the mounting substrate via connecting solder, and an inspection solder arranged on the front side of the mounting substrate, wherein the inspection method inspects the molten state of the connecting solder based on the reflection characteristics when light is irradiated onto the inspection solder. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a semiconductor device, a substrate assembly device, and an inspection method that can accurately evaluate the molten state of connecting solder. [Brief explanation of the drawing]

[0012] [Figure 1] This is a plan view of the semiconductor device in the first embodiment. [Figure 2] This is a cross-sectional view taken along the line II-II in Figure 1. [Figure 3] This is a cross-sectional view of a semiconductor device mounted on a printed circuit board in the first embodiment. [Figure 4] This is a plan view of the semiconductor device in the second embodiment. [Figure 5] This is a plan view of the semiconductor device in the third embodiment. [Figure 6] Figure 5 shows a cross-sectional view taken along the line VI-VI. [Figure 7] This is a plan view of the semiconductor device in the fourth embodiment. [Figure 8] This is a plan view of the semiconductor device in the fifth embodiment. [Figure 9] This is a plan view of the aggregate substrate device in the sixth embodiment. [Modes for carrying out the invention]

[0013] [First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. 1 to 3. The embodiments described below are presented as preferred specific examples for implementing the present invention, and although there are parts that specifically illustrate various technically preferable technical matters, the technical scope of the present invention is not limited to this specific aspect.

[0014] FIG. 1 is a plan view of the semiconductor device 1 in this embodiment. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG. 3 is a cross-sectional view of the semiconductor device 1 mounted on the printed wiring board 9.

[0015] This embodiment relates to a semiconductor device 1 and an inspection method for the semiconductor device 1.

[0016] [Semiconductor device 1] The semiconductor device 1 includes a package substrate 2, a semiconductor element 3, an inspection solder 4, and a protection element 5. The package substrate 2 has a base material 21 and mounting patterns 22a and 22c formed on the front surface 211 of the base material 21. The semiconductor element 3 is mounted on the mounting patterns 22a and 22c via connection solder 6. The inspection solder 4 is arranged on the front side of the package substrate 2. Here, the front side means one side in the thickness direction of the base material 21 and is the side where the semiconductor element 3 is located with respect to the base material 21, and the back side means the opposite side. The protection element 5 prevents an overcurrent from flowing through the semiconductor element 3.

[0017] The package substrate 2 is mounted on the printed wiring board 9 from the back side and is a fine substrate smaller than the printed wiring board 9. And since the semiconductor device 1 of this embodiment houses both the semiconductor element 3 and the inspection solder 4 on this fine package substrate 2, a temperature difference is less likely to occur between the connection solder 6 and the inspection solder 4 during reflow. Therefore, in the semiconductor device 1 of this embodiment, by checking the molten state of the inspection solder 4, it becomes possible to inspect the molten state of the connection solder 6 with high precision. Details of this inspection method will be described later.

[0018] The package substrate 2 further has back surface patterns 23a and 23c and an inspection pattern 24. In this embodiment, the package substrate 2 is a submount, and the semiconductor device 1 constitutes a so-called CoS (Chip on Submount). However, the package substrate 2 may be a cavity package.

[0019] The base material 21 is made of a material having electrical insulation and is formed in a rectangular flat plate shape. In this embodiment, each side of the base material 21 when viewed from the front side is 10 mm or less, preferably 5 mm or less. The base material 21 can be, for example, a ceramic substrate made of aluminum nitride (AlN), alumina (Al2O3), or the like. Also, for example, the base material 21 can be composed of high-temperature co-fired ceramic (HTCC) or low-temperature co-fired ceramic (LTCC).

[0020] The mounting patterns 22a and 22c, the back surface patterns 23a and 23c, and the inspection pattern 24 are made of a conductor. As an example, the mounting patterns 22a and 22c, the back surface patterns 23a and 23c, and the inspection pattern 24 are composed of a laminate of nickel / palladium / gold (Ni / Pd / Au).

[0021] The mounting patterns 22a and 22c are formed on the front surface 211 of the base material 21. The mounting patterns 22a and 22c have a mounting pattern 22a as an anode electrode and a mounting pattern 22c as a cathode electrode.

[0022] The mounting patterns 22a and 22c comprise a first pad 221 for mounting the semiconductor element 3, a second pad 222 for mounting the protection element 5, and a vertically elongated vertical pattern 223. The vertical direction is one direction along the substrate 21 in a plan view (for example, the up and down direction in Figure 1). The horizontal direction is a direction along the substrate 21 in a plan view that is perpendicular to the vertical direction (for example, the left and right direction in Figure 1). Electrically, the mounting patterns 22a and 22c are designed so that the semiconductor element 3 mounted on the first pad 221 and the protection element 5 mounted on the second pad 222 are connected in parallel between the pair of vertical patterns 223.

[0023] The pair of vertical patterns 223 of the mounting patterns 22a and 22c are arranged with a gap between them in the horizontal direction. The pair of vertical patterns 223 are the areas where a pair of probes are applied, for example, when performing an electrical test on the semiconductor device 1. When viewed from the front, the first pad 221 and the second pad 222 are pattern-designed so that the semiconductor element 3 and the protection element 5 are aligned vertically between the pair of vertical patterns 223.

[0024] The back side patterns 23a and 23c are formed on the back side 212 of the substrate 21. The back side patterns 23a and 23c include a back side pattern 23a that is electrically connected to the mounting pattern 22a via vias 25a, and a back side pattern 23c that is electrically connected to the mounting pattern 22c via vias 25c. The semiconductor device 1 is mounted on the printed circuit board 9 using the back side patterns 23a and 23c.

[0025] The inspection pattern 24 is formed on the front surface 211 of the substrate 21. The inspection pattern 24 is electrically separated from the mounting patterns 22a, 22c and the back surface patterns 23a, 23c, and is electrically floating. In other words, the inspection pattern 24 is in a non-energized state when the semiconductor device 1 is in use.

[0026] In this embodiment, the inspection pattern 24 is formed between a pair of vertical patterns 223. Also, when viewed from the front, the inspection pattern 24, the semiconductor element 3, and the protection element 5 are formed to be aligned in a single line in the vertical direction. In this embodiment, the inspection pattern 24 is formed in a position that sandwiches the semiconductor element 3 between it and the protection element 5. Furthermore, when viewed from the front, the inspection pattern 24, the semiconductor element 3, and the protection element 5 are formed in a position that falls within the vertical formation range of the pair of vertical patterns 223.

[0027] In this embodiment, the inspection pattern 24 is formed in a long rectangular shape in the horizontal direction. When viewed from the front, the area of ​​the inspection pattern 24 is preferably larger than 1 / 5 of the area of ​​the semiconductor element 3, and more preferably larger than 1 / 3 of the area of ​​the semiconductor element 3. By forming the inspection pattern 24 so widely, it is easier to increase the area of ​​the inspection solder 4 placed on the inspection pattern 24, making it easier to check the inspection solder 4. However, from the viewpoint of suppressing the enlargement of the package substrate 2, the area of ​​the inspection pattern 24 is preferably less than or equal to the area of ​​the semiconductor element 3.

[0028] A test solder 4 is placed on the test pattern 24. The test solder 4 is made of the same material as the connecting solder 6 used to connect the semiconductor element 3 to the package substrate 2. The material of the test solder 4 is not particularly limited, but for example, it can be gold-tin (AuSn) solder. In this embodiment, the test solder 4 is a deposited solder deposited on the test pattern 24, but it may also be a paste solder. The test solder 4 is not used to connect components to the test pattern 24, and no components are placed on its front side. That is, the entire front surface of the test solder 4 is exposed. The test solder 4 is reflowed at the same time as the connecting solder 6.

[0029] In this embodiment, the inspection solder 4 is formed in a long rectangular shape in the transverse direction along the inspection pattern 24. When viewed from the front, the area of ​​the inspection pattern 24 is preferably larger than 1 / 5 of the area of ​​the semiconductor element 3, and preferably larger than 1 / 4 of the area of ​​the semiconductor element 3.

[0030] In this embodiment, the inspection solder 4 is not distributed across the entire front surface of the inspection pattern 24, but only in a portion of it. As a result, an exposed surface 241 is formed on the front surface of the inspection pattern 24, exposed from the inspection solder 4. As will be described in detail later, by providing the exposed surface 241, it becomes possible to observe the contrast between the exposed surface 241 and the inspection solder 4 using the detection method described later. As an example, the size of the exposed surface 241 is preferably at least 1 / 5 of the area of ​​the inspection solder 4 when viewed from the front.

[0031] The test solder 4 is placed near the semiconductor element 3. For example, the shortest distance L1 between the test solder 4 and the semiconductor element 3 when viewed from the front is preferably within three times the dimension L2 of the semiconductor element 3, and more preferably less than or equal to the dimension L2 of the semiconductor element 3. The semiconductor element 3 has a square shape when viewed from the front, and the dimension L2 of the semiconductor element 3 is the length of one side of this square. If the shape of the semiconductor element 3 when viewed from the front is not a square, the dimension of the semiconductor element 3 refers to the maximum dimension of the semiconductor element 3. For example, if the shape of the semiconductor element 3 when viewed from the front is rectangular, the dimension of the semiconductor element 3 is the length of the longest side of this rectangle.

[0032] In this embodiment, the semiconductor element 3 is a light-emitting element such as a light-emitting diode (LED) or a semiconductor laser (LD). The semiconductor element 3 can emit ultraviolet light, visible light, or infrared light.

[0033] The semiconductor element 3 is formed so that its shape when viewed from the front is rectangular (specifically, a square). The semiconductor element 3 has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on top of each other, and an anode electrode and a cathode electrode are provided on the package substrate 2 side. The anode electrode of the semiconductor element 3 is electrically connected to the first pad 221 of the mounting pattern 22a, and the cathode electrode is electrically connected to the first pad 221 of the mounting pattern 22c, using connecting solder 6.

[0034] The protection element 5 is a constant voltage element such as a Zener diode. The protection element 5 is electrically connected to the second pads 222 of the mounting patterns 22a and 22c via bumps or the like. The protection element 5 may also be electrically connected to the second pads 222 via solder.

[0035] [Inspection method for semiconductor device 1] Next, the inspection method for the semiconductor device 1 of this embodiment will be described.

[0036] In the semiconductor device 1, the connecting solder 6 is located between the semiconductor element 3 and the package substrate 2, making it difficult to inspect from the front and back sides. Therefore, it is difficult to inspect the molten state of the connecting solder 6 (i.e., whether the semiconductor element 3 and the mounting patterns 22a and 22c are properly electrically connected) by directly inspecting the connecting solder 6.

[0037] Therefore, in this embodiment of the inspection method for the semiconductor device 1, an inspection solder 4 is placed on the semiconductor device 1, and the molten state of the connecting solder 6 is indirectly evaluated based on the reflection characteristics when light is irradiated onto the inspection solder 4 of the semiconductor device 1. That is, if the solder is properly melted by reflow, the reflectivity of light changes before and after reflow, so it is possible to determine whether the molten state of the connecting solder 6 is appropriate based on the reflection characteristics (i.e., appearance) when light is irradiated onto the inspection solder 4.

[0038] In the inspection method for the semiconductor device 1, for example, an inspection device may be used to measure whether the contrast between the inspection solder 4 of the semiconductor device 1 and the exposed surface 241 of the inspection pattern 24 is within a predetermined threshold range, and based on this, it may be determined whether the molten state of the connecting solder 6 is appropriate. Alternatively, an inspection device may be used to measure whether the light reflectance of the inspection solder 4 is within a predetermined threshold range, and based on this, it may be determined whether the molten state of the connecting solder 6 is appropriate.

[0039] Furthermore, inspection can also be performed visually without using inspection equipment. For example, a photograph of the inspection pattern 24 and inspection solder 4 when light is shone on the semiconductor device 1 before reflow, and a photograph of the inspection solder 4 and inspection pattern 24 when light is shone on the semiconductor device 1 after proper reflow, can be prepared as references. Then, by visually checking which reference the appearance of the inspection solder 4 when light is shone on the semiconductor device 1 to be inspected is closest to, it is possible to determine the melting state of the connecting solder 6.

[0040] (Operation and effects of the first embodiment) The semiconductor device 1 in this embodiment has a configuration in which a semiconductor element 3 and a test solder 4 are housed on the front side of a package substrate 2. The package substrate 2 is mounted on the back side of a printed circuit board 9 and is a fine substrate smaller than the printed circuit board 9. In this embodiment of the semiconductor device 1, both the semiconductor element 3 and the test solder 4 are housed on this fine package substrate 2, so that a temperature difference is less likely to occur between the connecting solder 6 and the test solder 4 during reflow soldering. Therefore, in this embodiment of the semiconductor device 1, the melting state of the connecting solder 6 can be inspected with high precision by checking the melting state of the test solder 4.

[0041] Furthermore, the package substrate 2 has an electrically floating inspection pattern 24 formed on its front surface 211, and the inspection solder 4 is formed on the inspection pattern 24. Therefore, the wetting spread of the inspection solder 4 is limited to the inspection pattern 24, and unintentional short circuits between the inspection solder 4 and other components are suppressed.

[0042] Furthermore, the semiconductor device 1 in this embodiment further includes a protective element 5 mounted on the package substrate 2, and when viewed from the front, the inspection pattern 24, the semiconductor element 3, and the protective element 5 are arranged in a line. Therefore, it is easy to miniaturize the semiconductor device 1.

[0043] Furthermore, the mounting patterns 22a and 22c have a pair of vertical patterns 223 that are elongated in the vertical direction and arranged horizontally via the semiconductor element 3, and the inspection pattern 24 is formed between the pair of vertical patterns 223. Therefore, it is easy to miniaturize the semiconductor device 1.

[0044] Furthermore, in the inspection method for the semiconductor device 1 of this embodiment, the molten state of the connecting solder 6 is inspected based on the reflection characteristics when light is irradiated onto the inspection solder 4. Therefore, unlike the inspection method described in, for example, the aforementioned Patent Document 1, the molten state of the connecting solder 6 can be evaluated with high accuracy regardless of the placement accuracy of the inspection solder.

[0045] As described above, this embodiment provides a semiconductor device and a method for inspecting a semiconductor device that can accurately evaluate the molten state of the solder used for connection.

[0046] [Second Embodiment] A second embodiment of the present invention will be described with reference to Figure 4. Figure 4 is a plan view of the semiconductor device 1 of this embodiment.

[0047] This embodiment is a modified version of the first embodiment in which the arrangement of the inspection solder 4 is changed. In this embodiment, the inspection solder 4 is formed on the mounting patterns 22a and 22c. Specifically, the inspection solder 4 is provided on each of the pair of vertical patterns 223. The inspection solder 4 is formed in a long length in the vertical direction along the vertical patterns 223. The inspection solder 4 is not distributed across the entire front surface of the vertical patterns 223, but only in a portion of it. As a result, an exposed surface 223a is formed on the front surface of the vertical patterns 223, exposed to the front side from the inspection solder 4.

[0048] In this embodiment, the inspection pattern shown in the first embodiment (see reference numeral 24 in Figure 1) is not formed. In particular, in this embodiment, vapor-deposited solder is preferred for the inspection solder 4. This is because paste solder is easily wetted and spread by reflow soldering, and if the inspection solder 4 on the mounting patterns 22a, 22c (i.e., conductive parts) is made of paste solder, there is a risk that the inspection solder 4 may unintentionally come into contact with other components.

[0049] Otherwise, it is the same as in the first embodiment. In addition, among the reference numerals used in the second embodiment and subsequent embodiments, those that are the same as those used in the previously described embodiments represent the same components, etc., as those in the previously described embodiments, unless otherwise specified.

[0050] (Operation and effects of the second embodiment) In this embodiment, the test solder 4 is formed on the mounting patterns 22a and 22c (i.e., conductive areas). Thus, since the test solder 4 only needs to be formed on the mounting patterns 22a and 22c that are always present on the package substrate 2, the configuration of the semiconductor device 1 can be easily simplified.

[0051] Furthermore, the inspection solder 4 is formed in a long, vertical shape on the vertical pattern 223. Therefore, the area of ​​the inspection solder 4 is ensured, making it easy to verify. Furthermore, it has the same functions and effects as the first embodiment.

[0052] [Third Embodiment] A third embodiment of the present invention will be described with reference to Figures 5 and 6. Figure 5 is a plan view of the semiconductor device 1 of this embodiment. Figure 6 is a cross-sectional view taken along the line VI-VI in Figure 5.

[0053] This embodiment is a modified version of the first embodiment in which the arrangement of the inspection pattern 24 and the inspection solder 4 is changed. In this embodiment, through holes 223b are formed in each vertical pattern 223, and the inspection pattern 24 is formed within the through holes 223b. For example, the through holes 223b are formed in a circular shape, and the inspection pattern 24 is formed in a circular shape with a smaller diameter than the through holes 223b. A circular inspection solder 4 is placed on the inspection pattern 24. Otherwise, it is the same as in the first embodiment.

[0054] (Operation and effects of the third embodiment) In this embodiment, through holes 223b are provided in the mounting patterns 22a and 22c, and an inspection pattern 24 is provided inside the through holes 223b, making it easier to miniaturize the semiconductor device 1. Furthermore, it has the same functions and effects as the first embodiment.

[0055] [Fourth Embodiment] A fourth embodiment of the present invention will be described with reference to Figure 7. Figure 7 is a plan view of the semiconductor device 1 of this embodiment.

[0056] This embodiment relates to a semiconductor device 1 in which a plurality of semiconductor elements 3 are mounted on a package substrate 2. In this embodiment, the number of semiconductor elements 3 on the package substrate 2 is four. Preferably, the number of semiconductor elements 3 on the package substrate 2 is four or less. In this embodiment as well, each side of the substrate 21 as viewed from the front is 10 mm or less, preferably 5 mm or less.

[0057] The mounting pattern 22 comprises four first pads 221 that electrically connect four semiconductor elements 3 via connecting solder 6. Electrically, the four first pads 221 are patterned such that the four semiconductor elements 3 connected to them are connected in series. Electrically, the second pads 222 are patterned such that the protection element 5 is connected in parallel with the four semiconductor elements 3 connected in series between a pair of long vertical patterns 223.

[0058] When viewed from the front, the four semiconductor elements 3 are arranged vertically and horizontally between a pair of vertical patterns 223. In other words, the four semiconductor elements 3 are formed in a 2x2 matrix arrangement in the vertical and horizontal directions.

[0059] Furthermore, the inspection pattern 24 is positioned so that, when viewed from the front, it is surrounded by the four semiconductor elements 3. This ensures that the inspection solder 4 on the inspection pattern 24 is positioned close to each of the connecting solders 6 of the four semiconductor elements 3. For example, the shortest distance L1 between the inspection solder 4 and each of the semiconductor elements 3 when viewed from the front is preferably within three times the dimension L2 of the semiconductor element 3, and more preferably less than or equal to the dimension L2 of the semiconductor element 3. In this embodiment, the inspection pattern 24 and the inspection solder 4 have a long rectangular shape in the lateral direction. Otherwise, it is the same as in the first embodiment.

[0060] (Operation and Effects of the Fourth Embodiment) This embodiment also has the same functions and effects as the first embodiment.

[0061] [Fifth Embodiment] A fifth embodiment of the present invention will be described with reference to Figure 8. Figure 8 is a plan view of the semiconductor device 1 of this embodiment.

[0062] This embodiment is a modified version of the fourth embodiment in which the arrangement of the inspection pattern 24 and the inspection solder 4 is changed. Specifically, the inspection pattern 24 and the inspection solder 4 are positioned on one side in the vertical direction from the arrangement areas of the mounting patterns 22a, 22c, the multiple semiconductor elements 3, and the protection element 5. In this embodiment, the inspection pattern 24 and the inspection solder 4 are positioned on one side in the vertical direction of one of the vertical patterns 223. The longest of the shortest distances L11 between the inspection solder 4 and each of the multiple semiconductor elements 3, as viewed from the front, is preferably within three times the dimension L2 of the semiconductor element 3. Otherwise, it is the same as in the fourth embodiment.

[0063] (Operation and effects of the fifth embodiment) This embodiment also has the same functions and effects as the fourth embodiment.

[0064] [Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to Figure 9. Figure 9 is a plan view of the assembled substrate device 10 of this embodiment.

[0065] This embodiment relates to a substrate assembly device 10. The substrate assembly device 10 comprises a substrate assembly 11, a plurality of semiconductor elements 3, a plurality of test solders 4, and a plurality of protective elements 5. The substrate assembly 11 has a base material 111 which is divided into a plurality of unit regions 100 by dicing, and mounting patterns 22a, 22c formed on the front surface 111b of each of the plurality of unit regions 100. The plurality of semiconductor elements 3 are mounted on each of the mounting patterns 22a, 22c of the plurality of unit regions 100 via connecting solders 6. The test solders 4 are located on the front side of the base material 111 and are arranged on each of the plurality of unit regions 100.

[0066] In this embodiment, the structure of each unit region 100 is the same as that of the semiconductor device (see reference numeral 1 in Figure 1) in the first embodiment. That is, in this embodiment, each of the multiple unit regions 100 in the assembled substrate device 10 becomes a semiconductor device in the first embodiment after dicing. In this embodiment, there are a total of 25 unit regions 100 arranged in a 5x5 grid, and after dicing, 25 semiconductor devices of the first embodiment are formed from one assembled substrate device 10. Note that the number of unit regions 100 in the assembled substrate device 10 is merely an example and could be, for example, 100 or more, 300 or more, etc. Also, the configuration of the unit regions 100 may be the configuration of any of the second to fifth embodiments, etc.

[0067] In this embodiment, groove-shaped scribe lines and modified layers for stealth dicing are formed on the grid-like dicing lines 111a of the substrate 111, which are the areas to be divided.

[0068] (Operation and Effects of the Sixth Embodiment) The assembled substrate device 10 in this embodiment includes multiple inspection solders 4 arranged in each of the multiple unit regions 100 on the front side of the assembled substrate 11. Therefore, the molten state of the connecting solder 6 in each unit region 100 can be accurately determined using the inspection solders 4 arranged in that unit region 100. Furthermore, it has the same functions and effects as the first embodiment.

[0069] (Summary of the embodiments) Next, the technical concept understood from the embodiments described above will be described using the reference numerals and other symbols from the embodiments. However, the reference numerals and other symbols in the following description are not limited to the components in the claims that are specifically shown in the embodiments.

[0070] [1] A first embodiment of the present invention is a semiconductor device 1 comprising a base material 21 and a package substrate 2 having mounting patterns 22a and 22c formed on the front surface 211 of the base material 21, a semiconductor element 3 mounted on the mounting patterns 22a and 22c via connecting solder 6, and an inspection solder 4 arranged on the front side of the package substrate 2. This allows for accurate evaluation of the molten state of the connecting solder 6.

[0071] [2] A second embodiment of the present invention is that, in the first embodiment, the package substrate 2 has an electrically floating inspection pattern 24 formed on the front surface 211, and the inspection solder 4 is formed on the inspection pattern 24. This prevents the test solder 4 from unintentionally short-circuiting to another component.

[0072] [3] A third embodiment of the present invention is the second embodiment, further comprising a protective element 5 mounted on the package substrate 2, wherein, when viewed from the front, the inspection pattern 24, the semiconductor element 3, and the protective element 5 are arranged in a line. This makes it easier to miniaturize the semiconductor device 1.

[0073] [4] A fourth embodiment of the present invention is that, in the second or third embodiment, the mounting patterns 22a, 22c have a pair of vertical patterns 223 that are elongated in the vertical direction and arranged horizontally with respect to the semiconductor element 3, and the inspection pattern 24 is formed between the pair of vertical patterns 223. This makes it easier to miniaturize the semiconductor device 1.

[0074] [5] A fifth embodiment of the present invention is that, in the first embodiment, the test solder 4 is formed on the mounting patterns 22a, 22c. This makes it easier to simplify the configuration of the semiconductor device 1.

[0075] [6] A sixth embodiment of the present invention is a substrate assembly device 10 comprising a substrate 111 divided into a plurality of unit regions 100 by dicing, and a substrate assembly 11 having mounting patterns 22a, 22c formed on the front surface 111b of each of the plurality of unit regions 100, a plurality of semiconductor elements 3 mounted on each of the mounting patterns 22a, 22c of the plurality of unit regions 100 via connecting solder 6, and a plurality of inspection solders 4 arranged on the front side of the substrate assembly 11 and on each of the plurality of unit regions 100. This allows for accurate evaluation of the molten state of the connecting solder 6.

[0076] [7] A seventh embodiment of the present invention is an inspection method for a mounting apparatus 1, 10 comprising mounting substrates 2, 11, a semiconductor element 3 mounted on the front side of the mounting substrates 2, 11 via connecting solder 6, and an inspection solder 4 arranged on the front side of the mounting substrates 2, 11, wherein the inspection method inspects the molten state of the connecting solder 6 based on the reflection characteristics when light is irradiated onto the inspection solder 4. This allows for accurate evaluation of the molten state of the connecting solder 6.

[0077] (Note) Although embodiments of the present invention have been described above, the embodiments described herein do not limit the invention as defined in the claims. Furthermore, it should be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention. Moreover, the present invention can be implemented with appropriate modifications without departing from its spirit. [Explanation of Symbols]

[0078] 1… Semiconductor equipment (mounting equipment) 10… Assembly and mounting equipment (mounting equipment) 100... Unit area 11… Assembly board (mounted circuit board) 111...Base material 111b…Front side 2…Package substrate (mounted substrate) 3…Semiconductor elements 4…Solder for inspection 5…Protective element 6…Solder for connections 21...Base material 211…Front side 223...Vertical pattern 22a…Implementation Pattern 22c…Implementation Pattern 24...Inspection pattern

Claims

1. A package substrate having a base material and a mounting pattern formed on the front surface of the base material, A semiconductor element mounted on the aforementioned mounting pattern via connecting solder, The package substrate comprises a test solder arranged on the front side, Semiconductor equipment.

2. The package substrate has an electrically floating inspection pattern formed on its front surface, The aforementioned inspection solder is formed on the aforementioned inspection pattern, The semiconductor device according to claim 1.

3. The package substrate further comprises a protective element mounted on the aforementioned package substrate. When viewed from the front, the inspection pattern, the semiconductor element, and the protection element are arranged in a straight line. The semiconductor device according to claim 2.

4. The aforementioned mounting pattern has a pair of vertical patterns that are elongated in the vertical direction and arranged horizontally with the semiconductor element in between. The inspection pattern is formed between the pair of vertical patterns. The semiconductor device according to claim 2.

5. The aforementioned test solder is formed on the aforementioned mounting pattern. The semiconductor device according to claim 1.

6. A substrate divided into multiple unit regions by dicing, and a composite substrate having mounting patterns formed on the front surface of each of the multiple unit regions, A plurality of semiconductor elements are mounted on each of the plurality of unit region mounting patterns via connecting solder, The assembly substrate comprises a plurality of test solders arranged on the front side of each of the plurality of unit regions, Collective board device.

7. A method for inspecting a mounting apparatus comprising a mounting substrate, a semiconductor element mounted on the front side of the mounting substrate via connecting solder, and an inspection solder arranged on the front side of the mounting substrate, The molten state of the connecting solder is inspected based on the reflection characteristics when light is irradiated onto the aforementioned inspection solder. Testing method.

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