Display device, method for controlling a display device

Abstract

There is a problem in that it is difficult to control the scan driver when displaying at different refresh rates. [Solution] The system comprises a display unit, a scanning driver that drives the display unit, and a control unit that controls the scanning driver. The scanning driver receives a plurality of clock signals with different phases from each other. When a first image and a second image with a lower frequency than the first image are displayed adjacent to each other, the control unit sets the refresh rate switching position according to the data of the first image, the data of the second image, and the phases of the plurality of clock signals.

Description

Technical Field

[0001] The present disclosure relates to a display device and the like.

Background Art

[0002] Patent Document 1 discloses a scanning driver used for a display device that performs partial display.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When displaying at different refresh rates, there is a problem that the control of the scanning driver becomes complicated.

Means for Solving the Problems

[0005] A driver circuit according to an aspect of the present disclosure includes a display unit including a plurality of rows, a scanning driver that drives the display unit, and a control unit that controls the scanning driver. A plurality of clock signals having different phases are input to the scanning driver. When the control unit displays a first video adjacent to a second video having a lower frequency than the first video, the control unit sets the switching position of the refresh rate according to the data of the first video, the data of the second video, and the phases of the plurality of clock signals.

Effects of the Invention

[0006] When displaying at different refresh rates, the control of the scanning driver becomes easy.

Brief Description of the Drawings

[0007] [Figure 1]This is a block diagram showing an example configuration of a display device according to this embodiment. [Figure 2] This is a block diagram showing an example configuration of a display device according to this embodiment. [Figure 3] This block diagram shows an example configuration of the scanning driver for this display device. [Figure 4] This is a timing chart showing the control method for the scanning driver of this display device. [Figure 5] This is a block diagram showing the driving method of this display device. [Figure 6] This is a block diagram showing the driving method of this display device. [Figure 7] This is a timing chart showing the control method for the scanning driver of this display device. [Figure 8] This is a timing chart showing the control method for the scanning driver of this display device. [Figure 9] This is a timing chart illustrating the control method of the scanning driver according to this embodiment and comparative embodiment. [Figure 10] This is a flowchart showing the operation of the control unit. [Figure 11] This is a timing chart showing the control method for the scanning driver of this display device. [Figure 12] This is a timing chart showing the control method for the scanning driver of this display device. [Modes for carrying out the invention]

[0008] Figures 1 and 2 are block diagrams showing an example configuration of the display device according to this embodiment. Figure 3 is a block diagram showing an example configuration of the scanning driver of this display device. Figure 4 is a timing chart showing the control method of the scanning driver of this display device. Figures 5 and 6 are block diagrams showing the driving method of this display device. As shown in Figures 1 to 6, this display device 20 comprises a display unit 30 including multiple lines, a scanning driver 9 that drives the display unit 30, and a control unit 15 that controls the scanning driver 9. Multiple clock signals K1 to K6 with different phases are input to the scanning driver 9. When displaying a first image and a second image with a lower frequency than the first image adjacent to each other, the control unit 15 sets the refresh rate (rewrite frequency) switching position PF according to the data DT of the first and second images and the phases of the multiple clock signals K1 to K6.

[0009] Here, a pixel row of the display unit 30 is simply referred to as a "row." The switching position PF may mean the switching row. The display unit 30 includes multiple scan lines (Gj-1, Gj, Gj+1, etc.) arranged in the first direction (vertical direction), and each row of the display unit 30 includes a scan line. The first and second images are displayed adjacent to each other in the first direction (column direction perpendicular to the row), and the second image has a lower image update frequency than the first image.

[0010] In this way, by setting the switching position PF based on the phases of multiple clock signals K1 to K6 in addition to the data DT of the first and second video, the control of the scanning driver 9 becomes easier.

[0011] The control unit 15 includes an input unit 14 that receives data DT (hereinafter referred to as data DT) of the first and second video, a level shifter IC (level shifter circuit) 16, a timing controller 17, and a memory 18. The timing controller 17 generates a control signal including reference signals E1 and E2 based on the data DT and outputs it to the level shifter IC 16.

[0012] Level shifter IC16 generates a plurality of clock signals K1 to K6 and pulse signals Q1 and Q2 based on control signals (including reference signals E1 and E2) from timing controller 17. Shift register 10 outputs scan signal Vj to scan line Gj of display unit 30 using the clock signals K1 to K6 and pulse signals Q1 and Q2 from level shifter IC16.

[0013] This display device 20 includes data driver 8 that drives display unit 30, and control unit 15 controls data driver 8 and scan driver 9. A plurality of sub-pixels SP are arranged in the row direction (horizontal direction) in each row (pixel row) of display unit 30, and sub-pixel SP is connected to data line DL and scan line Gj via a transistor (not shown). Scan driver 9 may be provided on both sides of display unit 30. Display unit 30 and scan driver 9 may be included in liquid crystal panel 13.

[0014] As shown in FIG. 3, scan driver 9 includes shift register 10 having a plurality of stages into which a plurality of clock signals K1 to K6 having different phases are input, and clock signal line group 11. Clock signal line group 11 includes first to m-th clock signal lines C1 to C6 (m = 6) through which a plurality of clock signals K1 to K6 are respectively transmitted.

[0015] The first to m-th clock signals K1 to K6 (m = 6) have the same period, and the phases of the first clock signal K1 and the m-th clock signal K6 are shifted by 1 / m period (= 1 / 6 period). 1 / m period (= 1 / 6 period) may be equal to one horizontal scan period.

[0016] The unit circuit Zn of the n-th stage of shift register 10 includes register circuit Hn including set terminal Sn, reset terminal Rn, input terminal IK of pulse signal Q1, and control terminal Un, and output circuit On including clock terminals I1 and I2, set terminal Sn, reset terminal Rn, and output terminals Xn and Yn.

[0017] In the output circuit On of the unit circuit Zn, the first clock signal K1 is input to the clock terminal I1, and the second clock signal K2 is input to the clock terminal I2. The pulse of the first clock signal K1 is output to the scanning line Gj (j = 2n - 1) via the output terminal Xn, and the pulse of the second clock signal K2 is output to the scanning line Gj+1 via the output terminal Yn. In the output circuit of the unit circuit Zn-1, the fifth clock signal K5 is input to the clock terminal I1, and the sixth clock signal K6 is input to the clock terminal I2. The pulse of the sixth clock signal K6 is output to the scanning line Gj-1 via the output terminal Yn-1. In the output circuit of the unit circuit Zn+1, the third clock signal K3 is input to the clock terminal I1, and the fourth clock signal K4 is input to the clock terminal I2. The pulse of the third clock signal K3 is output to the scanning line Gj+2 via the output terminal Xn+1.

[0018] As shown in FIGS. 4 to 6, the switching position PF is set to the row (the row including the scanning line Gj) where the pulse of the first clock signal K1 (the clock of the first clock signal line C1) is output. That is, the control unit 15 sets a part of the second video (low-frequency video) to the same refresh rate as the first video (high-frequency video) (raises the refresh rate) so that the switching position PF becomes the row (including the scanning line Gj) where the pulse of the first clock signal K1 is output. Specifically, it is as follows.

[0019] Let A be a natural number and T be an integer of 0 or more. When the end of the first video is the A-th row and the start of the second video (low-frequency video) is the (A + 1)-th row, the control unit 15 sets the rows from the A-th row to the (A + T)-th row in the display unit 30 to the first refresh rate, and sets the (A + T + 1)-th row, which is the switching position PF, to the second refresh rate lower than the first refresh rate. Here, let the phase number of the clock signal be m, 0 ≦ T ≦ m - 1, the first refresh rate is, for example, 60 to 240 [Hz], and the second refresh rate is, for example, 1 to 48 [Hz].

[0020] In Figures 4 and 5, since m=6 and A=243, the number of adjustment rows T=3 is used to set the switching position PF to the row containing scan line G247 (=243+3+1) where the pulse of the first clock signal K1 is output. In other words, by raising the refresh rate of three rows, including scan lines G244~G246, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PF is set to row 247 (including scan line G247), where the pulse of the first clock signal K1 is output.

[0021] Let B be a natural number greater than A and F be a non-negative integer. When the end of the second image is row B, the control unit 15 sets rows (A+T+1) to (BF) in the display unit 30 to the second refresh rate. Here, m is the number of phases of the clock signal, and 0 ≤ F ≤ m-1.

[0022] In Figures 4 and 5, since m=6, A=243, and B=480, T=3 and F=0, the 247th row (including scan line G247) to the 480th row (including scan line G480) of the display unit 30 are set to the second refresh rate.

[0023] In Figures 4 and 5, in the display unit 30, lines 1 to 246 (including G246) are the high refresh rate region HR, and lines 247 (including G247) to 480 (including G480) are the low refresh rate region LR. In this case, the last line of the high refresh rate region HR (including scan line G246) and the last line of the low refresh rate region LR (including scan line G480) are the lines on which the pulse of the sixth clock signal K6 is output (lines that are multiples of 6, which is the number of phases m of the clock signal).

[0024] As shown in Figures 1 to 6, the control unit 15 displays a third image adjacent to the second image, with a higher frequency than the second image. When the start of the third image is row (B+1), the control unit 30 sets row (B+1-F) to a third refresh rate different from the second refresh rate.

[0025] In Figures 4 and 6, since m=6 and B=480, the number of adjustment rows F=0, and row 481 (including scan line G481) in the display unit 30 is set to the third refresh rate. That is, by setting F=0, the refresh rate switching position PS is set to the row containing scan line G481 (=480+1-0) where the pulse of the first clock signal K1 is output. The third refresh rate is, for example, 60~240 [Hz].

[0026] In Figures 4 to 6, in the display unit 30, lines 0 to 246 (including scan line G246) are the high refresh rate region HR, lines 247 (including scan line G247) to 480 (including scan line G480) are the low refresh rate region LR, and lines 481 (including scan line G481) and onward are the high refresh rate region HR. In this case, the starting line of the low refresh rate region LR (line 247, which is the switching position PF) and the starting line of the high refresh rate region HR (line 481, which is the switching position PS) are lines that contain scan lines from which the pulse of the first clock signal K1 is output (lines corresponding to a number that is a multiple of 6, which is the number of phases m of the clock signal, plus 1).

[0027] In the display device 20, during periods when the second image is not updated, the pulse patterns of the first to m-th clock signals are blank (flat state without pulses) in the areas corresponding to rows (A+T+1) to (BF) in the display unit 30. That is, in the pulse patterns of the 6-phase clock signals K1 to K6 shown in Figure 4, the areas corresponding to rows 247 (including scan line G247) to 480 (including scan line G480) are blank.

[0028] Figure 7 is a timing chart showing the control method of the scanning driver of this display device. Figure 4 describes the pulse pattern during periods (frames) when the second image (low-frequency image) is not updated (the area corresponding to lines 247 to 480 is a blank with no pulses). However, during periods (frames) when the second image is updated, pulses are also formed in the area corresponding to lines 247 to 480, as shown in Figure 7. For example, if the first image is 120 Hz and the second image is 24 Hz, the second image will be updated once while the first image is updated five times.

[0029] Figure 8 is a timing chart showing the control method of the scanning driver of this display device. In Figure 8, since m=6 (number of phases of the clock signal) and B (end row of the second image)=482, the number of adjustment rows F=2 is set, and row 481, which is (B+1-F) rows in the display unit 30, is set to the third refresh rate. Here, by setting F=2, the refresh rate switching position PS is set to the row containing scan line G481 (=480+1-0) to which the pulse of the first clock signal K1 is output. That is, by raising the refresh rate of two rows, including scan lines G481~G482, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PS is set to row 481 (including scan line G481) to which the pulse of the first clock signal K1 is output. The third refresh rate is, for example, 60~240[Hz]. The first and third refresh rates may be the same.

[0030] Figure 9 is a timing chart showing the control method of the scanning driver according to this embodiment and comparative embodiment. As shown in Figure 9, the level shifter IC 16 of the display device 20 uses a plurality of reference signals E1 and E2 from the timing controller 17 to generate clock signals K1 to K6 with a number of phases greater than the plurality of reference signals E1 and E2.

[0031] The frequencies of the reference signals E1 and E2 are at least twice (for example, 6 times) the frequencies of the clock signals K1 to K6. As the reference signal E1 rises sequentially, the clock signals K1 to K6 rise sequentially, and as the reference signal E2, which is in the opposite phase to the reference signal E1, falls sequentially, the clock signals K1 to K6 fall sequentially, thereby forming the pulse pattern of the clock signals K1 to K6.

[0032] In the embodiment, the pulse is stopped by the clock signal K6, so pulse formation resumes from the clock signal K1, and the start data D481 of the third image is correctly written to line 481 (including scan line G481). On the other hand, in the comparative embodiment, the pulse is stopped by the clock signal K3, so pulse formation resumes from the clock signal K4, and the start data D481 of the third image is written to line 478. This results in a display misalignment of 3 lines. To eliminate the display misalignment, it becomes necessary to adjust the output timing of the start data according to the pulse stopping position, or the control of the scan driver becomes difficult.

[0033] Figure 10 is a flowchart showing the operation of the control unit. As shown in Figure 10, the control unit 15 receives data for the first and second video (step S50), determines the refresh rate region (step S60), sets the refresh rate switching position (step S70), generates a reference signal (step S80), and generates multiple clock signals (step S90).

[0034] The control unit 15 may receive position information (start position and end position) of the first and second images from an external source. For example, the position information of the first and second images may be included in the data DT input from an external source, and the refresh rate region may be determined based on this position information (step S60).

[0035] The control unit 15 may determine the position information (start position and end position) of the first and second images from the temporal changes in the input data DT. For example, the temporal changes may be determined by the data checksum for each unit area (e.g., row) spanning multiple frames, and the refresh rate area may be determined based on the determination result (step S60).

[0036] Figure 11 is a timing chart showing the control method of the scanning driver of this display device. In Figure 11, the number of phases of the clock signal is set to 8, and multiple clock signals K1 to K8 are used.

[0037] Let A be a natural number and T be a non-negative integer. When the end of the first image is row A and the beginning of the second image (low-frequency image) is row (A+1), the control unit 15 sets row A to row (A+T) in the display unit 30 as the first refresh rate, and row (A+T+1), which is the switching position PF, as the second refresh rate, which is lower than the first refresh rate. Here, m is the number of phases of the clock signal, 0 ≤ T ≤ m-1, and the first refresh rate is, for example, 60 to 240 [Hz], and the second refresh rate is, for example, 1 to 48 [Hz].

[0038] In Figure 11, since m=8 and A=236, setting T=4 sets the switching position PF to the row containing scan line G241 (=236+4+1) where the pulse of the first clock signal K1 is output. In other words, by raising the refresh rate of four rows, including scan lines G237~G240, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PF is set to row 241 (including scan line G241), where the pulse of the first clock signal K1 is output.

[0039] Let B be a natural number greater than A and F be a non-negative integer. When the end of the second image is row B, the control unit 15 sets rows (A+T+1) to (BF) in the display unit 30 to the second refresh rate. Here, m is the number of phases of the clock signal, and 0 ≤ F ≤ m-1.

[0040] In Figure 11, since m=8, A=236, and B=408, the number of adjustment lines T=4 and F=0, and lines 241 (including scan line G241) to 408 (including scan line G408) in the display unit 30 are set to the second refresh rate.

[0041] In Figure 11, in the display unit 30, lines 0 to 240 (including G240) are the high refresh rate region, and lines 241 (including G241) to 408 (including G408) are the low refresh rate region. In this case, the last line of the high refresh rate region (including scan line G240) and the last line of the low refresh rate region (including scan line G408) are the lines on which the pulse of the 8th clock signal K8 is output (lines that are multiples of 8, which is the number of phases m of the clock signal).

[0042] As shown in Figures 1 and 11, the control unit 15 displays a third image adjacent to the second image, with a higher frequency than the second image, and when the start of the third image is the (B+1) row, it sets the (B+1-F) row in the display unit 30 to a third refresh rate different from the second refresh rate.

[0043] In Figure 11, since m=8 and B=408, the number of adjustment rows F=0, and row 409 (including scan line G409) in the display unit 30 is set to the third refresh rate. That is, by setting F=0, the refresh rate switching position PS is set to the row containing scan line G409 (=408+1-0) where the pulse of the first clock signal K1 is output. The third refresh rate is, for example, 60~240[Hz].

[0044] In Figure 11, in the display unit 30, lines 0 to 240 (including scan line G240) are in the high refresh rate region, lines 241 (including scan line G241) to 408 (including scan line G408) are in the low refresh rate region, and lines 409 (including scan line G409) and onward are in the high refresh rate region. In this case, the starting line of the low refresh rate region (line 241, which is the switching position PF) and the starting line of the high refresh rate region (line 409, which is the switching position PS) are each lines that contain scan lines on which the pulse of the first clock signal K1 is output (lines corresponding to a number that is a multiple of 8, which is the number of phases m of the clock signal, plus 1).

[0045] Figure 12 is a timing chart showing the control method of the scanning driver of this display device. In Figure 12, since m=8 and B (end of the second image)=411, the number of adjustment rows F=3, and row 409, which is row (B+1-F) in the display unit 30, is set to the third refresh rate. Here, by setting F=3, the refresh rate switching position PS is set to the row containing scan line G409 (=411+1-3) to which the pulse of the first clock signal K1 is output. That is, by raising the refresh rate of three rows including scan lines G409~G411, which are part of the low-frequency image (second image), to the same refresh rate as the high-frequency image (first image), the refresh rate switching position PS is set to row 409 (including scan line G409) to which the pulse of the first clock signal K1 is output. The third refresh rate is, for example, 60~240[Hz]. The first and third refresh rates may be the same.

[0046] The embodiments described above are for illustrative and explanatory purposes only, and not for limitation. It will be apparent to those skilled in the art that many variations are possible based on these examples and descriptions.

[0047] 〔summary〕 The display device of embodiment 1 comprises a display unit including multiple lines, a scanning driver that drives the display unit, and a control unit that controls the scanning driver. The scanning driver receives a plurality of clock signals with different phases from each other, and the control unit sets the refresh rate switching position when displaying a first image and a second image with a lower frequency than the first image adjacent to each other, according to the phases of the data of the first image, the data of the second image, and the plurality of clock signals.

[0048] The display device of embodiment 2 is the display device of embodiment 1, wherein m is an integer of 2 or more, the plurality of clock signals are the first to the mth clock signals, and the switching position is the row on which the pulse of the first clock signal is output.

[0049] In the display device of embodiment 3, the control unit sets a portion of the second video to the same refresh rate as the first video, such that the switching position corresponds to the row on which the pulse of the first clock signal is output.

[0050] The display device of embodiment 4, in any one of the display devices of embodiments 1 to 3, where A is a natural number and T is a non-negative integer, and the end of the first image is row A and the beginning of the second image is row (A+1), the control unit sets row A to (A+T) in the display unit as the first refresh rate, and sets row (A+T+1), which is the switching position, as the second refresh rate, which is lower than the first refresh rate.

[0051] The display device of embodiment 5, in the display device of embodiment 4, sets the second refresh rate to rows (A+T+1) to (BF) in the display unit, where B is a natural number greater than A and F is a non-negative integer, and the end of the second image is row B.

[0052] The display device of embodiment 6 is the display device of embodiment 4, where 0 ≤ T ≤ m-1.

[0053] In the display device of embodiment 7, 0 ≤ F ≤ m-1 is observed in the display device of embodiment 5.

[0054] In the display device of embodiment 8, the pulses of the first clock signal are output to the (A+T+1) row and the (B-F+1) row, respectively, in the display device of embodiment 5.

[0055] The display device of embodiment 9, in the display device of embodiment 5, outputs the pulse of the m clock signal to the (A+T) row and the (BF) row, respectively, in the shift register.

[0056] The display device of embodiment 10, in the display device of embodiment 5, has a control unit that displays a third image adjacent to the second image with a higher frequency than the second image, and when the start of the third image is the (B+1) row, sets the (B+1-F) row in the display unit to a third refresh rate higher than the second refresh rate.

[0057] In the display device of embodiment 11, the pulse patterns of the first to m clock signals are blank in the portion corresponding to rows (A+T+1) to (BF) on the display unit.

[0058] The display device of embodiment 12 is one of the display devices of embodiments 2 to 11, in which the first to m clock signals have the same period, and the phases of the first clock signal and the m clock signal are shifted by 1 / m period.

[0059] In the display device of embodiment 13, the 1 / m period is equal to one horizontal scanning period, as in the display device of embodiment 12.

[0060] The display device of embodiment 14 is a display device of any one of embodiments 1 to 13, wherein the display unit includes a plurality of scan lines arranged in a first direction, and the first and second images are displayed adjacent to each other in the first direction.

[0061] The display device of embodiment 15 is one of the display devices of embodiments 1 to 14, in which the control unit receives position information of the first and second images from an external source.

[0062] In the display device of embodiment 16, in any one of the display devices of embodiments 1 to 15, the control unit determines the position information of the first and second images from the temporal changes of the images.

[0063] In the display device of embodiment 17, the control unit determines the temporal change by the data checksum for each unit area, as in the display device of embodiment 16.

[0064] The display device of embodiment 18 is a display device in any one of embodiments 1 to 17, wherein the control unit includes a timing controller and a level shifter circuit (IC).

[0065] The display device of embodiment 19, in the display device of embodiment 18, has a level shifter circuit that uses a plurality of reference signals from the timing controller to generate a plurality of clock signals with a larger number of phases than the plurality of reference signals.

[0066] The method for driving a display device according to embodiment 20 comprises a display unit including multiple lines, a scanning driver for driving the display unit, and a control unit for controlling the scanning driver, wherein a plurality of clock signals with different phases are input to the scanning driver, and when a first image and a second image with a lower frequency than the first image are displayed adjacent to each other, the refresh rate switching position is set according to the phases of the data of the first image, the data of the second image, and the plurality of clock signals. [Explanation of Symbols]

[0067] 9 Scanning Driver 10 Shift Registers 15 Control Unit 16 Level Shifter IC 17 Timing Controller 20 Display section PF PS switching position Gj scan line SP subpixel HR High Refresh Rate Area LR Low refresh rate area

Claims

1. It comprises a display unit including multiple lines, a scanning driver that drives the display unit, and a control unit that controls the scanning driver, Multiple clock signals with different phases are input to the aforementioned scanning driver. The control unit, when displaying a first image and a second image with a lower frequency than the first image adjacent to each other, sets the refresh rate switching position according to the phase of the data of the first image, the data of the second image, and the plurality of clock signals, in a display device.

2. When m is an integer of 2 or more, the plurality of clock signals are the first to the mth clock signals. The display device according to claim 1, wherein the switching position is the row on which the pulse of the first clock signal is output.

3. The display device according to claim 2, wherein the control unit sets a portion of the second image to the same refresh rate as the first image, such that the switching position corresponds to the row on which the pulse of the first clock signal is output.

4. The display device according to claim 2, wherein, when A is a natural number and T is a non-negative integer, and the end of the first image is row A and the beginning of the second image is row (A+1), the control unit sets row A to (A+T) in the display unit as a first refresh rate, and sets row (A+T+1), which is the switching position, as a second refresh rate lower than the first refresh rate.

5. The display device according to claim 4, wherein B is a natural number greater than A, and F is a non-negative integer, and when the end of the second image is row B, the control unit sets rows (A + T + 1) to (B - F) in the display unit to the second refresh rate.

6. The display device according to claim 4, wherein 0 ≤ T ≤ m-1.

7. The display device according to claim 5, wherein 0 ≤ F ≤ m-1.

8. The display device according to claim 5, wherein the pulse of the first clock signal is output to each of the (A+T+1) row and the (B-F+1) row.

9. The display device according to claim 5, wherein the shift register outputs pulses of the m clock signal to the (A+T) row and the (B-F) row, respectively.

10. The display device according to claim 5, wherein the control unit displays a third image adjacent to the second image with a higher frequency than the second image, and when the start of the third image is the (B+1) row, the (B+1-F) row in the display unit is set to a third refresh rate higher than the second refresh rate.

11. The display device according to claim 5, wherein in the pulse patterns of the first to m clock signals, the portions corresponding to rows (A+T+1) to (B-F) on the display unit are left blank.

12. The first to m clock signals have the same period. The display device according to any one of claims 2 to 9, wherein the phases of the first clock signal and the m clock signal are shifted by 1 / m period.

13. The display device according to claim 12, wherein the 1 / m period is equal to one horizontal scanning period.

14. The display unit includes a plurality of scan lines arranged in a first direction, The display device according to any one of claims 1 to 9, wherein the first and second images are displayed adjacent to each other in the first direction.

15. The display device according to any one of claims 1 to 9, wherein the control unit receives position information of the first and second images from an external source.

16. The display device according to any one of claims 1 to 9, wherein the control unit determines the position information of the first and second images from the temporal changes in the images.

17. The display device according to claim 16, wherein the control unit determines the temporal change by the data checksum for each unit region.

18. The display device according to any one of claims 1 to 9, wherein the control unit includes a timing controller and a level shifter circuit.

19. The display device according to claim 18, wherein the level shifter circuit generates a plurality of clock signals with a greater number of phases than the plurality of reference signals using a plurality of reference signals from the timing controller.

20. A control method for a display device comprising a display unit including multiple lines, a scanning driver that drives the display unit, and a control unit that controls the scanning driver, wherein multiple clock signals with different phases are input to the scanning driver, A control method for a display device, in which, when displaying a first image and a second image with a lower frequency than the first image adjacent to each other, the refresh rate switching position is set according to the phase of the data of the first image, the data of the second image, and the phase of the plurality of clock signals.

Images