Fractional-N type PLL circuit

Abstract

This invention provides a fractional-N type PLL circuit that can reduce spurious emissions while reducing the circuit size. [Solution] The fractional-N type PLL circuit 2 comprises a phase comparator 18, a voltage-controlled oscillator 24 that outputs an output clock signal having a frequency corresponding to the control voltage from the phase comparator 18, a multimodulus frequency divider 28 that generates a divided clock signal by dividing the output clock signal, a delta-sigma modulator 30 that varies the division ratio of the multimodulus frequency divider 28, an oversample clock generation circuit 10 that generates a pseudo-reference clock signal, and a fractional spurious correction circuit 6 and a reference spurious correction circuit 8 that generate a fractional spurious correction signal and a reference spurious correction signal, respectively, based on the pseudo-reference clock signal.

Description

[Technical Field]

[0001] This invention relates to a fractional-N type PLL circuit. [Background technology]

[0002] A fractional-N type PLL (Phase Locked Loop) circuit is known that can set the frequency of the output clock signal with fine resolution. This fractional-N type PLL circuit comprises a phase comparator that detects the phase difference between a reference clock signal and a feedback clock signal and outputs a control voltage corresponding to the detected phase difference, a voltage-controlled oscillator that outputs an output clock signal having a frequency corresponding to the control voltage, a frequency divider that generates a divided clock signal by dividing the output clock signal and inputs the generated divided clock signal to the phase comparator as a feedback clock signal, and a delta-sigma modulator that varies the division ratio of the frequency divider. In this fractional-N type PLL circuit, the delta-sigma modulator periodically varies the division ratio of the frequency divider, thereby achieving an average division ratio of "integer + decimal".

[0003] In the fractional-N type PLL circuit described above, spurious signals (i.e., unwanted signals other than the required output clock signal) are generated in the output clock signal due to fluctuations in the frequency division ratio caused by the delta-sigma modulator. To reduce such spurious signals, a DTC (Digital-to-Time Converter) based correction technique has been proposed (see, for example, Non-Patent Documents 1 and 2). In this DTC-based correction technique, spurious signals are reduced by adding fluctuations in the frequency division ratio caused by the delta-sigma modulator via a delay circuit to the signal path in which the reference clock signal is input to the phase comparator. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] S.Levantino,et ai.,IEEE JSSC,vol.49,no.8,pp.1762-1772,Aug 2014. [Non-Patent Document 2] W. Wu,et ai.,IEEE JSSC,vol.54,no.5,pp.1254-1265,May 2019. [Overview of the project] [Problems that the invention aims to solve]

[0005] However, the conventional DTC-based correction technology described above requires linearity correction of the delay characteristics of the delay circuit and background correction to prevent delay fluctuations due to environmental changes, which results in the problem of requiring a large circuit size.

[0006] The present invention aims to solve the above-mentioned problems, and its objective is to provide a fractional-N type PLL circuit that can reduce spurious emissions while reducing the circuit size. [Means for solving the problem]

[0007] To achieve the above objective, a fractional-N type PLL circuit according to one aspect of the present invention is a fractional-N type PLL (Phase Locked Loop) circuit comprising: a first phase comparator that detects the phase difference between a reference clock signal and a feedback clock signal and outputs a control voltage corresponding to the detected phase difference; a voltage-controlled oscillator that generates an output clock signal having a frequency corresponding to the control voltage and outputs the generated output clock signal; a frequency divider that generates a divided clock signal by dividing the output clock signal and inputs the generated divided clock signal to the first phase comparator as the feedback clock signal; a delta-sigma modulator that varies the division ratio of the frequency divider; and a frequency equal to the frequency of the reference clock signal based on the reference clock signal and the output clock signal. The system comprises: a generation unit that generates a pseudo-reference clock signal which has a phase and is synchronized with the phase of the output clock signal; (i) a first correction signal for reducing fractional spurious emissions caused by fluctuations in the phase of the output clock signal with respect to the phase of the reference clock signal, and a second correction signal for reducing reference spurious emissions caused by fluctuations in the phase of the frequency-divided clock signal by the delta-sigma modulator, based on the pseudo-reference clock signal; and (ii) a correction circuit that adds at least one of the generated first correction signal and the second correction signal onto the signal path between the first phase comparator and the voltage-controlled oscillator. [Effects of the Invention]

[0008] According to one aspect of the present invention, a fractional-N type PLL circuit can reduce spurious emissions while reducing the circuit size. [Brief explanation of the drawing]

[0009] [Figure 1A] This figure shows the overall configuration of a fractional-N type PLL circuit according to the embodiment. [Figure 1B] This figure shows the configuration of the oversample clock generation circuit of the fractional-N type PLL circuit according to the embodiment. [Figure 1C]It is a diagram showing the configuration of the lock detector of the fractional-N type PLL circuit according to the embodiment. [Figure 2] It is a diagram showing the circuit configuration of the charge pump in FIG. 1A. [Figure 3] It is a diagram showing the circuit configuration of the loop filter in FIG. 1A. [Figure 4] It is a diagram showing the circuit configuration of the oversampling clock generation circuit in FIG. 1B. [Figure 5] It is a diagram showing the circuit configuration of the lock detector in FIG. 1C. [Figure 6] It is a diagram for explaining the operation of the lock detector in FIG. 1C. [Figure 7] It is a diagram showing the circuit configuration of the lock detector in FIG. 1C. [Figure 8] It is a diagram for explaining the cause of fractional spurious generation. [Figure 9A] It is a diagram showing the configuration of the first correction circuit of the fractional spurious correction circuit. [Figure 9B] It is a diagram showing the configuration of the second correction circuit of the fractional spurious correction circuit. [Figure 9C] It is a diagram showing the configuration of the slope bias generation circuit of the fractional spurious correction circuit. [Figure 9D] It is a diagram showing the configuration of the CP gain equalizer of the fractional spurious correction circuit. [Figure 9E] It is a diagram showing the configuration of the delay circuit of the fractional spurious correction circuit. [Figure 10] It is a diagram showing the circuit configuration of the delay circuit in FIG. 9A. [Figure 11] It is a diagram showing the circuit configuration of the slope bias generation circuit in FIG. 9C. [Figure 12] It is a diagram showing the circuit configuration of the charge pump in FIG. 9B. [Figure 13] It is a diagram showing the circuit configuration of the CP gain equalizer in FIG. 9D. [Figure 14] It is a diagram showing the configuration of the reference spurious correction circuit. [Figure 15]This graph shows the results of Simulation Experiment 1. [Figure 16] This graph shows the results of Simulation Experiment 2. [Modes for carrying out the invention]

[0010] (Technology 1) A fractional-N type PLL (Phase Locked Loop) circuit comprising: a first phase comparator that detects the phase difference between a reference clock signal and a feedback clock signal and outputs a control voltage corresponding to the detected phase difference; a voltage-controlled oscillator that generates an output clock signal having a frequency corresponding to the control voltage and outputs the generated output clock signal; a frequency divider that generates a divided clock signal by dividing the output clock signal and inputs the generated divided clock signal to the first phase comparator as the feedback clock signal; a delta-sigma modulator that varies the division ratio of the frequency divider; and a frequency that is the same as the frequency of the reference clock signal and the output clock signal, and output A fractional-N type PLL circuit comprising: a generation unit that generates a pseudo-reference clock signal synchronized with the phase of a clock signal; (i) generating at least one of a first correction signal for reducing fractional spurious emissions caused by fluctuations in the phase of the output clock signal relative to the phase of the reference clock signal, and a second correction signal for reducing reference spurious emissions caused by fluctuations in the phase of the frequency-divided clock signal by the delta-sigma modulator, based on the pseudo-reference clock signal; and (ii) a correction circuit that adds at least one of the generated first correction signal and the second correction signal onto the signal path between the first phase comparator and the voltage-controlled oscillator.

[0011] According to Technique 1, the correction circuit generates at least one of a first correction signal for reducing fractional spurious emissions and a second correction signal for reducing reference spurious emissions by using a pseudo-reference clock signal. The correction circuit then adds at least one of the generated first and second correction signals onto the signal path between the first phase comparator and the voltage-controlled oscillator. This analog signal processing makes it possible to reduce at least one of fractional spurious emissions and reference spurious emissions while reducing the circuit size.

[0012] (Technology 2) The generation unit generates the pseudo-reference clock signal by oversampling the reference clock signal with the output clock signal, as described in Technical 1, for the fractional-N type PLL circuit.

[0013] According to Technique 2, a pseudo-reference clock signal can be easily generated by oversampling.

[0014] (Technology 3) The fractional-N type PLL circuit according to Technology 1 or 2, wherein the first phase comparator outputs an up signal and a down signal corresponding to the detected phase difference as the control voltage, and the fractional-N type PLL circuit further comprises a first charge pump that receives the up signal and the down signal from the first phase comparator and outputs a current signal corresponding to the up signal and the down signal, and a loop filter that converts the current signal from the first charge pump into a voltage signal, generates a frequency control voltage by smoothing the voltage signal, and outputs the generated frequency control voltage to the voltage control oscillator, and the correction circuit adds at least one of the generated first correction signal and the second correction signal onto the signal path between the first charge pump and the loop filter.

[0015] According to Technique 3, the correction circuit adds at least one of the first correction signal and the second correction signal as a current signal to the signal path between the first charge pump and the loop filter. This analog signal processing can reduce at least one of fractional spurious signals and reference spurious signals while reducing the circuit size.

[0016] (Technology 4) The correction circuit includes a fractional spurious correction circuit that generates the first correction signal, the fractional spurious correction circuit includes a delay circuit that delays the reference clock signal with a feedback signal, a second phase comparator that detects the phase difference between the reference clock signal delayed by the delay circuit and the pseudo-reference clock signal and outputs an up signal and a down signal corresponding to the detected phase difference, a second charge pump that receives the up signal and the down signal from the second phase comparator and outputs a current signal corresponding to the up signal and the down signal, and generates a filter voltage signal to balance the up signal and the down signal from the second phase comparator based on the current signal from the second charge pump. A fractional-N type PLL circuit according to Technology 3, comprising: a filter circuit that inputs the generated filter voltage signal to the delay circuit as a feedback signal; a slope bias generation circuit that generates a bias signal having a sawtooth waveform corresponding to the time change of the up signal and the down signal based on the filter voltage signal; a third phase comparator that detects the phase difference between the pseudo-reference clock signal and the pseudo-reference clock signal delayed using the bias signal and outputs an up signal and a down signal corresponding to the detected phase difference; and a third charge pump that receives the up signal and the down signal from the third phase comparator in reverse and generates the first correction signal, which is a current signal corresponding to the up signal and the down signal.

[0017] According to Technology 4, fractional spurious emissions can be reduced while reducing the circuit size by analog signal processing, which involves subtracting the first correction signal from the current signal from the first charge pump.

[0018] (Technology 5) The fractional-N type PLL circuit according to Art 3, wherein the correction circuit includes a reference spurious correction circuit that generates the second correction signal, the reference spurious correction circuit includes a fourth phase comparator that detects the phase difference between the pseudo-reference clock signal and the feedback clock signal and outputs an up signal and a down signal corresponding to the detected phase difference, and a fourth charge pump that receives the up signal and the down signal from the fourth phase comparator in reverse and generates the second correction signal, which is a current signal corresponding to the up signal and the down signal.

[0019] According to Technology 5, by analog signal processing that subtracts the second correction signal from the current signal from the first charge pump, the reference spurious signal can be reduced while reducing the circuit size.

[0020] Embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement positions of components, and connection configurations shown in the following embodiments are examples only and are not intended to limit the present invention. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components.

[0021] (Embodiment) [1. Overall Configuration of Fractional-N Type PLL Circuit] First, the overall configuration of the fractional-N type PLL circuit 2 according to the embodiment will be described with reference to Figures 1A to 7. Figure 1A is a diagram showing the overall configuration of the fractional-N type PLL circuit 2 according to the embodiment. Figure 1B is a diagram showing the configuration of the oversample clock generation circuit 10 of the fractional-N type PLL circuit 2 according to the embodiment. Figure 1C is a diagram showing the configuration of the lock detector 12 of the fractional-N type PLL circuit 2 according to the embodiment. Figure 2 is a diagram showing the circuit configuration of the charge pump 20 in Figure 1A. Figure 3 is a diagram showing the circuit configuration of the loop filter 22 in Figure 1A. Figure 4 is a diagram showing the circuit configuration of the oversample clock generation circuit 10 in Figure 1B. Figure 5 is a diagram showing the circuit configuration of the lock detector 12 in Figure 1C. Figure 6 is a diagram for explaining the operation of the lock detector 12 in Figure 1C. Figure 7 is a diagram showing the circuit configuration of the lock detector 12 in Figure 1C.

[0022] As shown in Figures 1A to 1C, the fractional-N type PLL circuit 2 comprises a PLL circuit section 4, a fractional spurious correction circuit 6 (an example of a correction circuit), a reference spurious correction circuit 8 (an example of a correction circuit), an oversample clock generation circuit 10 (an example of a generation section), and a lock detector 12.

[0023] The PLL circuit section 4 includes a delay circuit 14, a delay circuit 16, a phase comparator (PFD) 18 (an example of a first phase comparator), a charge pump (CP) 20 (an example of a first charge pump), a loop filter (LF) 22, a voltage-controlled oscillator (VCO) 24, a 1 / 2 frequency divider (DIV) 26, a multi-modulous divider (MMD) 28 (an example of a frequency divider), and a delta-sigma (ΔΣ) modulator 30.

[0024] The delay circuit 14 is a circuit for delaying a reference clock signal (Refclk) having a reference frequency. The delay circuit 14 includes a buffer 32 and a voltage-controlled delay line (VCDL) 34. The delay circuit 14 achieves a fixed delay using 1.5 periods of the operating clock of the multimodulus frequency divider 28 and a fixed voltage (Vx') applied to the voltage-controlled delay line 34. The reference clock signal is output from, for example, an external crystal oscillator (not shown).

[0025] The delay circuit 16 is a circuit for delaying the feedback clock signal (Fbclk) from the multimodulus frequency divider 28. The delay circuit 16 includes a buffer 36 and a voltage-controlled delay line 38. The delay circuit 16 achieves a fixed delay by using 1.5 periods of the operating clock of the multimodulus frequency divider 28 and a fixed voltage (Vx') applied to the voltage-controlled delay line 38.

[0026] In this embodiment, the PLL circuit section 4 is provided with delay circuits 14 and 16, but it is not limited to this, and these delay circuits 14 and 16 may be omitted.

[0027] The phase comparator 18 receives a reference clock signal (Refclkin) from the delay circuit 14 and a feedback clock signal (Fbclkin) from the delay circuit 16 as inputs. The phase comparator 18 detects the phase difference (and frequency difference) between the input reference clock signal and the feedback clock signal, and outputs an up signal (UP) and a down signal (DOWN) corresponding to the detected phase difference (and frequency difference) as control voltages to the charge pump 20. If the phase of the feedback clock signal lags behind the phase of the reference clock signal, the phase comparator 18 outputs an up signal to the charge pump 20. On the other hand, if the phase of the feedback clock signal leads the phase of the reference clock signal, the phase comparator 18 outputs a down signal to the charge pump 20.

[0028] The charge pump 20 has an up signal input terminal 40 and a down signal input terminal 42. The up signal and down signal from the phase comparator 18 are input to the up signal input terminal 40 and the down signal input terminal 42 of the charge pump 20, respectively. The charge pump 20 outputs a current signal to the loop filter 22 corresponding to the input up signal and down signal. Specifically, when an up signal is input to the up signal input terminal 40, the charge pump 20 flows current into the loop filter 22. On the other hand, when a down signal is input to the down signal input terminal 42, the charge pump 20 withdraws current from the loop filter 22. The charge pump 20 has a circuit configuration as shown in Figure 2, for example.

[0029] The loop filter 22 converts the current signal from the charge pump 20 into a voltage signal and generates a frequency control voltage by smoothing the converted voltage signal. The loop filter 22 outputs the generated frequency control voltage to the voltage control oscillator 24. The loop filter 22 has a circuit configuration, for example, as shown in Figure 3, and the filter voltage value V LF0 This is output externally using a voltage follower.

[0030] The voltage-controlled oscillator 24 generates an output clock signal (CLKO) having a frequency corresponding to the frequency control voltage from the loop filter 22 (i.e., corresponding to the control voltage from the phase comparator 18). The voltage-controlled oscillator 24 outputs the generated output clock signal to the outside as a PLL output.

[0031] The 1 / 2 frequency divider 26 divides the output clock signal output from the voltage-controlled oscillator 24 by 2. The 1 / 2 frequency divider 26 outputs the divided output clock signal as a divided clock signal (DCLK) to the multimodulus frequency divider 28. In this embodiment, the fractional-N type PLL circuit 2 is equipped with a 1 / 2 frequency divider 26, but it is not limited to this, and the 1 / 2 frequency divider 26 may be omitted.

[0032] The multimodulus frequency divider 28 generates a divided clock signal by dividing the divided clock signal from the 1 / 2 frequency divider 26 (i.e., the output clock signal from the voltage-controlled oscillator 24) by the division ratio set by the delta-sigma modulator 30. The multimodulus frequency divider 28 inputs the generated divided clock signal to the phase comparator 18 via the delay circuit 16 as a feedback clock signal. The multimodulus frequency divider 28 also inputs the generated divided clock signal to the delta-sigma modulator 30 as a feedback clock signal.

[0033] The delta-sigma modulator 30 varies the division ratio of the multimodulus divider 28 based on a frequency control word (FCW) for setting the division ratio of the output clock signal relative to the reference clock signal and the feedback clock signal. Specifically, the delta-sigma modulator 30 switches the division ratio of the multimodulus divider 28 based on the frequency control word, for example, between an integer N and an integer N+1, according to the ratio set based on the frequency control word.

[0034] In the PLL circuit section 4 described above, a feedback loop is formed by the voltage-controlled oscillator 24, 1 / 2 frequency divider 26, multimodulus frequency divider 28, phase comparator 18, charge pump 20, and loop filter 22. This feedback loop provides feedback until the frequency of the feedback clock signal output from the multimodulus frequency divider 28 matches the frequency of the reference clock signal. This matching of the frequency of the feedback clock signal and the frequency of the reference clock signal is called "locking".

[0035] Furthermore, in the PLL circuit section 4, the delta-sigma modulator 30 switches the division ratio of the multimodulus frequency divider 28 between, for example, an integer N and an integer N+1. This outputs a signal with a period between the output clock signal obtained by dividing the frequency of the reference clock signal by an integer N and the output clock signal obtained by dividing the frequency of the reference clock signal by an integer N+1. As a result, on average, an output clock signal obtained by dividing the frequency of the reference clock signal by an integer + decimal (for example, 3.5) between an integer N (for example, "3") and an integer N+1 (for example, "4") can be output as the PLL output. In other words, when the frequency is locked, the frequency of the output clock signal output from the voltage-controlled oscillator 24 will match the frequency of the reference clock signal multiplied by the division ratio.

[0036] The fractional spurious correction circuit 6 generates a fractional spurious correction signal (F) based on the pseudo-reference clock signal (Refclk_d) (described later) to reduce the modulation component called fractional spurious. spur The circuit generates a CTL (Clock Timer) (an example of a first correction signal). Fractional spurious signals are spurious signals caused by fluctuations in the phase of the output clock signal relative to the phase of the reference clock signal. The fractional spurious correction circuit 6 adds the generated fractional spurious correction signal to the analog signal path between the charge pump 20 and the loop filter 22 (i.e., the signal path between the phase comparator 18 and the voltage-controlled oscillator 24).

[0037] At this point, the timing difference between the reference clock signal and the pseudo-reference clock signal results in fractional spurious emissions. Therefore, the fractional spurious emission correction circuit 6 detects the timing difference between the reference clock signal and the pseudo-reference clock signal and generates a fractional spurious emission correction signal based on the detection result. The fractional spurious emission correction circuit 6 then superimposes the generated fractional spurious emission correction signal onto the current signal from the charge pump 20, thereby canceling the modulation component of the fractional spurious emissions.

[0038] The reference spurious correction circuit 8 generates a reference spurious correction signal (R) based on the pseudo-reference clock signal to reduce the modulation component called the reference spurious signal. spur The circuit generates a CTL (an example of a second correction signal). The reference spurious signal refers to a spurious signal caused by a phase variation in the feedback clock signal (divided clock signal) from the delta-sigma modulator 30. The reference spurious correction circuit 8 adds the generated reference spurious correction signal to the analog signal path between the charge pump 20 and the loop filter 22 (i.e., the signal path between the phase comparator 18 and the voltage-controlled oscillator 24).

[0039] More specifically, the reference spurious correction circuit 8 generates a pseudo-phase comparison signal between the pseudo-reference clock signal and the feedback clock signal as the reference spurious correction signal. The reference spurious correction circuit 8 then cancels the modulation component of the reference spurious signal by subtracting the generated pseudo-phase comparison signal from the actual phase comparison signal between the reference clock signal and the feedback clock signal.

[0040] As shown in Figure 1B, the oversample clock generation circuit 10 generates a pseudo-reference clock signal based on the reference clock signal and the divided clock signal (output clock signal). The pseudo-reference clock signal has the same frequency as the reference clock signal and is synchronized with the phase of the divided clock signal (output clock signal). In other words, the pseudo-reference clock signal is a pseudo-reference clock signal that has rising and falling edge timings close to those of the reference clock signal. The oversample clock generation circuit 10 outputs the generated pseudo-reference clock signal to the fractional spurious correction circuit 6 and the reference spurious correction circuit 8.

[0041] More specifically, the oversampled clock generation circuit 10 generates a pseudo-reference clock signal by oversampling the reference clock signal with a divided clock signal (output clock signal). The oversampled clock generation circuit 10 has a circuit configuration, for example, as shown in Figure 4, and is configured to suppress delay fluctuations due to metastable that may occur when the edges of both the reference clock signal and the feedback clock signal (output clock signal) are close together, by connecting two D flip-flops in stages.

[0042] In the example shown in Figure 4, the oversampled clock generation circuit 10 generates a pseudo-reference clock signal using a divided clock signal obtained by dividing the output clock signal by half. However, if the multimodulus divider 28 operates directly with the output clock signal, the pseudo-reference clock signal may be generated using the output clock signal. In this case, a pseudo-reference clock signal closer to the timing of the reference clock signal can be generated, and the noise level of fractional spurious signals that need to be corrected can be suppressed more effectively.

[0043] In this embodiment, the oversampled clock generation circuit 10 generates a pseudo-reference clock signal by oversampling the reference clock signal with a divided clock signal (output clock signal), but is not limited to this. The pseudo-reference clock signal may also be generated, for example, by performing a logic operation by a logic circuit on the reference clock signal. In this case, the pseudo-reference clock signal is generated to be a signal synchronized with the reference clock signal.

[0044] As shown in Figure 1C, the lock detector 12 detects whether the frequency is locked in the PLL circuit 4 based on the reference clock signal and the feedback clock signal.

[0045] As shown in Figure 5, the lock detector 12 includes a circuit that divides the reference clock signal by 2 and a circuit that divides the feedback clock signal by 2. Here, a two-phase divided-by-2 signal is used as the divided-by-2 signal of the feedback clock signal, which is generated by connecting two D-Latches. At this time, the timing charts for (a) the reference clock signal (Refclk), (b) the divided-by-2 signal of the reference clock signal (Refclk / 2), (c) the feedback clock signal (Fbclk), (d) the divided-by-2 signal of the first phase feedback clock signal (Fbclk-A / 2), and (e) the divided-by-2 signal of the second phase feedback clock signal (Fbclk-B / 2) are as shown in Figures 6(a) to (e), respectively.

[0046] Furthermore, the lock detector 12 has a circuit configuration as shown in Figure 7, for example. The lock detector 12 determines that the frequencies of the reference clock signal and the feedback clock signal are separated by a certain amount if each edge of the 1 / 2 divided signals of the two phases of the feedback clock signal (Fbclk-A / 2, Fbclk-B / 2) is detected with respect to the 1 / 2 divided signal of the reference clock signal (Refclk / 2) within a predetermined period. In this case, the frequency is unlocked in the PLL circuit 4, and the lock detector 12 does not detect that the frequency is locked in the PLL circuit 4.

[0047] On the other hand, the lock detector 12 determines that the difference between the frequencies of the reference clock signal and the feedback clock signal is within a certain range if, with respect to the 1 / 2 divided signal of the reference clock signal (Refclk / 2), the edges of the 1 / 2 divided signals of the two-phase feedback clock signals (Fbclk-A / 2, Fbclk-B / 2) are not detected for a predetermined period of time. In this case, the lock detector 12 detects that the frequency has been locked in the PLL circuit section 4 and issues a lock detection signal (LD sig The output is sent to the fractional spurious correction circuit 6 and the reference spurious correction circuit 8.

[0048] [2. Overall Operation of Fractional-N Type PLL Circuit] Next, the overall operation of the fractional-N type PLL circuit 2 according to the embodiment will be described. In the fractional-N type PLL circuit 2, (i) first, the frequency tracking mode is performed, and (ii) then the phase tracking mode is performed.

[0049] In frequency tracking mode, the feedback loop in the PLL circuit section 4 locks the frequency so that the frequency of the feedback clock signal matches the frequency of the reference clock signal.

[0050] In phase tracking mode, the fractional spurious correction signal generated by the fractional spurious correction circuit 6 and the reference spurious correction signal generated by the reference spurious correction circuit 8 are added to the analog signal path between the charge pump 20 and the loop filter 22. This suppresses the fractional spurious and reference spurious signals that occur in phase tracking mode.

[0051] Note that the fractional spurious correction circuit 6 and the reference spurious correction circuit 8 do not necessarily need to be operated together; they may be operated individually.

[0052] The configurations of the fractional spurious correction circuit 6 and the reference spurious correction circuit 8 will be described in detail below.

[0053] [3. Configuration of the Fractional Spurious Emission Correction Circuit] The configuration of the fractional spurious correction circuit 6 will be explained with reference to Figures 8 to 13.

[0054] Figure 8 is a diagram illustrating the factors that cause fractional spurious emissions. Figure 9A shows the configuration of the first correction circuit 44 of the fractional spurious emission correction circuit 6. Figure 9B shows the configuration of the second correction circuit 46 of the fractional spurious emission correction circuit 6. Figure 9C shows the configuration of the slope bias generation circuit 48 of the fractional spurious emission correction circuit 6. Figure 9D shows the configuration of the CP gain equalizer 50 of the fractional spurious emission correction circuit 6. Figure 9E shows the configuration of the delay circuit 52 of the fractional spurious emission correction circuit 6. Figure 10 shows the circuit configuration of the delay circuit 54 in Figure 9A. Figure 11 shows the circuit configuration of the slope bias generation circuit 48 in Figure 9C. Figure 12 shows the circuit configuration of the charge pump 72 in Figure 9B. Figure 13 shows the circuit configuration of the CP gain equalizer 50 in Figure 9D.

[0055] First, we will explain the factors that cause fractional spurious signals, referring to Figure 8. In the fractional-N type PLL circuit 2, the frequency of the output clock signal is locked at an integer + decimal multiple of the frequency of the reference clock signal. Therefore, as shown in Figures 8(a) to (d), the rising edge timing of the output clock signal changes relative to the rising edge timing of the reference clock signal as time progresses. Specifically, the rising edge timing of the output clock signal changes as time t approaches t. n ,t n+1 ,t n+2 ,t n+3 As it changes, it repeatedly changes in the order of "Figure 8(b) ⇒ Figure 8(c) ⇒ Figure 8(d) ⇒ Figure 8(b) ⇒...".

[0056] As a result, as shown in Figures 8(b) and 8(c), if the phase of the output clock signal lags behind the reference clock signal, an extra up signal is output from the phase comparator 18. On the other hand, as shown in Figure 8(d), if the phase of the output clock signal leads the reference clock signal, an extra down signal is output from the phase comparator 18.

[0057] Therefore, for example, when the reference clock signal is captured at the rising timing of the output clock signal by the oversampling clock generation circuit 10, the rising edge of the pseudo-reference clock signal changes as shown in (e) of FIG. 8 over time. As a result, a variation in the timing difference occurs between the reference clock signal and the pseudo-reference clock signal, and this variation in the timing difference becomes a cause of the generation of fractional spurs.

[0058] As shown in FIGS. 9A to 9E, the fractional spur correction circuit 6 includes a first correction circuit 44, a second correction circuit 46, a slope bias generation circuit 48, a CP gain equalizer 50, and a delay circuit 52.

[0059] As shown in FIG. 9A, the first correction circuit 44 includes a delay circuit 54, a phase comparator 56 (an example of a second phase comparator), a charge pump 58 (an example of a second charge pump), and a filter circuit 60.

[0060] The delay circuit 54 is a circuit for delaying the reference clock signal (Refclk) based on the feedback signal (R delay CTL) from the filter circuit 60. The delay circuit 54 has, for example, the circuit configuration shown in FIG. 10.

[0061] Note that since the pseudo-reference clock signal generated by capturing with a D flip-flop is delayed in timing due to the output delay of the D flip-flop or the like, the delay value of the delay circuit 54 is adjusted by the feedback signal so that the reference clock signal and the pseudo-reference clock signal have the same average timing at the input time to the phase comparator 56.

[0062] The phase comparator 56 receives the reference clock signal from the delay circuit 54 and the pseudo-reference clock signal (Refclk_d) generated by the oversample clock generation circuit 10 (see Figure 1B) as inputs. The phase comparator 56 detects the phase difference between the input reference clock signal and the pseudo-reference clock signal and outputs an up signal (UP1) and a down signal (DOWN1) corresponding to the detected phase difference to the charge pump 58. If the phase of the pseudo-reference clock signal is lagging behind the reference clock signal, the phase comparator 56 outputs an up signal to the charge pump 58. On the other hand, if the phase of the pseudo-reference clock signal is leading the reference clock signal, the phase comparator 56 outputs a down signal to the charge pump 58.

[0063] The charge pump 58 has an up signal input terminal 62 and a down signal input terminal 64. Up signals and down signals from the phase comparator 56 are input to the up signal input terminal 62 and down signal input terminal 64 of the charge pump 58, respectively. The charge pump 58 outputs a current signal to the filter circuit 60 corresponding to the input up signal and down signal. Specifically, when an up signal is input to the up signal input terminal 62, the charge pump 58 flows current into the filter circuit 60. On the other hand, when a down signal is input to the down signal input terminal 64, the charge pump 58 withdraws current from the filter circuit 60.

[0064] The filter circuit 60 consists of a resistor R0 and a capacitor C0. The voltage value of the filter circuit 60 is a predetermined voltage value V x The feedback signal from the filter circuit 60 (R) is set to equal to delay The CTL signal is input to the delay circuit 54.

[0065] By keeping the voltage value of the filter circuit 60 constant in this way, the up and down signals from the phase comparator 56, which correspond to the timing difference between the reference clock signal and the pseudo-reference clock signal, are balanced (i.e., they are equal in timing on average), and delay control of the delay circuit 54 is realized. At this time, the filter circuit 60 controls the filter voltage signal (LF spur The output is sent to the slope bias generation circuit 48. As shown in Figure 9A, the output of the charge pump 58 is in a state where UP pulse groups and DOWN pulse groups are generated alternately. When delay control is achieved, the number and intensity of the pulses that make up the UP pulse group and the DOWN pulse group are in a state of balance.

[0066] As shown in Figure 9C, the slope bias generation circuit 48 receives the filter voltage signal (LF) from the first correction circuit 44. spur ), and a frequency control word (FCW) are input. The slope bias generation circuit 48 generates a bias signal (BIAS) having a sawtooth waveform corresponding to the time change of the up signal and down signal, based on the filter voltage signal. fspur The slope bias generation circuit 48 generates a bias signal. The slope bias generation circuit 48 outputs the generated bias signal to the second correction circuit 46.

[0067] The slope bias generation circuit 48 has a circuit configuration as shown in Figure 11, for example. As shown in Figure 11, the slope bias generation circuit 48 inputs the filter voltage signal to two comparators, respectively, and V x A signal greater than +ΔV is treated as an UP pulse, V x A signal smaller than -ΔV is detected as a DOWN pulse. These two UP pulses and DOWN pulses are input to a logic circuit (FSM: Finite State Machine), and the timing of the switching between the UP pulse group and the DOWN pulse group in Figure 9A is detected by the logic circuit, thereby generating a clock slip signal (SLP). sig ) generates capacitor C x Current I according to the frequency control word xWhile the current is being pulled out, the clock slip signal periodically sets the voltage to a constant level. As a result, the slope bias generation circuit 48 generates a sawtooth-like voltage that varies over time as a bias signal corresponding to the timing difference between the reference clock signal and the pseudo-reference clock signal.

[0068] As shown in Figure 9B, the second correction circuit 46 includes a delay circuit 66, a delay circuit 68, a phase comparator 70 (an example of a third phase comparator), a charge pump 72 (an example of a third charge pump), a filter circuit 74, a switch 76, and a switch 78.

[0069] The delay circuit 66 is a circuit that delays the pseudo-reference clock signal so that the up and down signals from the phase comparator 70 are balanced.

[0070] The delay circuit 68 is a circuit that delays the pseudo-reference clock signal using the bias signal from the slope bias generation circuit 48. When the bias signal from the slope bias generation circuit 48 is input to the delay circuit 68, a delay value corresponding to the phase difference between the reference clock signal and the pseudo-reference clock signal is generated.

[0071] The phase comparator 70 receives the pseudo-reference clock signal from the delay circuit 66 and the pseudo-reference clock signal from the delay circuit 68 as inputs. The phase comparator 70 detects the phase difference between the two input pseudo-reference clock signals and outputs an up signal (UP2) and a down signal (DOWN2) corresponding to the detected phase difference to the charge pump 72. At this time, the phase difference detected by the phase comparator 70 is a phase difference that corresponds to a fractional spurious signal.

[0072] The charge pump 72 has an up signal input terminal 80 and a down signal input terminal 82. The up signal input terminal 80 and the down signal input terminal 82 of the charge pump 72 receive the down signal and up signal from the phase comparator 70, respectively. In other words, the up signal and down signal from the phase comparator 70 are input to the charge pump 72 in reverse. The charge pump 72 generates a current signal corresponding to the input up signal and down signal. The charge pump 72 outputs the generated current signal to the filter circuit 74. Specifically, when an up signal is input to the down signal input terminal 82, the charge pump 72 flows current into the filter circuit 74. On the other hand, when a down signal is input to the up signal input terminal 80, the charge pump 72 withdraws current from the filter circuit 74. As a result, the charge pump 72 filters the current signal through the filter circuit 74 to correct the fractional spurious signal (F spur The output is sent to the PLL circuit section 4 (see Figure 1A) as CTL.

[0073] The charge pump 72 has a circuit configuration as shown in Figure 12, for example. The charge pump 72 increases the current signal using the CP gain control signal (CP gain CTL) from the CP gain equalizer 50. This makes it possible to achieve a current intensity that reduces fractional spurious emissions.

[0074] Switch 76 is a switch for switching between conduction and non-conductivity between the charge pump 72 and the PLL circuit section 4. Switch 78 is a switch for switching between the charge pump 72 and resistor R x These are switches for switching between conductivity and non-conductivity. Switches 76 and 78 are turned on and off based on the lock signal from the lock detector 12 (see Figure 1C).

[0075] Specifically, if the lock detector 12 does not output a lock signal (i.e., the frequency is not locked), switch 76 is turned off and switch 78 is turned on. In this case, the fractional spurious correction signal from the charge pump 72 is blocked by switch 76 and therefore not output to the PLL circuit 4.

[0076] On the other hand, when a lock signal is output from the lock detector 12 (i.e., when the frequency is locked), switch 76 is turned on and switch 78 is turned off. In this case, the fractional spurious correction signal from the charge pump 72 is output to the PLL circuit section 4 via switch 76.

[0077] As shown in Figure 9D, the CP gain equalizer 50 adjusts the strength of the current signal from the charge pump 72 to be equivalent to the current strength corresponding to the actual fractional spurious signal. The CP gain equalizer 50 has a circuit configuration, for example, as shown in Figure 13. As shown in Figure 13, the CP gain equalizer 50 performs feedback control so that the magnitude of the pulse currents from the up signal (UP1) and down signal (DOWN1), which correspond to the phase variation of the pseudo-reference clock signal with respect to the reference clock signal, is equal to the magnitude of the currents from the up signal (UP2) and down signal (DOWN2) generated by the delay difference of two delay circuits 66 and 68 from the pseudo-reference clock signal. The CP gain equalizer 50 then outputs a signal to adjust the current amount of the NMOS transistor so that they are at equal levels, as a CP gain control signal.

[0078] As shown in Figure 9E, the delay circuit 52 generates a delayed pseudo-reference block signal (Refclk_dd) by delaying the reference clock signal. The delay circuit 52 outputs the generated delayed pseudo-reference clock signal to the reference spurious correction circuit 8.

[0079] [4. Configuration of the reference spurious emission correction circuit] The configuration of the reference spurious correction circuit 8 will be explained with reference to Figure 14. Figure 14 is a diagram showing the configuration of the reference spurious correction circuit 8.

[0080] As shown in Figure 14, the reference spurious correction circuit 8 includes a phase comparator 84 (an example of a fourth phase comparator), a charge pump 86 (an example of a fourth charge pump), a switch 88, and a switch 90.

[0081] The phase comparator 84 receives a delayed pseudo-reference clock signal (Refclk_dd) from the delay circuit 52 (see Figure 9E) and a feedback clock signal (Fbclkin) from the delay circuit 16 of the PLL circuit section 4 (see Figure 1A). The phase comparator 84 detects the phase difference between the input delayed pseudo-reference clock signal and the feedback clock signal (i.e., the phase difference between the pseudo-reference clock signal and the feedback clock signal) and outputs an up signal (UP) and a down signal (DOWN) corresponding to the detected phase difference to the charge pump 86. This makes it possible to extract a phase comparison fluctuation signal due to delta-sigma modulation synchronized with the voltage-controlled oscillator 24 (see Figure 1A). If the phase of the feedback clock signal is lagging behind the phase of the delayed pseudo-reference clock signal, the phase comparator 84 outputs an up signal to the charge pump 86. On the other hand, if the phase of the feedback clock signal is leading the phase of the delayed pseudo-reference clock signal, the phase comparator 84 outputs a down signal to the charge pump 86.

[0082] The charge pump 86 has an up signal input terminal 92 and a down signal input terminal 94. The down signal and up signal from the phase comparator 84 are input to the up signal input terminal 92 and down signal input terminal 94 of the charge pump 86, respectively. In other words, the up signal and down signal from the phase comparator 84 are input to the charge pump 86 in reverse. The charge pump 86 outputs a current signal corresponding to the reference spurious signal, corresponding to the input up signal and down signal, as a reference spurious correction signal (R spur Output as CTL.

[0083] Switch 88 is a switch for switching between conduction and non-conductivity between the charge pump 86 and the PLL circuit section 4. Switch 90 connects the charge pump 86 to resistor R x These are switches for switching between conductivity and non-conductivity. Switches 88 and 90 are turned on and off based on the lock signal from the lock detector 12 (see Figure 1C).

[0084] Specifically, if no lock signal is output from the lock detector 12, switch 88 is turned off and switch 90 is turned on. In this case, the reference spurious correction signal from the charge pump 86 is blocked by switch 88 and therefore not output to the PLL circuit 4.

[0085] On the other hand, when a lock signal is output from the lock detector 12, switch 88 is turned on and switch 90 is turned off. In this case, the reference spurious correction signal from the charge pump 86 is output to the PLL circuit section 4 via switch 88.

[0086] [5. Effects] In this embodiment, the fractional spurious correction circuit 6 and the reference spurious correction circuit 8 each generate a fractional spurious correction signal to reduce fractional spurious emissions and a reference spurious correction signal to reduce reference spurious emissions by using a pseudo-reference clock signal. The fractional spurious correction circuit 6 and the reference spurious correction circuit 8 then add the generated fractional spurious correction signal and reference spurious correction signal to the analog signal path between the charge pump 20 and the loop filter 22.

[0087] As a result, by analog signal processing that subtracts the fractional spurious correction signal and the reference spurious correction signal from the current signal output from the charge pump 20, it is possible to reduce fractional spurious emissions and reference spurious emissions while reducing the circuit size compared to the DTC-based correction technology using digital signal processing described in the background technology section.

[0088] [6. Experiment] [6-1. Simulation Experiment 1] To confirm the effect of the fractional-N type PLL circuit 2 according to the embodiment on reducing reference spurious emissions, the following simulation experiment 1 was conducted.

[0089] As Comparative Example 1, using a Matlab / Simulink(registered trademark) operational model simulation, the output clock signal frequency was locked to 2.5125 GHz in the PLL circuit section 4 shown in Figure 1A, and then the power spectrum of the output clock signal was analyzed. In Comparative Example 1, neither the fractional spurious correction circuit 6 nor the reference spurious correction circuit 8 was operated.

[0090] In Example 1, using a Matlab / Simulink operational model simulation, the frequency of the output clock signal in the PLL circuit section 4 shown in Figure 1A was locked to 2.5125 GHz, and then the reference spurious correction circuit 8 was activated. In this state, the power spectrum of the output clock signal was analyzed. In Example 1, the fractional spurious correction circuit 6 was not activated.

[0091] The results of Simulation Experiment 1 are shown in Figure 15. Figure 15 is a graph showing the results of Simulation Experiment 1. Figure 15(a) is a graph showing the experimental results of Comparative Example 1, and Figure 15(b) is a graph showing the experimental results of Example 1. In the graphs of Figure 15(a) and (b), the horizontal axis represents frequency (Hz) and the vertical axis represents power (dBc).

[0092] In Comparative Example 1, as shown in Figure 15(a), the reference spurious signal was -79.9 dB. Furthermore, a significant noise floor (area enclosed by dashed lines) associated with delta-sigma modulation was observed on both sides of the frequency peak.

[0093] On the other hand, in Example 1, as shown in Figure 15(b), the reference spurious emission was -102.4 dB, which was significantly reduced compared to Comparative Example 1. In addition, the noise floor (area enclosed by dashed lines) associated with delta-sigma modulation on both sides of the frequency peak was significantly reduced compared to Comparative Example 1.

[0094] [6-2. Simulation Experiment 2] To confirm the effect of the fractional-N type PLL circuit 2 according to the embodiment in reducing fractional spurious emissions, the following simulation experiment 2 was conducted.

[0095] As Comparative Example 2, using a Matlab / Simulink operation model simulation, the frequency of the output clock signal in the PLL circuit section 4 shown in Figure 1A was locked to 2.5125 GHz, and then the reference spurious correction circuit 8 was activated. In this state, the power spectrum of the output clock signal was analyzed. In Comparative Example 2, the fractional spurious correction circuit 6 was not activated.

[0096] In Example 2, using a Matlab / Simulink operational model simulation, the frequency of the output clock signal in the PLL circuit section 4 shown in Figure 1A was locked to 2.5125 GHz, and then the reference spurious correction circuit 8 and the fractional spurious correction circuit 6 were operated simultaneously. In this state, the power spectrum of the output clock signal was analyzed.

[0097] The results of Simulation Experiment 2 are shown in Figure 16. Figure 16 is a graph showing the results of Simulation Experiment 2. Figure 16(a) is a graph showing the experimental results of Comparative Example 2, and Figure 16(b) is a graph showing the experimental results of Example 2. In the graphs of Figure 16(a) and (b), the horizontal axis represents frequency (Hz) and the vertical axis represents power (dBc).

[0098] In Comparative Example 2, as shown in Figure 16(a), the fractional spurious emission (value at fractional frequency: 6.25 MHz) was -38.5 dB. Furthermore, significant fractional frequency harmonic components were generated on both sides of the frequency peak.

[0099] On the other hand, in Example 2, as shown in Figure 16(b), the reference spurious signal was -57.8 dB, which was significantly reduced compared to Comparative Example 2. In addition, the fractional frequency harmonic components on both sides of the frequency peak were reduced by approximately 10 dB to 20 dB compared to Comparative Example 2.

[0100] [6-3. Summary] From the results of the above simulation experiments 1 and 2, it was confirmed that the fractional-N type PLL circuit 2 according to the embodiment can achieve the effect of reducing both reference spurious and fractional spurious emissions.

[0101] (Variations, etc.) Although a fractional-N type PLL circuit according to an embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.

[0102] For example, in the above embodiment, the fractional-N type PLL circuit 2 is provided with both a fractional spurious correction circuit 6 and a reference spurious correction circuit 8, but it is not limited to this, and may be provided with only one of the fractional spurious correction circuit 6 and the reference spurious correction circuit 8. [Industrial applicability]

[0103] The fractional-N type PLL circuit according to the present invention can be installed in, for example, communication equipment that requires setting the frequency with fine resolution. [Explanation of Symbols]

[0104] 2. Fractional-N type PLL circuit 4 PLL circuit section 6. Fractional spurious emission correction circuit 8. Reference spurious emission correction circuit 10. Oversample Clock Generation Circuit 12 Lock detector 14,16,52,54,66,68 Delay Circuit 18,56,70,84 Phase comparator 20, 58, 72, 86 Charge pump 22 Loop Filters 24 Voltage-controlled oscillator 26 1 / 2 frequency divider 28 Multimodulus frequency divider 30 Delta-Sigma Modulator 32,36 buffers 34,38 Voltage-controlled delay lines 40, 62, 80, 92 Up-signal input terminals 42, 64, 82, 94 Down signal input terminals 44 First Correction Circuit 46. ​​Second Correction Circuit 48. Slope Bias Generation Circuit 50 CP Gain Equalizer 60,74 Filter Circuits 76, 78, 88, 90 switches

Claims

1. A fractional-N type PLL (Phase Locked Loop) circuit, A first phase comparator detects the phase difference between a reference clock signal and a feedback clock signal, and outputs a control voltage corresponding to the detected phase difference. A voltage-controlled oscillator that generates an output clock signal having a frequency corresponding to the control voltage and outputs the generated output clock signal, A frequency divider that generates a divided clock signal by dividing the output clock signal, and inputs the generated divided clock signal to the first phase comparator as the feedback clock signal, A delta-sigma modulator that varies the frequency division ratio of the frequency divider, A generation unit generates a pseudo-reference clock signal having the same frequency as the reference clock signal and synchronized with the phase of the output clock signal, based on the reference clock signal and the output clock signal. (i) A correction circuit that generates, based on the pseudo-reference clock signal, at least one of a first correction signal for reducing fractional spurious emissions caused by fluctuations in the phase of the output clock signal relative to the phase of the reference clock signal, and a second correction signal for reducing reference spurious emissions caused by fluctuations in the phase of the divided clock signal by the delta-sigma modulator; and (ii) adds at least one of the generated first correction signal and second correction signal onto the signal path between the first phase comparator and the voltage-controlled oscillator. Fractional-N type PLL circuit.

2. The generation unit generates the pseudo-reference clock signal by oversampling the reference clock signal with the output clock signal. The fractional-N type PLL circuit according to claim 1.

3. The first phase comparator outputs an up signal and a down signal corresponding to the detected phase difference as the control voltage. The aforementioned fractional-N type PLL circuit further comprises: A first charge pump receives the up signal and the down signal from the first phase comparator and outputs a current signal corresponding to the up signal and the down signal, The system includes a loop filter that converts the current signal from the first charge pump into a voltage signal, generates a frequency control voltage by smoothing the voltage signal, and outputs the generated frequency control voltage to the voltage control oscillator, The correction circuit adds at least one of the generated first correction signal and the second correction signal onto the signal path between the first charge pump and the loop filter. A fractional-N type PLL circuit according to claim 1 or 2.

4. The correction circuit includes a fractional spurious correction circuit that generates the first correction signal. The aforementioned fractional spurious correction circuit is A delay circuit that delays the reference clock signal using a feedback signal, A second phase comparator detects the phase difference between the reference clock signal delayed by the delay circuit and the pseudo-reference clock signal, and outputs an up signal and a down signal corresponding to the detected phase difference. A second charge pump receives the up signal and the down signal from the second phase comparator and outputs a current signal corresponding to the up signal and the down signal, A filter circuit that generates a filter voltage signal to balance the up signal and the down signal from the second phase comparator based on the current signal from the second charge pump, and inputs the generated filter voltage signal to the delay circuit as a feedback signal, A slope bias generation circuit generates a bias signal having a sawtooth waveform corresponding to the time variation of the up signal and the down signal based on the filter voltage signal, A third phase comparator detects the phase difference between the pseudo-reference clock signal and the pseudo-reference clock signal delayed using the bias signal, and outputs an up signal and a down signal corresponding to the detected phase difference. The system includes a third charge pump that receives the up signal and down signal from the third phase comparator in reverse and generates the first correction signal, which is a current signal corresponding to the up signal and down signal. The fractional-N type PLL circuit according to claim 3.

5. The correction circuit includes a reference spurious correction circuit that generates the second correction signal. The aforementioned reference spurious correction circuit is A fourth phase comparator detects the phase difference between the pseudo-reference clock signal and the feedback clock signal and outputs an up signal and a down signal corresponding to the detected phase difference. The system includes a fourth charge pump that receives the up signal and down signal from the fourth phase comparator in reverse and generates the second correction signal, which is a current signal corresponding to the up signal and down signal. The fractional-N type PLL circuit according to claim 3.

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