Radio frequency source circuit and method for generating laser frequency-shifted locked cavity signals

Abstract

The application provides a radio frequency source circuit and a laser frequency shift lock cavity signal generation method, which can be applied to the field of cold atom optical lattice clock technology. The radio frequency source circuit comprises a control sub-circuit, a phase-locked loop sub-circuit and an output power control sub-circuit. The control sub-circuit is used for receiving a digital control instruction from an upper computer and taking a synchronous clock as a working clock, performing amplitude-phase conversion and phase waveform conversion in parallel based on preset modulation data carried by the digital control instruction, and outputting a phase control word and a phase demodulation signal. The phase-locked loop sub-circuit is used for frequency multiplication of a reference clock and outputting a clock signal suitable for the working frequency of a frequency synthesizer as the working reference clock of the frequency synthesizer. The frequency synthesizer is used for taking the working reference clock as a frequency reference, realizing phase synchronization by combining the synchronous clock, and adjusting the phase of an output signal based on the phase control word. The output power control sub-circuit is used for adjusting the power of the output signal of the frequency synthesizer based on preset power modulation data to output a laser frequency shift lock cavity signal.

Description

Technical Field

[0001] This invention relates to the field of cold atom optical lattice clock technology, and in particular to a radio frequency source circuit and a method for generating laser frequency shift cavity-locked signals. Background Technology

[0002] Cold atom experiments rely on precise control of laser parameters, typically achieved through radio frequency (RF) signals to modulate the laser's frequency, phase, and amplitude. However, RF signal generation schemes based on Direct Digital Synthesis (DDS) still suffer from limitations such as restricted modulation rates, insufficient phase noise control, and limited modulation functionality, making it difficult to meet the complex experimental requirements of multi-stage, multi-parameter experiments in cold atom experiments, such as strontium atom optical lattice clocks. Summary of the Invention

[0003] In view of the above problems, the present invention provides an RF source circuit and a method for generating laser frequency-shifted cavity-locked signals.

[0004] According to a first aspect of the present invention, a radio frequency source circuit is provided, comprising: a control sub-circuit electrically connected to a host computer, the control sub-circuit being configured to receive digital control commands from the host computer, and using a synchronous clock as the operating clock, and based on preset modulation data carried by the digital control commands, to perform amplitude-phase conversion and phase waveform conversion in parallel, so as to output a phase control word and a phase demodulation signal; a phase-locked loop sub-circuit being configured to multiply a reference clock and output a clock signal adapted to the operating frequency of a frequency synthesizer, as the operating reference clock of the frequency synthesizer; a frequency synthesizer being electrically connected to the control sub-circuit and the phase-locked loop sub-circuit, the frequency synthesizer being configured to use the operating reference clock as a frequency reference, and in conjunction with the synchronous clock, to achieve phase synchronization with the control sub-circuit, and to adjust the phase of the output signal based on the phase control word; and an output power control sub-circuit being electrically connected to the output terminal of the frequency synthesizer, and being configured to adjust the power of the output signal of the frequency synthesizer based on preset power modulation data, so as to output a laser frequency-shifted cavity-locked signal, wherein the phase demodulation signal and the laser frequency-shifted cavity-locked signal are used to achieve laser frequency offset locking.

[0005] A second aspect of the present invention provides a method for generating a laser frequency-shift cavity-locked signal, using the aforementioned radio frequency source circuit, comprising: using a control sub-circuit to receive digital control commands from a host computer, and using a synchronous clock as the working clock, performing amplitude-phase conversion and phase waveform conversion in parallel based on preset modulation data carried by the digital control commands, to output a phase control word and a phase demodulation signal; using a phase-locked loop sub-circuit to multiply the reference clock and output a clock signal adapted to the working frequency of the frequency synthesizer, as the working reference clock of the frequency synthesizer; using the frequency synthesizer, using the working reference clock as a frequency reference, combining the synchronous clock to achieve phase synchronization with the control sub-circuit, and adjusting the phase of the output signal based on the phase control word; using an output power control sub-circuit to adjust the power of the output signal of the frequency synthesizer based on preset power modulation data, to output a laser frequency-shift cavity-locked signal, wherein the phase demodulation signal and the laser frequency-shift cavity-locked signal are used to achieve laser frequency offset locking.

[0006] According to the radio frequency source circuit and laser frequency-shifting cavity-locked signal generation method provided by the present invention, the control sub-circuit and the frequency synthesizer achieve synchronous timing based on a synchronous clock. The synchronous clock provided by the frequency synthesizer to the control sub-circuit enables the control sub-circuit to adjust the output signal of the frequency synthesizer based on the modulation rate of the synchronous clock, reducing the response delay of phase modulation and increasing the modulation rate. Since the generation of the phase control word and the phase demodulation signal are integrated into the same control sub-circuit, the optical path in the sideband PDH (Pound-Drever-Hall) frequency-locking experiment is simplified. Simultaneously, the control sub-circuit can perform amplitude-phase conversion and phase waveform conversion in parallel based on preset modulation data, ensuring that the phase control word and the phase demodulation signal originate from the same reference (i.e., the same preset modulation data), guaranteeing strict synchronization. Because a low-noise phase-locked loop sub-circuit is used in the radio frequency source circuit, the phase noise of the frequency synthesizer output signal is reduced. Furthermore, the control sub-circuit, frequency synthesizer, phase-locked loop sub-circuit, and output power control sub-circuit in the radio frequency source circuit are all integrated onto a single circuit board, improving integration density. Attached Figure Description

[0007] The above-mentioned contents, other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, which will be described in conjunction with the drawings.

[0008] Figure 1 A schematic diagram of the structure of a radio frequency source circuit according to an embodiment of the present invention is shown.

[0009] Figure 2 A schematic diagram of the control sub-circuit according to an embodiment of the present invention is shown.

[0010] Figure 3A schematic diagram of an apparatus for a sideband PDH frequency locking experiment according to an embodiment of the present invention is shown.

[0011] Figure 4 A schematic diagram of a phase-locked loop sub-circuit according to an embodiment of the present invention is shown.

[0012] Figure 5 A schematic diagram of the output power control sub-circuit according to an embodiment of the present invention is shown.

[0013] Figure 6 A schematic diagram of the structure of the analog sampling sub-circuit according to an embodiment of the present invention is shown.

[0014] Figure 7(a) shows the waveform of the timing sweep result according to an embodiment of the present invention.

[0015] Figure 7(b) shows the amplitude curve of the timing sweep result according to an embodiment of the present invention.

[0016] Figure 7(c) shows the frequency curve of the timing sweep result according to an embodiment of the present invention.

[0017] Figure 8 A schematic diagram of the circuit board containing the radio frequency source circuit according to an embodiment of the present invention is shown.

[0018] Figure 9(a) shows a schematic diagram of the phase noise test of the radio frequency source circuit at different carrier frequencies according to an embodiment of the present invention.

[0019] Figure 9(b) shows a schematic diagram of phase noise testing for different signal sources according to an embodiment of the present invention.

[0020] Figure 10 A schematic diagram of trigger delay test results under digital modulation according to an embodiment of the present invention is shown.

[0021] Figure 11 A flowchart of a method for generating laser frequency-shifted cavity-locked signals according to an embodiment of the present invention is shown. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0025] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0026] In the process of realizing this invention, it was discovered that a common method in cold atom experiments is to modulate the frequency, phase, and amplitude of a laser by driving an acousto-optic modulator (AOM) or an electro-optic modulator (EOM) with a radio frequency signal. Although traditional radio frequency signal sources are fully functional, they are usually bulky, expensive, have few channels, and lack optimization for cold atom experiments in terms of modulation rate, phase noise, and frequency resolution.

[0027] Direct digital frequency synthesis (DDS) technology is widely used in radio frequency signal generation due to its high frequency resolution and fast modulation capabilities. For example, the AD9914 DDS chip has an output frequency of up to 1.4 GHz and a sub-nanohertz frequency resolution. However, DDS-based solutions still suffer from limitations such as limited modulation rate, insufficient phase noise control, and limited modulation functionality, making it difficult to meet the complex experimental requirements of multi-stage and multi-parameter experiments in cold atom experiments, such as strontium atom optical lattice clocks.

[0028] Therefore, it is of great significance to develop a small radio frequency source to replace signal sources or DDS boards in atomic physics optical experiments and generate radio frequency signals that can be flexibly modulated in frequency and phase.

[0029] Therefore, embodiments of the present invention provide a radio frequency source circuit that can support rapid modulation of frequency, phase, and amplitude, and has the advantages of low phase noise, low cost, and small size.

[0030] Based on the demand analysis of the radio frequency (RF) source in cold atom optical lattice clocks (such as strontium atom optical lattice clocks), the RF source circuit of this invention adopts an architecture with a direct digital frequency synthesizer as the core and a field-programmable gate array (FPGA) as the control center. This architecture can be specifically described as follows: Figure 1 As shown. Based on this, the radio frequency (RF) circuit of the present invention can adjust the phase, frequency, and amplitude of the output signal of the frequency synthesizer within the RF circuit. Specifically, it can adjust the output signal of the frequency synthesizer by using different modulation sources, such as data provided by the host computer to the control sub-circuit (e.g., FPGA (Field Programmable Gate Array)), external analog signals collected by the analog sampling sub-circuit, or data generated by the FPGA according to specific functions. Therefore, the modulation source of the RF circuit of the present invention can be set and selected to adjust the phase, frequency, or amplitude of the output signal of the frequency synthesizer based on the modulation source. Since the embodiment of the present invention applies the RF source circuit to laser frequency locking, the RF source circuit in this embodiment is used to phase-modulate the output signal of the frequency synthesizer.

[0031] Figure 1 A schematic diagram of the structure of a radio frequency source circuit according to an embodiment of the present invention is shown.

[0032] like Figure 1 As shown, the RF source circuit includes a control sub-circuit, a phase-locked loop sub-circuit, a frequency synthesizer, and an output power control sub-circuit, which are integrated on a circuit board.

[0033] In one embodiment, the control sub-circuit can be an FPGA (Field Programmable Gate Array), and the frequency synthesizer can be a DDS. For example, the control sub-circuit can use an XC7A35T FPGA chip, and the frequency synthesizer can use an AD9914 DDS chip.

[0034] According to an embodiment of the present invention, the control sub-circuit can be electrically connected to the host computer. Specifically, the control sub-circuit may include a communication interface module, and the control sub-circuit can communicate with the host computer through the communication interface module to receive various instructions from the host computer.

[0035] In one embodiment, the host computer can be used to send digital control commands or analog control commands to the control sub-circuit, so that the RF source circuit can support not only digital modulation but also analog modulation. Analog modulation involves real-time control of the frequency synthesizer output signal via an external analog signal, while digital modulation involves the user sending digital control commands to the control sub-circuit through the host computer to control the frequency synthesizer output signal based on these commands. Therefore, Figure 1The diagram shows the part of the radio frequency source circuit used to implement digital modulation.

[0036] According to an embodiment of the present invention, the frequency synthesizer output signal is controlled by the radio frequency source circuit through digital modulation. The control sub-circuit can be used to receive digital control instructions from the host computer. The digital control instructions are used to instruct the control sub-circuit to execute the digital modulation method and carry preset modulation data for the digital modulation method.

[0037] In one embodiment, since the output signal of the frequency synthesizer is controlled by the control subcircuit, in order to achieve fast modulation, the components in the control subcircuit used to perform digital modulation are synchronized with the system clock of the frequency synthesizer to eliminate the delay uncertainty of cross-clock domain data transmission.

[0038] Based on this, such as Figure 1 As shown, the frequency synthesizer can send its system clock to the control sub-circuit via direct communication mode, serving as a synchronization clock between the frequency synthesizer and the control sub-circuit; that is, the synchronization clock is the system clock of the frequency synthesizer.

[0039] For example, a frequency synthesizer can provide a 146MHz synchronous clock to the control subcircuit.

[0040] According to an embodiment of the present invention, the control sub-circuit can use a synchronous clock as its working clock and perform amplitude-phase conversion and phase waveform conversion in parallel based on the preset modulation data carried by the digital control instructions, so as to output a phase control word and a phase demodulation signal.

[0041] Specifically, the control subcircuit can perform amplitude-phase conversion and output a phase control word based on preset modulation data; it can also perform phase waveform conversion and output a phase demodulated signal based on the same preset modulation data. Therefore, the control subcircuit can have two outputs to generate a phase control word and a phase demodulated signal based on the same preset modulation data.

[0042] Because the frequency synthesizer requires a reference clock input, namely a 3.5GHz clock signal with low phase noise, while the output frequency of the reference source commonly used in the laboratory is 10MHz, a phase-locked loop circuit is needed to multiply the output clock of the reference source to adapt it to the frequency synthesizer.

[0043] Based on this, a phase-locked loop (PLL) circuit can be used to multiply the reference clock and output a clock signal that matches the operating frequency of the frequency synthesizer, serving as the operating reference clock input for the frequency synthesizer. Here, the reference clock is the clock signal output from the reference source.

[0044] In one embodiment, a 10MHz reference clock can be multiplied to 3.5GHz using a phase-locked loop circuit, meaning that the frequency of the output clock signal, which is adapted to the operating frequency of the frequency synthesizer, is 3.5GHz.

[0045] Based on this, the frequency synthesizer is electrically connected to the control subcircuit and the phase-locked loop (PLL) subcircuit. The frequency synthesizer can receive the operating reference clock provided by the PLL subcircuit and the phase control word provided by the control subcircuit. Therefore, the frequency synthesizer can be used to achieve phase synchronization with the control subcircuit using the operating reference clock as the frequency base, combined with a synchronization clock, and to adjust the phase of the output signal based on the phase control word.

[0046] In one embodiment, after receiving a 3.5 GHz operating reference clock, the frequency synthesizer divides the 3.5 GHz operating reference clock by 24 to obtain a 146 MHz clock, and uses the 146 MHz clock as the system clock of the frequency synthesizer. At the same time, the frequency synthesizer also provides the 146 MHz clock to the control sub-circuit as a synchronization clock between the frequency synthesizer and the control sub-circuit.

[0047] In one embodiment, the control subcircuit supports parallel communication mode and direct communication mode. The control subcircuit can be electrically connected to the frequency synthesizer via a parallel data bus. The parallel communication mode is used to configure the internal registers of the frequency synthesizer to control the phase of the output signal of the frequency synthesizer and to achieve fast modulation. The direct communication mode (i.e., serial communication) is used to configure the synchronization clock between the frequency synthesizer and the control subcircuit.

[0048] For example, the control subcircuit and the frequency synthesizer can interact based on WISHBONE BUS (i.e., WISHBONE bus).

[0049] Specifically, the frequency synthesizer can use a working reference clock as the frequency reference to ensure the frequency accuracy and long-term stability of the output signal. At the same time, the frequency synthesizer and the control sub-circuit share the same synchronous clock to achieve timing synchronization between the frequency synthesizer and the control sub-circuit.

[0050] The phase control word can be a binary value. The output signal of the frequency synthesizer can be a sine wave, and the phase control word can be used to adjust the phase of the sine wave.

[0051] Since cold atom experiments require flexible control over the power of the output signal of the radio frequency source circuit, the radio frequency source circuit of this invention also includes an output power control sub-circuit after the frequency synthesizer, that is, the output power control sub-circuit is electrically connected to the output terminal of the frequency synthesizer.

[0052] Based on this, the output power control sub-circuit can be used to adjust the power of the output signal of the frequency synthesizer based on preset power modulation data, so as to output a laser frequency shift and cavity lock signal, wherein the phase demodulation signal and the laser frequency shift and cavity lock signal are used to achieve laser frequency offset locking.

[0053] The preset power modulation data represents the power control parameters, which are used to dynamically adjust the power of the output signal of the frequency synthesizer. Since power is proportional to the square of amplitude, controlling the power is equivalent to controlling the amplitude.

[0054] Based on the above, when the RF source circuit is applied to the sideband PDH frequency locking experiment in cold atom experiments, the signal output by the output power control sub-circuit of the RF source circuit is the laser frequency shifting cavity locking signal. Therefore, the laser frequency offset locking in the sideband PDH frequency locking experiment can be achieved based on the laser frequency shifting cavity locking signal and the phase demodulation signal output by the control sub-circuit.

[0055] According to embodiments of the present invention, the control subcircuit and the frequency synthesizer achieve synchronized timing based on a synchronous clock. The synchronous clock provided by the frequency synthesizer to the control subcircuit enables the control subcircuit to adjust the output signal of the frequency synthesizer based on the modulation rate of the synchronous clock, reducing the response delay of phase modulation and increasing the modulation rate. Since the generation of the phase control word and the phase demodulation signal are integrated into the same control subcircuit, the optical path in the sideband PDH frequency-locking experiment is simplified. Simultaneously, the control subcircuit can perform amplitude-phase conversion and phase waveform conversion in parallel based on preset modulation data, ensuring that the phase control word and the phase demodulation signal originate from the same reference (i.e., the same preset modulation data), guaranteeing strict synchronization. The use of a low-noise phase-locked loop (PLL) subcircuit in the RF source circuit reduces the phase noise of the frequency synthesizer's output signal. Furthermore, the control subcircuit, frequency synthesizer, PLL subcircuit, and output power control subcircuit in the RF source circuit are all integrated onto a single circuit board, improving integration density.

[0056] Based on the above, the main design of the RF source circuit is reflected in the phase-locked loop sub-circuit, the output power control sub-circuit, and the control sub-circuit, which will be described in sequence below. Figure 2 Explain the structure of the control sub-circuit, through Figure 4 Explain the structure of the phase-locked loop sub-circuit, through Figure 5 Describe the structure of the output power control sub-circuit.

[0057] In one embodiment, the control sub-circuit serves as the functional control core of the radio frequency source circuit of the present invention. The control sub-circuit is responsible for parsing the host computer instructions, managing on-chip components (such as internal components of the control sub-circuit), configuring peripheral components (such as phase-locked loop sub-circuit, digital-to-analog converter, analog-to-digital converter, and frequency synthesizer, etc.), and implementing various custom operating modes.

[0058] Figure 2 A schematic diagram of the control sub-circuit according to an embodiment of the present invention is shown.

[0059] like Figure 2 As shown, the control sub-circuit includes a direct digital frequency synthesis core, a modulation data processing unit, a digital phase shifter, a shaping unit, a clock buffer, and a programmable input / output interface core.

[0060] exist Figure 2 In the process, the clock buffer is electrically connected to the frequency synthesizer. The clock buffer is used to store the synchronization clock provided by the frequency synthesizer, which is used as the operating clock of the direct digital frequency synthesis core.

[0061] Based on this, the clock for the Direct Digital Synthesis Intellectual Property Core (DDS IP Core) is provided by the frequency synthesizer. For example, the DDS IP Core can operate using a 146MHz synchronous clock, while the operating clocks for other components in the control subcircuit, excluding functional units (such as the DDS IP Core and programmable input / output interface cores), can be, for example, an on-chip 200MHz crystal oscillator signal. This clock domain division is for achieving fast modulation: synchronizing the components in the control subcircuit used to modulate the frequency synthesizer's output signal with the frequency synthesizer's system clock eliminates the delay uncertainty of cross-clock domain data transmission. Furthermore, in high-frequency data transmission across clock domains, the sampling and holding times and setup times are difficult to meet, leading to data instability and data transmission errors. Therefore, the aforementioned clock domain division eliminates the cross-clock domain impact, laying the foundation for achieving a 146MHz frequency update rate.

[0062] like Figure 2 As shown, a direct digital frequency synthesis (DDS) core is instantiated within the control subcircuit, and its operating clock is constrained to the synchronous clock domain provided by the frequency synthesizer. This DDS core acts as a phase modulation source, synchronously generating two associated signals: a phase control word path and a phase demodulation signal path. Based on this, the DDS core within the control subcircuit can achieve dual-output, that is, it can output the phase control word and the phase demodulation signal in parallel, ensuring that the synchronously generated phase control word and phase demodulation signal originate from the same source and their phase difference is programmable.

[0063] In one embodiment, the preset modulation data may include a frequency control word, a phase modulation depth, and a phase shift bias. The preset modulation data is data set by the user through a host computer and provided to the control sub-circuit by the host computer in digital modulation mode.

[0064] In one embodiment, such as Figure 2 As shown, the control sub-circuit may also include a register. The host computer sends digital control commands to the control sub-circuit to adjust the frequency control word in the preset modulation data carried by the digital control commands. Phase modulation depth Phase shift bias Write it into the register within the control sub-circuit.

[0065] Because the user's input in the host computer is the modulation signal frequency The host computer will input the modulation signal frequency. Convert to frequency control word This is to provide it to the control sub-circuit.

[0066] Specifically, the host computer can use the following formula (1) to modulate the frequency of the signal. Convert to frequency control word 1.

[0067] (1);

[0068] Among them, frequency control word The bit width can be 48 bits.

[0069] Among them, phase modulation depth It can represent the modulation depth of phase modulation of the output signal of the frequency synthesizer, and the value ranges from 0 to 360°; It can represent the frequency of the output signal of the frequency synthesizer. The frequency of the modulation signal can be set directly, and its range is 0~25MHz.

[0070] based on Figure 2 As shown, the phase control word can be generated through a direct digital frequency synthesis core, a modulation data processing unit, and a programmable input / output interface core.

[0071] According to an embodiment of the present invention, the direct digital frequency synthesis kernel can be used to output amplitude data and phase accumulation value based on the frequency control word in the preset modulation data.

[0072] In one embodiment, the register can also configure the frequency control word in a direct digital frequency synthesis (DDS) core, which, driven by a synchronous clock, generates a frequency based on the frequency control word. amplitude data The amplitude data can be a 16-bit amplitude sequence, or it can be generated based on the frequency control word by the phase accumulator in the direct digital frequency synthesis kernel.

[0073] To control the phase offset range of the frequency synthesizer output signal, the amplitude data can be linearly scaled based on the phase modulation depth to control the phase offset range of the frequency synthesizer output signal.

[0074] According to an embodiment of the present invention, the modulation data processing unit is electrically connected to the direct digital frequency synthesis core. The modulation data processing unit can be used to linearly scale the amplitude data based on the phase modulation depth in the preset modulation data and output a phase control word.

[0075] Based on this, the amplitude data output by the direct digital frequency synthesizer core can be linearly scaled and then used as a phase control word in real time, which is then loaded onto the parallel data bus of the frequency synthesizer to achieve dynamic phase shift control of the frequency synthesizer's output signal. The frequency synthesizer can then perform phase modulation on its output signal based on the phase control word, generating a PDH phase-modulated signal containing positive and negative sidebands. This signal is then processed by the output power control sub-circuit and output as a laser frequency-shifted cavity-locked signal.

[0076] According to an embodiment of the present invention, the programmable input / output interface core is electrically connected to the modulation data processing unit and the clock buffer. The programmable input / output interface core can be used to perform phase calibration on the phase control word based on the synchronous clock.

[0077] Specifically, the SelectIO IP Core (Select Input / Output Intellectual Property Core) includes a programmable delay unit (ODELAY, Output Delay). To compensate for PCB (Printed Circuit Board) trace delays and component delays, the phase control word is calibrated by adjusting the programmable delay unit. Specifically, if the amount of delay to be compensated is known through simulation or hardware testing, the phase control word can be calibrated by setting the delay amount of the programmable delay unit within the SelectIO IP Core to achieve delay compensation. The effective range of the delay amount of the programmable delay unit is 0~31.

[0078] This ensures that, under a high-speed synchronous clock of 146MHz, the data signal (i.e., the phase control word) can strictly meet the setup time and hold time requirements of the frequency synthesizer, fundamentally eliminating code errors or metastability.

[0079] The generation and output of the phase control word can be explained in detail below.

[0080] In each synchronization clock cycle, the direct digital frequency synthesis core generates amplitude data based on the frequency control word under the drive of the synchronization clock. The modulation data processing unit can perform modulation data processing on the amplitude data. Specifically, based on the phase modulation depth, the modulation data processing unit processes the amplitude data... Linear scaling is performed, and the linear scaling process can be shown in the following formula (2).

[0081] (2);

[0082] in, For phase control word, For phase modulation depth, This is amplitude data.

[0083] Based on this, the control sub-circuit can write the phase control word into the internal register of the frequency synthesizer in real time via a parallel data bus. The frequency synthesizer can then perform phase modulation on its output signal, outputting a PDH phase-modulated signal with modulation sidebands, i.e., a PDH phase-modulated signal containing both positive and negative sidebands.

[0084] based on Figure 2 As shown, the phase demodulated signal can be generated by a direct digital frequency synthesis kernel, a digital phase shifter, and a shaping unit.

[0085] According to an embodiment of the present invention, the digital phase shifter is electrically connected to the direct digital frequency synthesis core. The digital phase shifter can be used to perform digital phase shifting processing on the phase accumulation value based on the phase shift bias in the preset modulation data to obtain the target phase value. The shaping unit can be used to convert the target phase value into a square wave signal with a preset duty cycle as a phase demodulation signal.

[0086] Based on this, the phase accumulation value inside the same direct digital frequency synthesis core can be extracted in the control sub-circuit, and after controllable digital phase shifting and square wave shaping, the phase demodulated signal is output.

[0087] Mix out is a multi-functional output port used for auxiliary signal monitoring or output demodulated signals, that is, Mix out can be used to control the output phase demodulated signals of sub-circuits.

[0088] In one embodiment, the square wave signal (i.e., the phase demodulated signal) is output through Mix out and then filtered externally to serve as the local oscillator reference of the mixer, which is used to demodulate the output signal of the photodetector containing cavity frequency response information in the laser frequency locking experiment.

[0089] In one embodiment, the digital phase shifter and shaping unit monitor and process the phase accumulation value phase_tdata output by the direct digital frequency synthesis kernel in real time to generate a phase demodulation signal. The specific description of the generation of the phase demodulation signal is as follows.

[0090] The phase accumulation value phase_tdata can be, for example, 48 bits.

[0091] In one embodiment, the digital phase shifter reads the current phase accumulation value phase_tdata of the direct digital frequency synthesis kernel at each rising edge of the synchronization clock, and then compares the phase accumulation value phase_tdata with a pre-quantized phase shift bias. Perform the model Accumulation is performed on the accumulated phase value to obtain the target phase value after phase superposition compensation. The process can be shown in the following formula (3).

[0092] (3);

[0093] in, To find the modulus function.

[0094] In one embodiment, since the phase accumulator in the direct digital frequency synthesis kernel has a bit width of 48 bits, the host computer can convert the user-inputted shift phase delt_p into a 48-bit bit width phase shift bias. To adjust the phase shift bias Provided to the control sub-circuit, phase shift bias It can be obtained through the following formula (4).

[0095] (4);

[0096] Among them, phase shift bias It can be used to adjust the relative phase between the phase demodulation signal output by the control sub-circuit and the phase control word.

[0097] The shaping unit can be used to compare target phase values. The target phase value is converted into a square wave signal with a preset duty cycle by a preset threshold value, which is then used as a phase demodulation signal.

[0098] The preset threshold can be half of the full range of the phase accumulator, i.e. (Corresponding radian system) ).

[0099] Based on this, the shaping unit can determine the square wave level of the square wave signal according to the comparison result. The square wave level can be determined by the following formula (5).

[0100] (5);

[0101] in, It can represent the square wave level of a square wave signal.

[0102] Therefore, if the target phase value is at If the target phase value is within the range, that is, less than or equal to half of the full range, the output logic low level "0" (i.e., square wave level) will be used; if the target phase value is within the range... If the range is greater than half of the full range, then output a logic high level "1".

[0103] Based on the above, the shaping unit can convert continuously linearly increasing phase data (i.e., phase accumulation value) into a square wave signal of the same frequency with a duty cycle of 50% and programmable phase adjustment in real time. The square wave signal can be output to an external circuit (such as a filter) through the I / O (Input / Output) pins of the control sub-circuit. Here, Mix out can be an I / O pin of the control sub-circuit.

[0104] According to an embodiment of the present invention, the generation processes of the phase demodulation signal and the phase control word are both completed synchronously within the control sub-circuit. The phase control word and the phase demodulation signal originate from the same frequency synthesis reference (i.e., the same frequency control word), ensuring strict frequency synchronization. Simultaneously, the programmable phase shift mechanism within the control sub-circuit (i.e., the phase shift bias can be pre-quantized) can accurately compensate for the group delay introduced by external links (such as cables, PCB traces, and analog circuits), allowing the relative phase difference between the phase demodulation signal and the phase control word to be dynamically adjusted to the most sensitive operating point (i.e., the quadrature zero or the center of the linear region). This facilitates the subsequent application of the RF source circuit in sideband PDH frequency locking experiments to achieve laser frequency offset locking.

[0105] Based on the above, the RF source circuit of the present invention can be applied to the sideband PDH frequency locking experiment to achieve laser frequency offset locking.

[0106] Figure 3 A schematic diagram of an apparatus for a sideband PDH frequency locking experiment according to an embodiment of the present invention is shown.

[0107] like Figure 3As shown, the device includes a laser, a fiber connector (FC), fibers, a polarizing beam splitter (PBS), a cavity, a beam detector (BD), a photodetector (PD), an amplifier (AMP), a mixer, a low-pass filter (LPF), a servo feedback loop, and the radio frequency source circuit (HB_DDS) of this invention.

[0108] like Figure 3 As shown, the RF source circuit includes a direct digital frequency synthesis core and a frequency synthesizer. The direct digital frequency synthesis core is used to control the output phase demodulation signal. Specifically, the RF source circuit processes the output phase demodulation signal through the direct digital frequency synthesis core, digital phase shifter, and shaping unit in the control sub-circuit. The frequency synthesizer is used to control the output laser frequency-shifted cavity-locked signal. Specifically, the RF source circuit processes the output laser frequency-shifted cavity-locked signal through the frequency synthesizer and the output power control sub-circuit.

[0109] in, This can represent the modulation frequency used to phase modulate the output signal of the frequency synthesizer, with a value ranging from 0 to 25 MHz. The modulation frequency used to phase modulate the output signal of the frequency synthesizer is consistent with the frequency of the phase demodulated signal, so that it can be used for subsequent demodulation. The frequency of the modulated signal represents the frequency of the output signal of the frequency synthesizer.

[0110] based on Figure 3 The square wave signal output by the control sub-circuit in the RF source circuit (i.e., the phase demodulated signal) passes through an external bandpass or low-pass filter (LPF) to filter out high-frequency harmonics and noise, restoring it to a pure sine wave or a high-quality square wave, which is then used as the demodulation reference signal for the mixer.

[0111] In one embodiment, the sideband PDH frequency-locking experiment uses a 922nm diode laser as the target, and the locking target is a 10cm reference cavity (i.e., a resonant cavity). The parameters are set as follows: modulation signal frequency... Modulation frequency =9.11MHz, phase modulation depth α=90°. This sideband PDH frequency-locking experiment can be used to verify the feasibility of the radio frequency source circuit of this invention in cold atom experiments.

[0112] The phase shift bias in the register of the control sub-circuit can be dynamically adjusted via the host computer. To directly change the target phase value The starting point for determination is determined, thereby linearly shifting the phase of the output phase demodulated signal, and further linearly shifting the phase of the demodulated reference signal.

[0113] Through such Figure 3 The device shown uses a laser frequency-shifting cavity-locking signal output from the HB_DDS (radio frequency source circuit) to drive a fiber optic modulator to phase-modulate the laser output from the laser. The modulated laser is injected into the resonant cavity, and the reflected optical signal is converted into an electrical signal by a photodetector. This electrical signal is then mixed with the phase demodulated signal output from the HB_DDS in a mixer and passed through a low-pass filter to obtain an error signal, which is used to feed back the laser frequency and achieve laser frequency locking.

[0114] Therefore, by observing the error signal output by the mixer, the phase shift bias can be continuously adjusted. The error signal continues until its amplitude reaches its maximum and its slope is steepest at the zero-crossing point. This means that the phase difference between the demodulated reference signal and the feedback signal under test is precisely adjusted to the quadrature zero point (or the center of the linear region). At this point, the error signal with the highest sensitivity can be obtained for subsequent closed-loop control (such as frequency locking or phase locking).

[0115] The feedback signal to be tested is the output signal of the photodetector.

[0116] In one embodiment, the output signal of the photodetector is controlled by a laser frequency-shifted cavity-locked signal applied to the laser. Adjusting the phase difference between the demodulation reference signal and the feedback signal under test is equivalent to adjusting the relative phase between the phase demodulation signal and the phase control word.

[0117] Based on this, when the phase difference between the demodulated reference signal and the feedback signal under test is precisely adjusted to the quadrature zero point, the optimized error signal is sent to the servo feedback loop (such as a proportional-integral-differential (PID) controller) to drive the laser (such as a piezoelectric ceramic (PZT) or current control terminal), thereby achieving long-term and stable locking of the laser frequency to the resonant cavity.

[0118] Specifically, the phase demodulation signal output by the control sub-circuit is used to demodulate the output of the photodetector to generate an error signal, and the laser frequency offset locking is achieved by inputting the error signal into the servo feedback loop.

[0119] Based on the method described above for generating the phase demodulated signal using the RF source circuit of this invention, when the modulation frequency is divided by a power of 2 to a power of 146MHz, the phase demodulated signal will obtain a stable 50% duty cycle. However, at other modulation frequencies, this method will result in phase truncation of the phase demodulated signal, which will be accompanied by some spurious signals. However, in practical use, these spurious signals do not affect the PDH phase-locking function. Typically, to obtain the best performance, the modulation frequency is set to a power of 2 to a power of 146MHz.

[0120] Based on the above, only one electro-optic modulator is needed to generate a high-quality PDH error signal in the sideband PDH frequency-locking experiment. It also provides a frequency shift range of up to 1.4 GHz and programmable modulation parameters, which provides great flexibility and integration advantages for laser systems in cold atom experiments, and ensures the free spectral range covering the optical cavity.

[0121] Specifically, the modulation signal frequency It can be modulated by external analog signals or programmable signals (i.e., input from the host computer), which provides an advantage for locking lasers of different frequencies.

[0122] Therefore, the RF source circuit of the present invention can provide a highly integrated and high-precision phase modulation and demodulation signal generation scheme for laser frequency locking, which can replace the complex architecture of traditional PDH technology that requires the simultaneous use of electro-optic modulator (EOM) and acousto-optic modulator (AOM).

[0123] Because the frequency synthesizer has strict requirements for the reference clock, it needs to be provided with a 3.5GHz clock signal with low phase noise. Therefore, the phase-locked loop sub-circuit in the RF source circuit of this invention can be as follows: Figure 4 As shown.

[0124] Figure 4 A schematic diagram of a phase-locked loop sub-circuit according to an embodiment of the present invention is shown.

[0125] like Figure 4 As shown, the phase-locked loop sub-circuit includes an RF interface, a temperature-controlled crystal oscillator, a relay, a fractional-frequency phase-locked loop, and a voltage-controlled oscillator.

[0126] In one embodiment, considering that the output frequency of a commonly used laboratory synchronization reference source (such as a rubidium clock) is 10MHz, the fractional frequency division phase-locked loop can be a fractional synthesizer of model HMC703, which has low noise and flexible fractional frequency division capability; the voltage-controlled oscillator can be a VCO (Voltage Controlled Oscillator) of model HMC389, whose output frequency covers the 3.5GHz requirement and provides relatively low additional phase noise.

[0127] According to an embodiment of the present invention, the first input terminal of the relay is electrically connected to the radio frequency interface, and the second input terminal of the relay is electrically connected to the temperature-controlled crystal oscillator. Based on this, the reference clock of the phase-locked loop sub-circuit can come from the onboard temperature-controlled crystal oscillator or an external high-stability reference source connected through the radio frequency interface.

[0128] Specifically, the output of the relay is electrically connected to the fractional frequency division phase-locked loop. The relay can be used to switch the conduction channel of the relay in response to the clock source signal from the control sub-circuit, so as to switch the channel conduction between the RF interface channel and the temperature-controlled crystal oscillator channel.

[0129] Based on this, the RF interface can be used to input an external reference clock when the relay is conducting the RF interface channel, so as to serve as the reference clock input for the fractional frequency division phase-locked loop; the temperature-controlled crystal oscillator can be used to output an internal reference clock when the relay is conducting the temperature-controlled crystal oscillator channel, so as to serve as the reference clock input for the fractional frequency division phase-locked loop.

[0130] Among them, EXT REF is the external reference input port, i.e., the RF interface, which can be locked to a higher precision external reference source; REF out is the reference clock output port, which provides a 10MHz crystal oscillator signal for external synchronization.

[0131] According to an embodiment of the present invention, the output terminal of the fractional frequency division phase-locked loop is electrically connected to the input terminal of the voltage-controlled oscillator, and the input terminal of the fractional frequency division phase-locked loop is also electrically connected to the output terminal of the voltage-controlled oscillator. Figure 4 As shown, the fractional-frequency phase-locked loop (PLL) includes a frequency divider, a phase detector (PD), and a charge pump (CP). The frequency divider assigns a reference clock division factor R to the relay output and a feedback division factor N to the voltage-controlled oscillator (VCO) output. The VCO output can be divided into two paths: one as the feedback signal of the PLL, and the other as the operating reference clock of the frequency synthesizer. Both the feedback signal and the operating reference clock are feedback clocks output by the frequency synthesizer.

[0132] Based on this, the reference clock output by the relay is processed sequentially by the frequency divider, phase detector and charge pump in the fractional frequency-locked loop to generate a voltage adjustment signal to drive the voltage-controlled oscillator.

[0133] Therefore, the fractional frequency division phase-locked loop can be used to output a voltage adjustment signal based on the frequency difference and phase difference between the reference clock and the feedback clock output by the voltage-controlled oscillator; the voltage-controlled oscillator can be used to modulate the output feedback clock based on the voltage adjustment signal until the frequency difference and phase difference meet the preset conditions, and output a clock signal that matches the operating frequency of the frequency synthesizer.

[0134] The preset conditions can characterize the phase difference and frequency difference between the feedback clock and the reference clock to be consistent and stable within a preset threshold range. The preset threshold range is set as needed to ensure that the phase and frequency of the feedback clock are consistent with the phase and frequency of the reference clock, thereby locking the frequency of the feedback clock to 3.5GHz.

[0135] Based on the above, in a fractional frequency division phase-locked loop, the frequency divider can divide the frequency of the reference clock by R and the frequency of the feedback clock by N; the phase detector can be used to compare the phase difference between the two signals after frequency division and output the corresponding phase error signal; the charge pump is used to receive the phase error signal output by the phase detector, convert the phase error signal into charge, and output a voltage adjustment signal.

[0136] For example, the reference clock division factor R can be 1, and the feedback division factor N can be 3500.

[0137] based on Figure 4 Taking a 10MHz reference clock as an example, the 10MHz reference clock is multiplied by a fractional-divider phase-locked loop and a voltage-controlled oscillator to produce a 3.5GHz clock signal. Because the fractional-divider phase-locked loop supports fractional division, it ensures precise locking of the 3.5GHz output frequency.

[0138] According to an embodiment of the present invention, the reference clock is multiplied by a phase-locked loop (PLL) sub-circuit to output a clock signal adapted to the operating frequency of the frequency synthesizer, i.e., the output frequency range of the PLL sub-circuit covers the 3.5 GHz requirement. Furthermore, based on the fractional-frequency PLL and voltage-controlled oscillator within the PLL sub-circuit, precise locking of the 3.5 GHz output frequency is ensured, while phase noise is reduced.

[0139] In one embodiment, the output power control sub-circuit is the link between the frequency synthesizer output and the final signal (i.e., the laser frequency-shifted cavity-locked signal) output, mainly realizing spectrum reconstruction and power control functions. The output power control sub-circuit in the RF source circuit of this invention can be as follows: Figure 5 As shown.

[0140] Figure 5 A schematic diagram of the output power control sub-circuit according to an embodiment of the present invention is shown.

[0141] like Figure 5 As shown, the output power control sub-circuit may include an analog amplitude modulation interface, a digital-to-analog converter, a resistor network, two cascaded voltage-controlled attenuators, and two cascaded power amplifiers. The two cascaded voltage-controlled attenuators include voltage-controlled attenuator 1 and voltage-controlled attenuator 2 connected in series, and the two cascaded power amplifiers include power amplifier 1 and power amplifier 2 connected in series.

[0142] In one embodiment, the digital-to-analog converter (DAC) in the output power control sub-circuit can be an AD5541 DAC chip, the voltage-controlled attenuator can be an F2255, and the power amplifier can be an ADL8111 AMP.

[0143] Since the frequency synthesizer output signal spectrum contains image frequency components in multiple Nyquist zones, only by filtering out components other than the fundamental frequency can a pure sinusoidal signal be obtained. Therefore, the RF source circuit of this invention also includes a filter at the output of the frequency synthesizer (specifically, as shown in the image). Figure 5 As shown in the figure, the high-frequency spurious and image frequency components are filtered out by the filter, and the filtered signal is input into the output power control sub-circuit.

[0144] For example, the filter is a seventh-order elliptic function filter.

[0145] According to an embodiment of the present invention, the radio frequency source circuit has analog modulation and digital modulation methods. Therefore, the source of control of the attenuation of the voltage-controlled attenuator can be a digital-to-analog converter or a power modulation source connected externally through an analog amplitude modulation interface.

[0146] Specifically, the resistor network includes resistors R1, R2, and R3. The first input terminal of the resistor network, i.e., one end of resistor R1, is electrically connected to the analog amplitude modulation interface, or the second input terminal of the resistor network, i.e., one end of resistor R2, is electrically connected to the digital-to-analog converter. The control source of the voltage-controlled attenuator is determined after the RF source circuit board is soldered.

[0147] Based on this, the resistor network can be used to take the external control signal input through the analog amplitude modulation interface or the internal control signal output by the digital-to-analog converter as the input signal of the resistor network based on the connection status of the first input terminal and the second input terminal, and output preset power modulation data based on the input signal.

[0148] Based on this, the analog amplitude modulation interface can be used to input external control signals when the analog amplitude modulation interface is electrically connected to the first input terminal of the resistor network; the input terminal of the digital-to-analog converter is electrically connected to the digital-to-analog conversion communication module of the control sub-circuit, and the digital-to-analog converter is used to convert the power control word received from the digital-to-analog conversion communication module in the control sub-circuit and output internal control signals when the output terminal of the digital-to-analog converter is electrically connected to the second input terminal of the resistor network.

[0149] Based on the above, the inherent Sinc response of the frequency synthesizer will cause the power of the output signal to be uneven. Therefore, the power of the output signal of the frequency synthesizer can be linearly adjusted by controlling the sub-circuit or an external power modulation source.

[0150] AM stands for Analog Amplitude Modulation Interface, which is used to achieve linear control of output power, i.e., external control signals are input through AM.

[0151] According to an embodiment of the present invention, a two-stage cascaded voltage-controlled attenuator is electrically connected to a resistor network and a frequency synthesizer. The two-stage cascaded voltage-controlled attenuator is used to perform power attenuation processing on the output signal of the frequency synthesizer based on preset power modulation data.

[0152] In one embodiment, the voltage-controlled attenuator can be an F2255 attenuator, whose attenuation is controlled by the output of the digital-to-analog converter or the input of the analog amplitude modulation interface (i.e., preset power modulation data). The F2255 has good linearity and a large dynamic range; theoretically, the attenuation range can reach over 60dB after two stages are cascaded.

[0153] Specifically, external or internal control signals can change the attenuation of the voltage-controlled attenuator, thereby changing the amplitude of the frequency synthesizer's output signal and thus regulating the power.

[0154] Therefore, the voltage-controlled attenuator supports linear step power adjustment. Combined with the power control word provided by the control sub-circuit or the external control signal, it can achieve quasi-continuous power control, and the linear dynamic range of power adjustment can reach 66dB.

[0155] Based on this, the voltage-controlled attenuator is controlled by the channel output provided by the resistor network. By changing the channel configuration of the resistor network, that is, changing the connection between the first input terminal of the resistor network and the analog amplitude modulation interface and the connection between the second input terminal of the resistor network and the digital-to-analog converter, one of the two channels of the resistor network can be turned into an input channel. This allows the voltage-controlled attenuator to be directly controlled by an external control signal or controlled by the output of the digital-to-analog converter, thus realizing feedback control applications such as stable optical power.

[0156] According to an embodiment of the present invention, a two-stage cascaded power amplifier is electrically connected to a two-stage cascaded voltage-controlled attenuator. The two-stage cascaded power amplifier is used to amplify the attenuated output signal and output a laser frequency-shifted cavity-locked signal.

[0157] In one embodiment, a two-stage cascaded power amplifier can be used to compensate for insertion loss introduced by the attenuator and increase the final output power. RF out is the main radio frequency signal output port, used to output a 0~1.4GHz laser frequency-shifted cavity-locked signal.

[0158] The amplification factor of the power amplifier can be set based on the frequency requirements of the desired laser frequency-shifted cavity-locked signal.

[0159] According to an embodiment of the present invention, based on the two-stage cascaded voltage-controlled attenuator and the two-stage cascaded power amplifier in the output power control sub-circuit, the maximum output power of the output power control sub-circuit can reach 15dBm, and the dynamic adjustment range is 66dB, which can meet the requirements of cold atom experiments for flexible power control of the output signal of the radio frequency source circuit.

[0160] To support external analog modulation, the RF source circuit of this invention also includes an analog sampling sub-circuit, which can be configured as follows: Figure 6 As shown.

[0161] Figure 6 A schematic diagram of the structure of the analog sampling sub-circuit according to an embodiment of the present invention is shown.

[0162] like Figure 6 As shown, the analog sampling sub-circuit includes a differential amplifier unit and an analog-to-digital converter unit.

[0163] The differential amplifier unit includes differential amplifier 1 and differential amplifier 2 connected in parallel, and the analog-to-digital converter unit includes analog-to-digital converter 1 and analog-to-digital converter 2 connected in parallel.

[0164] In one embodiment, the differential amplifier unit may be a differential amplifier of model ADA4930-2, and the analog-to-digital converter unit may be a chip of model AD9655.

[0165] exist Figure 6 In this circuit, the analog sampling sub-circuit can employ a 2-channel 16-bit analog-to-digital converter (ADC) and its preamplifier.

[0166] According to an embodiment of the present invention, when the modulation method is analog modulation, the differential amplifier unit is electrically connected to an external analog signal source and is used to differentially amplify the two acquired external analog signals respectively, that is, the differential amplifier unit can be used to simultaneously acquire two external analog signals.

[0167] Specifically, the differential amplifier unit is used to convert two single-ended analog input signals into differential signals to provide high-quality input for the analog-to-digital converter unit, while also having common-mode noise suppression capability.

[0168] Mod_in1 and Mod_in2 are both analog sampling input ports. External analog signals are converted from analog to digital and used to modulate the output signal of the frequency synthesizer in real time.

[0169] According to an embodiment of the present invention, the input terminal of the analog-to-digital conversion unit is electrically connected to the output terminal of the frequency synthesizer and the output terminal of the differential amplifier unit. The analog-to-digital conversion unit is used to use a synchronous clock as the working clock and to perform analog-to-digital conversion and parallel-to-serial conversion on each differentially amplified analog signal to obtain an analog modulated signal.

[0170] Specifically, the analog-to-digital conversion unit also includes a serializer and a driver. The two input terminals of the serializer are electrically connected to the output terminals of the two analog-to-digital converters, respectively, to convert the output signals of the two analog-to-digital converters into parallel signals.

[0171] In one embodiment, the output signal of the analog-to-digital converter (ADC) can be 16-bit parallel data, and the outputs of ADC1 and ADC2 are two independent parallel data streams. The serializer can be configured with independent parallel-to-serial conversion logic for each ADC to convert the 16-bit parallel data output from ADC1 into serial data, and to convert the 16-bit parallel data output from ADC2 into serial data.

[0172] In one embodiment, the two output terminals of the serializer are electrically connected to the input terminals of driver 1 and driver 2, respectively. The driver is an LVDS (Low-Voltage Differential Signaling) driver. Driver 1 and driver 2 can convert the single-ended serial data output by the serializer into low-voltage differential signals, output mutually isolated serial data streams (i.e., analog modulated signals) in low-voltage differential form, and realize high-speed serial transmission through double-edge triggering.

[0173] In one embodiment, the analog-to-digital conversion unit uses a synchronous clock as its operating clock, that is, the analog-to-digital conversion unit and the frequency synthesizer use the same clock to prevent disordered jumps in the output signal of the frequency synthesizer under analog modulation.

[0174] For example, if the analog-to-digital conversion unit uses the AD9655 analog-to-digital converter, the analog sampling sub-circuit supports a sampling rate of up to 125 MS / s.

[0175] Based on the above, the external analog signal is digitized by the analog sampling sub-circuit and then sent to the control sub-circuit, which controls the frequency synthesizer in real time according to a preset algorithm.

[0176] In one embodiment, based on the communication signal bandwidth of the analog-to-digital converter (ADC) and the control sub-circuit, the actual sampling clock of the ADC is set to 146MHz divided by 8, i.e., 18.25MHz. Therefore, the analog sampling sub-circuit supports simultaneous modulation of two parameters (i.e., the inputs of Mod_in1 and Mod_in2) at a rate of 18.25MHz, satisfying the requirements of multi-parameter collaborative control, and the modulation delay is 1.15. .

[0177] In one embodiment, if more channels are required in the application scenario of the RF source circuit, the number of channels in the analog sampling sub-circuit of the RF source circuit can be upgraded to increase the number of channels.

[0178] According to embodiments of the present invention, since the RF source circuit also includes an analog sampling sub-circuit, the RF source circuit supports both digital and analog modulation methods, i.e., it can externally modulate the frequency synthesizer by acquiring external analog signals. Based on this, since digital modulation is achieved through the control sub-circuit and analog modulation is provided by the analog sampling sub-circuit, the modulation function of the RF source circuit is enhanced. Furthermore, the analog sampling sub-circuit employs dual-channel acquisition to meet the requirements of multi-parameter coordinated control.

[0179] According to an embodiment of the present invention, the control sub-circuit further includes an analog-to-digital conversion decoding unit. The input terminal of the analog-to-digital conversion decoding unit is electrically connected to the output terminal of the analog sampling sub-circuit. The analog-to-digital conversion decoding unit is used to decode the analog modulation signal to obtain a voltage code value, and to process the voltage code value based on a preset code value from the host computer to obtain an external phase control word.

[0180] In one embodiment, for analog modulation, the control sub-circuit further includes an analog-to-digital conversion decoding unit, which is electrically connected to the output of the analog sampling sub-circuit and is used to process the output of the analog sampling sub-circuit to obtain an external phase control word.

[0181] The analog-to-digital conversion decoding unit can process the analog modulation signal output by the analog sampling sub-circuit to obtain the external phase control word using the following formula (6).

[0182] (6);

[0183] in, This indicates the external phase control word provided by the control sub-circuit to the frequency synthesizer. This represents the voltage code value obtained by decoding the analog modulated signal output from the analog sampling sub-circuit. Represents the modulation coefficient. Indicates the bias amount. Modulation coefficient. and bias The analog-to-digital conversion decoding unit in the control sub-circuit is provided by the host computer.

[0184] For example, the voltage code value can be 16 bits of binary data.

[0185] According to an embodiment of the present invention, since the radio frequency source circuit also includes an analog sampling sub-circuit and the control sub-circuit includes an analog-to-digital conversion decoding unit, the radio frequency source circuit supports both digital modulation and analog modulation. In analog modulation, the analog-to-digital conversion decoding unit in the control sub-circuit processes the output of the analog sampling sub-circuit to provide an external phase control word to the frequency synthesizer, thereby achieving external control of the frequency synthesizer.

[0186] According to an embodiment of the present invention, the frequency synthesizer is also used to achieve phase synchronization with the control sub-circuit by using the working reference clock as the frequency reference and combining it with the synchronization clock, and to adjust the phase of the output signal based on the external phase control word.

[0187] In one embodiment, under analog modulation, an external analog signal is acquired by an analog sampling sub-circuit, and the analog-to-digital conversion decoding unit in the control sub-circuit is used to process the output of the analog sampling sub-circuit to obtain an external phase control word. Then, the control sub-circuit can control the output signal of the frequency synthesizer based on the external phase control word.

[0188] Specifically, the frequency synthesizer can use the working reference clock as the frequency reference, combine it with the synchronization clock to achieve phase synchronization with the control sub-circuit, and adjust the phase of the output signal based on the external phase control word.

[0189] According to embodiments of the present invention, the frequency synthesizer can support control not only under digital modulation mode, but also under analog modulation mode.

[0190] According to embodiments of the present invention, the radio frequency source circuit of the present invention can also be verified by a timing frequency sweep function.

[0191] Specifically, the control sub-circuit may also include a programmable scanning unit, which is electrically connected to the frequency synthesizer.

[0192] The programmable scanning unit can be used to store a list of scanning points, wherein the scanning point data in the list consists of a frequency control word, an amplitude control word, and a phase control word.

[0193] For example, the scan point is defined by a 64-bit frequency control word, a 12-bit amplitude control word, and a 16-bit phase control word.

[0194] In one embodiment, the test conditions for verifying the timing sweep function can be shown in Table 1 below.

[0195] Table 1

[0196]

[0197] in, For trigger interval, The point interval is [value], and the triggering method is an external TTL (Transistor-Transistor Logic) square wave.

[0198] In one embodiment, under the custom timing frequency sweep function, the RF source circuit supports external signal triggering and internal signal triggering. The host computer provides internal signal triggering, so the triggering method, point interval, trigger interval, number of sweep points, etc. can be set by the host computer, or the triggering method, point interval, trigger interval, number of sweep points, etc. can be set by an external triggering source to achieve external signal triggering.

[0199] If there are 6 scan points (i.e., scan points) in the scan point list, the scan point related data input to the host computer can be shown in Table 2 below.

[0200] Table 2

[0201]

[0202] in, ~ Used to represent the frequency of scan points 1 to 6. ~ Used to represent the normalized amplitude of scan points 1 to 6.

[0203] In one embodiment, the data in Table 2 can be converted into frequency control words, amplitude control words, and phase control words by a host computer. The frequency control words, amplitude control words, and phase control words corresponding to each scan point are then provided to the programmable scanning unit in the control sub-circuit for storage as a scan point list. Here, the frequency control words, amplitude control words, and phase control words are configured for the frequency synthesizer.

[0204] For example, the host computer can calculate the frequency control word for the frequency synthesizer using the following formula (7). .

[0205] (7);

[0206] Among them, frequency The frequencies in Table 2 ~ .

[0207] The host computer can calculate the amplitude control word for the frequency synthesizer using the following formula (8). .

[0208] (8);

[0209] Among them, amplitude The amplitude can be found in Table 2 ~ .

[0210] The host computer can calculate the phase control word for the frequency synthesizer using the following formula (9). .

[0211] (9);

[0212] The phase is not shown in Table 2. Because phase changes are difficult to observe during testing, the default phase is set to 0, thus not changing the phase. Based on Tables 1 and 2 above, this timing sweep function can be set with a trigger interval of 40... , point interval 5 The frequency sweep is started by using an external trigger source.

[0213] The trigger interval refers to the interval of the trigger signal, specifically the period of the trigger signal supplied by the external trigger source to the control sub-circuit. For example, the external trigger source can supply the control sub-circuit with a 40-second trigger signal. A periodic TTL square wave triggers a frequency sweep on each rising edge.

[0214] Therefore, the programmable scanning unit can also be used to respond to scanning function commands from the host computer and adjust the output signal of the frequency synthesizer sequentially based on the scanning point order in the scanning point list to achieve the timing frequency sweep function.

[0215] Figure 7(a) shows the waveform of the timing sweep result according to an embodiment of the present invention.

[0216] Figure 7(b) shows the amplitude curve of the timing sweep result according to an embodiment of the present invention.

[0217] Figure 7(c) shows the frequency curve of the timing sweep result according to an embodiment of the present invention.

[0218] Figures 7(a) to 7(c) show the waveforms, amplitude curves, and frequency curves of the laser frequency-shifted cavity-locked signal output by the RF source circuit adjusting the output signal of the frequency synthesizer according to the scanning point order in the scanning point list.

[0219] In Figures 7(a) to 7(c), the horizontal axis represents time (in units of 10 ... The vertical axis represents voltage (in V), amplitude (in V), and frequency (in MHz), respectively.

[0220] Based on the amplitude envelope and instantaneous frequency changes over time extracted from the laser frequency-shifted cavity-locked signal using the oscilloscope shown in Figures 7(a) to 7(c), it is evident that the frequency switching process is smooth, with a minimum switching interval as low as 5. Furthermore, no significant frequency overshoot was observed.

[0221] In one embodiment, the timing frequency sweep function supports continuous preset of up to 4,000 scan points, exhibiting high flexibility in the atomic preparation stage of the strontium atom optical lattice clock. Complex frequency jump sequences can be completed with a single instruction to realize the timing frequency sweep function.

[0222] According to an embodiment of the present invention, the RF source circuit also supports a timing sweep function to sequentially adjust the output signal of the frequency synthesizer, thereby verifying the performance of the RF source circuit.

[0223] Based on the above, the control sub-circuit internally implements analog modulation, digital modulation, programmable scanning (i.e., sequential frequency sweep function) and communication to support a variety of application scenarios.

[0224] Meanwhile, the configuration of programmable chips (such as phase-locked loop sub-circuit, output power control sub-circuit, analog sampling sub-circuit, and frequency synthesizer) in the RF source circuit is achieved through an independent communication configuration module in the control sub-circuit.

[0225] Specifically, the phase-locked loop (PLL) communication configuration module: Since the fractional-frequency PLL uses a serial peripheral interface for configuration, the PLL communication configuration module can access the internal registers of the PLL sub-circuit by writing to the corresponding address via the WISHBONE bus. The PLL sub-circuit internally generates a serial waveform that meets timing requirements according to the bus commands. The digital-to-analog converter (DAC) communication configuration module: manages multiple DACs, used for voltage-controlled oscillator tuning voltage (i.e., voltage adjustment signal), voltage-controlled attenuator control voltage (i.e., the output of the DAC in the output power control sub-circuit), and fine-tuning of the temperature-controlled crystal oscillator. Each DAC uses a three-wire serial interface. The host computer sends instructions to the control sub-circuit (e.g., FPGA). After receiving the instructions, the corresponding configuration module generates pulse triggers and configuration data for the DAC chip; that is, when updating the pulse trigger, 16-bit configuration data is sent to the DAC chip. The analog-to-digital converter (ADC) communication configuration module: the ADC is configured with its operating mode via a serial interface. After configuration, the sampled data is processed by an independent analog-to-digital conversion decoding unit within the control sub-circuit. The direct digital frequency synthesizer (DFD) parallel drive: the frequency synthesizer supports both serial and parallel programming interfaces. In the control sub-circuit of this invention, the communication interface module adopts a parallel interface to achieve high-speed configuration of the frequency synthesizer. The communication interface module generates an 8-bit address, 16-bit data, and read / write control signals according to the bus command, and processes the parallel timing.

[0226] Figure 8A schematic diagram of the circuit board containing the radio frequency source circuit according to an embodiment of the present invention is shown.

[0227] like Figure 8 As shown, the circuit board illustrates the various interfaces in the RF source circuit, such as RF out, Mod_in1, Mod_in2, AM, REF out, EXT REF, Mix out, switch, and trigger, as well as the locations of the phase-locked loop sub-circuit, frequency synthesizer, analog sampling sub-circuit, control sub-circuit, and output power control sub-circuit on the circuit board.

[0228] The `switch` interface controls the on / off state of the RF source circuit's output signal. Under the custom timing sweep function, its on / off state is set via a host computer. For example, an external high / low level can be applied to the `switch` interface to control the RF source circuit's output. The `trigger` interface is the input terminal (trigger port) for the trigger signal of an external trigger source. Generally, a digital signal can be provided to the RF source circuit via a signal source or digital I / O as the trigger signal. Some functions of the RF source circuit require the rising edge of the trigger signal to operate.

[0229] In one embodiment, the circuit board can employ an eight-layer design, with the top layer serving as the primary radio frequency (RF) signal layer and the bottom layer primarily used for power distribution. The inner layers are arranged in the order of ground-signal-ground-power-signal-ground, comprising one power layer, two digital signal layers, and three ground layers. Digital and analog grounds are separated to effectively suppress digital noise coupling into the RF signals (i.e., the laser frequency-shifted cavity-locked signal). Critical RF signal traces are impedance-matched to 50Ω to optimize voltage standing wave ratio (VSWR) performance. The critical RF signals may refer to the 3.5GHz signal output from the phase-locked loop (PLL) sub-circuit and the output signal from the frequency synthesizer.

[0230] In one embodiment, the circuit board housing the RF source circuit involves a wide variety of power supplies with varying requirements. Due to the 3U (3 Unit) chassis standard design, all circuit boards draw power from the chassis backplane, thus limiting board size and requiring a uniform supply voltage of +5V and ±15V. The power supply design not only needs to minimize noise and ripple but also maximize efficiency and reduce power loss.

[0231] The LT3045 is a high-performance, low-dropout linear regulator that delivers 500mA of current at a typical dropout voltage of 260mV, with a noise RMS (Root Mean Square) value of 0.8 at 10Hz to 100kHz. It features low power supply noise, providing low-noise operation for the two-stage RF power amplifier ADL8111ACCZN (i.e., a two-stage cascaded power amplifier) ​​on the circuit board. To ensure that the two RF power amplifiers can be independently controlled for power supply, two LT3045 chips are selected for separate power supply, with a supply voltage of +5V. The ±3.3V switching voltage of the ADL8111ACCZN power amplifier has low noise requirements; therefore, two Zener diodes are used to achieve voltage conversion, which simplifies the circuit.

[0232] The AD9914 frequency synthesizer also requires protection against additional noise from the power supply. Since the AD9914's maximum operating current is 640mA, two LP38798 chips are used for power supply. These LP38798 chips feature ultra-low output noise: 5 The VRMS (10Hz to 100kHz) and maximum operating current of 800mA provide the AD9914 with +3.3V and +1.8V operating voltages, respectively.

[0233] The PLL chip (i.e., phase-locked loop sub-circuit) requires +3.8V, analog +3.3V, digital +3.3V, and +3.1V power supplies. In actual tests, the total supply current of the phase-locked loop sub-circuit under 3.5GHz lockout is 189mA. Using a single ultra-low noise, four-channel output LDO (Low Dropout Regulator) chip HMC1060LP3E can fully cover all the supply voltages.

[0234] Based on this, the power supply architecture of the RF source circuit mainly provides +15V, -15V, +5V, and ground. Multiple low-dropout linear regulators are used to supply power to each voltage domain, and ferrite beads are used to isolate the shared voltage rails of different chips (i.e., chips such as the phase-locked loop sub-circuit in the RF source circuit) to suppress noise coupling.

[0235] The circuit board designed based on the above power supply scheme conforms to the 3U chassis standard and operates by drawing power from the chassis back panel, improving system integration consistency. It communicates with the upper-level device via serial data transmission through the integrated accessory IPort-3 (embedded Ethernet to serial module IPort-3), with a baud rate of 921.6Kbps and a maximum power consumption of approximately 10W.

[0236] Figure 9(a) shows a schematic diagram of the phase noise test of the radio frequency source circuit at different carrier frequencies according to an embodiment of the present invention.

[0237] As shown in Figure 9(a), the phase noise at carrier frequencies of 10MHz, 80MHz, 100MHz, 1GHz, and 1.4GHz was measured using a Keysight E5052B signal source analyzer. The carrier frequency is the frequency of the output signal from the RF source circuit (HB_DDS). The output signal frequency (reference) of the phase-locked loop sub-circuit is 3.5GHz, and the output signal frequency of the oven-controlled crystal oscillator (OCXO) is 10MHz.

[0238] The horizontal axis of Figure 9(a) represents frequency offset (in Hz), and the vertical axis represents phase noise (in dBc / Hz). When the carrier frequency is 80MHz, the phase noise is less than -90dBc / Hz@1Hz, and the integration time jitter from 1Hz to 5MHz is 426fs.

[0239] Figure 9(b) shows a schematic diagram of phase noise testing for different signal sources according to an embodiment of the present invention.

[0240] As shown in Figure 9(b), the horizontal axis of Figure 9(b) represents frequency offset (unit: Hz), and the vertical axis represents phase noise (unit: dBc / Hz). Compared with commonly used signal sources in the laboratory (N5171B, 33600A), HB_DDS (i.e., the RF source circuit of this invention) has better phase noise performance at 100MHz output.

[0241] Therefore, although the radio frequency source circuit of the present invention has not yet reached the level of signal sources in related technologies (such as SMA-100B), it is sufficient for most cold atom experimental scenarios and its performance can be further improved by using an external reference source.

[0242] Figure 10 A schematic diagram of trigger delay test results under digital modulation according to an embodiment of the present invention is shown.

[0243] like Figure 10 As shown, the time-domain response characteristic curve of the RF source circuit during digital modulation is illustrated. The trigger delay refers to the delay provided by the external trigger source to the trigger port of the RF source circuit (e.g., ...). Figure 8 The delay from the rising edge of the trigger signal of the trigger interface shown to the modulation of the output signal of the RF source circuit or the delay from the rising edge of the trigger signal of the host computer to the modulation of the output signal of the RF source circuit. Figure 10 The horizontal axis represents time (unit: The left side of the vertical axis represents the output voltage (unit: V), and the right side represents the extracted phase information (unit: °).

[0244] Experiments showed that the total physical delay from the trigger signal received from the host computer by HB_DDS to the laser frequency-shifted cavity-locked signal output from the RF source circuit, resulting in a phase change, was 158 ns, while the total physical delay for amplitude change remained stable at 95.1 ns. This measured data verifies the effectiveness of the aforementioned timing compensation logic, ensuring data transmission accuracy under a 146MHz synchronous clock.

[0245] Figure 10 The phase curves exhibit a clear stepped distribution, and the fine time resolution of the single-step modulation response reaches 6.9 ns, corresponding to a modulation rate of 146 MHz.

[0246] Based on the above, the RF source circuit of this invention has the following advantages: High performance: The output frequency of the laser frequency-shifted cavity-locked signal reaches up to 1.4 GHz, the phase noise is lower than -90 dBc / Hz@1 Hz (at 80 MHz output), and the modulation frequency reaches 146 MHz, meeting the stringent requirements of cold atom experiments for RF signals. Multifunctional: Supports rapid modulation of frequency, phase, and amplitude, with multiple built-in scanning modes, suitable for various scenarios such as laser frequency stabilization, atomic spectral scanning, and quantum gate operations. Low latency: Phase modulation response delay is 158 ns, and amplitude modulation response delay is 95.1 ns, suitable for fast feedback control systems. High scalability: Based on FPGA architecture, it can be applied to various functionalities in specific cold atom physics experiments and is easy to integrate into complex experimental systems. Low cost and small size: Compared with signal sources in related technologies, this invention integrates modulation source (i.e., direct digital frequency synthesis kernel) generation, digital phase shifting, and square wave shaping into a single FPGA, simplifying external analog circuits and reducing system noise. This solution has significant cost advantages and high integration, exhibiting high integration and strong stability, and is suitable for space-constrained experimental platforms. Wide range of applications: Successfully applied in strontium atom optical lattice clock experiments, demonstrating excellent practicality and potential for wider adoption. Wide locking range: Through optimized high-speed data interface and modulation algorithm, it possesses an extremely wide frequency acquisition range, with a laser locking detuning threshold reaching up to 1.4 GHz, significantly improving the robustness of the optical locking system. High phase adjustment accuracy: Supports full-range, high-resolution phase adjustment from 0 to 360°, accurately matching the physical characteristics of different optical links to ensure the demodulated error signal exhibits excellent linearity and zero-crossing stability.

[0247] Therefore, the radio frequency source circuit of the present invention can solve the following problems.

[0248] To address the coherence issue, the RF source circuit of this invention, through a single-core multi-output architecture, eliminates frequency drift between the modulation and demodulation signals, ensuring long-term stability of phase-sensitive detection. Regarding the large detuning locking problem, the RF source circuit of this invention, based on laser frequency stabilization technology, generates a modulation signal (i.e., a laser frequency-shifted cavity-locked signal) that supports high bandwidth and a wide range of frequency offset compensation. This enables effective extraction of error signals and reliable locking even when there is an initial frequency difference (detuning) of up to 1.4 GHz between the laser frequency and the optical cavity resonant frequency. Regarding digital phase compensation, the RF source circuit of this invention uses a digital phase shifter to solve the transmission delay introduced by the analog link, achieving optimized adjustment of demodulation sensitivity.

[0249] Figure 11 A flowchart of a method for generating laser frequency-shifted cavity-locked signals according to an embodiment of the present invention is shown.

[0250] In one embodiment, the method 1100 can be applied as described above. Figures 1-6 and Figure 8 The RF source circuit shown is implemented.

[0251] like Figure 11 As shown, the method 1100 includes operations S1110 to S1140.

[0252] When operating S1110, the control sub-circuit receives digital control commands from the host computer and uses the synchronous clock as the working clock. Based on the preset modulation data carried by the digital control commands, it performs amplitude-phase conversion and phase waveform conversion in parallel to output phase control words and phase demodulation signals.

[0253] When operating S1120, the phase-locked loop circuit is used to multiply the reference clock and output a clock signal that matches the operating frequency of the frequency synthesizer, which is then used as the operating reference clock for the frequency synthesizer.

[0254] When operating S1130, a frequency synthesizer is used to achieve phase synchronization with the control sub-circuit by using the working reference clock as the frequency reference and combining it with the synchronization clock. Based on the phase control word, the phase of the output signal is adjusted.

[0255] In operation of S1140, the output power control sub-circuit is used to adjust the power of the output signal of the frequency synthesizer based on preset power modulation data, so as to output the laser frequency shift cavity lock signal.

[0256] Among them, the phase demodulation signal and the laser frequency shifting cavity-locking signal are used to achieve laser frequency offset locking.

[0257] According to embodiments of the present invention, the control subcircuit and the frequency synthesizer achieve synchronized timing based on a synchronous clock. The synchronous clock provided by the frequency synthesizer to the control subcircuit enables the control subcircuit to adjust the output signal of the frequency synthesizer based on the modulation rate of the synchronous clock, reducing the response delay of phase modulation and increasing the modulation rate. Since the generation of the phase control word and the phase demodulation signal are integrated into the same control subcircuit, the optical path in the sideband PDH frequency-locking experiment is simplified. Simultaneously, the control subcircuit can perform amplitude-phase conversion and phase waveform conversion in parallel based on preset modulation data, ensuring that the phase control word and the phase demodulation signal originate from the same reference (i.e., the same preset modulation data), guaranteeing strict synchronization. The use of a low-noise phase-locked loop (PLL) subcircuit in the RF source circuit reduces the phase noise of the frequency synthesizer's output signal. Furthermore, the control subcircuit, frequency synthesizer, PLL subcircuit, and output power control subcircuit in the RF source circuit are all integrated onto a single circuit board, improving integration density.

[0258] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0259] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A radio frequency source circuit, characterized in that, Integrated on the circuit board, the radio frequency source circuit includes: The control sub-circuit is electrically connected to the host computer. The control sub-circuit is used to receive digital control commands from the host computer and uses a synchronous clock as the working clock. Based on the preset modulation data carried by the digital control commands, it performs amplitude-phase conversion and phase waveform conversion in parallel to output phase control words and phase demodulation signals. The phase-locked loop circuit is used to multiply the reference clock and output a clock signal that matches the operating frequency of the frequency synthesizer, so as to serve as the operating reference clock input of the frequency synthesizer. The frequency synthesizer is electrically connected to the control sub-circuit and the phase-locked loop sub-circuit. The frequency synthesizer is used to achieve phase synchronization with the control sub-circuit by using the working reference clock as the frequency reference and combining it with the synchronization clock, and to adjust the phase of the output signal based on the phase control word. The output power control sub-circuit is electrically connected to the output terminal of the frequency synthesizer. It is used to adjust the power of the output signal of the frequency synthesizer based on preset power modulation data to output a laser frequency shift and cavity lock signal. The phase demodulation signal and the laser frequency shift and cavity lock signal are used to achieve laser frequency offset locking.

2. The radio frequency source circuit according to claim 1, characterized in that, The control sub-circuit includes a direct digital frequency synthesis core, a modulation data processing unit, a digital phase shifter, and a shaping unit; A direct digital frequency synthesis kernel is used to output amplitude data and phase accumulation value based on the frequency control word in the preset modulation data; The modulation data processing unit is electrically connected to the direct digital frequency synthesis core. The modulation data processing unit is used to linearly scale the amplitude data based on the phase modulation depth in the preset modulation data and output the phase control word. The digital phase shifter is electrically connected to the direct digital frequency synthesis core. The digital phase shifter is used to perform digital phase shifting on the phase accumulation value based on the phase shift bias in the preset modulation data to obtain the target phase value. The shaping unit is used to convert the target phase value into a square wave signal with a preset duty cycle, which is then used as a phase demodulation signal.

3. The radio frequency source circuit according to claim 2, characterized in that, The control sub-circuit also includes a clock buffer and a programmable input / output interface core; The clock buffer is electrically connected to the frequency synthesizer. The clock buffer is used to store the synchronization clock of the frequency synthesizer. The operating clock of the direct digital frequency synthesis core adopts the synchronization clock. The programmable input / output interface core is electrically connected to the modulation data processing unit and the clock buffer, and is used to perform phase calibration on the phase control word based on the synchronous clock.

4. The radio frequency source circuit according to claim 1, characterized in that, The phase-locked loop sub-circuit includes an RF interface, a temperature-controlled crystal oscillator, a relay, a fractional-frequency phase-locked loop, and a voltage-controlled oscillator; The first input terminal of the relay is electrically connected to the radio frequency interface, the second input terminal of the relay is electrically connected to the temperature-controlled crystal oscillator, and the output terminal of the relay is electrically connected to the fractional frequency division phase-locked loop. The relay is used to switch the conduction channel of the relay in response to the clock source signal from the control sub-circuit, so as to switch the channel conduction between the channel of the radio frequency interface and the channel of the temperature-controlled crystal oscillator. The radio frequency interface is used to input an external reference clock when the channel of the radio frequency interface is turned on by the relay, so as to serve as the reference clock input for the fractional frequency division phase-locked loop; Thermostatic crystal oscillator is used to output an internal reference clock when the relay turns on the channel of the thermostatic crystal oscillator, so as to serve as the reference clock input for the fractional phase-locked loop. The fractional frequency division phase-locked loop is electrically connected to the voltage-controlled oscillator. The fractional frequency division phase-locked loop is used to output a voltage adjustment signal based on the frequency difference and phase difference between the reference clock and the feedback clock output by the voltage-controlled oscillator. A voltage-controlled oscillator is used to modulate the output feedback clock according to the voltage adjustment signal until the frequency difference and phase difference meet the preset conditions, and output a clock signal that matches the operating frequency of the frequency synthesizer.

5. The radio frequency source circuit according to claim 1, characterized in that, The output power control sub-circuit includes an analog amplitude modulation interface, a digital-to-analog converter, a resistor network, a two-stage cascaded voltage-controlled attenuator, and a two-stage cascaded power amplifier. The first input terminal of the resistor network is electrically connected to the analog amplitude modulation interface, or the second input terminal of the resistor network is electrically connected to the digital-to-analog converter. The resistor network is used to take the external control signal input through the analog amplitude modulation interface or the internal control signal output by the digital-to-analog converter as the input signal of the resistor network based on the connection status of the first input terminal and the second input terminal, and output preset power modulation data based on the input signal. An analog amplitude modulation interface is used to input external control signals when the analog amplitude modulation interface is electrically connected to the first input terminal of the resistor network; The input terminal of the digital-to-analog converter is electrically connected to the digital-to-analog conversion communication module of the control sub-circuit. When the output terminal of the digital-to-analog converter is electrically connected to the second input terminal of the resistor network, the digital-to-analog converter converts the power control word received from the digital-to-analog conversion communication module of the control sub-circuit and outputs an internal control signal. The two-stage cascaded voltage-controlled attenuator is electrically connected to the resistor network and the frequency synthesizer. The two-stage cascaded voltage-controlled attenuator is used to perform power attenuation processing on the output signal of the frequency synthesizer based on preset power modulation data. The two-stage cascaded power amplifier is electrically connected to the two-stage cascaded voltage-controlled attenuator. The two-stage cascaded power amplifier is used to amplify the attenuated output signal and output the laser frequency-shifted cavity-locked signal.

6. The radio frequency source circuit according to claim 5, characterized in that, The radio frequency source circuit also includes an analog sampling sub-circuit, which comprises a differential amplifier unit and an analog-to-digital converter unit. When the modulation method is analog modulation... The differential amplifier unit is electrically connected to an external analog signal source and is used to differentially amplify the two acquired external analog signals respectively; The input terminal of the analog-to-digital converter is electrically connected to the output terminal of the frequency synthesizer and the output terminal of the differential amplifier unit. The analog-to-digital converter unit is used to use the synchronous clock as the working clock and to perform analog-to-digital conversion and parallel-to-serial conversion on each differentially amplified analog signal to obtain an analog modulated signal.

7. The radio frequency source circuit according to claim 6, characterized in that, The control sub-circuit also includes an analog-to-digital conversion decoding unit, the input of which is electrically connected to the output of the analog sampling sub-circuit. The analog-to-digital conversion decoding unit is used to decode the analog modulation signal to obtain the voltage code value, and based on the preset code value from the host computer, process the voltage code value to obtain the external phase control word.

8. The radio frequency source circuit according to claim 7, characterized in that, The frequency synthesizer is also used to achieve phase synchronization with the control sub-circuit by using the working reference clock as the frequency reference and combining it with the synchronization clock, and to adjust the phase of the output signal based on the external phase control word.

9. The radio frequency source circuit according to any one of claims 1 to 8, characterized in that, The control sub-circuit also includes a programmable scanning unit, which is electrically connected to the frequency synthesizer. A programmable scanning unit is used to store a list of scanning points, wherein the scanning point data in the list consists of a frequency control word, an amplitude control word, and a phase control word; The programmable scanning unit is also used to adjust the output signal of the frequency synthesizer sequentially based on the scanning point order in the scanning point list in response to scanning function commands from the host computer.

10. A method for generating a laser frequency-shifted cavity-locked signal, characterized in that, The application of the radio frequency source circuit as described in any one of claims 1 to 9 includes: Using the control sub-circuit, it receives digital control commands from the host computer and uses the synchronous clock as the working clock. Based on the preset modulation data carried by the digital control commands, it performs amplitude-phase conversion and phase waveform conversion in parallel to output phase control words and phase demodulation signals. Using a phase-locked loop circuit, the reference clock is multiplied to output a clock signal that matches the operating frequency of the frequency synthesizer, which is then used as the operating reference clock for the frequency synthesizer. Using a frequency synthesizer, with the working reference clock as the frequency base, and combined with a synchronization clock, phase synchronization with the control sub-circuit is achieved, and the phase of the output signal is adjusted based on the phase control word; The output power control sub-circuit adjusts the power of the output signal of the frequency synthesizer based on preset power modulation data to output a laser frequency shift and cavity lock signal. The phase demodulation signal and the laser frequency shift and cavity lock signal are used to achieve laser frequency offset locking.

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