Phase-locked loop and method of generating an output clock with reduced jitter

Abstract

A phase-locked loop and a method for generating an output clock with reduced jitter. The phase-locked loop with reduced jitter comprises a phase detector for comparing a phase of a reference clock with a phase of a feedback clock to generate a plurality of up and down control signals; a voltage-controlled oscillator for generating an oscillation signal according to the plurality of up and down control signals; an output divider for dividing the oscillation signal to generate the output clock; a non-integer feedback divider for dividing the oscillation signal according to a modulated sequence to generate a modulated clock; a divider in series with the non-integer feedback divider and for dividing the modulated clock by a fixed modulus to generate a divided clock; wherein a frequency of the modulated clock is an integer multiple of a frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.

Description

Technical Field

[0001] This invention relates to phase-locked loops (PLLs), and more particularly to a PLL that can reduce output jitter. Background Technology

[0002] A standard phase-locked loop (PLL) uses negative feedback for frequency multiplication and generates a more stable output frequency relative to the comparison frequency of a phase detector by comparing a reference frequency with a feedback frequency provided by the negative feedback mechanism. The reference frequency is an input signal divided by a factor N. Once the PLL is locked, the output frequency equals N * the reference frequency. Therefore, by changing the value of N, the PLL can be tuned within a specific frequency band, provided the minimum frequency resolution equals the reference frequency. When a new value of N is programmed, the PLL establishes an error voltage based on the phase difference between the two input signals, which drives a voltage oscillator to generate the output frequency.

[0003] Please refer to Figure 1 , Figure 1 The diagram shows a phase-locked loop 100. Figure 1 As shown, the phase-locked loop 100 includes a reference divider 110, a phase frequency detector (PFD) 120, a charge pump 130, a loop filter (LPF) 140, a voltage controlled oscillator (VCO) 150, and an output divider 160. In addition, the phase-locked loop 100 includes a feedback loop, wherein the feedback loop includes a feedback divider 170 and a sigmoid modulator (SDM) 180.

[0004] Reference divider 110 receives an input signal / clock and divides the input signal / clock to generate a reference clock REF CLK. The reference clock REF CLK is input to phase frequency detector 120, which compares the positive edge of the reference clock REF CLK with the positive edge of a feedback signal FE CLK output by self-feedback divider 170 to generate a digital output. The digital output can be a pulse signal whose width is proportional to the phase difference between the two positive edges of the two signals (i.e., the reference clock REF CLK and the feedback signal FE CLK). The pulse signal is also input to charge pump 130 to generate an analog current representing the phase error. The analog current is input to loop filter 140 to generate a voltage-controlled oscillator (VCO) control voltage to drive VCO 150. The multi-phase output VCO CLK generated by VCO 150 is input to output divider 160 to generate an output clock OUT CLK. The multi-phase output VCO CLK may have a frequency that is an integer multiple of the reference clock REF CLK and is further transmitted to feedback divider 170. Feedback divider 170 generates a feedback clock FB CLK that is transmitted to phase frequency detector 120 by comparing the multi-phase output VCO CLK with a divider modulus N to form a feedback loop. When the phase-locked loop 100 is locked, the reference clock REK CLK and the feedback clock FB CLK are equal, so that the multi-phase output VCO CLK is the result of multiplying the divider modulus N and the feedback clock FB CLK (i.e., VCO CLK = N * FB CLK). Therefore, the output frequency of the output clock OUT CLK can be changed by changing the value of the divider modulus N.

[0005] Phase-locked loop 100 acts as a low-pass filter relative to the output of either the reference clock REK CLK or the charge pump 130, and it can suppress high-frequency jitter. Relative to the noise output of the voltage-controlled oscillator 150, phase-locked loop 100 acts as a high-pass filter; therefore, the noise output of phase-locked loop 100 depends on the operating bandwidth (e.g., a modulation frequency at which phase-locked loop 100 can maintain a locked state). Because the phase frequency detector 120 performs discrete sampling at the edge of the reference clock REK CLK, the bandwidth of the loop filter 140 is approximately one-tenth of the reference frequency. Although increasing the bandwidth of the loop filter 140 can improve the set-time (e.g., lock-in time) of the phase-locked loop 100, the output clock OUT CLK may become unstable at higher reference frequencies. Although a lower reference frequency can improve the frequency resolution of the phase-locked loop 100, it will also increase the set-time of the phase-locked loop 100 and the noise output by the voltage-controlled oscillator 150. Therefore, there is a tradeoff between the bandwidth and tuning resolution of the phase-locked loop 100.

[0006] To improve tuning resolution, non-integer phase-locked loops have been developed where the divider modulus N is not restricted to an integer, allowing for greater fine-tuning. Since the divider modulus N cannot actually be a non-integer, it is updated every reference cycle, for example, by switching between two different integer values ​​(e.g., N and N+1) of the divider modulus N. Over multiple clock cycles, the average value of the divider modulus N can converge to the desired non-integer value.

[0007] Since the difference between the actual divider modulus and the ideal (e.g., average) divider modulus is considered an error, phase noise is generated, which leads to a spurious tone at low frequencies. The only way to suppress the spurious tone is to reduce the bandwidth of the phase-locked loop 100, which is impractical for most applications. Therefore, the phase-locked loop 100 (especially the feedback loop) includes a trigonometric modulator 180, which addresses the aforementioned problem by introducing randomness into the modulus to break the periodicity. The random sequence generated by the trigonometric modulator 180 ensures that the quantization noise has maximum power in a frequency band higher than the bandwidth required by the phase-locked loop 100.

[0008] However, the dynamic and periodic variations in the divider value can introduce periodic low-frequency interference. This quantization noise typically peaks at half the frequency of the delta-integral modulator clock SDM CLK, and the delta-integral modulator clock SDM CLK is usually located at the frequency of the feedback clock FB CLK (i.e., the frequency F of the reference clock REF CLK). REF (Same), its peak value representing quantization noise is located at F REF / 2. Due to the characteristic of the phase-locked loop 100 that low-frequency signals will pass through the loop filter 140, this low-frequency interference will also pass through and appear in the output clock OUT CLK.

[0009] One way to reduce this noise is to reduce the bandwidth of the phase-locked loop 100 so that less jitter passes through the loop filter 140. This leads to the same problem present in standard non-integer phase-locked loops, namely, the loop filter 140 must have a sufficiently small bandwidth to provide a stable output and prevent voltage-controlled oscillator drift. Furthermore, some programs have specific protocols that require specific operating bandwidths.

[0010] U.S. Patent No. 9,559,704 discloses a multiplier coupled to a trigonometric integrator and a frequency divider coupled between the trigonometric integrator and a non-integer frequency divider, wherein both the multiplier and the frequency divider have the same modulus. This architecture allows for greater fine-tuning resolution; for example, if the modulus is 2, this circuit can provide a modulus that varies between N and N+0.5, rather than between N and N+1 (e.g., the modulus in the standard phase-locked loop described above).

[0011] Furthermore, U.S. Patent No. 8,933,733 teaches a phase-locked loop that can operate in both integer and non-integer modes by means of a multi-modulus divider (MMD) connected in parallel with an integer divider, and a multiplexer (MUX) that can receive multiple outputs from the integer divider and the MMD divider and dynamically select among the multiple outputs based on a specific reference clock source.

[0012] Although the two existing technologies mentioned above improve the performance of the phase-locked loop by increasing the tuning resolution, the noise generated by the trigonometric modulator may still exist in the output, and therefore the jitter problem is not solved.

[0013] Therefore, there is a great need for a novel method that can reduce the noise generated by non-integer phase-locked loops of trigonometric integrals without reducing the operating bandwidth, in order to solve the above problems. Summary of the Invention

[0014] Therefore, one of the objectives of this invention is to provide a circuit and a related method for generating a phase-locked loop output clock with reduced jitter, in order to solve the above-mentioned problems.

[0015] According to an embodiment of the present invention, a phase-locked loop (PLL) is provided. The PLL includes a phase detector, a voltage-controlled oscillator (VCO), an output divider, and a feedback loop. The phase detector receives a reference clock and a feedback clock, and compares a phase of the reference clock with a phase of the feedback clock to generate a plurality of up / down control signals. The VCO generates an oscillation signal based on the plurality of up / down control signals. The output divider divides the oscillation signal to generate an output clock. The feedback loop receives the oscillation signal and divides it according to a modulus to generate a feedback clock. The feedback loop includes a non-integer feedback divider and a frequency divider. The non-integer feedback divider receives the oscillation signal and divides it according to a modulated sequence to generate a modulated clock, wherein an average of the modulated sequence is a non-integer over a plurality of clock cycles. The frequency divider is connected in series with the non-integer feedback divider and divides the modulated clock of the non-integer feedback divider by a fixed modulus to generate a divided clock. The frequency of the modulated clock of the non-integer feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.

[0016] The feedback loop also includes a trigonometric integrator modulator coupled to a non-integer feedback divider, used to generate a modulated sequence based on an integer division factor and a non-integer division factor. The trigonometric integrator modulator further generates and transmits a phase selection signal to the non-integer feedback divider, and receives the modulated clock from the non-integer feedback divider. A multiplexer is used to: receive the divided clock from the divider; receive the modulated clock from the trigonometric integrator modulator; and output the divided or modulated clock to a phase detector as a feedback clock based on an input signal. When the input signal is a high voltage level, the phase-locked loop is configured as an integer N phase-locked loop, the trigonometric integrator modulator generates the modulated sequence based only on an integer input, and the multiplexer directly selects the modulated clock output from the non-integer feedback divider as the feedback clock. When the input signal is at a low voltage level, the phase-locked loop is configured as a non-integer N-phase-locked loop. The triangular integral modulator generates the modulated sequence based on the integer input and a non-integer input, and the multiplexer selects the divided clock from the frequency divider output as the feedback clock.

[0017] The phase-locked loop also includes a charge pump and a loop filter, wherein the charge pump generates an analog control signal based on multiple up and down control signals output by the phase detector; and the loop filter filters the analog control signal to generate a filtered signal, which is then input to the voltage-controlled oscillator. In one embodiment, the frequency of the modulated clock of the non-integer feedback divider is twice the frequency of the divided clock.

[0018] According to an embodiment of the present invention, a method is provided for generating an output clock with reduced jitter from a reference clock. The method includes: receiving a reference clock and a feedback clock, and comparing a phase of the reference clock with a phase of the feedback clock to generate a plurality of up / down control signals; generating an oscillation signal based on the plurality of up / down control signals; performing a frequency division operation on the oscillation signal according to a modulated sequence to generate a modulated clock, wherein an average of the modulated sequence is a non-integer over a plurality of clock cycles; performing a frequency division operation on the modulated clock using a fixed modulus to generate a divided clock; and using one of the modulated clock and the divided clock as a feedback clock, wherein a frequency of the modulated clock is an integer multiple of a frequency of the divided clock.

[0019] The step of frequency division of the oscillating signal based on the modulated sequence further includes: generating the modulated sequence based on an integer frequency division factor and a non-integer frequency division factor. The method also includes: generating a phase selection signal.

[0020] The step of generating an oscillation signal based on the plurality of up and down control signals includes: generating an analog control signal based on the plurality of up and down control signals; and filtering the analog control signal to generate a filtered signal, wherein the filtered signal is used to generate the oscillation signal.

[0021] Based on an input signal, one of the frequency-divided clock and the modulated clock is used as the feedback clock. When the input signal is at a high voltage level, the modulated clock is selected as the feedback clock; and when the input signal is at a low voltage level, the frequency-divided clock is selected as the feedback clock. In one embodiment, the frequency of the modulated clock is twice the frequency of the frequency-divided clock. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a phase-locked loop.

[0023] Figure 2 This is a schematic diagram of a phase-locked loop according to an embodiment of the present invention.

[0024] Figure 3A for Figure 2 The diagram shows the operation of a phase-locked loop in non-integer mode.

[0025] Figure 3B for Figure 2 The diagram shown illustrates the operation of a phase-locked loop in integer mode.

[0026] Figure 4A for Figure 1 The diagram shows the operation of the phase-locked loop.

[0027] Figure 4B for Figure 2 The diagram shows the operation of the phase-locked loop.

[0028] [Symbol Explanation]

[0029] 100, 200: Phase-locked loop

[0030] 110, 210: Reference frequency divider

[0031] 120, 220: Phase-frequency detectors

[0032] 130, 230: Charge pump

[0033] 140, 240: Loop Filters

[0034] 150, 250: Voltage-controlled oscillators

[0035] 160, 260: Output frequency dividers

[0036] 165, 265:4 frequency divider circuit

[0037] 170: Feedback divider

[0038] 180, 280: Trigonometric Integral Modulator

[0039] REF CLK: Reference clock

[0040] OUT CLK: Output clock

[0041] FB CLK: Feedback Clock

[0042] VCO CLK, VCO CLK <p:0>VCO CLK<3:0>: Multi-phase output

[0043] 273: Non-integer feedback frequency divider

[0044] 275: Frequency divider

[0045] 290: Multiplexer

[0046] SDM CLK: Trigonometric Integrator Modulator Clock

[0047] PHASE SELECT <p:0>PHASE SELECT<3:0>: Phase selection signal

[0048] N DIV: Modulus

[0049] VCO_DIV CLK: Multi-phase output after frequency division Detailed Implementation

[0050] The main objective of this invention is to provide a phase-locked loop that can generate a trigonometric modulator clock at a frequency higher than a reference frequency in a non-integer mode, such that the phase noise / jitter generated by the trigonometric modulator in the phase-locked loop also appears at a higher frequency and can therefore be filtered out by the low filtering characteristics of the phase-locked loop.

[0051] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a phase-locked loop 200 according to an embodiment of the present invention, wherein the phase-locked loop 200 includes a reference frequency divider 210, a phase frequency detector 220, a charge pump 230, a loop filter 240, a voltage-controlled oscillator 250, and an output frequency divider 260. Figure 1 Compared to the phase-locked loop 100 shown, the difference between phase-locked loop 200 and phase-locked loop 100 lies in the feedback loop, such as... Figure 2 As shown, the feedback loop of the phase-locked loop 200 includes two frequency dividers connected in series (e.g., a non-integer feedback frequency divider 273 and a frequency divider 275), a trigonometric modulator 280, and a multiplexer 290.

[0052] As previously described, a trigonometric integral modulator is used to generate a random sequence to achieve a desired non-integer modulus, wherein the non-integer modulus may include an integer part and a non-integer part. In this embodiment, the integer part (denoted as "INTEGER" for simplicity) and the non-integer part (denoted as "FRACTION" for simplicity) of the non-integer modulus are input to the trigonometric integral modulator 280, and the trigonometric integral modulator 280 can use these inputs to generate and transmit a modulus NDIV to the non-integer feedback divider 273, wherein the modulus NDIV can change dynamically for each clock cycle. The trigonometric integral modulator 280 further generates and transmits a phase selection signal PHASE SELECT. <p:0>The non-integer feedback frequency divider 273, and the non-integer feedback frequency divider 273 receive a multi-phase output VCO CLK from the voltage-controlled oscillator 250. <p:0>The phase selection signal PHASE SELECT <p:0>It is used in conjunction with the modulus N DIV (e.g., a modulated sequence) to adjust the multi-phase output VCO CLK according to the modulus N DIV (e.g., the modulated sequence). <p:0>Perform frequency division operation.

[0053] Furthermore, phase-locked loop 200 is operated as a standard trigonometric integral non-integer phase-locked loop, and... Figure 1 The difference in the phase-locked loop 100 shown lies in the frequency divider 275. By connecting the frequency divider 275 in series with the non-integer feedback frequency divider 270, the triangular integral modulator clock SDM CLK generated by the non-integer feedback frequency divider 273 can be generated at twice the required frequency, while still allowing the feedback clock FB CLK to be generated at its required frequency. In this way, the quantization noise generated by the integral modulator clock SDM CLK in the phase-locked loop 200 can reach a peak frequency at a higher frequency than that of the integral modulator clock SDM CLK in the phase-locked loop 100, and can be filtered out by the phase-locked loop 200.

[0054] Furthermore, the phase-locked loop 200 can be operated in both integer and non-integer modes via the multiplexer 290, such as... Figure 2 As shown, multiplexer 290 receives the divided clock from frequency divider 275 and the trigonometric integral modulator clock SDM CLK from non-integer feedback frequency divider 273, wherein the trigonometric integral modulator clock SDM CLK is fed back to trigonometric integral modulator 280. An input signal (labeled "Integer mode" for simplicity) is input to multiplexer 290, wherein when the input signal is active, phase-locked loop 200 operates in integer mode, and when the input signal is invalid, phase-locked loop 200 operates in non-integer mode.

[0055] Please refer to Figure 3A , Figure 3A for Figure 2 The diagram illustrates the operation of the phase-locked loop 200 in non-integer mode. Since the triangular-integral modulator 280 generates and transmits the modulated sequence to the non-integer feedback divider 273, a non-integer modulus can be generated. The triangular-integral modulator 280 receives both integer and non-integer inputs and generates and transmits the modulus NDIV (e.g., the modulated sequence) and the phase selection signal PHASE SELECT. <p:0>The non-integer feedback frequency divider 273 feeds back the triangular integral modulator clock SDM CLK to the triangular integral modulator 280 but not to the multiplexer 290. The multiplexer 290 outputs the divided clock received from the frequency divider 275 as the feedback clock FB CLK. Due to the factor of the frequency divider 275, the frequency of the feedback clock FB CLK is lower than the frequency of the triangular integral modulator clock SDM CLK.

[0056] Please refer to Figure 3B , Figure 3B for Figure 2 The diagram shown illustrates the operation of the phase-locked loop 200 in integer mode. (As shown...) Figure 3B As shown, no non-integer inputs are input to the trigonometric integrator 280. Furthermore, the phase selection signal PHASE SELECT from the trigonometric integrator 280... <p:0>The signal will not be input to the non-integer feedback divider 273, thus the same modulus will be applied to the non-integer feedback divider 273 for each clock cycle. Although the delta-sigma modulator clock SDM CLK is input to the divider 275, the signal generated by the divider 275 will not be output to the multiplexer 290 because the input signal is valid. Therefore, the delta-sigma modulator clock SDM CLK without division is directly input to the multiplexer 290 and fed back to the delta-sigma modulator 280. In this case, the phase-locked loop 200 is operated as a standard integer phase-locked loop, where the frequency of the delta-sigma modulator clock SDM CLK is the same as the feedback frequency FB CLK.

[0057] By using frequency divider 275, the frequency of the delta-integral modulator clock SDM CLK of phase-locked loop 200 is twice that of the delta-integral modulator clock SDM CLK of phase-locked loop 100, but it can still be divided to a frequency close to the reference clock REF CLK. Due to the low-pass filtering characteristics of loop filter 240, the higher frequency portion will not pass through the output, thus resulting in less overall jitter.

[0058] Figure 4A for Figure 1 The diagram shows the operation of the phase-locked loop 100. The phase-locked loop 100 also includes a divide-by-4 circuit 165. Note that this is for illustrative purposes only; the phase-locked loop 100 may include divide-by-4 circuits with different moduli or may not have any divide-by-4 circuits. Assuming the voltage-controlled oscillator 150 is to be operated at 10.25 GHz, the input to the delta-sigma modulator 180 is an integer value (e.g., 25) and a non-integer value (e.g., 0.625). Through the divide-by-4 circuit 165, the multi-phase output VCO_DIV CLK after division can be <3:0>, and the phase selection signal generated by the delta-sigma modulator 180 can also be <3:0>, which will cause the delta-sigma modulator clock SDM CLK to be generated at a frequency of 100 MHz.

[0059] Figure 4B According to an embodiment of the present invention Figure 2 The diagram shows the operation of the phase-locked loop 200, where the phase-locked loop 200 operates in non-integer mode. (See diagram for example.) Figure 4B As shown, the phase-locked loop 200 also includes a divide-by-4 circuit 265, enabling multi-phase output VCO CLK. <p:0>It can be VCO CLK<3:0>, and the phase selection signal PHASE SELECT generated by the triangular integral modulator 280. <p:0>This could be PHASE SELECT<3:0>. In this embodiment, the frequency divider 275 has a modulus of 2, and the input to the delta-sigma modulator 280 is an integer (e.g., 12) and a non-integer (e.g., 0.825). When the phase-locked loop 200 operates in non-integer mode, the output of the frequency divider 275 can be input to the multiplexer 290 and fed back to the delta-sigma modulator 280. Due to the presence of the frequency divider 275 with a modulus of 2, the delta-sigma modulator clock SDM CLK can be generated at a frequency of 200MHz, which is then divided by 2 to generate the feedback clock FB CLK at a frequency of 100MHz. Any noise generated by the feedback to the delta-sigma modulator 280 can be located at a higher frequency and therefore will not pass through the loop filter 240. Thus, the output of the phase-locked loop 200 has less noise compared to the phase-locked loop 100.

[0060] The design of the trigonometric integral modulator 280 will affect the size of the frequency divider 275, and the size of the trigonometric integral modulator 280 and the frequency divider 275, as well as the frequency of the input clock, depend on the target to be achieved.

[0061] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A phase-locked loop with reduced jitter, comprising: A phase detector is used to receive a reference clock and a feedback clock, and compare the phase of the reference clock with the phase of the feedback clock to generate multiple up and down control signals. A voltage-controlled oscillator is used to generate an oscillation signal based on the multiple up and down control signals; The output frequency divider is used to divide the oscillation signal to generate an output clock. as well as A feedback loop, used to receive the oscillation signal and divide the oscillation signal according to the modulus to generate the feedback clock, includes: A non-integer feedback frequency divider is used to receive the oscillation signal and divide the oscillation signal according to the modulated sequence to generate a modulated clock, wherein the average of the modulated sequence is non-integer over multiple clock cycles. as well as A frequency divider is connected in series with the non-integer feedback frequency divider and is used to divide the modulated clock of the non-integer feedback frequency divider by a fixed modulus to generate a divided clock. The frequency of the modulated clock of the non-integer feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and the divided clock is used as the feedback clock.

2. The phase-locked loop as described in claim 1, wherein the feedback loop further comprises: A triangular integral modulator, coupled to the non-integer feedback divider, is used to generate the modulated sequence based on integer and non-integer division factors.

3. The phase-locked loop as claimed in claim 2, wherein the triangular integral modulator is further configured to generate and transmit a phase selection signal to the non-integer feedback divider, and to receive the modulated clock from the non-integer feedback divider.

4. The phase-locked loop as described in claim 3 further comprises: Multiplexers are used to: The frequency divider receives the divided clock signal; The modulated clock is received from the trigonometric integrator; and The frequency-divided clock or the modulated clock is output to the phase detector based on the input signal as the feedback clock.

5. The phase-locked loop as claimed in claim 4, wherein when the input signal is at a high voltage level, the phase-locked loop is configured as an integer N phase-locked loop, the trigonometric modulator generates the modulated sequence based solely on the integer input, and the multiplexer directly selects the modulated clock output from the non-integer feedback divider as the feedback clock; and when the input signal is at a low voltage level, the phase-locked loop is configured as a non-integer N phase-locked loop, the trigonometric modulator generates the modulated sequence based on both the integer and non-integer inputs, and the multiplexer selects the divided clock output from the divider as the feedback clock.

6. The phase-locked loop as described in claim 2, further comprising: A charge pump for generating analog control signals based on the plurality of up and down control signals output by the phase detector; and A loop filter is used to filter the analog control signal to generate a filtered signal, which is then input to the voltage-controlled oscillator.

7. The phase-locked loop of claim 1, wherein the frequency of the modulated clock of the non-integer feedback divider is twice the frequency of the divided clock.

8. A method for generating an output clock with reduced jitter from a self-referenced clock, comprising: The system receives the reference clock and the feedback clock, and compares the phase of the reference clock with the phase of the feedback clock to generate multiple up and down control signals. An oscillation signal is generated based on these multiple up and down control signals; The oscillating signal is divided according to the modulated sequence to generate a modulated clock, wherein the average of the modulated sequence is a non-integer over multiple clock cycles. The modulated clock is divided by a fixed modulus to generate a divided clock. as well as The modulated clock and one of the divided clocks are used as the feedback clock; The frequency of the modulated clock is an integer multiple of the frequency of the divided clock.

9. The method of claim 8, wherein the step of performing a frequency division operation on the oscillation signal based on the modulated sequence further comprises: The modulated sequence is generated based on integer and non-integer frequency division factors.

10. The method of claim 9, further comprising: Generate a phase-selective signal.

11. The method of claim 8, further comprising: The feedback clock is one of the frequency-divided clock and the modulated clock, depending on the input signal.

12. The method of claim 11, wherein when the input signal is at a high voltage level, the modulated clock is selected as the feedback clock; and when the input signal is at a low voltage level, the frequency-divided clock is selected as the feedback clock.

13. The method of claim 8, wherein the step of generating the oscillation signal based on the plurality of up and down control signals comprises: Analog control signals are generated based on these multiple up and down control signals; and The analog control signal is filtered to generate a filtered signal, which is then used to generate the oscillation signal.

14. The method of claim 8, wherein the frequency of the modulated clock is twice the frequency of the divided clock.

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