Skew resistance PID device and processing method

The skew-resistant PID device and method address load imbalance in PID-Join algorithms by duplicating Join keys on banks and ranks, optimizing data distribution, and performing set-aware partitioning to enhance parallel processing performance and efficiency.

JP2026079660AActive Publication Date: 2026-05-15IND ACADEMIC COOP FOUND YONSEI UNIV
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
IND ACADEMIC COOP FOUND YONSEI UNIV
Filing Date
2025-02-19
Publication Date
2026-05-15

AI Technical Summary

Technical Problem

Existing PID-Join algorithms suffer from reduced performance and scalability due to load imbalance caused by skewed input tables, which leads to some IDPs processing data while others remain idle.

Method used

A skew-resistant PID device and processing method that duplicates Join keys on a bank and rank basis, determines an optimal replication ratio through a cost model, and performs Bank and Rank Set-aware Partitioning to distribute data evenly among IDPs, using a Host-to-DIMM scatter operation and All-to-All Inter-IDP Shuffle to ensure balanced processing.

Benefits of technology

Improves parallel processing performance by reducing load imbalance and optimizing data distribution, resulting in faster and more efficient Join operations even with skewed data distributions.

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Abstract

The objective is to provide a skew resistance PID device and processing method with improved parallel processing performance of an IDP (In-DIMM Processor). [Solution] The skew resistance PID device according to the present invention comprises a DIMM (Dual In-line Memory Module) consisting of multiple ranks, each containing multiple banks, and including an IDP that processes internal memory operations; a memory controller; and a host CPU connected to the DIMM via the memory controller, which duplicates Join keys on a bank and rank basis to improve the parallel processing performance of the IDP.
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