Stacked integrated circuit elements

Abstract

To provide stacked integrated circuit elements that can be scaled down. [Solution] The stacked integrated circuit element according to the present invention includes a lower transistor and an upper transistor, each arranged on either side of a coupled gate cut structure among a plurality of lower transistors and a plurality of upper transistors, wherein the lower gate electrode and the upper gate electrode are electrically connected to each other adjacent to each other via a connecting extension of the upper gate electrode, and the lower gate electrode and the upper gate electrode are cross-coupled transistors, the connecting extension being the portion of the upper gate electrode that remains without being removed in the process of forming the coupled gate cut structure.

Description

Technical Field

[0001] The present invention relates to an integrated circuit device, and more particularly to a stacked integrated circuit device capable of scaling down.

Background Art

[0002] With the development of electronic technology, the down-scaling of integrated circuit devices is rapidly progressing. In addition, in order to further increase the integration density of integrated circuit devices, stacked integrated circuit devices have been studied, and improving their performance has become an everyday issue.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the problems in the above-described conventional stacked integrated circuit devices, and an object of the present invention is to provide a stacked integrated circuit device capable of scaling down.

Means for Solving the Problems

[0004] To achieve the above objective, the stacked integrated circuit element according to the present invention comprises a plurality of nanosheet stacked structures arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, each including a lower nanosheet stacked structure and an upper nanosheet stacked structure disposed on the lower nanosheet stacked structure; a gate isolation portion interposed between the lower nanosheet stacked structure and the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; a lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures; an upper gate electrode enclosing the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; and adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures. The nanosheet stacking structure comprises a lower gate cut structure disposed between two lower nanosheet stacking structures included in the two nanosheet stacking structures in at least one of the spaces between the two nanosheet stacking structures, an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacking structures included in the two nanosheet stacking structures, and a bonded gate cut structure disposed between the two nanosheet stacking structures in at least one other space between two adjacent nanosheet stacking structures along the second horizontal direction among the plurality of nanosheet stacking structures, wherein the upper gate electrode extends along the side surface of the bonded gate cut structure and is connected to the lower gate electrode.

[0005] Furthermore, the stacked integrated circuit element according to the present invention, made to achieve the above objective, comprises a plurality of nanosheet stacked structures arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, each including a lower nanosheet stacked structure and an upper nanosheet stacked structure disposed on the lower nanosheet stacked structure; an intermediate insulating layer interposed between the lower nanosheet stacked structure and the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; a lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures; an upper gate electrode enclosing the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; and at least the space between two adjacent nanosheet stacked structures along the second horizontal direction within the plurality of nanosheet stacked structures. The invention comprises a lower gate cut structure disposed in one space between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures, and a bonded gate cut structure disposed between the two nanosheet stacked structures in at least one other space in the space between two adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures, wherein the upper gate electrode includes a connecting extension portion that extends along the side surface of the bonded gate cut structure and connects to the lower gate electrode, and a protruding portion that projects vertically from a portion overlapping with the intermediate insulating layer to a portion overlapping with the lower gate cut structure.

[0006] Furthermore, the stacked integrated circuit element according to the present invention, made to achieve the above objective, includes a plurality of nanosheet stacked structures, each comprising: a lower nanosheet stacked structure consisting of a plurality of lower nanosheets arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and each separated from each other along the vertical direction; an upper nanosheet stacked structure consisting of a plurality of upper nanosheets arranged on the lower nanosheet stacked structure and separated from each other along the vertical direction; a gate isolation portion interposed between the lower nanosheet stacked structure and the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; a lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures; an upper gate electrode enclosing the upper nanosheet stacked structure of each of the plurality of nanosheet stacked structures; and in at least one space between two adjacent nanosheet stacked structures along the second horizontal direction within the plurality of nanosheet stacked structures, the two nanosheets The nanosheet stacked structure comprises a lower gate cut structure disposed between two lower nanosheet stacked structures, an upper gate cut structure disposed on the lower gate cut structure between two upper nanosheet stacked structures, and a bonded gate cut structure disposed between the two nanosheet stacked structures in at least one other space in the space between two adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures, wherein the upper gate electrode includes a connecting extension portion that extends along the side surface of the bonded gate cut structure and connects to the lower gate electrode, and a protruding portion that projects from a portion overlapping with the gate separation portion in the vertical direction to a portion overlapping with the lower gate cut structure, covering a portion of the upper surface of the lower gate cut structure, wherein the horizontal width of each of the plurality of lower nanosheets is greater than the horizontal width of each of the plurality of upper nanosheets. [Effects of the Invention]

[0007] According to the stacked integrated circuit element of the present invention, the lower transistors and upper transistors, respectively, arranged on either side of a coupled gate cut structure among a plurality of lower transistors and a plurality of upper transistors, include at least one pair of transistors in which the lower gate electrode and the upper gate electrode are electrically connected to each other adjacent to each other via a connecting extension of the upper gate electrode and are cross-coupled. Furthermore, since the connecting extension is the portion of the upper gate electrode that remains without being removed during the process of forming the bonded gate cut structure, a separate patterning process is not required to form the connecting extension. Therefore, scaling down is possible, and the integration density can be further increased. [Brief explanation of the drawing]

[0008] [Figure 1] This is an equivalent circuit diagram of a stacked integrated circuit element according to an embodiment of the present invention. [Figure 2] This is a schematic layout illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 3A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 3B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 3C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 4A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 4B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 4C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 5A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 5B]This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 5C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 6A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 6B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 6C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 7A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 7B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 7C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 8A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 8B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 8C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 9A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 9B] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 9C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 10A] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 10B]A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 10C] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 11A] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 11B] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 11C] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 12A] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 12B] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 12C] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 13A] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 13B] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 13C] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 14A] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 14B] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 14C] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 15A] A cross-sectional view for explaining a method of manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 15B]This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 15C] This is a cross-sectional view illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 16A] This is a cross-sectional view showing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 16B] This is a cross-sectional view showing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 16C] This is a cross-sectional view showing a stacked integrated circuit element according to an embodiment of the present invention. [Figure 17] This is a cross-sectional view showing a stacked integrated circuit element according to another embodiment of the present invention. [Figure 18] This is a cross-sectional view showing a stacked integrated circuit element according to another embodiment of the present invention. [Modes for carrying out the invention]

[0009] Next, specific examples of embodiments for implementing the stacked integrated circuit element according to the present invention will be described with reference to the drawings.

[0010] Figure 1 is an equivalent circuit diagram of a stacked integrated circuit element according to an embodiment of the present invention. Referring to Figure 1, the stacked integrated circuit element 1000 according to an embodiment of the present invention includes a plurality of transistors. The stacked integrated circuit element 1000 includes at least one pair of cross-coupled transistors.

[0011] "Cross-coupled" means that two similar devices are connected in parallel, but the output of one device moves to the input of the other. For example, cross-coupled NAND gates (negative-AND gates) create an SR flip-flop or latch. In one embodiment, at least some of the multiple transistors included in the stacked integrated circuit element 1000 constitute a static random access memory (SRAM), but this is not limited to the embodiment. SRAM is a type of random-access memory that uses latch circuits to store one or more bits. Figure 1 shows the equivalent circuit diagram of the SRAM included in the stacked integrated circuit element 1000.

[0012] SRAM contains six metal oxide semiconductor field-effect transistors (MOSFETs). The six MOSFETs consist of two pull-up transistors (PU), two pull-down transistors (PD), and two pass-gate transistors (PG). The corresponding pull-up transistors PU and pull-down transistors PD form an inverter, and the two inverters formed by two pull-up transistors PU and two pull-down transistors PD are cross-connected. For example, the gate of the pull-up transistor PU and the gate of the pull-down transistor PD of one inverter are connected to the source of the pull-up transistor PU and the source of the pull-down transistor PD of another inverter. The two pass gate transistors PG control access during read and write operations to the memory cell, which is composed of two cross-connected inverters.

[0013] For example, the source of one pass-gate transistor PG is electrically connected to the source of the pull-up transistor PU and the source of the pull-down transistor PD of one inverter, and the gate of the pull-up transistor PU and the gate of the pull-down transistor PD of another inverter. The gate of one pass-gate transistor PG is electrically connected to the word line WL, and the drain of one pass-gate transistor PG is electrically connected to the bit line BL. The source of the other pass-gate transistor PG is electrically connected to the gate of the pull-up transistor PU and the gate of the pull-down transistor PD of one inverter, and the source of the pull-up transistor PU and the source of the pull-down transistor PD of the other inverter; the gate of the pass-gate transistor PG is electrically connected to the word line WL; and the drain of the other pass-gate transistor PG is connected to the complementary bit line BLB.

[0014] The drain of the pull-up transistor PU is connected to the power supply VDD, and the drain of the pull-down transistor PD is connected to the ground VSS. During a read operation, the word line WL is set high (e.g., logical state "1") to activate access to the memory cell by two pass gate transistors PG. By activating the word line WL, the value of the memory cell (e.g., "0" or "1") is read out via the bit line BL and / or the complementary bit line BLB. For example, if a memory cell stores a logical state of "1," and the word line WL turns on two pass gate transistors PG, the bit line BL will read "1," and the complementary bit line BLB will read "0." During a write operation, for example, if an instruction is executed to write "1" to the memory cell, the word line WL is set high, two pass gate transistors PG are turned on, and the bit line BL is set to a high voltage to override the value "0" stored in the memory cell. Therefore, one or more bits are stored in SRAM and accessed.

[0015] Each of the two pull-up transistors PU is a p-type metal-oxide-semiconductor (PMOS) transistor, and each of the two pull-down transistors PD is an n-type metal-oxide-semiconductor (NMOS) transistor. Both of the two pass gate transistors PG are either NMOS or PMOS transistors.

[0016] Figure 2 is a schematic layout illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention, and Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A-13C, 14A-14C, and 15A-15C are cross-sectional views illustrating a method for manufacturing a stacked integrated circuit element according to an embodiment of the present invention. Specifically, Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are cross-sectional views obtained by cutting along the line A-A' in Figure 2; Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are cross-sectional views obtained by cutting along the line B-B' in Figure 2; and Figures 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, and 15C are cross-sectional views obtained by cutting along the line C-C' in Figure 2.

[0017] Referring to Figure 2, the stacked integrated circuit element 100 includes multiple nanosheet stacked structures NSS, multiple gate electrodes GL, and multiple source / drain regions SD. Multiple nanosheet layered structures (NSSs) are arranged in rows and columns along the first horizontal direction (X direction) and the second horizontal direction (Y direction). The first horizontal direction (X direction) and the second horizontal direction (Y direction) are orthogonal to each other. Multiple gate electrodes GL are spaced apart from each other in the first horizontal direction (X direction) and extend along the second horizontal direction (Y direction). In one embodiment, the source / drain region SD is interposed between a pair of nanosheet stacked structures NSS that are adjacent in the first horizontal direction (X direction) among a plurality of nanosheet stacked structures NSS. For example, multiple nanosheet stacked structures (NSS) and multiple source / drain regions (SD) are arranged alternately along the first horizontal direction (X direction).

[0018] Multiple nanosheet stacked structures (NSS) include lower nanosheet stacked structures (LNSS in Figures 16A and 16B) that are separated from each other along the vertical direction (Z direction) and upper nanosheet stacked structures (UNSS in Figures 16A and 16B). In the first horizontal direction (X direction), source / drain regions (SDs) are positioned on each side of the multiple nanosheet stacked structures (NSSs). The source / drain region SD includes a lower source / drain region (SDL in Figure 16C) and an upper source / drain region (SDU in Figure 16C) that are separated from each other along the vertical direction (Z direction). The lower source / drain region SDL is connected to each of the multiple lower nanosheets (LNS in Figure 16A and UGM Figure 16B) contained in the adjacent lower nanosheet stacking structure LNSS in the first horizontal direction (X direction), and the upper source / drain region SDU may be connected to each of the multiple upper nanosheets (UNS in Figure 16A and Figure 16B) contained in the adjacent upper nanosheet stacking structure UNSS in the first horizontal direction (X direction).

[0019] The stacked integrated circuit element 100 includes multiple logic cells. Logic cells include multiple circuit elements such as transistors and resistors, and can be configured in a variety of ways. At least some of the logic cells may include a pair of cross-coupled transistors. Logic cells consist of, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FIL (filter), multiplexers (MXT / MXIT), OAI (OR / AND / INVERTER), AO (AND / OR), AOI (AND / OR / INVERTER), D flip-flops, reset flip-flops, master-slave flip-flops, latches, etc. Logic cells constitute standard cells that perform logical functions.

[0020] Referring to both Figures 3A and 3C, multiple lower sacrificial layers (LSL) and multiple lower nanosheets (LNS) are alternately stacked one layer at a time on the base substrate layer (BSUB). For example, one of several lower nanosheet LNSs is interposed between two lower sacrificial layer LSLs that are adjacent in the vertical direction (Z direction). Multiple lower nanosheet LNSs constitute a lower nanosheet stacked structure LNSS. After forming an intermediate structure MST on multiple lower sacrificial layers LSL and multiple lower nanosheets LNS, multiple upper sacrificial layers USL and multiple upper nanosheets UNS are alternately stacked one layer at a time on the intermediate structure MST. In one embodiment, the intermediate structure MST includes a pair of intermediate sacrificial layers MSL that are separated from each other in the vertical direction (Z direction) and an intermediate nanosheet MNS interposed between the pair of intermediate sacrificial layers MSL.

[0021] Multiple upper nanosheets (UNS) constitute an upper nanosheet stacked structure (UNSS). An intermediate structure, MST, is interposed between the lower nanosheet layered structure LNSS and the upper nanosheet layered structure UNSS. The lower nanosheet layered structure (LNSS) and the upper nanosheet layered structure (UNSS) are collectively referred to as the nanosheet layered structure (NSS). Multiple lower sacrificial layers (LSL) and multiple upper sacrificial layers (USL) are collectively referred to as multiple sacrificial layers (LS). In one embodiment, the intermediate nanosheet MNS is formed to be thicker than each of the multiple lower nanosheets LNS and each of the multiple upper nanosheets UNS.

[0022] In one embodiment, the number of lower nanosheets LNS constituting the lower nanosheet stacked structure LNSS and the number of upper nanosheets UNS constituting the upper nanosheet stacked structure UNSS are different from each other. For example, the number of nanosheets constituting the nanosheet stacking structure for creating a PMOS transistor within the lower nanosheet stacking structure LNSS and the upper nanosheet stacking structure UNSS is even greater than the number of nanosheets constituting the nanosheet stacking structure for creating an NMOS transistor. For example, if a lower nanosheet stacked structure (LNSS) forms a PMOS transistor and an upper nanosheet stacked structure (UNSS) forms an NMOS transistor, the number of lower nanosheets (LNS) may be even greater than the number of upper nanosheets (UNS).

[0023] In one embodiment, the plurality of lower nanosheets LNS and the plurality of upper nanosheets UNS are made of a material having the same or similar etching properties as the constituent material of the base substrate layer BSUB. The base substrate layer (BSUB) may contain semiconductor materials such as silicon (Si) or germanium (Ge), or compound semiconductor materials such as SiGe (silicon germanium), SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), or InP (indium phosphide). In one embodiment, the base substrate layer BSUB may consist of at least one of the group III-V materials and the group IV material. III-V group materials can be binary, ternary, or quaternary compound semiconductor materials containing at least one group III element and at least one group V element. The base substrate layer BSUB may include conductive regions, such as impurity-doped wells or impurity-doped structures. In one embodiment, each of the base substrate layer BSUB, the plurality of lower nanosheets LNS, and the plurality of upper nanosheets UNS may contain a semiconductor material such as Si or Ge. In one embodiment, the multiple lower sacrificial layers (LSL) and the multiple upper sacrificial layers (USL) may consist of the same constituent material or a material having similar etching properties. Multiple lower sacrificial layers (LSL) and multiple upper sacrificial layers (USL) consist of multiple lower nanosheets (LNS) and multiple upper nanosheets (UNS) and a material having an etching selectivity ratio. For example, each of the multiple lower sacrificial layers (LSL) and the multiple upper sacrificial layers (USL) may contain a compound semiconductor material such as SiGe.

[0024] A pair of intermediate sacrificial layers (MSL) consists of a material having an etching selectivity ratio with multiple lower nanosheets (LNS), multiple upper nanosheets (UNS), multiple lower sacrificial layers (LSL), and multiple upper sacrificial layers (USL). For example, each of the pair of intermediate sacrificial layers (MSL), the multiple lower sacrificial layers (LSL), and the multiple upper sacrificial layers (USL) contains a compound semiconductor material such as SiGe, but the concentration of Ge atoms among the Si atoms in each of the pair of intermediate sacrificial layers (MSL) and the concentration of Ge atoms among the Si atoms in each of the multiple lower sacrificial layers (LSL) and the multiple upper sacrificial layers (USL) are different from each other. In one embodiment, the intermediate nanosheet MNS comprises a material having an etching selectivity ratio with a plurality of lower nanosheets LNS, a plurality of upper nanosheets UNS, a plurality of lower sacrificial layers LSL, and a plurality of upper sacrificial layers USL, but is not limited thereto. For example, the intermediate nanosheet MNS consists of a material having an etching selectivity ratio with multiple lower sacrificial layers LSL and multiple upper sacrificial layers USL, but it may also consist of the same constituent material as the multiple lower nanosheets LNS and multiple upper nanosheets UNS, or a material having similar etching properties.

[0025] Referring to Figures 4A to 4C, the nanosheet stacked structure NSS, which includes the lower nanosheet stacked structure LNSS and the upper nanosheet stacked structure UNSS, and the intermediate structure MST are patterned to form the element isolation recess STR. Each of the nanosheet layered structure NSS and intermediate structure MST is patterned in multiples and arranged in rows and columns along the first horizontal direction (X direction) and the second horizontal direction (Y direction). In the process of patterning the nanosheet laminated structure NSS and the intermediate structure MST, the upper portion of the base substrate layer BSUB that is exposed between the patterned results is also removed. For example, the element isolation recess STR extends from the top of the nanosheet stacked structure NSS into the base substrate layer BSUB.

[0026] Next, a lower insulating layer BDI is formed that fills at least a portion of the space where the upper portion of the base substrate layer BSUB has been removed. The lower insulating layer BDI consists of an insulating material. The lower insulating layer BDI contains oxides. For example, the lower insulating layer BDI may consist of a material containing at least one of silicon oxide, silicon nitride, or silicon oxynitride. The lower insulating layer BDI may consist of a single layer made of one type of insulating film, a double layer made of two types of insulating films, or a multilayer made of a combination of at least three types of insulating films. For example, the lower insulating layer BDI consists of two different insulating films. For example, the lower insulating layer BDI consists of a silicon oxide film and a silicon nitride film. For example, the lower insulating layer BDI consists of a triple layer comprising a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0027] The lower insulating layer BDI is referred to as the element isolation film. Each of the upper portions of the base substrate layer BSUB, which is limited by the lower insulating layer BDI, is referred to as a pin-type active region. A first insulating material layer CDL1 is formed that covers the surface of the lower insulating layer BDI, the multiple nanosheet stacked structure NSS, and the multiple intermediate structure MST. The first insulating material layer CDL1 is formed to conformally cover the surfaces of the lower insulating layer BDI, the multiple nanosheet stacked structure NSS, and the multiple intermediate structure MST. The first insulating layer CDL1 is made of an insulating material. In one embodiment, the first insulating material layer CDL1 contains an oxide.

[0028] Referring to both Figures 4A-4C and 5A-5C, a laminated structure is formed on the first insulating material layer CDL1, consisting of multiple dummy gate layers DPC and multiple second insulating material layers CDL2. The laminated structure of multiple dummy gate layers (DPC) and multiple second insulating material layers (CDL2) is formed by first forming a preliminary conductive layer and a preliminary insulating layer covering the preliminary conductive layer on the first insulating material layer (CDL1), and then patterning the preliminary conductive layer and the preliminary insulating layer. In the process of patterning the preliminary conductive layer and preliminary insulating layer, the portion of the first insulating material layer CDL1 that is exposed between the patterned results is also removed. For example, at the bottom of the stacked structure between multiple dummy gate layers (DPC) and multiple second insulating material layers (CDL2), a nanosheet stacked structure (NSS), an intermediate structure (MST), and a lower insulating layer (BDI) are exposed. The dummy gate layer DPC contains polysilicon, and the second insulating material layer CDL2 contains silicon nitride.

[0029] After forming a laminated structure of multiple dummy gate layers (DPC) and multiple second insulating material layers (CDL2), an intermediate structure (MST) containing an intermediate nanosheet (MNS) interposed between a pair of intermediate sacrificial layers (MSL) is removed, and an intermediate insulating layer (MDI) is formed to fill the space left by the removal of the intermediate structure (MST). The intermediate insulating layer MDI contains nitride. For example, the intermediate insulating layer MDI includes silicon nitride or silicon oxynitride. The intermediate insulating layer is called the gate separator. Multiple dummy gate layers (DPC), multiple second insulating material layers (CDL2), a nanosheet laminated structure (NSS), an intermediate insulating layer (MDI), and a third insulating material layer (CDL3) are formed to cover the exposed surfaces of each of the lower insulating layer (BDI). For example, the third insulating material layer CDL3 is formed to conformally cover the exposed surfaces of multiple dummy gate layers DPC, multiple second insulating material layers CDL2, nanosheet laminated structure NSS, intermediate insulating layer MDI, and lower insulating layer BDI. The third insulating material layer CDL3 includes, but is not limited to, silicon nitride. In one embodiment, the third insulating material layer CDL3 has a laminated structure of an oxide layer and a nitride layer.

[0030] Referring to both Figures 6A and 6C, a portion of the nanosheet stacked structure NSS and the intermediate insulating layer MDI are removed between the stacked structures of multiple dummy gate layers DPC and multiple second insulating material layers CDL2, forming multiple source / drain recesses SDR. For example, multiple source / drain recesses in the SDR are formed by an anisotropic etching process. In the process of forming multiple source / drain recess SDRs, portions of the third insulating material layer CDL3 covering the upper surfaces of multiple dummy gate layers DPC, nanosheet stacked structure NSS, and lower insulating layer BDI are all removed. The base substrate layer BSUB and the lower insulating layer BDI are exposed on the bottom surface of each of the multiple source / drain recesses of the SDR. In one embodiment, during the process of forming multiple source / drain recesses (SDRs), a portion of the upper part of the base substrate layer (BSUB) located below the stacked structure of multiple dummy gate layers (DPCs) and multiple second insulating material layers (CDL2s) is also removed. For example, multiple source / drain recess SDRs are extended into the base substrate layer BSUB through the uppermost edge of the base substrate layer BSUB.

[0031] Referring to Figures 7A to 7C, multiple source / drain regions (SDs) are formed by epitaxial growth from the surface of multiple nanosheet stacked structures (NSSs) and base substrate layers (BSUBs) exposed within multiple source / drain recesses (SDRs). Each of the multiple source / drain regions (SD) includes a lower source / drain region (SDL) and an upper source / drain region (SDU). After forming multiple source / drain regions (SD), an interlayer insulating layer (FDI) is formed that satisfies each of the multiple source / drain recesses (SDR). The interlayer insulating layer FDI is formed to fill all the spaces between the laminated structures of the multiple dummy gate layers DPC and the multiple second insulating material layers CDL2. In one embodiment, after forming the lower source / drain region SDL, a portion of the interlayer insulating layer FDI is formed that encloses the lower source / drain region SDL and fills the lower portion of the source / drain recess SDR. Then, after forming the upper source / drain region SDU, the remaining portion of the interlayer insulating layer FDI is formed that encloses the upper source / drain region SDU and fills the upper portion of the source / drain recess SDR. In one embodiment, after forming the lower source / drain region SDL and the upper source / drain region SDU, an interlayer insulating layer FDI is formed that encloses the lower source / drain region SDL and the upper source / drain region SDU while filling the source / drain recess SDR.

[0032] Each of the multiple source / drain regions (SD) consists of an embedded SiGe structure containing multiple epitaxially grown SiGe layers, an epitaxially grown Si layer, or an epitaxially grown SiC layer. The lower source / drain region (SDL) is formed by epitaxial growth from the surfaces of the multiple lower nanosheets (LNS) and the base substrate layer (BSUB) contained within the lower nanosheet stacked structure (LNSS). The upper source / drain region (SDU) is formed by epitaxial growth from the surface of each of the multiple upper nanosheets (UNS) contained within the upper nanosheet stacked structure (UNSS). For example, the interlayer insulating layer FDI is made of silicon oxide or an insulating material with a lower dielectric constant than silicon oxide. In one embodiment, the interlayer insulating layer FDI consists of a TEOS (tetraethyl orthosilicate) film or an ULK (ultra low K) film having an ultra low dielectric constant of about 2.2 to 2.4. The ULK film includes either a SiOC film or a SiCOH film.

[0033] The lower source / drain region (SDL) and the upper source / drain region (SDU) contain impurities of different conductivity types. Multiple lower nanosheets LNS in contact with the lower source / drain region SDL and multiple upper nanosheets UNS in contact with the upper source / drain region SDU contain impurities of different conductivity types. In one embodiment, n-type metal oxide semiconductor (NMOS) transistors are formed in the upper source / drain region SDU and a plurality of upper nanosheets UNS, and p-type metal oxide semiconductor (PMOS) transistors are formed in the lower source / drain region SDL and a plurality of lower nanosheets LNS. For example, the lower source / drain region SDL contains p-type impurities, while the upper source / drain region SDU contains n-type impurities. For example, each of the multiple lower nanosheets LNS contains n-type impurities, and each of the multiple upper nanosheets UNS contains p-type impurities. In other embodiments, p-type metal oxide semiconductor (PMOS) transistors may be formed in the upper source / drain region (SDU) and multiple upper nanosheets (UNS), and n-type metal oxide semiconductor (NMOS) transistors may be formed in the lower source / drain region (SDL) and multiple lower nanosheets (LNS). For example, the lower source / drain region SDL contains n-type impurities, while the upper source / drain region SDU contains p-type impurities. For example, each of the multiple lower nanosheets LNS contains p-type impurities, and each of the multiple upper nanosheets UNS contains n-type impurities.

[0034] Referring to both Figures 7A-7C and 8A-8C, multiple second insulating material layers CDL2 are removed to expose multiple dummy gate layers DPC, and then the multiple dummy gate layers DPC are removed. In the process of removing multiple second insulating material layers CDL2, a portion of the upper side of both the third insulating material layer CDL3 and the interlayer insulating layer FDI is removed. After removing multiple dummy gate layers (DPC), the first insulating material layer (CDL1) is removed. In one embodiment, multiple dummy gate layers (DPC) are removed by a wet etching process. For wet etching, etching solutions consisting of, for example, HNO3, DHF (diluted fluoric acid), NH4OH, TMAH (tetramethyl ammonium hydroxide), KOH, or combinations thereof can be used.

[0035] Referring to both Figures 8A-8C and 9A-9C, a portion of each of the multiple upper nanosheets UNS and multiple upper sacrificial layers USL contained within the upper nanosheet stacked structure UNSS is removed. As a result, in the second horizontal direction (Y direction), the widths of each of the multiple upper nanosheets UNS and multiple upper sacrificial layers USL are smaller than the widths of each of the multiple lower nanosheets LNS and multiple lower sacrificial layers LSL. For example, after forming a mold layer that fills the lower part of the element isolation recess STR so as to cover the sides of each of the multiple lower nanosheets LNS and multiple lower sacrificial layers LSL, an etching process is performed to remove a portion of both sides of each of the multiple upper nanosheets UNS and multiple upper sacrificial layers USL in the second horizontal direction (Y direction).

[0036] In one embodiment, during the etching process that removes portions of each of the multiple upper nanosheets UNS and multiple upper sacrificial layers USL, the intermediate insulating layer MDI remains without being removed. For example, the horizontal width of the intermediate insulating layer (MDI) is approximately the same as or similar to the widths of the multiple lower nanosheets (LNS) and the multiple lower sacrificial layers (LSL). A recess space (TNR) is limited between two adjacent upper nanosheet stacked structures (UNSS) in the second horizontal direction (Y direction). In the second horizontal direction (Y direction), the horizontal width of the recess space (TNR) is greater than the horizontal width of the element isolation recess STR portion, which is limited to the two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction).

[0037] Referring to both Figures 9A-9C and 10A-10C, multiple sacrificial layers LS, including multiple lower sacrificial layers LSL and multiple upper sacrificial layers USL, are removed to form multiple gate spaces GS. Multiple gate spaces include multiple lower gate spaces (LGS), which are spaces from which multiple lower sacrificial layers (LSL) have been removed, and multiple upper gate spaces (UGS), which are spaces from which multiple upper sacrificial layers (USL) have been removed.

[0038] Referring to both Figures 11A and 11C, a lower gate insulating layer LGox is formed that encloses multiple lower nanosheets LNS, and a lower gate electrode LGL is formed that covers the lower gate insulating layer LGox while filling multiple lower gate spaces LGS. The lower gate insulating layer LGox and the lower gate electrode LGL are formed by a replacement metal gate (RMG) process. The lower gate insulating layer LGox and the lower gate electrode LGL are formed to enclose multiple lower nanosheets LNS and fill a portion of the lower side of the device isolation recess STR. In one embodiment, the lower gate insulating layer LGox and the lower gate electrode LGL are formed to fill a portion of the space of the element isolation recess STR between two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction), but not completely. For example, the lower gate electrode LGL is formed to enclose multiple lower nanosheets LNS, cover the lower gate insulating layer LGox, fill multiple lower gate spaces LGS, and cover the bottom surface and a portion of the inner wall of the element isolation recess STR. The lower gate electrode LGL covers at least a portion of the upper surface of the lower insulating layer BDI.

[0039] In one embodiment, the lower gate electrode LGL completely covers the upper surface of the lower insulating layer BDI, but is not limited to this. For example, the lower gate electrode LGL may not cover at least a portion of the upper surface of the lower insulating layer BDI. The uppermost end of the lower gate electrode LGL is located between the lower and upper surfaces of the intermediate insulating layer MDI. For example, the uppermost edge of the lower gate electrode LGL is located at a vertical level that is the same as or higher than the lower surface of the intermediate insulating layer MDI, and the same as or lower than the upper surface of the intermediate insulating layer MDI. The lower gate insulating layer LGox may consist of a silicon oxide film, a high-dielectric film, or a combination thereof.

[0040] In one embodiment, the lower gate insulating layer LGox is composed of a laminated structure of an interface layer and a high dielectric film. The interface film is made of a low-dielectric material with a dielectric constant of approximately 9 or less. For example, the interface film may consist of an oxide, nitride, or oxidnitride. High dielectric films consist of metal oxides or metal oxide nitrides. High dielectric films are made of materials with a dielectric constant even higher than that of silicon oxide films. For example, high dielectric films have a dielectric constant of approximately 10 to 25. High dielectric films typically have a thickness of approximately 10 Å to 40 Å, but are not limited to this range. In one embodiment, the interface film may be omitted. For example, the lower gate insulating layer LGox may consist of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0041] The lower gate electrode LGL includes a metal-containing layer for work function adjustment and a gap-filling metal-containing layer that fills the space above the work function adjustment metal-containing layer. The work function metal-containing layer may contain at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In one embodiment, the lower gate electrode LGL has a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap fill metal film are sequentially laminated. The metal nitride layer and the metal layer may contain at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, or Hf. The gap fill metal film consists of a W film or an Al film. In one embodiment, the lower gate electrode LGL includes, but is not limited to, a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN / W stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure.

[0042] Referring to both Figures 12A and 12C, a lower gate insulating layer UGox encloses multiple upper nanosheets UNS, and an upper main gate layer UGM is formed that covers the upper gate insulating layer UGox while filling multiple upper gate spaces UGS. The upper gate insulating layer UGox and the upper main gate layer UGM are formed by a metal gate replacement process. The upper gate insulating layer UGox and the upper main gate layer UGM are formed to enclose multiple upper nanosheets UNS while satisfying both the recess space TNR and the element isolation recess STR. For example, the recess space TNR between two adjacent upper nanosheet stacked structures UNSS in the second horizontal direction (Y direction) is filled by both the upper gate insulating layer UGox and the upper main gate layer UGM. For example, any space in the device isolation recess STR between two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction) that is not filled by the lower gate insulating layer LGox and the lower gate electrode LGL is filled by the upper main gate layer UGM.

[0043] The upper main gate layer (UGM) extends into the lower portion of the element isolation recess (STR). For example, the upper main gate layer (UGM) is extended between two adjacent lower nanosheet stacked structures (LNSS) in the second horizontal direction (Y direction). Within the lower portion of the element isolation recess STR, the upper main gate layer UGM is separated from each of the multiple lower nanosheets LNS via the lower gate electrode LGL. The upper main gate layer (UGM) is separated from the lower insulating layer (BDI) via the lower gate electrode layer (LGL). In one embodiment, if the lower gate electrode LGL does not cover at least a portion of the upper surface of the lower insulating layer BDI, the upper main gate layer UGM is formed to cover the portion of the upper surface of the lower insulating layer BDI that is not covered by the lower gate electrode LGL. The upper main gate layer UGM covers the upper gate insulating layer UGox, and is formed such that the upper surface of the upper main gate layer UGM is at a higher vertical level than the upper surface of the uppermost upper nanosheet UNS, which are included in the upper nanosheet stacked structure UNSS.

[0044] The upper gate insulating layer LGox may consist of a silicon oxide film, a high-dielectric film, or a combination thereof. In one embodiment, the upper gate insulating layer LGox is composed of a laminated structure of an interface film and a high dielectric film. The interface film is made of a low-dielectric material with a dielectric constant of approximately 9 or less. High dielectric films consist of metal oxides or metal oxide nitrides. High dielectric films are made of materials with a dielectric constant even higher than that of silicon oxide films. For example, high dielectric films have a dielectric constant of approximately 10 to 25. In one embodiment, the interface film may be omitted. For example, the upper gate insulating layer UGox may consist of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0045] The upper main gate layer (UGM) includes a metal-containing layer for work function adjustment and a gap-filling metal-containing layer that fills the space above the work function adjustment metal-containing layer. The work function metal-containing layer may contain at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In one embodiment, at least a portion of the work function adjusting metal-containing layer included in the upper main gate layer (UGM) is made of a different material from the work function adjusting metal-containing layer included in the lower gate electrode (LGL). In one embodiment, the upper main gate layer UGM has a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap fill metal film are sequentially laminated. In one embodiment, the upper main gate layer UGM includes, but is not limited to, a TiAlC / TiN / W laminated structure, a TiN / TaN / TiAlC / TiN / W laminated structure, or a TiN / TaN / TiN / TiAlC / TiN / W laminated structure.

[0046] Referring to both Figures 13A and 13C, a first gate cut space GC1 is formed, extending from the upper surface of the upper main gate layer UGM through two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction) to the lower insulating layer BDI. The first gate cut space GC1 is formed so that the side surface of the intermediate insulating layer MDI is exposed. With respect to the first gate cut space GC1, the portions of the upper main gate layer UGM that enclose the two upper nanosheet stacked structures UNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the first gate cut space GC1, and with respect to the first gate cut space GC1, the portions of the lower gate electrode LGL that enclose the two lower nanosheet stacked structures LNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the first gate cut space GC1.

[0047] In some parts of the space between two adjacent nanosheet stacked structures (NSS) in the second horizontal direction (Y direction) of the multiple nanosheet stacked structures (NSS), a first gate cut space (GC1) is formed, but in other parts, the first gate cut space (GC1) is not formed. For example, if a first gate cut space GC1 is not formed between two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction), the portion of the upper main gate layer UGM surrounding the two upper nanosheet stacked structures UNSS and the portion of the lower gate electrode LGL surrounding the two lower nanosheet stacked structures LNSS will not be separated but will form a single unit. A lower gate cut structure LCT is formed in a portion of the lower side of the first gate cut space GC1.

[0048] The lower gate-cut structure LCT is interposed between two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction), but does not interpose between two adjacent upper nanosheet stacked structures UNSS in the second horizontal direction (Y direction), thus filling a portion of the lower part of the first gate-cut space GC1. The uppermost end of the lower gate cut structure LCT is located between the uppermost end of the lower gate electrode LGL and the lowermost end of the upper main gate layer UGM. For example, the uppermost end of the lower gate cut structure LCT is located at the same or higher vertical level as the uppermost end of the lower gate electrode LGL, i.e., the lower surface of the intermediate insulating layer MDI. For example, the uppermost edge of the lower gate cut structure LCT is located at the same or lower vertical level as the lowermost edge of the upper main gate layer UGM, i.e., the upper surface of the intermediate insulating layer MDI. The lower gate-cut structure LCT is made of nitride. For example, the lower gate-cut structure LCT contains silicon nitride.

[0049] Referring to both Figures 14A and 14C, an upper charging gate layer UGF is formed that fills the upper portion of the first gate cut space GC1. The first gate cut space GC1 is filled by both the lower gate cut structure LCT and the upper charging gate layer UGF. The upper charging gate layer UGF connects to the upper main gate layer UGM, which is separated and isolated by the first gate cut space GC1. At least a portion of the upper charging gate layer (UGF) is made of the same material as at least a portion of the upper main gate layer (UGM). In one embodiment, at least a portion of the upper charging gate layer UGF is made of the same material as the gap fill metal-containing layer included in the upper main gate layer UGM. For example, the upper charging gate layer (UGF) includes a laminated structure of W or TiN / W. The upper main gate layer (UGM) and the upper charging gate layer (UGF) constitute the upper gate electrode (UGL). The upper gate electrode UGL and the lower gate electrode LGL constitute the gate electrode GL. The gate electrode GL corresponds to the gate of the pull-up transistor PU, the gate of the pull-down transistor PD, or the gate of the pass-gate transistor PG shown in Figure 1.

[0050] Referring to both Figures 15A and 15C, a second gate cut space GC2 is formed where the lower gate cut structure LCT is exposed at the bottom surface after penetrating the upper charging gate layer UGF, and a third gate cut space GC3 is formed where the lower insulating layer BDI is exposed at the bottom surface after penetrating the upper main gate layer UGM. The second gate cut space GC2 is formed within the first gate cut space GC1. The lower portion of the first gate cut space GC1 is filled by the lower gate cut structure LCT, a portion of the upper portion of the first gate cut space GC1 is filled by the upper charging gate layer UGF, and the remaining portion of the upper portion of the first gate cut space GC1 is the second gate cut space GC2, which is limited by the upper charging gate layer UGF, or the upper charging gate layer UGF and the upper main gate layer UGM. The third gate cut space GC3 is formed between two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction) where the first gate cut space GC1 is not formed. The third gate cut space GC3 is formed to extend from the upper surface of the portion of the upper main gate layer UGM that fills the space between two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction), through the space between the two adjacent nanosheet stacked structures NSS, to the lower insulating layer BDI.

[0051] With respect to the second gate cut space GC2, the portions of the upper gate electrode UGL that enclose the two upper nanosheet stacked structures UNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the second gate cut space GC2. With respect to the third gate cut space GC3, the portions of the upper gate electrode UGL that enclose the two upper nanosheet stacked structures UNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the third gate cut space GC3. With respect to the third gate cut space GC3, the portion of the lower gate electrode LGL that encloses the two lower nanosheet stacked structures LNSS located on both sides in the second horizontal direction (Y direction) and the portion of the upper gate electrode UGL that is in contact with them are separated and moved apart by the third gate cut space GC3.

[0052] Next, an upper gate cut structure UCT that satisfies the second gate cut space GC2, a coupled gate cut structure MCT that satisfies the third gate cut space GC3, and a gate capping layer GCP that covers the gate electrode GL are formed. The upper gate-cut structure UCT and the bonded gate-cut structure MCT are each made of nitride. For example, the upper gate cut structure UCT and the bonded gate cut structure MCT each contain silicon nitride. In one embodiment, the upper gate cut structure UCT and the binding gate cut structure MCT are formed from the same material. The gate capping layer (GCP) is made of nitride. For example, the gate capping layer (GCP) contains silicon nitride. In one embodiment, the upper gate cut structure UCT, the bonded gate cut structure MCT, and the gate capping layer GCP are formed together from the same material and form a single unit.

[0053] The lower gate-cut structure LCT is interposed between two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction). With the lower gate-cut structure LCT as the reference, the portions of the lower gate electrode LGL that enclose the two lower nanosheet stacked structures LNSS located on both sides in the second horizontal direction (Y direction) are separated and moved apart by the lower gate-cut structure LCT. In other words, with respect to the lower gate-cut structure LCT, the gates of the two transistors formed on the two lower nanosheet stacked structures LNSS located on either side in the second horizontal direction (Y direction) are not connected to each other. The upper gate-cut structure UCT is interposed between two adjacent upper nanosheet stacked structures UNSS in the second horizontal direction (Y direction). With the upper gate-cut structure UCT as the reference, the portions of the upper gate electrode UGL that enclose the two upper nanosheet stacked structures UNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the upper gate-cut structure UCT. In other words, with respect to the upper gate-cut structure UCT, the gates of the two transistors formed on the two upper nanosheet stacked structures UNSS located on either side in the second horizontal direction (Y direction) are not connected to each other.

[0054] The upper gate-cut structure UCT is formed on the lower gate-cut structure LCT. The upper gate cut structure UCT is in contact with the lower gate cut structure LCT. Both the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT are adjacent in the second horizontal direction (Y direction) and interposed between two nanosheet stacking structures NSS, each containing an upper nanosheet stacking structure UNSS and a lower nanosheet stacking structure LNSS. With respect to the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT, in the second horizontal direction (Y direction), the portions of the upper gate gate UGL that enclose the upper nanosheet stacking structure UNSS contained in each of the two nanosheet stacking structures NSS located on both sides are separated and distanced from each other by the upper gate cut structure UCT. With respect to the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT, in the second horizontal direction (Y direction), the portions of the lower gate gate LGL that enclose the lower nanosheet stacking structure LNSS contained in each of the two nanosheet stacking structures NSS located on both sides are separated and distanced from each other by the lower gate cut structure LCT. In other words, with reference to the lower gate-cut structure LCT and the upper gate-cut structure UCT on the lower gate-cut structure LCT, the gates of the transistors formed in the upper nanosheet stacked structure UNSS, which is included in the nanosheet stacked structure NSS located at least one side in the second horizontal direction (Y direction), and the gates of the transistors formed in the lower nanosheet stacked structure LNSS are not connected to each other.

[0055] The bonded gate-cut structure MCT is adjacent in the second horizontal direction (Y direction) and interposed between two nanosheet stacking structures NSS, each containing an upper nanosheet stacking structure UNSS and a lower nanosheet stacking structure LNSS. With the bonded gate-cut structure MCT as the reference, in the second horizontal direction (Y direction), the upper gate electrode UGL portion that encloses the upper nanosheet stacking structure UNSS contained in each of the two nanosheet stacking structures NSS located on both sides is separated and distanced from each other by the bonded gate-cut structure MCT. With the bonded gate-cut structure MCT as the reference, in the second horizontal direction (Y direction), the lower gate electrode LGL portion that encloses the lower nanosheet stacking structure LNSS contained in each of the two nanosheet stacking structures NSS located on both sides is separated and distanced from each other by the bonded gate-cut structure MCT.

[0056] In other words, with respect to the bonded gate-cut structure MCT, the gates of the two transistors formed in the upper nanosheet stacked structure UNSS contained within each of the two nanosheet stacked structures NSS located on both sides in the second horizontal direction (Y direction) are not connected to each other, and with respect to the bonded gate-cut structure MCT, the gates of the two transistors formed in the lower nanosheet stacked structure LNSS contained within each of the two nanosheet stacked structures NSS located on both sides in the second horizontal direction (Y direction) are not connected to each other. With respect to the bonded gate-cut structure MCT, in the second horizontal direction (Y direction), the portion of the lower gate electrode LGL that encloses the lower nanosheet stacked structure LNSS contained within each of the two nanosheet stacked structures NSS located on both sides comes into contact with the portion of the upper gate electrode UGL that encloses the upper nanosheet stacked structure UNSS contained within each of the two nanosheet stacked structures NSS, and is electrically connected. In other words, with respect to the coupled gate-cut structure MCT, the gates of the transistors formed in the upper nanosheet stacked structure UNSS, which is contained within each of the two nanosheet stacked structures NSS located on either side in the second horizontal direction (Y direction), are connected to the gates of the transistors formed in the lower nanosheet stacked structure LNSS.

[0057] Figures 16A to 16C are cross-sectional views showing a stacked integrated circuit element according to an embodiment of the present invention. Specifically, Figure 16A is a cross-sectional view taken along the line A-A' in Figure 2, Figure 16B is a cross-sectional view taken along the line B-B' in Figure 2, and Figure 16C is a cross-sectional view taken along the line C-C' in Figure 2.

[0058] Referring to both Figures 15A-15C and 16A-16C, a first contact plug CTA connected to the upper source / drain region SDU and a second contact plug CTB connected to the lower source / drain region SDL are formed, thus forming the stacked integrated circuit element 1. In one embodiment, the stacked integrated circuit element 1 further includes a third contact plug CTC connecting the upper source / drain region SDU and the lower source / drain region SDL. The first contact plug CTA, the second contact plug CTB, and the third contact plug CTC each contain metal. In one embodiment, the first contact plug CTA, the second contact plug CTB, and the third contact plug CTC are each composed of a metal layer and a conductive metal nitride layer surrounding the metal layer. For example, the metal layer is W or Al, and the conductive metal nitride layer is TiN or TaN.

[0059] The first contact plug CTA is formed to penetrate the interlayer insulation layer FDI and / or the gate capping layer GCP and connect to the upper part of the upper source / drain region SDU. The second contact plug CTB is formed to penetrate the lower insulating layer BDI and / or the base substrate layer BSUB and connect to the lower part of the lower source / drain region SDL. The third contact plug CTC is formed to penetrate the gate capping layer GCP, the upper source / drain region SDU, and the interlayer insulation layer FDI to connect to the upper part of the lower source / drain region SDL, but is not limited to this. For example, the third contact plug CTC may be formed to penetrate the lower insulating layer BDI and / or the base substrate layer BSUB, the lower source / drain region SDL, and the interlayer insulating layer FDI to connect to the lower part of the upper source / drain region SDU.

[0060] Before forming the first contact plug CTA and / or the third contact plug CTC, the upper portion of the gate capping layer GCP, the third insulating material layer CDL3, and the interlayer insulating layer FDI is removed. Before forming the second contact plug CTB, a portion of the lower side of the base substrate layer BSUB is removed. In one embodiment, the lower portion of the base substrate layer BSUB may be removed so that the lower insulating layer BDI is exposed before forming the second contact plug CTB, and at least a portion of the remaining base substrate layer BSUB may be removed in the process of forming the second contact plug CTB. For example, the second contact plug CTB is formed to penetrate the lower insulating layer BDI and connect to the lower part of the lower source / drain region SDL.

[0061] The stacked integrated circuit element 1 includes a lower insulating layer BDI, a lower nanosheet stacked structure LNSS disposed on the lower insulating layer BDI, and a plurality of nanosheet stacked structures NSS, each including an upper nanosheet stacked structure UNSS disposed on the lower nanosheet stacked structure LNSS, an intermediate insulating layer MDI interposed between the lower nanosheet stacked structure LNSS and the upper nanosheet stacked structure UNSS, a gate electrode GL including a lower gate electrode LGL surrounding the lower nanosheet stacked structure LNSS and an upper gate electrode UGL surrounding the upper nanosheet stacked structure UNSS, a first contact plug CTA connected to the upper source / drain region SDU, and a lower source / drain region SDL connected to The structure includes a second contact plug CTB, a lower gate cut structure LCT interposed between two lower nanosheet stacked structures LNSS adjacent in the second horizontal direction (Y direction), an upper gate cut structure UCT placed on the lower gate cut structure LCT and interposed between two upper nanosheet stacked structures UNSS adjacent in the second horizontal direction (Y direction), and a bonded gate cut structure MCT interposed between two nanosheet stacked structures NSS adjacent in the second horizontal direction (Y direction), separating the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT with at least one nanosheet stacked structure NSS in between.

[0062] The upper gate electrode UGL includes a connecting extension (GL-E) and a protruding portion (UGL-P). The lower gate cut structure LCT occupies the lower portion of the first gate cut space GC1, the upper gate cut structure UCT occupies the second gate cut space GC2, and the combined gate cut structure MCT occupies the third gate cut space GC3. The projection (UGL-P) of the upper gate electrode UGL and the upper gate cut structure UCT fill the upper portion of the first gate cut space GC1. The lower nanosheet stacked structure LNSS includes multiple lower nanosheet LNS. Multiple lower nanosheet LNS are arranged spaced apart from each other along the vertical direction (Z direction). The upper nanosheet layered structure UNSS includes multiple upper nanosheet UNS. Multiple upper nanosheet UNS are arranged spaced apart from each other along the vertical direction (Z direction). In the second horizontal direction (Y direction), each of the multiple upper nanosheets UNS has a first horizontal width W1, and in the second horizontal direction (Y direction), each of the multiple lower nanosheets LNS has a second horizontal width W2 that is greater than the first horizontal width W1.

[0063] The stacked integrated circuit element 1 further includes a first contact plug CTA connected to the upper source / drain region SDU, a second contact plug CTB connected to the lower source / drain region SDL, and a third contact plug CTC connecting the upper source / drain region SDU and the lower source / drain region SDL. In one embodiment, the stacked integrated circuit element 1 further includes a base substrate layer BSUB below the lower nanosheet stacked structure LNSS and the lower insulating layer BDI. In some parts of the space between two adjacent nanosheet stacked structures (NSS) in the second horizontal direction (Y direction) of the multiple nanosheet stacked structures (NSS), a lower gate cut structure (LCT) and an upper gate cut structure (UCT) on the lower gate cut structure (LCT) are interposed, while in other parts, a bonded gate cut structure (MCT) is interposed. In other words, there is no bonded gate-cut structure MCT between the lower gate-cut structure LCT and two nanosheet stacked structures NSS adjacent in the second horizontal direction (Y direction) where the upper gate-cut structure UCT on the lower gate-cut structure LCT is interposed, and there is no lower gate-cut structure LCT or upper gate-cut structure UCT between two nanosheet stacked structures NSS adjacent in the second horizontal direction (Y direction) where the bonded gate-cut structure MCT is interposed.

[0064] Each of the multiple nanosheet stacked structures NSS contains a lower nanosheet stacked structure LNSS and a lower gate electrode LGL surrounding it, which constitute a lower transistor TRL. Each of the multiple nanosheet stacked structures NSS contains an upper nanosheet stacked structure UNSS and a upper gate electrode UGL surrounding it, which constitute an upper transistor TRU. The lower transistor TRL and the upper transistor TRU are different types of metal oxide semiconductor transistors. In one embodiment, the lower transistor TRL is a PMOS transistor, and the upper transistor TRU is an NMOS transistor. Alternatively, in one embodiment, the lower transistor TRL may be an NMOS transistor, and the upper transistor TRU may be a PMOS transistor.

[0065] The lower gate-cut structure LCT is interposed between two adjacent lower nanosheet stacked structures LNSS in the second horizontal direction (Y direction). With the lower gate-cut structure LCT as the reference, the portions of the lower gate electrode LGL that enclose the two lower nanosheet stacked structures LNSS located on both sides in the second horizontal direction (Y direction) are separated and moved apart by the lower gate-cut structure LCT. In other words, with respect to the lower gate-cut structure LCT, the upper gate electrodes UGL of the two upper nanosheet stacked structures UNSS, which are formed on the two lower nanosheet stacked structures LNSS located on both sides in the second horizontal direction (Y direction), are not connected to each other. The upper gate-cut structure UCT is interposed between two adjacent upper nanosheet stacked structures UNSS in the second horizontal direction (Y direction). With the upper gate-cut structure UCT as the reference, the portions of the upper gate electrode UGL that enclose the two upper nanosheet stacked structures UNSS located on both sides in the second horizontal direction (Y direction) are separated and distanced from each other by the upper gate-cut structure UCT. In other words, with respect to the upper gate-cut structure UCT, the upper gate electrodes UGL of the two upper transistors TRU formed on the two upper nanosheet stacked structures UNSS located on either side in the second horizontal direction (Y direction) are not connected to each other.

[0066] The upper gate cut structure UCT, which is positioned on the lower gate cut structure LCT, is in contact with the lower gate cut structure LCT. Both the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT are adjacent in the second horizontal direction (Y direction) and interposed between two nanosheet stacking structures NSS, each containing an upper nanosheet stacking structure UNSS and a lower nanosheet stacking structure LNSS. With respect to the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT, in the second horizontal direction (Y direction), the portions of the upper gate gate UGL that enclose the upper nanosheet stacking structure UNSS contained in each of the two nanosheet stacking structures NSS located on both sides are separated and distanced from each other by the upper gate cut structure UCT. With respect to the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT, in the second horizontal direction (Y direction), the portions of the lower gate gate LGL that enclose the lower nanosheet stacking structure LNSS contained in each of the two nanosheet stacking structures NSS located on both sides are separated and distanced from each other by the lower gate cut structure LCT. In other words, with reference to the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT, the upper gate electrode UGL, which is the gate of the upper transistor TRU formed in the upper nanosheet stacked structure UNSS included in the nanosheet stacked structure NSS located at least one side in the second horizontal direction (Y direction), and the lower gate electrode LGL, which is the gate of the lower transistor TRL formed in the lower nanosheet stacked structure LNSS, are not connected to each other with the intermediate insulating layer MDI and the lower gate cut structure LCT in between.

[0067] The bonded gate-cut structure MCT is adjacent in the second horizontal direction (Y direction) and interposed between two nanosheet stacking structures NSS, each containing an upper nanosheet stacking structure UNSS and a lower nanosheet stacking structure LNSS. With the bonded gate-cut structure MCT as the reference, in the second horizontal direction (Y direction), the upper gate electrode UGL portion that encloses the upper nanosheet stacking structure UNSS contained in each of the two nanosheet stacking structures NSS located on both sides is separated and distanced from each other by the bonded gate-cut structure MCT. With the bonded gate-cut structure MCT as the reference, in the second horizontal direction (Y direction), the lower gate electrode LGL portion that encloses the lower nanosheet stacking structure LNSS contained in each of the two nanosheet stacking structures NSS located on both sides is separated and distanced from each other by the bonded gate-cut structure MCT. In other words, with respect to the coupled gate-cut structure MCT, the upper gate electrodes UGL of the two upper transistors TRU formed in the upper nanosheet stacking structure UNSS contained within each of the two nanosheet stacking structures NSS located on both sides in the second horizontal direction (Y direction) are not connected to each other. Similarly, with respect to the coupled gate-cut structure MCT, the lower gate electrodes LGL of the two lower transistors TRL formed in the lower nanosheet stacking structure LNSS contained within each of the two nanosheet stacking structures NSS located on both sides in the second horizontal direction (Y direction) are not connected to each other.

[0068] With the bonded gate cut structure MCT as a reference, in the second horizontal direction (Y direction), the portion of the lower gate electrode LGL that encloses the lower nanosheet stacked structure LNSS contained in each of the two nanosheet stacked structures NSS located on both sides comes into contact with the portion of the upper gate electrode UGL that encloses the upper nanosheet stacked structure UNSS contained in each of the two nanosheet stacked structures NSS, and is electrically connected. In other words, with respect to the coupled gate-cut structure MCT, the upper gate electrode UGL, which is the gate of the upper transistor TRU formed in the upper nanosheet stacked structure UNSS contained in each of the two nanosheet stacked structures NSS located on both sides in the second horizontal direction (Y direction), and the lower gate electrode LGL, which is the gate of the lower transistor TRL formed in the lower nanosheet stacked structure LNSS, are connected to each other.

[0069] The connection extension (GL-E) of the upper gate electrode UGL extends from the portion of the upper gate electrode UGL that encloses the upper nanosheet stacked structure UNSS along the side of the bonded gate cut structure MCT and connects to the lower gate electrode LGL. For example, the connection extension (GL-E) of the upper gate electrode UGL extends between the coupled gate cut structure MCT and the intermediate insulating layer MDI, and between the coupled gate cut structure MCT and the lower gate electrode LGL. The connection extension portion (GL-E) of the upper gate electrode UGL is the portion of the upper gate electrode UGL that satisfies the element isolation recess STR shown in Figure 14B, and is the portion that remains without being removed during the process of forming the third gate cut space GC3. The protrusion (UGL-P) of the upper gate electrode UGL is the portion of the upper gate electrode UGL that protrudes onto the lower gate cut structure LCT from the portion of the upper gate electrode UGL that encloses the upper nanosheet stacked structure UNSS. For example, the protruding portion (UGL-P) of the upper gate electrode UGL is the portion of the upper gate electrode UGL that protrudes from the portion that overlaps with the intermediate insulating layer MDI in the vertical direction (Z direction) to the portion that overlaps with the lower gate cut structure LCT. In one embodiment, the protruding portion (UGL-P) of the upper gate electrode UGL is the portion that remains without being removed during the process of forming the second gate cut space GC2 in the upper charging gate layer UGF shown in Figure 14B.

[0070] The width of the lower surface of the upper gate cut structure UCT, which is placed on the lower gate cut structure LCT, is smaller than the width of the upper surface of the lower gate cut structure LCT. Therefore, the lower gate cut structure LCT and the upper gate cut structure UCT placed on the lower gate cut structure LCT have a staircase structure between the lower gate cut structure LCT and the upper gate cut structure UCT. A portion of the upper surface of the lower gate cut structure LCT is covered by the lower surface of the upper gate cut structure UCT, and the other portion of the upper surface of the lower gate cut structure LCT is covered by the lower surface of the projection (UGL-P) of the upper gate electrode UGL. In one embodiment, with respect to the upper gate cut structure UCT, the projection lengths of the pair of upper gate electrodes UGL located on both sides in the second horizontal direction (Y direction) are the same. The projection length of the projection (UGL-P) of the upper gate electrode UGL refers to the horizontal width of the projection (UGL-P), i.e., the horizontal width in the second horizontal direction (Y direction) of the upper surface portion of the lower gate cut structure LCT covered by the projection (UGL-P). The spacing between two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction), where a lower gate cut structure LCT, an upper gate cut structure UCT on the lower gate cut structure LCT, and a protrusion (UGL-P) of the upper gate electrode UGL are interposed, is the same as the spacing between two adjacent nanosheet stacked structures NSS in the second horizontal direction (Y direction), where a bonded gate cut structure MCT and a connecting extension (GL-E) of the upper gate electrode UGL are interposed.

[0071] With respect to a coupled gate-cut structure MCT among the plurality of lower transistors TRL and plurality of upper transistors TRU included in the stacked integrated circuit element 1, the lower transistors TRL and upper transistors TRU arranged on both sides respectively include at least one pair of transistors that are cross-coupled, with their respective gates, the lower gate electrode LGL and the upper gate electrode UGL, being adjacent to each other and electrically connected. Furthermore, the connecting extension (GL-E) for connecting the upper transistor TRU and the lower transistor TRL is the portion of the upper gate electrode UGL that remains without being removed in the process of forming the third gate cut space GC3 and the coupled gate cut structure MCT that fills the third gate cut space GC3. Therefore, a separate patterning process is not required to form the connecting extension (GL-E). Therefore, the stacked integrated circuit element 1 can form a cross-coupled transistor with 2CPP (contacted poly pitches). In other words, the stacked integrated circuit element 1 can form a transistor with a pitch of 2, which is twice the pitch, which is the sum of the horizontal width of each of the multiple gate electrodes GL in the first horizontal direction (X direction) and the distance between two adjacent gate electrodes GL in the first horizontal direction (X direction), thus enabling scaling down.

[0072] Figure 17 is a cross-sectional view showing a stacked integrated circuit element according to another embodiment of the present invention. Specifically, Figure 17 is a cross-sectional view taken along the line B-B' in Figure 2. In the stacked integrated circuit element 2 shown in Figure 17, the cross-sectional view obtained by cutting along the line A-A' in Figure 2 is substantially identical to that of Figure 16A, and the cross-sectional view obtained by cutting along the line C-C' in Figure 2 is substantially identical to that of Figure 16C.

[0073] Referring to Figures 16A, 16C, and 17, the stacked integrated circuit element 2 includes a lower insulating layer BDI, a lower nanosheet stacked structure LNSS disposed on the lower insulating layer BDI, and a plurality of nanosheet stacked structures NSS, each including an upper nanosheet stacked structure UNSS disposed on the lower nanosheet stacked structure LNSS, an intermediate insulating layer MDI interposed between the lower nanosheet stacked structure LNSS and the upper nanosheet stacked structure UNSS, a gate electrode GL including a lower gate electrode LGL enclosing the lower nanosheet stacked structure LNSS and an upper gate electrode UGL enclosing the upper nanosheet stacked structure UNSS, a first contact plug CTA connected to the upper source / drain region SDU, and a lower source / drain The structure includes a second contact plug CTB connected to the rain region SDL, a lower gate cut structure LCT interposed between two lower nanosheet stacked structures LNSS adjacent in the second horizontal direction (Y direction), an upper gate cut structure UCT placed on the lower gate cut structure LCT and interposed between two upper nanosheet stacked structures UNSS adjacent in the second horizontal direction (Y direction), and a bonding gate cut structure MCT interposed between two nanosheet stacked structures NSS adjacent in the second horizontal direction (Y direction), separating the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT with at least one nanosheet stacked structure NSS in between.

[0074] The upper gate electrode UGL includes a connecting extension (GL-E) and a protruding portion (UGL-Pa). The lower gate cut structure LCT occupies the lower portion of the first gate cut space GC1, the upper gate cut structure UCT occupies the second gate cut space GC2a, and the combined gate cut structure MCT occupies the third gate cut space GC3. The protrusion (UGL-Pa) of the upper gate electrode UGL and the upper gate cut structure UCT fill the upper portion of the first gate cut space GC1. In one embodiment, the projection (UGL-Pa) of the upper gate electrode UGL is positioned on one side in the second horizontal direction (Y direction) with respect to the upper gate cut structure UCT, but not on the other side. For example, one portion of the upper surface of the lower gate cut structure LCT in the second horizontal direction (Y direction) is covered by the lower surface of the projection (UGL-Pa) of the upper gate electrode UGL, and the other portion in the second horizontal direction (Y direction) is covered by the lower surface of the upper gate cut structure UCT.

[0075] Figure 18 is a cross-sectional view showing a stacked integrated circuit element according to another embodiment of the present invention. Specifically, Figure 18 is a cross-sectional view taken along the line B-B' in Figure 2. In the stacked integrated circuit element 3 shown in Figure 18, the cross-sectional view obtained by cutting along the line A-A' in Figure 2 is substantially identical to that of Figure 16A, and the cross-sectional view obtained by cutting along the line C-C' in Figure 2 is substantially identical to that of Figure 16C.

[0076] Referring to Figures 16A, 16C, and 18, the stacked integrated circuit element 3 includes a lower insulating layer BDI, a lower nanosheet stacked structure LNSS disposed on the lower insulating layer BDI, and a plurality of nanosheet stacked structures NSS, each including an upper nanosheet stacked structure UNSS disposed on the lower nanosheet stacked structure LNSS, an intermediate insulating layer MDI interposed between the lower nanosheet stacked structure LNSS and the upper nanosheet stacked structure UNSS, a gate electrode GL including a lower gate electrode LGL surrounding the lower nanosheet stacked structure LNSS and an upper gate electrode UGL surrounding the upper nanosheet stacked structure UNSS, a first contact plug CTA connected to the upper source / drain region SDU, and a lower source / drain The structure includes a second contact plug CTB connected to the rain region SDL, a lower gate cut structure LCT interposed between two lower nanosheet stacked structures LNSS adjacent in the second horizontal direction (Y direction), an upper gate cut structure UCT placed on the lower gate cut structure LCT and interposed between two upper nanosheet stacked structures UNSS adjacent in the second horizontal direction (Y direction), and a bonding gate cut structure MCT interposed between two nanosheet stacked structures NSS adjacent in the second horizontal direction (Y direction), separating the lower gate cut structure LCT and the upper gate cut structure UCT on the lower gate cut structure LCT with at least one nanosheet stacked structure NSS.

[0077] The upper gate electrode UGL includes a connecting extension (GL-E) and a protruding portion (UGL-Pb). The lower gate cut structure LCT occupies the lower portion of the first gate cut space GC1, the upper gate cut structure UCT occupies the second gate cut space GC2b, and the combined gate cut structure MCT occupies the third gate cut space GC3. The protrusion (UGL-Pb) of the upper gate electrode UGL and the upper gate cut structure UCT fill the upper portion of the first gate cut space GC1. In one embodiment, the projection lengths of the pair of upper gate electrodes UGLs (UGL-Pb) located on both sides in the second horizontal direction (Y direction) with respect to the upper gate cut structure UCT are different from each other. For example, with respect to the upper gate cut structure UCT, the projection length of the projection portion (UGL-Pb) of the upper gate electrode UGL located on one side in the second horizontal direction (Y direction) is longer than the projection length of the projection portion (UGL-Pb) of the upper gate electrode UGL located on the other side.

[0078] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0079] 1, 2, 3 Stacked Integrated Circuit Elements BDI lower insulation layer BSUB base substrate layer CDL3 Third insulating layer CTA 1st Contact Plug CTB 2nd Contact Plug FDI interlayer insulation layer GC1 First gate cut space GC2 Second Gate Cut Space GC3 Third Gate Cut Space GCP Gate Capping Layer GL gate GL-E Connection Extension GS Gate Space LCT Lower Gate Cut Structure LGL Lower Shuttle Gate LGox lower gate insulating layer LGS Lower Gate Space LNS Lower Nanosheet LNSS Lower Nanosheet Laminated Structure MCT Joint Gate Cut Structure MDI Interlayer NSS Nanosheet Laminated Structure SD Source / Drain Area SDL Lower Source / Drain Area SDU Upper Source / Drain Area STR element isolation recess TRL lower transistor TRU (Top Transistor) UCT Upper Gate Cut Structure UGF Upper Charging Gate Layer UGL Upper Terminal UGM Upper Main Gate Layer UGox lower gate insulating layer UGS Upper Gate Space UGL-P, UGL-Pa, UGL-Pb protrusion UNS Upper Nanosheet UNSS upper nanosheet layered structure

Claims

1. A plurality of nanosheet laminated structures are arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, each including a lower nanosheet laminated structure and an upper nanosheet laminated structure placed on the lower nanosheet laminated structure. A gate separation portion interposed between the lower nanosheet laminated structure and the upper nanosheet laminated structure of each of the plurality of nanosheet laminated structures, A lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures, Each of the above-mentioned multiple nanosheet stacked structures comprises an upper gate electrode enclosing the upper nanosheet stacked structure, In at least one of the spaces between two adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures, a lower gate cut structure is disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure is disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures, The plurality of nanosheet stacked structures comprises a bond gate cut structure disposed between the two nanosheet stacked structures in at least one other space in the space between two adjacent nanosheet stacked structures along the second horizontal direction, A stacked integrated circuit element characterized in that the upper gate electrode extends along the side surface of the coupled gate cut structure and is connected to the lower gate electrode.

2. The stacked integrated circuit element according to claim 1, characterized in that the portion of the lower gate electrode that encloses the lower nanosheet stacked structure, which is located at least one side in the second horizontal direction between the lower gate cut structure and the upper gate cut structure on the lower gate cut structure, and the upper gate electrode that encloses the upper nanosheet stacked structure are separated from each other and not connected.

3. The width of the upper surface of the lower gate cut structure is greater than the width of the lower surface of the upper gate cut structure which is placed on the lower gate cut structure. The stacked integrated circuit element according to claim 1, characterized in that the upper gate electrode includes a protruding portion that protrudes vertically from a portion overlapping the gate separation portion to a portion overlapping the lower gate cut structure.

4. A portion of the upper surface of the lower gate cut structure is covered by the lower surface of the upper gate cut structure. The stacked integrated circuit element according to claim 3, characterized in that the other portion of the upper surface of the lower gate cut structure is covered by the lower surface of the protrusion.

5. The aforementioned lower nanosheet stacked structure includes a plurality of lower nanosheets arranged apart from each other along the vertical direction, The upper nanosheet stacked structure includes a plurality of upper nanosheets arranged spaced apart from each other along the vertical direction, The stacked integrated circuit element according to claim 1, characterized in that, in the second horizontal direction, the horizontal width of each of the plurality of lower nanosheets is greater than the horizontal width of each of the plurality of upper nanosheets.

6. A plurality of nanosheet laminated structures are arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, each including a lower nanosheet laminated structure and an upper nanosheet laminated structure placed on the lower nanosheet laminated structure. An intermediate insulating layer is interposed between the lower nanosheet laminated structure and the upper nanosheet laminated structure of each of the plurality of nanosheet laminated structures, A lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures, Each of the above-mentioned multiple nanosheet stacked structures comprises an upper gate electrode enclosing the upper nanosheet stacked structure, In at least one of the spaces between two adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures, a lower gate cut structure is disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure is disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures, The plurality of nanosheet stacked structures comprises a bond gate cut structure disposed between the two nanosheet stacked structures in at least one other space in the space between two adjacent nanosheet stacked structures along the second horizontal direction, The aforementioned upper terminal is, A connecting extension portion extends along the side surface of the coupling gate cut structure and is connected to the lower gate electrode, A stacked integrated circuit element characterized by including a protruding portion that extends vertically from a portion overlapping the intermediate insulating layer to a portion overlapping the lower gate cut structure.

7. The width of the upper surface of the lower gate cut structure is greater than the width of the lower surface of the upper gate cut structure which is placed on the lower gate cut structure. A portion of the upper surface of the lower gate cut structure is covered by the lower surface of the upper gate cut structure. The stacked integrated circuit element according to claim 6, characterized in that the other portion of the upper surface of the lower gate cut structure is covered by the lower surface of the protrusion.

8. The stacked integrated circuit element according to claim 6, characterized in that the portion of the lower gate electrode that encloses the lower nanosheet stacked structure, which is located at least one side in the second horizontal direction between the lower gate cut structure and the upper gate cut structure on the lower gate cut structure, and the portion of the upper gate electrode that encloses the upper nanosheet stacked structure, are not connected to each other and are separated by the intermediate insulating layer and the lower gate cut structure.

9. The upper nanosheet laminated structure includes a plurality of upper nanosheets arranged spaced apart from each other along the vertical direction and each having a first horizontal width in the second horizontal direction. The stacked integrated circuit element according to claim 6, characterized in that the lower nanosheet stacked structure includes a plurality of lower nanosheets arranged spaced apart from each other along the vertical direction and each having a second horizontal width greater than the first horizontal width in the second horizontal direction.

10. A plurality of nanosheet laminated structures, including a lower nanosheet laminated structure comprising a plurality of lower nanosheets arranged in rows and columns along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and each separated from each other along the vertical direction, and an upper nanosheet laminated structure comprising a plurality of upper nanosheets arranged on the lower nanosheet laminated structure and separated from each other along the vertical direction, A gate separation portion interposed between the lower nanosheet laminated structure and the upper nanosheet laminated structure of each of the plurality of nanosheet laminated structures, A lower gate electrode enclosing the lower nanosheet stacked structure of each of the plurality of nanosheet stacked structures, Each of the above-mentioned multiple nanosheet stacked structures comprises an upper gate electrode enclosing the upper nanosheet stacked structure, In at least one of the spaces between two adjacent nanosheet stacked structures along the second horizontal direction among the plurality of nanosheet stacked structures, a lower gate cut structure is disposed between two lower nanosheet stacked structures comprising the two nanosheet stacked structures, and an upper gate cut structure is disposed on the lower gate cut structure between two upper nanosheet stacked structures comprising the two nanosheet stacked structures, The plurality of nanosheet stacked structures comprises a bond gate cut structure disposed between the two nanosheet stacked structures in at least one other space in the space between two adjacent nanosheet stacked structures along the second horizontal direction, The aforementioned upper terminal is, A connecting extension portion extends along the side surface of the coupling gate cut structure and is connected to the lower gate electrode, It includes a projection that extends from the portion overlapping the gate separation portion in the vertical direction to the portion overlapping the lower gate cut structure, and covers a portion of the upper surface of the lower gate cut structure, A stacked integrated circuit element characterized in that, in the second horizontal direction, the horizontal width of each of the plurality of lower nanosheets is greater than the horizontal width of each of the plurality of upper nanosheets.

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