Display control unit

Abstract

This prevents white streaks from appearing on the LCD display unit screen when the power is turned off, such as during a forced power off. [Solution] The CPU 112 outputs a vertical synchronization signal (VSYNC), a screen display control signal (DISP signal), and a backlight signal (LEDA signal) to the LCD 130. When the PMIC 111 detects the pressing of the power switch PSW while the PMIC 111 is powered on, and a power-off operation signal is input from the PMIC 111 to the CPU 112, the CPU 112 performs a first switching process to switch the LEDA signal from output operation to output stop. After the first switching process, the CPU 112 performs a second switching process to switch the DISP signal from output operation to output stop. After the second switching process, the CPU 112 performs a third switching process to switch the vertical synchronization signal from output operation to output stop.

Description

Technical Field

[0001] The present invention relates to a display control unit, and more particularly to a display control unit that switches the screen of a liquid crystal display unit between a display state and a non-display state.

Background Art

[0002] Conventionally, various techniques have been provided to solve problems occurring in the display of display units such as liquid crystal display units. For example, Patent Document 1 individually controls a plurality of partial display panels corresponding to a plurality of divided regions obtained by dividing the display region of a display unit with a plurality of sub-display control units provided in association with these plurality of partial display panels, detects a display abnormality in each sub-display control unit or the corresponding partial display panel with a display abnormality detection unit, and restarts the sub-display control unit in which an abnormality has occurred based on the detection result of the display abnormality detection unit, so that the display of the partial display panel corresponding to the sub-display control unit in which no abnormality has occurred is continued and the partial display abnormality on the screen is normally restored.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when the device enters an abnormal state such as freezing and the power of the device is forcibly turned off, in a conventional display control system that controls the display of a liquid crystal display unit, white streaks may appear on the screen of the liquid crystal display unit. This will be described below.

[0005] Conventional display control systems include a power management unit to which a power switch is connected, a first board equipped with a first control unit capable of communicating with the power management unit, and a second board equipped with an FET arranged in the wire between the power management unit and the liquid crystal display unit, and a second control unit capable of switching the conductive and non-conductive states of the FET and communicating with the first control unit.

[0006] The first control unit outputs a Vertical Synchronizing Signal (VSYNC) and image data signals to the liquid crystal display unit. The second control unit outputs a screen display control signal (DISP signal) and a backlight signal (LEDA signal) to the liquid crystal display unit. When the DISP signal level is high, the screen of the liquid crystal display unit is displayed, and when the signal level is low, the screen of the liquid crystal display unit is not displayed. Also, when the LEDA signal level is high, the backlight of the liquid crystal display unit is turned on, and when the signal level is low, the backlight is turned off.

[0007] In the event of a forced power off due to an abnormality such as the device freezing, if the user presses and holds the power switch for a predetermined amount of time or longer while the device is powered on, the power management unit detects the prolonged press and forcibly switches the device, including the display control system, to a power-off state.

[0008] At this time, the first control unit, which can communicate with the power management unit, detects that the power is being forcibly turned off based on the forced power-off operation signal that the power management unit outputs to the first control unit when it detects that the power switch has been pressed for a predetermined amount of time or longer while the power is on. The first control unit then stops outputting the image data signal and the vertical synchronization signal to the liquid crystal display unit, causing the signal level of the vertical synchronization signal to remain at a low level.

[0009] On the other hand, the second control unit, which does not communicate with the power management unit, cannot detect that the power is forcibly turned off even if the power management unit detects that the power switch has been pressed for a predetermined amount of time or longer while the power is on. Therefore, at the moment when voltage is no longer supplied to the liquid crystal display unit, the output of the DISP signal and LEDA signal from the second control unit to the liquid crystal display unit stops, the signal levels of the DISP signal and LEDA signal transition from high to low, and the signal levels of the DISP signal and LEDA signal remain at a low level.

[0010] In conventional display control systems, the output of the DISP signal and LEDA signal by the second control unit stops after the output of the image data signal and vertical synchronization signal by the first control unit. As a result, white streaks appear on the screen of the liquid crystal display unit during the period between the stop of the output of the image data signal and vertical synchronization signal by the first control unit and the stop of the output of the DISP signal and LEDA signal by the second control unit.

[0011] This invention has been made in view of the above circumstances, and aims to prevent white streaks from appearing on the screen of the liquid crystal display unit when the power is turned off, such as by forced power off. [Means for solving the problem]

[0012] A display control unit according to one aspect of the present invention is a display control unit that controls the display of a liquid crystal display unit, comprising: a power management unit to which a power switch is connected; and a control unit that receives a voltage signal from the power management unit and communicates with the power management unit, wherein the control unit outputs a vertical synchronization signal, a screen display control signal which causes the screen of the liquid crystal display unit to display when the signal level is high and the screen of the liquid crystal display unit to be turned off when the signal level is low, and a backlight signal which causes the backlight constituting the liquid crystal display unit to be turned on when the signal level is high and the backlight to be turned off when the signal level is low, and when the power management unit detects the pressing of the power switch while the power management unit is powered on and outputs a power off operation signal to the control unit, the control unit performs a first switching process which switches the output operation to output stop for the backlight signal, after the first switching process, performs a second switching process which switches the output operation to output stop for the screen display control signal, and after the second switching process, performs a third switching process which switches the output operation to output stop for the vertical synchronization signal. [Effects of the Invention]

[0013] According to the present invention, a single control unit that can communicate with the power management unit controls the switching of output operation (on) to output stop (off) for the backlight signal, screen display control signal, and vertical synchronization signal. This makes it possible to control the order in which the output of the backlight signal, screen display control signal, and vertical synchronization signal is stopped. By controlling the output to stop (off) in the order of backlight signal, screen display control signal, and vertical synchronization signal, it is possible to prevent white streaks from appearing on the screen of the liquid crystal display unit when the power is turned off, such as in a forced power off. [Brief explanation of the drawing]

[0014] [Figure 1] This is a system configuration diagram of a display control system according to one embodiment of the present invention. [Figure 2]This flowchart shows the processing steps performed by the CPU mounted on the main board shown in Figure 1. [Figure 3] This figure shows the timing chart for some of the signals in the display control system shown in Figure 1. [Figure 4] This is a system configuration diagram of the display control system in the comparative example. [Figure 5] This figure shows the sequence of screen blackouts for the LCD when the display control system of the comparative example in Figure 4 is forcibly powered off. [Figure 6] Figure 5 shows an example of white lines that appear on the LCD screen during the screen blackout sequence when the power is forcibly turned off. [Modes for carrying out the invention]

[0015] The following describes a display control system according to one embodiment of the present invention, with reference to the drawings.

[0016] First, the system configuration of the display control system 100 according to one embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a system configuration diagram of the display control system 100 according to one embodiment of the present invention.

[0017] The display control system 100 performs display control of an LCD (Liquid Crystal Display) 130, and includes a main board 110 equipped with a PMIC (Power Management Integrated Circuit) 111 and a CPU (Central Processing Unit) 112, and a panel board 120 equipped with a FET (Field Effect Transistor) 121 and a CPU 122. The unit including the PMIC 111 and the CPU 112 mounted on the main board 110 is an example of a display control unit in the claims. The PMIC 111 is an example of a power management unit in the claims. The CPU 112 is an example of a control unit in the claims. The main board 110 is an example of a first board in the claims. The CPU 122 is an example of another control unit in the claims. The panel board 120 is an example of a second board in the claims.

[0018] A power switch PSW is connected to the PMIC 111. The PMIC 111 is an IC that performs power management such as converting a voltage of 24 (V) to a voltage of 3.3 (V). When the PMIC 111 detects that the user has performed an operation to turn on the power using the power switch PSW, it performs an output operation of the 3.3V1_C signal (3.3V1_C signal ON), and supplies the 3.3V1_C signal with a voltage of 3.3 (V) to the CPU 112, the CPU 122, the FET 121, etc. Also, when the PMIC 111 detects that the user has performed an operation to turn off the power using the power switch PSW (for example, an operation of pressing the power switch PSW for less than a predetermined time (normal power-off operation), an operation of pressing and holding the power switch PSW for a predetermined time or longer (forced power-off operation)), it stops the output of the 3.3V1_C signal (3.3V1_C signal OFF), the voltage of the 3.3V1_C signal becomes 0 (V), and the voltage is no longer supplied from the PMIC 111 to the CPU 112, the CPU 122, the FET 121, etc.

[0019] The CPU 112 is constructed by, for example, an ASIC (Application Specific Integrated Circuit) and is supplied with a 3.3V1_C signal having a voltage of 3.3 (V) or 0 (V) from the PMIC 111. The CPU 112 is capable of communicating with the PMIC 111, a communication signal is transmitted and received between the CPU 112 and the PMIC 111, the CPU 112 is capable of communicating with the CPU 122 mounted on the panel board 120, and a communication signal is transmitted and received between the CPU 112 and the CPU 122.

[0020] The FET 121 is arranged on the electric wire between the PMIC 111 and the LCD 130 and is switched between a conductive state and a non-conductive state by the CPU 122. Note that the FET 121 is an example of a switching circuit, and the switching circuit arranged on the electric wire between the PMIC 111 and the LCD 130 may be a switching circuit other than the FET.

[0021] The CPU 122 is supplied with a 3.3V1_C signal having a voltage of 3.3 (V) or 0 (V) from the PMIC 111. The CPU 122 is capable of communicating with the CPU 112 mounted on the main board 110, and a communication signal is transmitted and received between the CPU 122 and the CPU 112. The CPU 122 switches the FET 121 between a conductive state and a non-conductive state. The CPU 122, for example, turns on the FET 121 when the power is turned on and controls the FET 121 to be in a non-conductive state when the power is turned off. The 3.3V1_REC signal supplied to the LCD 130 becomes 3.3 (V) when the CPU 122 controls the FET 121 to be in a conductive state when the voltage of the 3.3V1_C signal is 3.3 (V), and becomes 0 (V) when the CPU 122 controls the FET 121 to be in a non-conductive state when the voltage of the 3.3V1_C signal is 3.3 (V), and also becomes 0 (V) when the voltage of the 3.3V1_C signal is 3.3 (V).

[0022] The CPU 112 outputs a backlight signal (LEDA signal) to the LCD 130. The LEDA signal is used to switch between the on and off states of the backlight of the LED 130. When the signal level is high (greater than 0(V), for example 2(V)), the backlight is on, and when the signal level is low (0(V)), the backlight is off. For example, when the CPU 112 receives a power-on operation signal from the PMIC 111, which is output to the CPU 112 when the PMIC 111 has been turned on using the power switch PSW, the CPU 112 performs the LEDA signal output operation (LEDA signal ON), transitions the signal level of the LEDA signal from low to high, and outputs the high-level LEDA signal to the LCD 130. For example, when the CPU 112 receives a power-off operation signal from the PMIC 111 that the PMIC 111 outputs to the CPU 112 when it detects an operation to turn off the power using the power switch PSW (normal power-off operation, forced power-off operation), it stops outputting the LEDA signal (LEDA signal OFF) as described later, and the signal level of the LEDA signal remains at a low level.

[0023] The CPU 112 outputs a screen display control signal (DISP signal) to the LCD 130. The DISP signal is used to switch the LCD 130 screen between a displayed state and a hidden state. When the signal level is high (greater than 0(V), for example 2(V)), the LCD 130 screen is displayed, and when the signal level is low (0(V)), the LCD 130 screen is hidden. For example, when the CPU 112 receives the power-on operation signal from the PMIC 111 as described above, it performs the DISP signal output operation (DISP signal ON), transitions the signal level of the DISP signal from low to high, and outputs a DISP signal with a high signal level to the LCD 130. For example, when the CPU 112 receives the power-off operation signal from the PMIC 111 as described above, it stops outputting the DISP signal (DISP signal OFF) as described later, and the signal level of the DISP signal remains low.

[0024] The CPU 112 outputs a vertical synchronization signal to the LCD 130. The vertical synchronization signal is a signal that indicates the timing for starting the scanning of one screen (one frame). For example, when the CPU 112 receives the power-on operation signal from the PMIC 111 as described above, it performs the operation of outputting the vertical synchronization signal (VSYNC) (vertical synchronization signal ON), and outputs a vertical synchronization signal to the LCD 130 that alternates between a high level (greater than 0(V), for example, 2(V)) and a low level (0(V)). For example, when the CPU 112 receives the power-off operation signal from the PMIC 111 as described above, it stops outputting the vertical synchronization signal (VSYNC) (vertical synchronization signal OFF) as described later, and the signal level of the vertical synchronization signal remains at a low level.

[0025] The CPU 122 outputs image data signals for the images to be displayed on the LCD 130 screen, which are stored in memory (not shown), to the LCD 130. The image data signals have two signal levels: high level (greater than 0(V), for example, 2(V): image data value "1") and low level (0(V): image data value "0").

[0026] LCD130 displays the screen when the DISP signal level is high, turns on the backlight when the LEDA signal level is high, and displays an image on the screen based on the image data signal while maintaining vertical synchronization with the vertical synchronization signal. On the other hand, LCD130 turns off the screen when the DISP signal level is low, and turns off the backlight when the LEDA signal level is low. When the DISP signal level is high, LCD130 displays an image on the screen by operating the drive circuits that drive each part of LCD130. On the other hand, when the DISP signal level is low, LCD130 prevents an image from being displayed on the screen by stopping the drive circuits that drive each part of LCD130.

[0027] When the aforementioned power-off operation signal is input from the PMIC111, the CPU112 performs a first switching process to switch the LEDA signal from output operation to output stop, and after the first switching process, it performs a second switching process to switch the DISP signal from output operation to output stop, and after the second switching process, it performs a third switching process to switch the vertical synchronization signal from output operation to output stop.

[0028] When a power-off operation signal is input from the PMIC111, the CPU112 restarts itself until the output operation of the LEDA signal is confirmed. After the output operation of the backlight signal is confirmed, the CPU112 performs the first switching process.

[0029] CPU 112 determines whether or not the LEDA signal is being output. If it determines that the LEDA signal is being output, it performs a first switching process to switch the LEDA signal from output to output stop. After the first switching process, it determines whether or not the DISP signal is being output. If it determines that the DISP signal is not being output, it determines again whether or not the LEDA signal is being output. If it determines that the DISP signal is being output, it performs a second switching process to switch the DISP signal from output to output stop. After the second switching process, it determines whether or not the DISP signal is output stop. If it determines that the DISP signal is not output stop, it performs a second switching process to switch the DISP signal from output to output stop. If it determines that the DISP signal is output stop, it determines whether or not the vertical synchronization signal is being output. If it determines that the vertical synchronization signal is not being output, it determines again whether or not the DISP signal is being output. If it determines that the vertical synchronization signal is being output, it performs a third switching process to switch the vertical synchronization signal from output to output stop.

[0030] Next, the processing performed by the CPU 112 in Figure 1 will be explained with reference to Figure 2. Figure 2 is a flowchart showing the processing steps of the CPU 112 in Figure 1. The CPU 112 executes the processing steps shown in the flowchart of Figure 2 by reading a program containing the processing steps shown in the flowchart of Figure 2, which is stored in memory (not shown), from that memory and executing it. The processing steps shown in the flowchart of Figure 2 may also be implemented in hardware.

[0031] If the PMIC111 detects that the user has performed an operation to turn off the power using the power switch PSW while the power is on (a normal power-off operation or a forced power-off operation), it outputs a power-off operation signal to the CPU112. The CPU112 determines whether or not the user pressed the power switch PSW to turn off the power using the power switch PSW, based on whether or not it received the power-off operation signal from the power IC111 (step S1). In the determination process of step S1, if the CPU112 determines that the user did not press the power switch PSW to turn off the power using the power switch PSW (S1:NO), the CPU112 returns to the process of step S1.

[0032] In the determination process of step S1, if the CPU 112 determines that the user has pressed the power switch PSW to turn the power off from the power-on state (S1:YES), the CPU 112 determines whether or not its unit is performing the LEDA signal output operation (whether or not the LEDA signal is ON) (step S2). In the determination process of step S2, if the CPU 112 determines that its unit is performing the LEAD signal output operation (S2:YES), the CPU 112 proceeds to the process of step S5.

[0033] If the CPU 112 determines in the determination process of step S2 that its unit is not performing the LEDA signal output operation (S2: NO), the CPU 112 restarts its own unit (CPU 112) (step S3).

[0034] Following step S3, the CPU 112 determines whether or not its unit is performing the LEDA signal output operation (whether or not the LEDA signal is ON) (step S4). If the CPU 112 determines in the determination process of step S4 that its unit is not performing the LEDA signal output operation (S4: NO), the CPU 112 returns to the process of step S3. On the other hand, if the CPU 112 determines in the determination process of step S4 that its unit is performing the LEDA signal output operation (S4: YES), the CPU 112 proceeds to the process of step S5.

[0035] For example, if an abnormality occurs in the operation of the CPU 112 from the beginning and the LEDA signal is not output from the CPU 112 to the LCD 130 (i.e., the backlight that makes up the LCD 130 does not light up from the beginning), the CPU 112 will repeatedly restart itself through the processes from steps S2 to S4 described above until it confirms that its own unit is outputting the LEDA signal. If no abnormality occurs, the CPU 112 will perform output operations such as the LEDA signal, DISP signal, and vertical synchronization signal after restarting.

[0036] If the CPU 112 determines in the determination process of step S2 that its unit is performing an LEDA signal output operation (S2:YES), or if the CPU 112 determines in the determination process of step S4 that its unit is performing an LEDA signal output operation (S4:YES), the CPU 112 switches from output operation (LEAD signal ON) to output stop (LEDA signal OFF) for the LEDA signal, and the signal level of the LEDA signal remains at a low level (step S5).

[0037] Following the processing in step S5, the CPU 112 determines whether or not its unit is performing the DISP signal output operation (whether or not the DISP signal is ON) (step S6). If the CPU 112 determines in the determination process in step S6 that its unit is not performing the DISP signal output operation (S6: NO), the CPU 112 returns to the processing in step S2. For example, if the DISP signal output operation is not performed due to an abnormality, the CPU 112 returns to the processing in step S2 to check again whether or not the LEAD signal output operation is being performed. This makes it possible to more reliably switch from output operation to output stop for the LEDA signal, and switch from output operation to output stop for the DIPS signal while the LEDA signal output is stopped.

[0038] In the determination process of step S6, if the CPU 112 determines that its unit is performing the output operation of the DISP signal (S6: YES), the CPU 112 switches from output operation (DISP signal ON) to output stop (DISP signal OFF) for the DISP signal, the signal level of the DISP signal transitions from a high level to a low level and remains at a low level, and the flag is set to "0" (step S7). For example, when the CPU 112 performs the output operation of the DISP signal (DISP signal ON), it sets the flag to "1".

[0039] Following step S7, CPU 112 determines whether the flag is "0" (whether its unit has stopped outputting the DISP signal) (step S8). If CPU 112 determines in the determination process of step S8 that the flag is not "0" (S8:NO), CPU 112 returns to the process of step S7. For example, if it is determined that the flag is not "0" due to an abnormality, CPU 112 returns to the process of step S7 and stops outputting the DISP signal again (DISP signal OFF), causing the signal level of the DISP signal to transition from high level to low level, and sets the flag to "0".

[0040] If the CPU 112 determines in the determination process of step S8 that the flag is "0" (S8:YES), the CPU 112 determines whether or not its unit is outputting the vertical synchronization signal (VSYNC) (whether or not the vertical synchronization signal is ON) (step S9). If the CPU 112 determines in the determination process of step S9 that it is not outputting the vertical synchronization signal (S9:NO), the CPU 112 returns to the process of step S6. For example, if the vertical synchronization signal is not outputting due to an abnormality, the CPU 112 returns to the process of step S6 to check again whether or not the DISP signal is being outputted. This makes it possible to more reliably switch from outputting to stopping outputting the DISP signal, and from outputting to stopping outputting the vertical synchronization signal while the DISP signal is stopped from outputting.

[0041] In the determination process of step S9, if the CPU 112 determines that its unit is performing the output operation of the vertical synchronization signal (S9: YES), the CPU 112 switches from output operation (vertical synchronization signal ON) to output stop (vertical synchronization signal OFF) for the vertical synchronization signal, and the signal level of the vertical synchronization signal remains at a low level (step S10).

[0042] Following the processing in step S10, the CPU 112 outputs an inquiry signal to the PMIC 111 to ask whether or not it is performing the 3.3V1_C signal output operation (whether or not the 3.3V1_C signal is ON), receives a response signal from the PMIC 111 indicating whether or not it is performing the 3.3V1_C signal output operation, and determines whether or not the PMIC 111 is performing the 3.3V1_C signal output operation based on the response signal (step S11). Here, the CPU 112 is able to operate even if the voltage of the 3.3V1_C signal becomes 0 (V) due to its built-in capacitor. If the CPU 112 determines in the determination process of step S11 that the PMIC 111 is not performing the 3.3V1_C signal output operation (S11: NO), the CPU 112 returns to the processing in step S9. For example, if the 3.3V1_C signal output operation is not performed due to an abnormality, the CPU 112 returns to the processing in step S9 and checks again whether the vertical synchronization signal output operation is being performed.

[0043] In the determination process of step S11, if the CPU 112 determines that the PMIC 111 is performing the output operation of the 3.3V1_C signal (S11: YES), the CPU 112 outputs a request signal to the PMIC 111 requesting that it switch from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal (step S12). Upon receiving the request signal from the CPU 112, the PMIC 111 switches from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal, and the voltage supply from the PMIC 111 to the CPU 112, CPU 122, and FET 121 downstream of the PMIC 111 stops.

[0044] In this way, when the CPU 112 executes the processing steps shown in the flowchart of Figure 2, the LEDA signal is turned OFF, the DISP signal is turned OFF, the vertical synchronization signal is turned OFF, and the 3.3V1_C signal is turned OFF in that order (LEDA signal OFF → DISP signal OFF → vertical synchronization signal OFF → 3.3V1_C signal OFF).

[0045] Next, the processing of the display control system 100 in Figure 1 will be explained with reference to Figure 3. Figure 3 is a timing chart of some of the signals in the display control system 100 in Figure 1.

[0046] At timing T1, if the PMIC111 detects that the user has performed an operation to turn off the power using the power switch PSW while the power is on (a normal power off operation, a forced power off operation), it will output a power off operation signal to the CPU112. Upon receiving the power off operation signal from the power IC111, the CPU112 determines that the user has pressed the power switch PSW to turn the power off from the power-on state (step S1, YES in step S1).

[0047] The CPU 112 determines whether its unit is performing an output operation of the LEDA signal (whether the LEDA signal is ON or OFF) (step S2). If it determines that its unit is performing an output operation of the LEDA signal (YES in step S2), it switches from output operation (LEAD signal ON) to output stop (LEDA signal OFF) for the LEDA signal at a timing T2 that is later than timing T1 (for example, timing T2 that is 1 second or more later than timing T1), and the signal level of the LEDA signal remains at a low level (step S5).

[0048] The CPU 112 determines whether its unit is performing the DISP signal output operation (whether the DISP signal is ON or OFF) (step S6), and if it determines that its unit is performing the DISP signal output operation (YES in step S6), at timing T3, which is later than timing T2, it switches from output operation (DISP signal ON) to output stop (DISP signal OFF) for the DISP signal, the signal level of the DISP signal transitions from a high level to a low level and remains at a low level, and the flag is set to "0" (step S7).

[0049] The CPU 112 determines whether the flag is "0" (step S8), determines that the flag is "0" (YES in step S8), determines whether its unit is performing the vertical synchronization signal (VSYNC) output operation (whether the vertical synchronization signal is ON) (step S9), determines that its unit is performing the vertical synchronization signal output operation (YES in step S9), and at timing T4, which is later than timing T3, switches from output operation (vertical synchronization signal ON) to output stop (vertical synchronization signal OFF) for the vertical synchronization signal, and the signal level of the vertical synchronization signal remains at a low level (step S10).

[0050] The CPU 112 determines whether the PMIC 111 is performing the output operation of the 3.3V1_C signal (step S11), and if it determines that the PMIC 111 is performing the output operation of the 3.3V1_C signal (YES in step S11), it outputs a request signal to the PMIC 111 requesting that it switch from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal (step S12). Upon receiving the request signal from the CPU 112, the PMIC 111 switches from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal at a timing T5 that is later than timing T4 (for example, timing T5 that is 100 milliseconds or more later than timing T4), and the voltage supply from the PMIC 111 to the CPU 112, CPU 122, and FET 121 that are downstream of the PMIC 111 stops. Additionally, the 3.3V1_REC signal from FET121 to LCD130 changes from 3.3V to 0V.

[0051] The display control system 100C, which is compared with the display control system 100 of this embodiment, will be described below with reference to Figures 4 to 6.

[0052] Figure 4 is a system configuration diagram of the comparative example display control system 100C. The display control system 100C controls the display of the LCD 130 and comprises a main board 110C equipped with a PMIC 111 connected to a power switch PSW and a CPU 112C, and a panel board 120C equipped with an FET 121 and a CPU 122C.

[0053] The comparative example PMIC111 operates similarly to the PMIC111 of this embodiment. However, unlike the PMIC111 of this embodiment, the comparative example PMIC111 does not receive a notification signal from the CPU112 to switch from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal. Instead, it switches from output operation (3.3V1_C signal ON) to output stop (3.3V1_C signal OFF) for the 3.3V1_C signal after a predetermined time has elapsed since detecting that the power switch PSW has been pressed while the power is on. Furthermore, the comparative example LCD130 operates similarly to the LCD130 of this embodiment.

[0054] CPU112C is supplied with a 3.3V1_C signal from PMIC111, with a voltage of either 3.3V or 0V. CPU112C can communicate with PMIC111 and can communicate with CPU122C mounted on panel board 120C.

[0055] The CPU122C is supplied with a 3.3V1_C signal from the PMIC111, with a voltage of either 3.3V or 0V. The CPU122C can communicate with the CPU112C mounted on the main board 110C. The CPU122C switches the FET121, which is located in the wire between the PMIC111 and the LCD130, between a conductive state and a non-conductive state. For example, the CPU122C controls the FET121 to be conductive when the power is turned on and to a non-conductive state when the power is turned off. The 3.3V1_REC signal supplied to the LCD130 is 3.3V when the voltage of the 3.3V1_C signal is 3.3V and the FET121 is controlled to a conduction state by the CPU122C, and is 0V when the voltage of the 3.3V1_C signal is 3.3V and the FET121 is controlled to a non-conduction state by the CPU122, or when the voltage of the 3.3V1_C signal is 3.3V.

[0056] The CPU 112C outputs a vertical synchronization signal and an image data signal to the LCD 130. The signals that the CPU 112 in this embodiment outputs to the LCD 130 are the vertical synchronization signal, the screen display control signal (DISP signal), and the backlight signal (LEDA signal). Thus, the signals that the CPU 112C in the comparative example outputs to the LCD 130 are different from the signals that the CPU 112 in this embodiment outputs to the LCD 130.

[0057] The CPU 122C outputs a screen display control signal (DISP signal) and a backlight signal (LEDA signal) to the LCD 130. The signal that the CPU 122 in this embodiment outputs to the LCD 130 is an image data signal. Thus, the signal that the CPU 122C in the comparative example outputs to the LCD 130 is different from the signal that the CPU 122 in this embodiment outputs to the LCD 130.

[0058] Next, we will explain the sequence for turning off the LCD 130 screen during normal power-off using the comparative example display control system 100C, whose system configuration is shown in Figure 4 (the sequence for switching the LCD 130 screen from the displayed state to the hidden state).

[0059] In a normal power-off state, the PMIC111 detects when the power switch PSW is pressed for less than a predetermined time while the power is on, and outputs a normal power-off operation signal to the CPU112C. When the CPU112C receives a normal power-off operation signal from the PMIC111, it outputs a normal power-off operation signal to the CPU122C. The CPU112C and CPU122C communicate with each other, and the blackout sequence is performed in the following order: (1) CPU112C switches the output operation for the image data signal output to LCD130 from output ON (image data signal ON) to output stop (image data signal OFF); (2) CPU122C switches the output operation for the LEDA signal from output ON (LEDA signal ON) to output stop (LEDA signal OFF) and the output operation for the DISP signal from output ON (DISP signal ON) to output stop (DISP signal OFF); (3) CPU112C switches the output operation for the signal level of the vertical synchronization signal from output ON (vertical synchronization signal ON) to output stop (vertical synchronization signal OFF); and (4) CPU122C controls FET121 to a non-conductive state (as a result, the voltage of the 3.3V1_REC signal becomes 0 (V), and voltage is no longer supplied to LCD130).

[0060] In the normal power-off sequence for the LCD130 screen described above, the LEDA signal and DISP signal stop outputting (LEDA signal OFF and DISP signal OFF) and remain at a low level before the vertical sync signal stops outputting (vertical sync signal OFF) and remains at a low level, so no white streaks appear on the LCD130 screen.

[0061] Next, we will explain the sequence of screen blackout of the LCD 130 when the display control system 100C of the comparative example, whose system configuration is shown in Figure 4, is forcibly powered off in the event of an abnormality such as the device freezing, with reference to Figure 5. Figure 5 is a diagram illustrating the sequence of screen blackout of the LCD 130 when the display control system 100C of the comparative example in Figure 4 is forcibly powered off.

[0062] In the case of a forced power off, the PMIC111 detects that the power switch PSW has been pressed for a predetermined amount of time or longer while the power is on, and outputs a forced power off operation signal to the CPU112C, which can communicate with the PMIC111. The CPU112C can detect that the power has been forcibly turned off by receiving the forced power off operation signal. On the other hand, the PMIC111 cannot output a forced power off operation signal to the CPU112C, which cannot communicate with the PMIC111, and the CPU112C cannot detect that the power has been forcibly turned off. For this reason, the screen off sequence of the LCD130 in the case of a forced power off is different from the screen off sequence of the LCD130 in the case of a normal power off, and is as shown in Figure 5 below, in the order of (1) and (2) below.

[0063] (1) Based on the forced power off operation signal input from PMIC111, CPU112C detects that the power is forcibly turned off and switches the output operation for the image data signal from output operation (image data signal ON) to output stop (image data signal OFF), and also switches the output operation for the vertical synchronization signal from output operation (vertical synchronization signal ON) to output stop (vertical synchronization signal OFF), and the signal level of the vertical synchronization signal remains at a low level.

[0064] (2) At the moment the voltage of the 3.3V1_REC signal supplied to the LCD130 becomes 0(V), the LEDA signal and DISP signal output from the CPU122C to the LCD130 switch from output operation (LEDA signal ON, DISP signal ON) to output stop (LEDA signal OFF, DISP signal OFF), and the signal levels of the LEDA signal and the DISP signal remain at a low level.

[0065] In the LCD130 screen blackout sequence during the forced power-off described above, a white streak appears on the LCD130 screen during the period from when the vertical synchronization signal output stops (vertical synchronization signal OFF) to when the LEDA signal output stops (LEDA signal) and the DISP signal output stops (DISP signal OFF) (for example, 0.1 seconds), as shown in Figure 6 as an example.

[0066] According to the embodiment described above, a single CPU 112 that can communicate with the PMIC 111 controls the switching of output operation (on) to output stop (off) for the LEDA signal, DISP signal, and vertical synchronization signal, thereby enabling control of the order in which the LEDA signal, DISP signal, and vertical synchronization signal are stopped from output. By controlling the switching from output operation to output stop in the order of LEDA signal, DISP signal, and vertical synchronization signal, it is possible to prevent white lines from appearing on the LCD 130 screen during normal power off and forced power off.

[0067] It should be noted that the present invention is not limited to the configurations of the above embodiments, and various modifications are possible. Furthermore, the configurations and processes shown in the above embodiments using Figures 1 to 3 are merely one embodiment of the present invention, and the present invention is not intended to be limited to these configurations and processes. [Explanation of symbols]

[0068] 100 Display Control System 110 Mainboard 111 PMIC (power management IC) 112 CPU 120 Panel Board 121 FET 122 CPU 130 LCD

Claims

1. A display control unit that controls the display of a liquid crystal display unit, The system comprises a power management unit to which a power switch is connected, and a control unit that receives a voltage signal from the power management unit and communicates with the power management unit. The control unit, A vertical synchronization signal, a screen display control signal which causes the screen of the liquid crystal display unit to display when the signal level is high and to turn off when the signal level is low, and a backlight signal which causes the backlight constituting the liquid crystal display unit to turn on when the signal level is high and to turn off when the signal level is low are output to the liquid crystal display unit. When the power management unit detects the pressing of the power switch while the power management unit is powered on, and a power-off operation signal is input from the power management unit to the control unit, A first switching process is performed to switch the backlight signal from output operation to output stop. After the first switching process, a second switching process is performed to switch the screen display control signal from output operation to output stop. After the second switching process, a third switching process is performed to switch the output operation to output stop in relation to the vertical synchronization signal. Display control unit.

2. The display control unit according to claim 1, wherein when the power off operation signal is input from the power management unit, the control unit restarts until the output operation of the backlight signal is confirmed, and after the output operation of the backlight signal is confirmed, the first switching process is performed.

3. The aforementioned display control unit is mounted on the first board, The display control unit according to claim 1 or claim 2, wherein the control unit is mounted on a second board and communicates with another control unit that outputs image data of an image to be displayed on the screen of the liquid crystal display unit to the liquid crystal display unit.

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