Signal processing device, image sensor, and electronic device

Abstract

To further improve the characteristics. [Solution] The comparator comprises a differential pair formed by a first group of transistors to which a first input signal is input to the gate terminal via a first capacitor, and a second group of transistors to which a second input signal, whose magnitude relationship with the first input signal is compared, is input to the gate terminal via a second capacitor. The number of transistors to which the first input signal is input to the gate terminal of the first group of transistors is switchable, and the number of transistors to which the second input signal is input to the gate terminal of the second group of transistors is switchable. This technology can be applied, for example, to a CMOS image sensor.

Description

Technical Field

[0005] , , ,

[0001] The present disclosure relates to a signal processing device, an imaging device, and an electronic device, and particularly to a signal processing device, an imaging device, and an electronic device that can further improve characteristics.

Background Art

[0002] Conventionally, in a current mirror circuit used in a comparator included in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, countermeasures against RTS (Random Telegraph Signal) noise have been demanded.

[0003] For example, Patent Document 1 discloses a signal processing device that short-circuits the gate of an amplification transistor to a potential that reduces the voltage between the gate and source of the amplification transistor when the amplification transistor is in a non-operating state in order to suppress the generation of RTS noise.

Prior Art Documents

Patent Documents

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, one method to counter RTS noise is to increase the size of the transistors that make up the differential pair connected to the current mirror circuit. However, as the size of the transistors increases, the gate-source capacitance also increases, which increases the adverse effect of kickback during the inversion of the output signal output from the comparator on the reference signal, resulting in a deterioration of streaking performance. In other words, it has been difficult to suppress both the generation of RTS noise and the deterioration of streaking performance, so there is a need to improve the characteristics compared to conventional methods by achieving both.

[0006] This disclosure is made in light of these circumstances and aims to enable further improvement of the characteristics. [Means for solving the problem]

[0007] A signal processing device according to one aspect of the present disclosure includes a comparator in which a differential pair is formed by a first group of transistors to which a first input signal is input to the gate terminal via a first capacitor, and a second group of transistors to which a second input signal, whose magnitude relationship with the first input signal is compared, is input to the gate terminal via a second capacitor, wherein the number of transistors to which the first input signal is input to the gate terminal of the first group of transistors is switchable, and the number of transistors to which the second input signal is input to the gate terminal of the second group of transistors is switchable.

[0008] An image sensor according to one aspect of this disclosure includes a comparator in which a differential pair is formed by a first group of transistors to which a first input signal is input to the gate terminal via a first capacitor, and a second group of transistors to which a second input signal, whose magnitude relationship with the first input signal is compared, is input to the gate terminal via a second capacitor, wherein the number of transistors to which the first input signal is input to the gate terminal of the first group of transistors is switchable, and the number of transistors to which the second input signal is input to the gate terminal of the second group of transistors is switchable.

[0009] An electronic device according to one aspect of the present disclosure includes a comparator in which a differential pair is formed by a first group of transistors to which a first input signal is input to the gate terminal via a first capacitor, and a second group of transistors to which a second input signal, whose magnitude relationship with the first input signal is compared, is input to the gate terminal via a second capacitor, and an image sensor is configured such that the number of transistors to which the first input signal is input to the gate terminal of the first group of transistors is switchable, and the number of transistors to which the second input signal is input to the gate terminal of the second group of transistors is switchable.

[0010] In one aspect of this disclosure, the comparator is configured as a differential pair by a first group of transistors to which a first input signal is input to the gate terminal via a first capacitor, and a second group of transistors to which a second input signal, whose magnitude relationship with the first input signal is compared, is input to the gate terminal via a second capacitor. The number of transistors to which the first input signal is input to the gate terminal of the first group of transistors is switchable, and the number of transistors to which the second input signal is input to the gate terminal of the second group of transistors is switchable. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example configuration of one embodiment of an image sensor to which this technology is applied. [Figure 2]This is a circuit diagram showing a first example configuration of a comparator. [Figure 3] This is a circuit diagram showing a modified version of the comparator in Figure 2. [Figure 4] This is a circuit diagram showing a second example configuration of the comparator. [Figure 5] This is a circuit diagram showing a third configuration example of the comparator. [Figure 6] This is a circuit diagram showing a fourth configuration example of the comparator. [Figure 7] This is a circuit diagram showing a fifth configuration example of the comparator. [Figure 8] This is a circuit diagram showing a sixth example configuration of the comparator. [Figure 9] This is a block diagram showing an example of the configuration of an imaging device. [Figure 10] This figure shows an example of use with an image sensor. [Modes for carrying out the invention]

[0012] The following describes in detail a specific embodiment of this technology, with reference to the drawings.

[0013] <Example of image sensor configuration> Figure 1 shows an example configuration of one embodiment of a CMOS image sensor, which is an image sensor to which this technology is applied.

[0014] As shown in Figure 1, the CMOS image sensor 11 is configured to include a pixel array section 21, a vertical drive circuit 22, a column signal processing circuit 23, a reference signal generation circuit 24, a horizontal drive circuit 25, and a timing control circuit 26.

[0015] The pixel array section 21 is composed of multiple pixels 31 arranged in an array and receives light focused by an optical system (not shown). The multiple pixels 31 sequentially output pixel signals corresponding to the amount of light they received, at timings selected by the vertical drive circuit 22, to the column signal processing circuit 23 via vertical signal lines.

[0016] The vertical drive circuit 22 sequentially supplies drive signals (such as transfer, selection, reset, etc.) for driving each pixel 31 to the pixels 31 via horizontal signal lines, for each row of the plurality of pixels 31 arranged in the pixel array section 21.

[0017] The column signal processing circuit 23 performs CDS (Correlated Double Sampling) processing on the pixel signals output from the plurality of pixels 31 arranged in the pixel array section 21 via vertical signal lines, thereby performing AD (Analog to Digital) conversion on the pixel signals in parallel for each column of the pixels 31 and removing reset noise. As shown in the figure, the column signal processing circuit 23 is configured to include a number of AD converters 32 corresponding to the number of columns of the plurality of pixels 31 arranged in the pixel array section 21, and each AD converter 32 has a comparator 41, a counter 42, and a latch 43.

[0018] In the AD converter 32, the RAMP signal supplied from the reference signal generation circuit 24 and the pixel signal supplied from the pixel 31 via the vertical signal line are input to the comparator 41. The comparator 41 compares the magnitude relationship between the RAMP signal and the pixel signal, and outputs an OUT signal indicating the timing when their magnitude relationship is inverted to the counter 42. The counter 42 starts counting from the timing when the RAMP signal starts to change at a predetermined slope, acquires the count value up to the timing when the magnitude relationship between the RAMP signal and the pixel signal is inverted as the result of AD conversion of the pixel signal, and supplies it to the latch 43. The latch 43 holds the AD-converted pixel signal supplied from the counter 42, and sequentially outputs the held pixel signal to the data output signal line at the timing selected by the horizontal drive circuit 25.

[0019] The reference signal generation circuit 24 generates a RAMP signal that is referred to when the pixel signal is AD-converted in the AD converter 32, and supplies it to the comparator 41 of the AD converter 32.

[0020] The horizontal drive circuit 25 sequentially supplies drive signals to the latch 43 of the column signal processing circuit 23 for outputting the AD-converted pixel signals to the data output signal lines for each row of multiple pixels 31 arranged in the pixel array section 21.

[0021] The timing control circuit 26 controls the timing of the operation of each block of the CMOS image sensor 11 by generating and supplying clock signals according to the drive cycle of each block. For example, the timing control circuit 26 can control the slope of the RAMP signal generated in the reference signal generation circuit 24, and the opening and closing of the switches (see Figures 2 to 8) provided in the comparator 41.

[0022] The CMOS image sensor 11 configured in this way can capture an image based on light focused onto the pixel array 21 by an optical system (not shown), and outputs the pixel signals output from multiple pixels 31 provided in the pixel array 21 after performing AD conversion. At this time, the CMOS image sensor 11 can capture an image with less noise by using a comparator 41 configured as described later with reference to Figures 2 to 8.

[0023] <Example of comparator configuration> Refer to Figures 2 to 8 to explain an example of the configuration of the comparator 41.

[0024] Figure 2 is a circuit diagram showing a first configuration example of the comparator 41.

[0025] Figure 2A shows the circuit diagram of comparator 41 at high gain, and Figure 2B shows the circuit diagram of comparator 41 at low gain.

[0026] As shown in Figure 2, the comparator 41 is composed of capacitors 51 and 52, N-type transistors 53 to 56, switches 57 to 62, P-type transistors 63 and 64, and an N-type transistor 65. In the comparator 41, a differential pair is formed by a first transistor group 81 consisting of N-type transistors 53 and 54, to which the RAMP signal is input to the gate terminal via capacitor 51, and a second transistor group 82 consisting of N-type transistors 55 and 56, to which the pixel signal is input to the gate terminal via capacitor 52.

[0027] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41. The other end of capacitor 51 is directly connected to the gate terminal of N-type transistor 53 and is also connected to the gate terminal of N-type transistor 54 via switch 57. The gate terminal of N-type transistor 54 is also connected to ground level (GND) via switch 59.

[0028] N-type transistors 53 and 54 are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of N-type transistors 53 and 54 is connected to the drain power supply VDD via a P-type transistor 63 that forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 53 and switch 57 via an auto-zero switch 61.

[0029] The connection point between the source terminals of N-type transistors 53 and 54 is connected to the source power supply VSS via N-type transistor 65, which supplies a bias voltage BIAS1 to its gate terminal.

[0030] One end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from pixel 31 to comparator 41. The other end of capacitor 52 is directly connected to the gate terminal of N-type transistor 55 and also connected to the gate terminal of N-type transistor 56 via switch 58. The gate terminal of N-type transistor 56 is also connected to ground level via switch 60.

[0031] N-type transistors 55 and 56 are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of N-type transistors 55 and 56 is connected to the drain power supply VDD via a P-type transistor 64 that forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 55 and switch 58 via an auto-zero switch 62.

[0032] The connection point between the source terminals of N-type transistors 55 and 56 is connected to the source power supply VSS via N-type transistor 65, which supplies a bias voltage BIAS1 to its gate terminal.

[0033] Furthermore, parasitic capacitance occurs between the gate terminal and drain terminal of the N-type transistor 53, as shown by the dashed line, and also between the gate terminal and drain terminal of the N-type transistor 55, as shown by the dashed line.

[0034] The comparator 41 configured in this way compares the magnitude relationship between the RAMP signal input to the gate terminal of the first transistor group 81 and the pixel signal input to the gate terminal of the second transistor group 82. The comparator 41 then outputs an OUT signal, indicating the timing when the magnitude relationship between these signals is reversed, to the counter 42 (Figure 1) from the connection point between the N-type transistor 55 and the N-type transistor 56 and the P-type transistor 64.

[0035] In the CMOS image sensor 11, when the amount of light illuminating the pixel 31 is small and the pixel signal is converted to AD with high gain, a RAMP signal with a small slope, as shown in Figure 2A, is generated in the reference signal generation circuit 24 and input to the comparator 41. On the other hand, in the CMOS image sensor 11, when the amount of light illuminating the pixel 31 is large and the pixel signal is converted to AD with low gain, a RAMP signal with a large slope, as shown in Figure 2B, is generated in the reference signal generation circuit 24 and input to the comparator 41.

[0036] When the comparator 41 performs AD conversion of the pixel signal with high gain, that is, when the slope of the RAMP signal is small, the switching of switches 57 and 58 is turned on and switches 59 and 60 are turned off, as shown in Figure 2A. As a result, the comparator 41 has a connection configuration in which both the number of transistors constituting the first transistor group 81 and the number of transistors constituting the second transistor group 82 are increased. In this case, the comparator 41 has a connection configuration in which the RAMP signal is input to the gate terminals of both N-type transistors 53 and 54 via capacitor 51, and the pixel signal is input to the gate terminals of both N-type transistors 55 and 56 via capacitor 52.

[0037] Therefore, when the comparator 41 performs AD conversion of the pixel signal at high gain, it can suppress the generation of RTS noise by switching the connection configuration so that the transistor sizes of the first transistor group 81 and the second transistor group 82 become larger.

[0038] On the other hand, when the comparator 41 performs AD conversion of the pixel signal with low gain, that is, when the slope of the RAMP signal is large, the switching of switches 57 and 58 is turned off and switches 59 and 60 are turned on, as shown in Figure 2B. As a result, the comparator 41 has a connection configuration in which both the number of transistors constituting the first transistor group 81 and the number of transistors constituting the second transistor group 82 are reduced. In this case, the comparator 41 has a connection configuration in which the RAMP signal is input to the gate terminal of only the N-type transistor 53 via capacitor 51, and the pixel signal is input to the gate terminal of only the N-type transistor 55 via capacitor 52.

[0039] Therefore, when the comparator 41 performs AD conversion of the pixel signal at low gain, it can reduce the occurrence of parasitic capacitance as shown by the dashed line and suppress deterioration of streaking performance by switching the connection configuration so that the transistor sizes of the first transistor group 81 and the second transistor group 82 become smaller.

[0040] Thus, the comparator 41 is configured such that the number of transistors to which the RAMP signal is input at the gate terminal of the first transistor group 81 can be switched (two transistors, N-type transistor 53 and N-type transistor 54, or one N-type transistor 53), and the number of transistors to which the RAMP signal is input at the gate terminal of the second transistor group 82 can be switched (two transistors, N-type transistor 55 and N-type transistor 56, or one N-type transistor 55).

[0041] Furthermore, the comparator 41 can control the opening and closing of switches 57 to 60 as described above, according to the gain (i.e., the slope of the RAMP signal) when performing AD conversion of the pixel signal. This allows the comparator 41 to suppress the generation of RTS noise by increasing the transistor size at high gain, and to suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain, thereby improving characteristics at both high and low gain.

[0042] In particular, when using a trench-structured Fin FET (Fin Field-Effect Transistor) instead of a planar-structured one as the transistor constituting the comparator 41, there are concerns that RTS noise may worsen and parasitic capacitance may increase. Therefore, it is preferable to apply this technology to improve the characteristics.

[0043] Figure 3 shows a modified example of the comparator 41 shown in Figure 2.

[0044] The comparator 41 in Figure 2 described above was configured such that the gate terminal of the N-type transistor 54 was connected to ground level via switch 59, and the gate terminal of the N-type transistor 56 was connected to ground level via switch 60. In contrast, the comparator 41' shown in Figure 3 is configured such that the gate terminal of the N-type transistor 54 was connected to the source power supply VSS via switch 59 and N-type transistor 65, and the gate terminal of the N-type transistor 56 was connected to the source power supply VSS via switch 60 and N-type transistor 65. As described above, switches 59 and 60 are controlled to be off when performing AD conversion of the pixel signal at high gain and on when performing AD conversion of the pixel signal at low gain.

[0045] Therefore, when the pixel signal is AD converted at low gain, the comparator 41' is controlled to switch 59 and switch 60 on, and the gate electrodes of N-type transistors 54 and 56 are connected to the source power supply VSS via N-type transistor 65.

[0046] The comparator 41' configured in this way, like the comparator 41 in Figure 2, controls the opening and closing of switches 57-60 according to the gain when performing AD conversion of the pixel signal, thereby improving the characteristics at both high and low gain levels. Furthermore, the comparator 41' can reduce the GIDL (Gate-Induced-Drain-Leakage current) compared to the comparator 41 in Figure 2, resulting in even better characteristics.

[0047] Figure 4 is a circuit diagram showing a second configuration example of comparator 41. In comparator 41A shown in Figure 4, components common to comparator 41 in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0048] As shown in Figure 4, comparator 41A is composed of capacitors 51 and 52, P-type transistors 53A to 56A, switches 57 to 62, N-type transistors 63A and 64A, and P-type transistor 65A. In comparator 41A, a differential pair is formed by a first transistor group 81A, which consists of P-type transistors 53A and 54A, to which the RAMP signal is input to the gate terminal via capacitor 51, and a second transistor group 82A, which consists of P-type transistors 55A and 56A, to which the pixel signal is input to the gate terminal via capacitor 52.

[0049] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41. The other end of capacitor 51 is directly connected to the gate terminal of P-type transistor 53A and is also connected to the gate terminal of P-type transistor 54A via switch 57. The gate terminal of P-type transistor 54A is also connected to the drain power supply VDD via switch 59.

[0050] P-type transistors 53A and 54A are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of P-type transistors 53A and 54A is connected to the drain power supply VDD via P-type transistor 65A, which supplies the bias voltage BIAS1 to its gate terminal.

[0051] The connection point between the source terminals of P-type transistors 53A and 54A is connected to the source power supply VSS via N-type transistor 63A, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of P-type transistor 53A and switch 57 via auto-zero switch 61.

[0052] One end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from the pixel 31 to the comparator 41. The other end of capacitor 52 is directly connected to the gate terminal of P-type transistor 55A and is also connected to the gate terminal of P-type transistor 56A via switch 58. The gate terminal of P-type transistor 56A is also connected to the drain power supply VDD via switch 60.

[0053] P-type transistors 55A and 56A are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of P-type transistors 55A and 56A is connected to the drain power supply VDD via P-type transistor 65A, which supplies the bias voltage BIAS1 to its gate terminal.

[0054] The connection point between the source terminals of P-type transistors 55A and 56A is connected to the source power supply VSS via N-type transistor 64A, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of P-type transistor 55A and switch 58 via auto-zero switch 62.

[0055] Furthermore, parasitic capacitance occurs between the gate and source terminals of the P-type transistor 53A, as shown by the dashed line, and also between the gate and source terminals of the P-type transistor 55A, as shown by the dashed line.

[0056] The comparator 41A, configured in this way, compares the relative magnitudes of the RAMP signal input to the gate terminal of the first transistor group 81A and the pixel signal input to the gate terminal of the second transistor group 82A. The comparator 41A then outputs an OUT signal, indicating the timing when these relative magnitudes are reversed, to the counter 42 (Figure 1) from the connection point between the P-type transistor 55A and the P-type transistor 56A and the N-type transistor 64A.

[0057] Thus, comparator 41A has a different configuration from comparator 41 in Figure 2, in that the differential pair is formed by P-type transistors 53A to 56A.

[0058] When the comparator 41A performs AD conversion of the pixel signal at high gain, it controls the switching of switches 57 and 58 to turn on and switches 59 and 60 to turn off, as shown in Figure 4. On the other hand, when the comparator 41A performs AD conversion of the pixel signal at low gain, it controls the switching of switches 57 and 58 to turn off and switches 59 and 60 to turn on.

[0059] As a result, comparator 41A, like comparator 41 in Figure 2, can suppress the generation of RTS noise by increasing the transistor size at high gain, and suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain. Therefore, comparator 41A can improve characteristics at both high and low gain. Furthermore, comparator 41A can reduce GIDL more than comparator 41 in Figure 2, and can obtain better characteristics.

[0060] Figure 5 is a circuit diagram showing a third configuration example of comparator 41. In comparator 41B shown in Figure 5, components common to comparator 41 in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0061] As shown in Figure 5, comparator 41B is composed of capacitors 51 and 52, P-type transistors 53B to 56B, switches 57 to 62, N-type transistors 63B and 64B, P-type transistor 65B, and capacitor 66. Comparator 41B has a differential pair formed by a first transistor group 81B, which consists of P-type transistors 53B and 54B, to which the RAMP signal is input to the gate terminal via capacitor 51 and the pixel signal is input to the gate terminal via capacitor 52, and a second transistor group 82B, which consists of P-type transistors 55B and 56B, whose gate terminals are connected to ground level via capacitor 66.

[0062] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41, and one end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from the pixel 31 to the comparator 41. The other ends of both capacitors 51 and 52 are directly connected to the gate terminal of the P-type transistor 53B and also connected to the gate terminal of the P-type transistor 54B via a switch 57. The gate terminal of the P-type transistor 54B is also connected to the drain power supply VDD via a switch 59.

[0063] P-type transistors 53B and 54B are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of P-type transistors 53B and 54B is connected to the drain power supply VDD via P-type transistor 65B, which supplies the bias voltage BIAS1 to its gate terminal.

[0064] The connection point between the source terminals of P-type transistors 53B and 54B is connected to the source power supply VSS via N-type transistor 63B, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of P-type transistor 53B and switch 57 via auto-zero switch 61.

[0065] One end of capacitor 66 is connected to ground level. The other end of capacitor 66 is directly connected to the gate terminal of P-type transistor 55B and is also connected to the gate terminal of P-type transistor 56B via switch 58. The gate terminal of P-type transistor 56B is also connected to the drain power supply VDD via switch 60.

[0066] P-type transistors 55B and 56B are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of P-type transistors 55B and 56B is connected to the drain power supply VDD via P-type transistor 65B, which supplies the bias voltage BIAS1 to its gate terminal.

[0067] The connection point between the source terminals of P-type transistors 55B and 56B is connected to the source power supply VSS via N-type transistor 64B, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of P-type transistor 55B and switch 58 via auto-zero switch 62.

[0068] Furthermore, parasitic capacitance occurs between the gate and source terminals of the P-type transistor 53B, as shown by the dashed line, and also between the gate and source terminals of the P-type transistor 55B, as shown by the dashed line.

[0069] The comparator 41B, configured in this way, compares the difference between the RAMP signal input to the gate terminal of the first transistor group 81B and the pixel signal input to the gate terminal of the first transistor group 81B, with the ground level connected to the gate terminal of the second transistor group 82B. The comparator 41 then outputs an OUT signal, indicating the timing when this magnitude relationship is reversed, to the counter 42 (Figure 1) from the connection point between the P-type transistor 55B and the P-type transistor 56B and the N-type transistor 64B.

[0070] When the comparator 41B performs AD conversion of the pixel signal at high gain, it controls the switching of switches 57 and 58 to turn on and switches 59 and 60 to turn off, as shown in Figure 5. On the other hand, when the comparator 41B performs AD conversion of the pixel signal at low gain, it controls the switching of switches 57 and 58 to turn off and switches 59 and 60 to turn on.

[0071] As a result, comparator 41B, like comparator 41 in Figure 2, can suppress the generation of RTS noise by increasing the transistor size at high gain, and suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain. Therefore, comparator 41B can improve its characteristics at both high and low gain.

[0072] Figure 6 is a circuit diagram showing a fourth configuration example of comparator 41. In comparator 41C shown in Figure 6, components common to comparator 41 in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0073] As shown in Figure 6, the comparator 41C is composed of capacitors 51 and 52, P-type transistors 53C and 54C, switches 57, 59, and 61, an N-type transistor 63C, and an N-type transistor 65. In the comparator 41C, the RAMP signal is input to the gate terminal via capacitor 51, and the pixel signal is input to the gate terminal via capacitor 52. A differential pair is formed by a transistor group 83 composed of P-type transistors 53C and 54C. In other words, in the comparator 41C, the same functions as the first transistor group 81 and the second transistor group 82 are performed by a single transistor group 83.

[0074] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41, and one end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from the pixel 31 to the comparator 41. The other ends of both capacitors 51 and 52 are directly connected to the gate terminal of the P-type transistor 53C and also connected to the gate terminal of the P-type transistor 54C via switch 57. The gate terminal of the P-type transistor 54C is connected to the drain power supply VDD via switch 59 and the N-type transistor 63C.

[0075] P-type transistors 53C and 54C are connected in parallel between the drain power supply VDD and the source power supply VSS. The connection point between the drain terminals of P-type transistors 53C and 54C is connected to the drain power supply VDD via an N-type transistor 63C, which supplies a bias voltage BIAS2 to its gate terminal.

[0076] The connection point between the source terminals of P-type transistors 53C and 54C is connected to the source power supply VSS via an N-type transistor 65, which supplies a bias voltage BIAS1 to the gate terminal. This connection point is also connected to the connection point between the gate terminal of P-type transistor 53C and switch 57 via an auto-zero switch 61.

[0077] Furthermore, parasitic capacitance occurs between the gate and source terminals of the P-type transistor 53C, as shown by the dashed line in the diagram.

[0078] The comparator 41C, configured in this way, compares the relative magnitudes of the RAMP signal input to the gate terminal of transistor group 83 and the pixel signal input to the gate terminal of transistor group 83. The comparator 41B then outputs an OUT signal, indicating the timing when these relative magnitudes are reversed, to the counter 42 (Figure 1) from the connection point between P-type transistor 53C and P-type transistor 54C and N-type transistor 65.

[0079] When the comparator 41C performs AD conversion of the pixel signal at high gain, it controls the switching of switch 57 to ON and switch 59 to OFF, as shown in Figure 6. On the other hand, when the comparator 41C performs AD conversion of the pixel signal at low gain, it controls the switching of switch 57 to OFF and switch 59 to ON.

[0080] As a result, comparator 41C, like comparator 41 in Figure 2, can suppress the generation of RTS noise by increasing the transistor size at high gain, and suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain. Therefore, comparator 41C can improve characteristics at both high and low gain.

[0081] Figure 7 is a circuit diagram showing a fifth configuration example of comparator 41. In comparator 41D shown in Figure 7, components common to comparator 41 in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0082] As shown in Figure 7, the comparator 41D is composed of capacitors 51 and 52, N-type transistors 53 to 56, switches 57 to 62, P-type transistors 63 and 64, and an N-type transistor 65. In the comparator 41, a differential pair is formed by a first transistor group 81D, which consists of N-type transistors 53 and 54, to which the RAMP signal is input to the gate terminal via capacitor 51, and a second transistor group 82D, which consists of N-type transistors 55 and 56, to which the pixel signal is input to the gate terminal via capacitor 52.

[0083] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41. The other end of capacitor 51 is directly connected to the gate terminal of N-type transistor 53 and also connected to the gate terminal of N-type transistor 54 via switch 57. The gate terminal of N-type transistor 54 is connected to the drain power supply VDD via switch 59.

[0084] N-type transistors 53 and 54 are connected in series between the drain power supply VDD and the source power supply VSS. The drain terminal of N-type transistor 53 is connected to the source terminal of N-type transistor 54, and the drain terminal of N-type transistor 54 is connected to the drain power supply VDD via P-type transistor 63, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 53 and switch 57 via auto-zero switch 61.

[0085] The source terminal of the N-type transistor 53 is connected to the source power supply VSS via the N-type transistor 65, to which the bias voltage BIAS1 is supplied to the gate terminal.

[0086] One end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from the pixel 31 to the comparator 41. The other end of capacitor 52 is directly connected to the gate terminal of N-type transistor 55 and also connected to the gate terminal of N-type transistor 56 via switch 58. The gate terminal of N-type transistor 56 is also connected to the drain power supply VDD via switch 60.

[0087] N-type transistors 55 and 56 are connected in series between the drain power supply VDD and the source power supply VSS. The drain terminal of N-type transistor 55 is connected to the source terminal of N-type transistor 56, and the drain terminal of N-type transistor 56 is connected to the drain power supply VDD via a P-type transistor 64 that forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 55 and switch 58 via an auto-zero switch 62.

[0088] The source terminal of the N-type transistor 55 is connected to the source power supply VSS via the N-type transistor 65, which supplies the bias voltage BIAS1 to the gate terminal.

[0089] Furthermore, parasitic capacitance occurs between the gate terminal and drain terminal of the N-type transistor 53, as shown by the dashed line, and also between the gate terminal and drain terminal of the N-type transistor 55, as shown by the dashed line.

[0090] The comparator 41D, configured in this way, compares the relative magnitudes of the RAMP signal input to the gate terminal of the first transistor group 81D and the pixel signal input to the gate terminal of the second transistor group 82D. The comparator 41D then outputs an OUT signal, indicating the timing when these relative magnitudes are reversed, from the connection point between the N-type transistor 56 and the P-type transistor 64 to the counter 42 (Figure 1).

[0091] Thus, comparator 41D differs from comparator 41 in Figure 2 in that the N-type transistors 53 and 54 constituting the first transistor group 81D are connected in series, and the N-type transistors 55 and 56 constituting the second transistor group 82D are connected in series.

[0092] When the comparator 41D performs AD conversion of the pixel signal at high gain, it controls the switching of switches 57 and 58 to turn on and switches 59 and 60 to turn off, as shown in Figure 7. On the other hand, when the comparator 41D performs AD conversion of the pixel signal at low gain, it controls the switching of switches 57 and 58 to turn off and switches 59 and 60 to turn on.

[0093] As a result, comparator 41D, like comparator 41 in Figure 2, can suppress the generation of RTS noise by increasing the transistor size at high gain, and suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain. Therefore, comparator 41D can improve characteristics at both high and low gain.

[0094] Figure 8 is a circuit diagram showing a sixth configuration example of comparator 41. In comparator 41E shown in Figure 8, components common to comparator 41 in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0095] As shown in Figure 8, the comparator 41E is composed of capacitors 51 and 52, N-type transistors 53 to 56, switches 57 to 62, P-type transistors 63 and 64, N-type transistor 65, N-type transistors 67 and 68, and switches 69 to 72. In the comparator 41, a differential pair is formed by a first transistor group 81E consisting of N-type transistors 53, 54, and 67, to which the RAMP signal is input to the gate terminal via capacitor 51, and a second transistor group 82E consisting of N-type transistors 55, 56, and 68, to which the pixel signal is input to the gate terminal via capacitor 52.

[0096] One end of capacitor 51 is connected to a signal line that inputs the RAMP signal supplied from the reference signal generation circuit 24 to the comparator 41. The other end of capacitor 51 is directly connected to the gate terminal of N-type transistor 53, and is also connected to the gate terminal of N-type transistor 54 via switch 57, and to the gate terminal of N-type transistor 67 via switch 69. In addition, the gate terminal of N-type transistor 54 is connected to ground level (GND) via switch 59, and the gate terminal of N-type transistor 67 is connected to the drain power supply VDD via switch 71.

[0097] N-type transistors 53 and 67 are connected in parallel to N-type transistor 54 between the drain power supply VDD and the source power supply VSS, while N-type transistors 53 and 67 are connected in series between the drain power supply VDD and the source power supply VSS. The drain terminal of N-type transistor 53 is connected to the source terminal of N-type transistor 67, and the connection point between the drain terminals of N-type transistor 67 and N-type transistor 54 is connected to the drain power supply VDD via P-type transistor 63, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 53 and switches 57 and 69 via an auto-zero switch 61.

[0098] The connection point between the source terminals of N-type transistors 53 and 54 is connected to the source power supply VSS via N-type transistor 65, which supplies a bias voltage BIAS1 to its gate terminal.

[0099] One end of capacitor 52 is connected to a vertical signal line that inputs the pixel signal supplied from the pixel 31 to the comparator 41. The other end of capacitor 52 is directly connected to the gate terminal of N-type transistor 55, and is also connected to the gate terminal of N-type transistor 56 via switch 58, and to the gate terminal of N-type transistor 68 via switch 70. In addition, the gate terminal of N-type transistor 56 is connected to ground level via switch 60, and the gate terminal of N-type transistor 68 is connected to the drain power supply VDD via switch 72.

[0100] N-type transistors 55 and 68 are connected in parallel to N-type transistor 56 between the drain power supply VDD and the source power supply VSS, while N-type transistors 55 and 68 are connected in series between the drain power supply VDD and the source power supply VSS. The drain terminal of N-type transistor 55 is connected to the source terminal of N-type transistor 68, and the connection point between the drain terminals of N-type transistors 68 and 56 is connected to the drain power supply VDD via P-type transistor 64, which forms a current mirror circuit. This connection point is also connected to the connection point between the gate terminal of N-type transistor 55 and switches 58 and 70 via an auto-zero switch 62.

[0101] The connection point between the source terminals of N-type transistors 55 and 56 is connected to the source power supply VSS via N-type transistor 65, which supplies a bias voltage BIAS1 to its gate terminal.

[0102] Furthermore, parasitic capacitance occurs between the gate terminal and drain terminal of the N-type transistor 53, as shown by the dashed line, and also between the gate terminal and drain terminal of the N-type transistor 55, as shown by the dashed line.

[0103] The comparator 41E, configured in this way, compares the relative magnitudes of the RAMP signal input to the gate terminal of the first transistor group 81E and the pixel signal input to the gate terminal of the second transistor group 82E. The comparator 41E then outputs an OUT signal, indicating the timing when these relative magnitudes are reversed, from the N-type transistor 56 and the connection point between the N-type transistor 68 and the P-type transistor 64 to the counter 42 (Figure 1).

[0104] When comparator 41E performs AD conversion of the pixel signal at high gain, it controls the switching of switches 57, 58, 69, and 70 to turn on, and switches 59, 60, 71, and 72 to turn off, as shown in Figure 8. On the other hand, when comparator 41B performs AD conversion of the pixel signal at low gain, it controls the switching of switches 57, 58, 69, and 70 to turn off, and switches 59, 60, 71, and 72 to turn on.

[0105] As a result, comparator 41E, like comparator 41 in Figure 2, can suppress the generation of RTS noise by increasing the transistor size at high gain and suppress the deterioration of streaking performance by reducing the generation of parasitic capacitance at low gain. Therefore, comparator 41E can improve characteristics at both high and low gain. Furthermore, comparator 41E can be configured with the same circuit area aspect ratio as conventional comparators.

[0106] In each of the embodiments described above, the comparator 41 compares the RAMP signal and the pixel signal, but it may also compare other signals. For example, the comparator 41 can be configured such that one vertical signal line is connected to capacitor 51 and the other vertical signal line is connected to capacitor 52, so as to compare the pixel signals output from two pixels 31 via vertical signal lines. Such a comparator 41 can be applied, for example, to a sensing sensor for detection.

[0107] Furthermore, this technology can be applied to CMOS image sensors 11 with various configurations, such as back-illuminated types where light is irradiated to the back side of the semiconductor substrate, and stacked types where a sensor substrate on which a photodiode is provided and a signal processing substrate on which peripheral circuits are provided are stacked.

[0108] <Example of electronic device configuration> The CMOS image sensor 11 described above can be applied to various electronic devices, such as imaging systems for digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0109] Figure 9 is a block diagram showing an example configuration of an imaging device mounted on an electronic device.

[0110] As shown in Figure 9, the imaging device 101 is configured to include an optical system 102, an image sensor 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing both still and moving images.

[0111] The optical system 102 is composed of one or more lenses and guides the image light (incident light) from the subject to the image sensor 103, forming an image on the light-receiving surface (sensor part) of the image sensor 103.

[0112] The image sensor 103 is the CMOS image sensor 11 described above. Electrons are accumulated in the image sensor 103 for a certain period of time, depending on the image formed on the light-receiving surface via the optical system 102. Then, a signal corresponding to the electrons accumulated in the image sensor 103 is supplied to the signal processing circuit 104.

[0113] The signal processing circuit 104 performs various signal processing operations on the pixel signals output from the image sensor 103. The image (image data) obtained by the signal processing circuit 104 is supplied to the monitor 105 for display or supplied to the memory 106 for storage (recording).

[0114] With the imaging device 101 configured in this way, by applying the CMOS image sensor 11 described above, it is possible to capture, for example, high-quality images with less noise.

[0115] <Examples of image sensor usage> Figure 10 shows an example of using the image sensor (imaging element) described above.

[0116] The image sensor described above can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0117] • Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. Devices used for traffic purposes, such as on-board sensors that photograph the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognizing the driver's condition; surveillance cameras that monitor moving vehicles and roads; and distance measuring sensors that measure the distance between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and perform device operations according to those gestures. • Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. • Security devices such as surveillance cameras for crime prevention and cameras for person recognition. • Devices used for cosmetic purposes, such as skin measuring devices for photographing skin and microscopes for photographing the scalp. • Action cameras, wearable cameras, and other devices used for sports purposes. • Cameras and other devices used for agricultural purposes to monitor the condition of fields and crops.

[0118] Furthermore, the technologies described in this specification can be implemented independently, as long as they do not create a contradiction. Of course, any multiple technologies can also be implemented in combination. For example, some or all of the technologies described in one embodiment can be combined with some or all of the technologies described in another embodiment. In addition, some or all of the above-mentioned technologies can be implemented in combination with other technologies not mentioned above.

[0119] <Examples of configuration combinations> Furthermore, this technology can also be configured as follows. (1) A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and The comparator comprises a differential pair formed by the following: In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. Signal processing device. (2) The second input signal is the pixel signal output from the pixel via the vertical signal line, The first input signal is a RAMP signal that is referenced when performing an A / D (Analog to Digital) conversion of the pixel signal, The number of transistors in the first transistor group and the second transistor group is switched according to the gain when performing AD conversion of the pixel signal. The signal processing device described in (1) above. (3) When performing AD conversion of the aforementioned pixel signal with high gain, the first transistor group and the second transistor group are switched to increase the number of transistors in both groups. When performing AD conversion of the aforementioned pixel signal with low gain, the number of transistors in both the first transistor group and the second transistor group is switched to be reduced. The signal processing device described in (2) above. (4) The first group of transistors comprises a first transistor whose gate terminal is directly connected to one end of the first capacitor, and a second transistor whose gate terminal is connected to one end of the first capacitor via a first switch. The second group of transistors comprises a third transistor whose gate terminal is directly connected to one end of the second capacitor, and a fourth transistor whose gate terminal is connected to one end of the second capacitor via a second switch. The number of transistors in the first transistor group and the second transistor group is switched by controlling the opening and closing of the first switch and the second switch according to the gain when performing AD conversion of the pixel signal. The signal processing device described in (3) above. (5) The first transistor and the second transistor are connected in parallel between the drain power supply and the source power supply, and the third transistor and the fourth transistor are connected in parallel between the drain power supply and the source power supply. The signal processing device described in (4) above. (6) The first transistor and the second transistor are connected in series between the drain power supply and the source power supply, and the third transistor and the fourth transistor are connected in series between the drain power supply and the source power supply. The signal processing device described in (4) above. (7) The gate terminal of the first group of transistors is input to the first input signal via the first capacitor, and the second input signal is input via the second capacitor. The gate terminal of the second group of transistors is grounded via the third capacitor instead of receiving the second input signal. The signal processing device described in (3) above. (8) The functions of the first group of transistors and the second group of transistors are combined into a single group of transistors, and the first input signal is input to the gate terminal of that group of transistors via the first capacitor, and the second input signal is input via the second capacitor. The signal processing device described in (3) above. (9) The first group of transistors comprises a first transistor whose gate terminal is directly connected to one end of the first capacitor, a second transistor whose gate terminal is connected to one end of the first capacitor via a first switch, and a third transistor whose gate terminal is connected to one end of the first capacitor via a second switch, wherein the first transistor and the second transistor are connected in series with respect to the drain power supply and the source power supply, and the first transistor, the second transistor and the third transistor are connected in parallel with respect to the drain power supply and the source power supply. The second group of transistors comprises a fourth transistor whose gate terminal is directly connected to one end of the second capacitor, a fifth transistor whose gate terminal is connected to one end of the second capacitor via a third switch, and a sixth transistor whose gate terminal is connected to one end of the second capacitor via a fourth switch, wherein the fourth transistor and the fifth transistor are connected in series with respect to the drain power supply and the source power supply, and the fourth transistor, the fifth transistor and the sixth transistor are connected in parallel with respect to the drain power supply and the source power supply. The opening and closing of the first to fourth switches is controlled according to the gain obtained when performing AD conversion on the aforementioned pixel signal. The signal processing device described in (3) above. (10) Each of the first and second transistor groups is composed of multiple N-type transistors. A signal processing device as described in any of (1) through (9) above. (11) Each of the first and second transistor groups is composed of multiple P-type transistors. A signal processing device as described in any of (1) through (9) above. (12) The comparator compares the pixel signals output from two pixels via vertical signal lines. A signal processing device as described in any of (1) through (11) above. (13) A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and The comparator comprises a differential pair formed by the following: In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. Image sensor. (14) A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and It has a comparator in which the differential pair is formed by In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. An electronic device equipped with an image sensor.

[0120] It should be noted that this embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist. [Explanation of symbols]

[0121] 11 CMOS image sensor, 21 Pixel array section, 22 Vertical drive circuit, 23 Column signal processing circuit, 24 Reference signal generation circuit, 25 Horizontal drive circuit, 26 Timing control circuit, 31 Pixel, 32 AD converter, 41~41E Comparator, 42 Counter, 43 Latch, 51 and 52 Capacitors, 53~56 N-type transistors, 53A~56A P-type transistors, 53B~56B P-type transistors, 53C and 54C P-type transistors, 57~62 Switches, 63 and 64 P-type transistors, 63A and 64A N-type transistors, 63B and 64B N-type transistors, 63C N-type transistor, 65 N-type transistor, 65A and 65B P-type transistors, 66 Capacitors, 67 and 68 N-type transistors, 69~72 Switches 81-81E First transistor group, 82-82E Second transistor group, 83 Transistor group

Claims

1. A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and The comparator comprises a differential pair formed by the following: In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. Signal processing device.

2. The second input signal is a pixel signal output from a pixel via a vertical signal line. The first input signal is a RAMP signal that is referenced when performing an A / D (Analog to Digital) conversion of the pixel signal, The number of transistors in the first transistor group and the second transistor group is switched according to the gain when performing AD conversion on the pixel signal. The signal processing apparatus according to claim 1.

3. When performing AD conversion of the aforementioned pixel signal with high gain, the first transistor group and the second transistor group are switched to increase the number of transistors in both groups. When performing AD conversion of the aforementioned pixel signal at low gain, the number of transistors in both the first transistor group and the second transistor group is switched to be reduced. The signal processing apparatus according to claim 2.

4. The first group of transistors comprises a first transistor whose gate terminal is directly connected to one end of the first capacitor, and a second transistor whose gate terminal is connected to one end of the first capacitor via a first switch. The second group of transistors comprises a third transistor whose gate terminal is directly connected to one end of the second capacitor, and a fourth transistor whose gate terminal is connected to one end of the second capacitor via a second switch. The number of transistors in the first transistor group and the second transistor group can be switched by controlling the opening and closing of the first switch and the second switch according to the gain when performing AD conversion of the pixel signal. The signal processing apparatus according to claim 3.

5. The first transistor and the second transistor are connected in parallel between the drain power supply and the source power supply, and the third transistor and the fourth transistor are connected in parallel between the drain power supply and the source power supply. The signal processing apparatus according to claim 4.

6. The first transistor and the second transistor are connected in series between the drain power supply and the source power supply, and the third transistor and the fourth transistor are connected in series between the drain power supply and the source power supply. The signal processing apparatus according to claim 4.

7. The gate terminal of the first group of transistors is input to the first input signal via the first capacitor, and the second input signal is input via the second capacitor. The gate terminal of the second group of transistors is grounded via the third capacitor instead of receiving the second input signal. The signal processing apparatus according to claim 3.

8. The functions of the first group of transistors and the second group of transistors are combined into a single group of transistors, and the first input signal is input to the gate terminal of that group of transistors via the first capacitor, and the second input signal is input via the second capacitor. The signal processing apparatus according to claim 3.

9. The first group of transistors comprises a first transistor whose gate terminal is directly connected to one end of the first capacitor, a second transistor whose gate terminal is connected to one end of the first capacitor via a first switch, and a third transistor whose gate terminal is connected to one end of the first capacitor via a second switch, wherein the first transistor and the second transistor are connected in series with respect to the drain power supply and the source power supply, and the first transistor, the second transistor and the third transistor are connected in parallel with respect to the drain power supply and the source power supply. The second group of transistors comprises a fourth transistor whose gate terminal is directly connected to one end of the second capacitor, a fifth transistor whose gate terminal is connected to one end of the second capacitor via a third switch, and a sixth transistor whose gate terminal is connected to one end of the second capacitor via a fourth switch, wherein the fourth transistor and the fifth transistor are connected in series with respect to the drain power supply and the source power supply, and the fourth transistor, the fifth transistor and the sixth transistor are connected in parallel with respect to the drain power supply and the source power supply. The opening and closing of the first to fourth switches is controlled according to the gain obtained when performing AD conversion on the aforementioned pixel signal. The signal processing apparatus according to claim 3.

10. Each of the first and second transistor groups is composed of multiple N-type transistors. The signal processing apparatus according to claim 1.

11. Each of the first and second transistor groups is composed of multiple P-type transistors. The signal processing apparatus according to claim 1.

12. The comparator compares the pixel signals output from two pixels via vertical signal lines. The signal processing apparatus according to claim 1.

13. A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and The comparator comprises a differential pair formed by the following: In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. Image sensor.

14. A first group of transistors, to which a first input signal is input to the gate terminal via a first capacitor, A second group of transistors, to which a second input signal whose magnitude is compared with the first input signal is input to the gate terminal via a second capacitor, and It has a comparator in which the differential pair is formed by In the first group of transistors, the number of transistors to which the first input signal is input at the gate terminal is switchable, and in the second group of transistors, the number of transistors to which the second input signal is input at the gate terminal is switchable. An electronic device equipped with an image sensor.

Images