Design support device, implementation system, design support method, and program

Abstract

When designing a circuit with some redundancy, if the resulting circuit does not meet the target performance, the burden on the designer to redesign it is relatively small. [Solution] The design support device, based on circuit information in which the circuit before redundancy is divided into blocks, and designation information indicating whether or not each block of the circuit before redundancy should be subject to redundancy, and the priority if it is subject to redundancy, redundancies at least some of the blocks that are subject to redundancy, determines the placement of the redundanted circuit, which is the circuit in which the blocks have been redundantized, on the mounting target, determines whether or not the mounted circuit satisfies the specified target performance if the redundanted circuit is mounted on the mounting target according to the determined placement, and if it is determined that the mounted circuit does not satisfy the target performance, changes the blocks to be redundantized based on the designation information, and repeats the redundancy, placement determination, and determination.

Description

Technical Field

[0001] The present disclosure relates to a design support apparatus, an implementation system, a design support method, and a program.

Background Art

[0002] In some cases, a part of a circuit implemented in a semiconductor device such as an FPGA may be multiplexed. For example, the semiconductor device described in Patent Document 1 compares outputs of two of the triple logic circuits with three comparators, takes a majority vote of the comparison results, and performs a failure determination on these triple logic circuits and the three comparators.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When designing a circuit in which a part is multiplexed, if the circuit obtained in the design does not satisfy the target performance, it may be considered to redo the design. In that case, it is preferable that the burden on the designer to redo the design is as small as possible.

[0005] An example of an object of the present disclosure is to provide a design support apparatus, an implementation system, a design support method, and a program capable of solving the above-described problems.

Means for Solving the Problems

[0006] According to a first aspect of this disclosure, the design support device includes: a multiplexing means that multiplexes at least some of the blocks that are to be multiplexed based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks; designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing; placement means that determines the placement of the multiplexed circuit, which is the circuit into which the blocks have been multiplexed, on an implementation target; performance determination means that determines whether or not the implemented circuit satisfies a specified target performance if the multiplexed circuit is implemented on the implementation target according to the determined placement; and, if it is determined that the implemented circuit does not satisfy the target performance, a repeating control means that changes the blocks to be multiplexed based on the designation information and causes the multiplexing by the multiplexing means, the placement determination by the placement means, and the determination by the performance determination means to be performed again.

[0007] According to a second aspect of this disclosure, the implementation system comprises a design support device and an implementation device, the design support device comprising: multiplexing means for multiplexing at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make the block subject to multiplexing and the priority if it is subject to multiplexing, for each block of the pre-multiplexing circuit; placement means for determining the placement of the multiplexed circuit, which is the circuit into which the blocks have been multiplexed, on the implementation target; performance determination means for determining whether or not the implemented circuit satisfies a designated target performance if the multiplexed circuit is implemented on the implementation target according to the determined placement; and, if it is determined that the implemented circuit does not satisfy the target performance, repeat control means for changing the blocks to be multiplexed based on the designation information and causing the multiplexing by the multiplexing means, the placement determination by the placement means, and the determination by the performance determination means to be performed again, the implementation device implements the circuit into which the blocks have been multiplexed on the implementation target according to the design by the design support device.

[0008] According to a third aspect of this disclosure, the design support method includes a computer multiplexing at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing, determining the placement of the multiplexed circuit, which is the circuit into which the blocks have been multiplexed, on the mounting target, determining whether or not the mounted circuit satisfies the designated target performance if the multiplexed circuit is mounted on the mounting target according to the determined placement, and if it is determined that the mounted circuit does not satisfy the target performance, changing the blocks to be multiplexed based on the designation information, and repeating the multiplexing, the placement determination, and the determination.

[0009] According to a fourth aspect of this disclosure, the program causes a computer to perform the following actions based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing: to multiplex at least some of the blocks subject to multiplexing; to determine the placement of the multiplexed circuit, which is the circuit into which the blocks have been multiplexed, on the implementation target; to determine whether or not the implemented circuit satisfies the specified target performance if the multiplexed circuit is implemented on the implementation target according to the determined placement; and if it is determined that the implemented circuit does not satisfy the target performance, to change the blocks to be multiplexed based on the designation information and repeat the multiplexing, the placement determination, and the determination. [Effects of the Invention]

[0010] According to the embodiments of this disclosure, when designing a partially redundant circuit, if the resulting circuit does not satisfy the target performance, the burden on the designer to redesign it can be relatively reduced. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example of the configuration of a design support device according to at least one embodiment. [Figure 2] This figure shows an example of the procedure for designing a circuit after multiplexing by a design support device according to at least one embodiment. [Figure 3] This figure shows a first example of circuit information to be multiplexed according to at least one embodiment. [Figure 4] This figure shows a first example of multiplexed circuit information according to at least one embodiment. [Figure 5] This figure shows a first example of assigning a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 6] This figure shows a second example of circuit information to be multiplexed according to at least one embodiment. [Figure 7] This figure shows a second example of multiplexed circuit information according to at least one embodiment. [Figure 8] This figure shows a second example of assigning a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 9] This figure shows a third example of circuit information to be multiplexed according to at least one embodiment. [Figure 10] This figure shows a third example of multiplexed circuit information according to at least one embodiment. [Figure 11] This figure shows a third example of assigning a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 12] This figure shows a fourth example of circuit information to be multiplexed according to at least one embodiment. [Figure 13]A diagram showing a fourth example of multiplexed circuit information according to at least one embodiment. [Figure 14] A diagram showing a fourth example of the assignment of a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 15] A diagram showing a first example of a specification for multiplexing according to at least one embodiment. [Figure 16] A diagram showing a fifth example of multiplexed circuit information according to at least one embodiment. [Figure 17] A diagram showing a fifth example of the assignment of a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 18] A diagram showing a second example of a specification for multiplexing according to at least one embodiment. [Figure 19] A diagram showing a sixth example of multiplexed circuit information according to at least one embodiment. [Figure 20] A diagram showing a sixth example of the assignment of a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 21] A diagram showing a seventh example of multiplexed circuit information according to at least one embodiment. [Figure 22] A diagram showing a seventh example of the assignment of a multiplexed circuit to an FPGA according to at least one embodiment. [Figure 23] A diagram showing an example of the configuration of an implementation system according to at least one embodiment. [Figure 24] A diagram showing an example of the configuration of a design support device according to at least one embodiment. [Figure 25] A diagram showing an example of the configuration of an implementation system according to at least one embodiment. [Figure 26] A diagram showing an example of the processing procedure in a design support method according to at least one embodiment. [Figure 27] A diagram showing an example of the configuration of a computer according to at least one embodiment.

Embodiments for Carrying Out the Invention

[0012] The embodiments relating to this disclosure will be described below. <First Embodiment> Figure 1 shows an example of the configuration of a design support device according to at least one embodiment. In the configuration shown in Figure 1, the design support device 100 includes a communication unit 110, a display unit 120, an operation input unit 130, a storage unit 180, and a processing unit 190. The processing unit 190 includes a condition acquisition unit 191, a multiplexing unit 192, an arrangement unit 193, a performance determination unit 194, and a repeat control unit 195.

[0013] The design support device 100 assists in the design of circuits to be implemented on a target device such as an FPGA (Field Programmable Gate Array). In particular, the design support device 100 determines whether the target performance is satisfied when a portion of the circuit to be designed is multiplexed and the multiplexed portion of the circuit is implemented on the target device. The target performance may be predetermined by the designer.

[0014] If the design support device 100 determines that a partially redundant circuit does not satisfy the target performance, it modifies the redundant portion and determines whether the target performance is satisfied when the modified circuit with the redundant portion is implemented in the target device. The design support device 100 changing the redundant parts can be understood as redesigning a partially redundant circuit.

[0015] The design support device 100 can relatively reduce the burden on the designer of redesigning by redesigning a portion of the redundant circuit. The design support device 100 may be configured using a computer such as a workstation (WS) or a personal computer (PC).

[0016] The following explanation uses the case where the circuit is implemented on an FPGA as an example. However, the implementation target of the circuit designed by the design support device 100 is not limited to FPGAs. For example, the design support device 100 may design a program to be implemented on an ASIC (Application Specific Integrated Circuit). The target of the circuit implementation can be considered as a semiconductor device.

[0017] Furthermore, in the following, a part of a circuit will also be referred to as a block. The design support device 100 acquires circuit information indicating a block of a circuit that is to be partially duplicated (a circuit that has not been duplicated), and then duplicates the block. Duplicating a part of the circuit to be designed is also referred to as "duplicating a block."

[0018] Furthermore, the following explanation will describe an example in which the design support device 100 multiplexes the blocks to be multiplexed into an odd number of blocks and provides a majority voting circuit that takes a majority vote of the outputs of the multiplexed odd number of blocks. Multiplexing is also called N-multiplication, where N represents an odd number of 3 or more (3, 5, 7, ...).

[0019] The circuit that is to be partially redundantd is also called the pre-redundancy circuit. The pre-redundancy circuit may be a circuit designed by the designer (a circuit designed by a human). A circuit that has been partially duplicated is also referred to as the duplicated circuit. The design support device 100 receiving circuit information representing the circuit before duplicatement and generating circuit information representing the duplicated circuit can be considered as the design of the duplicated circuit by the design support device 100.

[0020] The communication unit 110 communicates with other devices. For example, the communication unit 110 may receive circuit information from other devices that shows the circuit before multiplexing. Alternatively, the communication unit 110 may transmit ROM code to other devices for implementing the circuit design result from the design support device 100 onto the FPGA.

[0021] The display unit 120 has a display screen such as a liquid crystal panel or an LED (Light Emitting Diode) panel, and displays various images. For example, the display unit 120 may display an input screen for receiving user operations to specify the conditions for the design support device 100 to duplicate blocks (conditions for duplicate a part of the circuit). Also, if the design support device 100 determines that it cannot design a circuit that satisfies the target performance, the display unit 120 may display a message indicating that it cannot design a circuit that satisfies the target performance.

[0022] The operation input unit 130 is configured to include, for example, input devices such as a keyboard and a mouse, and accepts user operations. For example, while the display unit 120 is displaying an input screen for accepting user operations to specify conditions for when the design support device 100 multiplexes blocks, the operation input unit 130 may be configured to accept user operations to specify conditions for when the design support device 100 multiplexes blocks.

[0023] The memory unit 180 stores various types of data. For example, the memory unit 180 may store the conditions under which the design support device 100 duplicates blocks. The memory unit 180 is configured using the memory devices provided by the design support device 100.

[0024] The processing unit 190 controls various parts of the design support device 100 to perform various processes. The functions of the processing unit 190 are performed, for example, by the CPU (Central Processing Unit) of the design support device 100 reading a program from the storage unit 180 and executing it.

[0025] The condition acquisition unit 191 acquires the conditions for the design support device 100 to duplicate a portion of the circuit before redundancy. The conditions for the design support device 100 to duplicate a portion of the circuit before redundancy are also referred to as the conditions for block redundancy. The conditions for block redundancy include, for each block of the circuit before redundancy, whether or not to include that block in the redundancy process, and, if so, the priority of that block. The conditions for multiplexing blocks may be specified by the user. For example, the operation input unit 130 may be configured to accept user input to specify the conditions for multiplexing blocks.

[0026] The multiplexing unit 192 multiplexes at least some of the blocks that are to be multiplexed, based on the circuit information in which the circuit before multiplexing is divided into blocks and the specified information. The specified information shall indicate, for each block of the circuit before multiplexing, whether or not that block should be subject to multiplexing, and if so, the priority of that block. The multiplexing unit 192 is an example of a multiplexing means. The multiplexing unit 192 may also be configured to multiplex the blocks to be multiplexed into an odd number of blocks. This makes it easier to take a majority vote of the outputs of the multiplexed blocks.

[0027] The placement unit 193 determines the placement of the multiplexed circuits on the FPGA. The arrangement section 193 is an example of an arrangement means. When the multiplexing unit 192 multiplexes the blocks to be multiplexed into an odd number of blocks, the placement means may divide the FPGA area where the blocks to be multiplexed are placed into an area of ​​one greater number than the number of blocks to be multiplexed. The multiplexing unit 192 may then assign the odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas.

[0028] Alternatively, the placement unit 193 may determine the placement of at least some of the multiplexed blocks into the FPGA area using simulated annealing with an evaluation function that includes a subexpression indicating reliability evaluation based on the distance between the blocks to be placed. For example, the placement unit 193 may perform simulated annealing using an evaluation function such that the reliability evaluation improves as the distance between the blocks to be placed increases. This is expected to increase the distance between blocks, thus preventing soft errors from occurring when multiple blocks are simultaneously affected by cosmic rays or other radiation. In this context, a "soft error" refers to a temporary error.

[0029] The performance determination unit 194 determines whether the implemented circuit satisfies the specified target performance, assuming that the multiplexed circuit is implemented on the target according to the determined arrangement. For example, the performance determination unit 194 may determine conditions such as the clock operating frequency in the FPGA circuit, the area of ​​the FPGA circuit, the power consumption of the FPGA circuit, the number of Fits, and an index related to the arrangement of the FPGA circuit (distance between N redundant circuits). However, the conditions specified as target performance are not limited to specific conditions. The performance determination unit 194 is an example of a performance determination means.

[0030] The repeating control unit 195 controls the repeated execution of multiplexing by the multiplexing unit 192, placement determination by the placement unit 193, and determination by the performance determination unit 194. Specifically, if the performance determination unit 194 determines that the implemented circuit does not satisfy the target performance, the repeating control unit 195 changes the blocks to be multiplexed based on the specified information. Then, the repeating control unit 195 causes the multiplexing by the multiplexing unit 192, placement determination by the placement unit 193, and determination by the performance determination unit 194 to be performed again. The repeating control unit 195 is an example of a repeating control means.

[0031] Figure 2 shows an example of the procedure for the design support device 100 to design the circuit after multiplexing. In the example shown in Figure 2, the processing unit 190 acquires the circuit information before multiplexing (step S101). For example, the design support device 100 may acquire circuit information of a designer-created circuit that is not redundant. Then, the processing unit 190 may acquire terminal information from the circuit information of the designer-created circuit and automatically generate a higher-level circuit for connecting redundant blocks.

[0032] The terminal information here refers to the input and output terminals of the circuit block designed by the designer. For example, the terminal name, bit width, and input / output attribute information of the input / output terminal may be used as terminal information. The higher-level circuit, as referred to here, is the circuit that connects the signals between the multiplexed blocks and the majority voting circuit. For example, in the case of triple redundancy of blocks (i.e., when N=3), the signal input to the higher-level circuit is input to all blocks of the tripled circuit (the tripled blocks). The output signals from each block of the tripled circuit are connected to the majority voting circuit, where a majority vote is calculated, and the result of the majority vote is output from the higher-level circuit.

[0033] Next, the condition acquisition unit 191 sets a mode to determine whether the conditions for block multiplexing are set by the designer or by the design support device 100 (step S102). The mode in which the designer sets the conditions for block multiplexing is also called the designer mode. The mode in which the design support device 100 sets the conditions for block multiplexing is also called the tool mode. For example, the operation input unit may accept user input to specify a mode, and the condition acquisition unit 191 may set the mode according to the user input.

[0034] Next, the condition acquisition unit 191 determines whether the mode is set to designer mode or tool mode (step S103). If it is determined that the system is set to designer mode (step S103: YES), the condition acquisition unit 191 accepts the conditions set by the designer when the blocks are duplicated (step S111). For example, the operation input unit may accept a user operation specifying the conditions when the blocks are duplicated, and the condition acquisition unit 191 may set the conditions when the blocks are duplicated according to the user operation. As described above, the conditions for multiplexing blocks include specifying whether or not to include each block in the circuit before multiplexing in the multiplexing process, and, if so, the priority of that block. Furthermore, in step S111, options / parameters for logic synthesis / place and route may be set. These options / parameters for logic synthesis / place and route may impose constraints on the execution results during logic synthesis and place and route (for example, limiting the number of fan-outs), or they may set which of the target performances should be prioritized (for example, which of operating frequency, power consumption, or area should be prioritized).

[0035] Next, the multiplexing unit 192 automatically performs block multiplexing and generates a majority voting circuit according to the conditions for block multiplexing (step S131).

[0036] Next, the processing unit 190 obtains the verification results of the multiplexed circuit (step S132). For example, the designer may perform circuit verification, or the design support device 100 may obtain the verification results. Alternatively, the processing unit 190 may perform circuit verification automatically or semi-automatically.

[0037] Next, the repeating control unit 195 determines whether or not circuit modification is necessary based on the verification results (step S133). If the control unit 195 repeatedly determines that a modification is necessary (step S133: YES), the processing unit 190 acquires circuit information of the modified circuit (the circuit modified from the designer-created circuit before multiplexing) (step S141). Alternatively, the designer may modify the circuit and the design support device 100 may acquire circuit information of the modified circuit. Or, the processing unit 190 may perform the circuit modification automatically or semi-automatically. After step S141, the process returns to step S103.

[0038] On the other hand, if the iterative control unit 195 determines in step S133 that no correction is necessary (step S133: NO), the processing unit 190 performs logic synthesis of the circuit (step S151). Logic synthesis, in this context, is the process of translating the logical description of the circuit's operation into a circuit on the FPGA. Next, the processing unit 190 determines the placement of each block in the FPGA and determines the wiring between the blocks (step S152). Next, the repeating control unit 195 determines whether the target performance is satisfied if the designed circuit were implemented on the FPGA (step S153).

[0039] If it is determined that the resulting circuit does not meet the target performance (step S153: NO), the process returns to step S103. In this case, the design support device 100 performs a design using a different type of redundancy than previously performed, according to the conditions for redundancy of the blocks. For example, the memory unit 180 may store a history of multiplexing that has been performed so far. The multiplexing unit 192 may then select blocks other than those that have been multiplexed so far and multiplex the selected blocks.

[0040] On the other hand, if it is determined in step S153 that the obtained circuit meets the target performance (step S153: YES), the processing unit 190 generates ROM code for implementing the obtained design on the FPGA (step S161). The memory unit 180 may store the generated ROM code. Alternatively, the communication unit 110 may transmit the generated ROM code to another device. For example, the communication unit 110 may transmit the generated ROM code to an implementation device, which may then implement the designed circuit on the FPGA according to the ROM code. After step S161, the design support device 100 completes the process shown in Figure 2.

[0041] On the other hand, if it is determined in step S103 that the system is set to tool mode (step S103: NO), the condition acquisition unit 191 acquires the specification of the block multiplexing priority (step S121). For example, the operation input unit 130 may accept user input to specify whether or not to multiplex each block, and the priority if multiplexing is performed. The condition acquisition unit 191 may then set whether or not to multiplex each block, and the priority if multiplexing is performed, according to the user input.

[0042] Next, the condition acquisition unit 191 sets the conditions for multiplexing the blocks (step S122). For example, the condition acquisition unit 191 sets whether or not to multiplex the block specified in step S121, and the priority if multiplexing is to be performed. The condition acquisition unit 191 may also set the conditions for multiplexing the blocks by storing the conditions for multiplexing the blocks in the storage unit 180.

[0043] In step S122, the condition acquisition unit 191 may set options / parameters for logic synthesis / placement and routing. As described above, the options / parameters for logic synthesis / placement and routing may set constraints on the execution results when performing logic synthesis and placement and routing (for example, limiting the number of fan-outs), or which of the target performance to prioritize (which of the operating frequency, power consumption, or area to prioritize). After step S122, the process proceeds to step S131.

[0044] Figure 3 shows a first example of the circuit information to be duplicated (design information of the circuit to be designed by the design support device 100). In the example in Figure 3, the circuit to be multiplexed is configured as a circuit consisting of block A, and block A is connected to TOP. The block connected to TOP is treated as the top-level block. The top-level block can also be called the first-layer block.

[0045] Figure 4 shows a first example of multiplexed circuit information. Figure 4 shows an example where block A of the circuit shown in Figure 3 is triple-redundant. Block A in Figure 3 is triple-redundant in Figure 4 as blocks A-1, A-2, and A-3. In addition, Figure 4 includes a majority voting circuit that takes a majority vote of the outputs of blocks A-1, A-2, and A-3. Blocks A-1, A-2, and A-3 are all connected to TOP in the majority voting circuit. Figure 4 shows an example where the top-level block is subject to triple redundancy.

[0046] Figure 5 shows a first example of assigning a multiplexed circuit to an FPGA. Figure 5 shows an example of assigning the tripled circuit shown in Figure 4 to an FPGA. The design support device 100 divides the FPGA area into four sections and assigns the triple-redundant blocks A-1, A-2, and A-3 to one of these four sections. The design support device 100 also assigns the majority voting circuit to the remaining section of the four sections.

[0047] Figure 6 shows a second example of the circuit information to be multiplexed. In the example in Figure 6, the circuit to be multiplexed is configured as a circuit consisting of blocks A, B, and C. Block A is connected to the top, and blocks B and C are each connected to block A. Therefore, block A is the highest-level block. Blocks B and C are each lower-level blocks of block A. As a result, blocks B and C are the second-layer blocks.

[0048] Figure 7 shows a second example of multiplexed circuit information. Figure 7 shows an example where block B of the circuit shown in Figure 6 is triple-redundant. Block B in Figure 6 is triple-redundant in Figure 7 as blocks B-1, B-2, and B-3. In addition, Figure 7 includes a majority voting circuit that takes a majority vote of the outputs of blocks B-1, B-2, and B-3. Blocks B-1, B-2, B-3, and the majority voting circuit are all connected to Block A.

[0049] Figure 7 shows an example where a lower-level block is subject to triple redundancy than in the example in Figure 4. In the example in Figure 4, the top-level block, Block A, is triple-redundant, whereas in the example in Figure 7, the second-level block, Block B, is triple-redundant.

[0050] Figure 8 shows a second example of assigning a multiplexed circuit to an FPGA. Figure 8 shows an example of assigning the tripled circuit shown in Figure 7 to an FPGA. The design support device 100 divides the region of block B in the FPGA into four parts and assigns the triple-redundant blocks B-1, B-2, and B-3 to one of the four divided regions. The design support device 100 also assigns the majority voting circuit to the remaining of the four divided regions. Furthermore, the design support device 100 allocates the areas of blocks A and C, which are not triple-redundant, in such a way that they do not overlap with the area of ​​the triple-redundant block B. In the example in Figure 8, the region of Block B within the FPGA is divided into four parts, resulting in a shorter distance between the tripled blocks compared to the example in Figure 5, where the FPGA region is divided into four parts. This is expected to improve the operating frequency of the circuit implemented on the FPGA.

[0051] Figure 9 shows a third example of circuit information to be multiplexed. In the example in Figure 9, the circuit to be multiplexed is configured as a circuit consisting of block A and FF. Block A is connected to the top, and block FF is connected to block A. Therefore, block A is the topmost block. Block FF is a lower block than block A. As a result, block FF is a second-layer block. The block FF may also be a flip-flop circuit, similar to the one used in block A.

[0052] Figure 10 shows a third example of multiplexed circuit information. Figure 10 shows an example where the block flip-flops in the circuit shown in Figure 9 are triple-redundant. In Figure 10, the block flip-flops in Figure 9 are triple-redundant as blocks FF-1, FF-2, and FF-3. In addition, Figure 10 includes a majority voting circuit that takes a majority vote of the outputs of blocks FF-1, FF-2, and FF-3. Blocks FF-1, FF-2, FF-3, and the majority voting circuit are all connected to Block A.

[0053] Figure 10 shows an example where blocks at a lower hierarchical level than those in Figure 4 are subject to triple redundancy. In the example in Figure 4, the top-level block, Block A, is triple-redundant, whereas in the example in Figure 10, the second-level block, Block FF, is triple-redundant.

[0054] Figure 11 shows a third example of assigning a multiplexed circuit to an FPGA. Figure 11 shows an example of assigning the triple-redundant circuit shown in Figure 10 to an FPGA. When redundant flip-flop circuits, logic circuits, or wiring, it is advisable to space the three redundant parts apart to avoid soft errors occurring when two or more of the triple-redundant parts are simultaneously affected by cosmic rays or other radiation. In the example shown in Figure 11, the design support device 100 has blocks FF-1, FF-2, FF-3, and the majority voting circuit arranged at a distance from each other.

[0055] The design support device 100 may use simulated annealing (SA) as a method for determining the arrangement of multiplexed flip-flop circuits, logic circuits, or wiring. In this case, the design support device 100 may perform simulated annealing using an evaluation function that includes a subexpression indicating reliability based on the distance between the arranged parts, in addition to a subexpression indicating circuit size and a subexpression indicating wiring length. On the other hand, the distance between flip-flop circuits, logic circuits, or blocks other than wiring shall not be specified. However, the method by which the design support device 100 determines the arrangement of multiplexed flip-flop circuits, logic circuits, or wiring is not limited to a specific method.

[0056] Figure 12 shows a fourth example of circuit information to be multiplexed. In the example in Figure 12, the circuit to be multiplexed is configured as a circuit consisting of blocks A, B, C, and BB. Block A is connected to the top, and blocks B and C are each connected to block A. Also, block BB is connected to block B. Therefore, block A is the topmost block. Blocks B and C are lower blocks of block A. Block BB is lower blocks of block B. As a result, blocks B and C are second-layer blocks. Block BB is a third-layer block.

[0057] Figure 13 shows a fourth example of multiplexed circuit information. Figure 13 shows an example where block BB of the circuit shown in Figure 11 is triple-redundant. Block BB in Figure 12 is triple-redundant in Figure 13 as blocks BB-1, BB-2, and BB-3. In addition, Figure 13 includes a majority voting circuit that takes a majority vote of the outputs of blocks BB-1, BB-2, and BB-3. Blocks BB-1, BB-2, BB-3, and the majority voting circuit are all connected to Block B.

[0058] Figure 13 shows an example where a lower-level block is subject to triple redundancy than in the example in Figure 7. In the example in Figure 7, block B, which is in the second layer, is triple-redundant, whereas in the example in Figure 13, block BB, which is in the third layer, is triple-redundant.

[0059] Figure 14 shows a fourth example of assigning a multiplexed circuit to an FPGA. Figure 14 shows an example of assigning the triple-redundant circuit shown in Figure 13 to an FPGA. The design support device 100 divides the area of ​​block BB in the FPGA into four sections and assigns the triple-redundant blocks BB-1, BB-2, and BB-3 to one of these four sections. The design support device 100 also assigns a majority voting circuit to the remaining section of the four sections. Furthermore, the design support device 100 allocates the areas of blocks A, B, and C, which are not triple-redundant, in such a way that they do not overlap with the area of ​​the triple-redundant block BB. In the example in Figure 14, the region of block BB within the FPGA area is divided into four parts. Similar to the case in Figure 8, in the example in Figure 14, the distance between the tripled blocks is closer than in the example in Figure 5, where the FPGA area is divided into four parts. In this respect, an improvement in the operating frequency of the circuit implemented on the FPGA is expected.

[0060] Figure 15 shows a first example of a specification for multiplexing. Figure 15 shows an example of how the design support device 100 specifies the multiplexing of the circuit information blocks in Figure 12. In the example shown in Figure 15, the specification information indicating the multiplexing specification is presented as tabular data. The display unit 120 may display a table showing the specification information, and the operation input unit 130 may accept user operations to input values ​​into each column of the table showing the specification information. The specification information shown in Figure 15 indicates the specifications for each of the block names "TOP", "A", "B", "BB", and "C", for the following items: "N-level redundancy / not redundancy", "N-level redundancy / not redundancy for all lower levels", "placement method", and "placement location".

[0061] The "N-Duplicate / Do Not Duplicate" column indicates whether or not the corresponding block should be subject to duplicatement. The "Do not duplicate all lower levels" column indicates whether or not to duplicate all lower levels connected to the block in question, when the block in question is to be duplicated. The "Placement Method" column specifies how the placement of duplicated blocks is determined when the corresponding block is duplicated. The value "No.1" in the "Arrangement Method" column indicates a method of dividing the area to be multiplexed and assigning the multiplexed blocks and majority voting circuits, as shown in the examples in Figure 5, Figure 8, and Figure 14. The value "No.2" in the "Placement Method" column indicates a method of assigning multiplexed blocks and majority voting circuits using simulated annealing with an evaluation function that includes a subexpression showing the reliability evaluation based on the distance between the parts to be placed, as shown in the example in Figure 11.

[0062] The "Placement Location" column specifies the area within the FPGA where the corresponding block will be assigned. In the example in Figure 15, the position within the FPGA area is represented by two-dimensional coordinates (X and Y coordinates), and the "Placement Location" column specifies the range of the X and Y coordinates within the area of ​​the corresponding block. In the "Placement Location" field for block name "A", X1_A and X2_A specify the lower and upper limits of the X coordinate within the area of ​​block A. In the "Placement Location" field for block name "A", Y1_A and Y2_A specify the lower and upper limits of the Y coordinate within the area of ​​block A. In the "Placement Location" field for block name "B", X1_B and X2_B specify the lower and upper limits of the X coordinate within the area of ​​block B. In the "Placement Location" field for block name "B", Y1_B and Y2_B specify the lower and upper limits of the Y coordinate within the area of ​​block B. In the "Placement Location" field for block name "BB", X1_BB and X2_BB specify the lower and upper limits of the X coordinate within the block BB area. In the "Placement Location" field for block name "BB", Y1_BB and Y2_BB specify the lower and upper limits of the Y coordinate within the block BB area. In the "Placement Location" field for block name "C", X1_C and X2_C specify the lower and upper limits of the X coordinate within the area of ​​block C. In the "Placement Location" field for block name "C", Y1_C and Y2_C specify the lower and upper limits of the Y coordinate within the area of ​​block C.

[0063] A value of "-" in the field indicates that the item is not included in the selection. For the block name "TOP," the value in all fields is "-". In other words, none of the items for TOP are applicable. If you select "Yes" for the "Do not duplicate N levels" option, you will then be able to select either "Yes" or "No" for the "Do not duplicate all lower levels" option. In other words, for a block designated as the target of duplication, you can specify whether or not to include all lower-level blocks connected to that block in the duplication process. However, for the lowest-level block, even if "Yes" is selected in the "Do not make N-level" column, the value in the "Do not make all lower levels N-level" column will be set to "-" and it will be excluded from the specification. In the example in Figure 15, the value in the "Do not make N-level" column for the block name "BB" is "Yes," but since block BB is the lowest-level block, the value in the "Do not make all lower levels N-level" column is set to "-".

[0064] Furthermore, if "Do not duplicate" is selected for the item "Duplicate all lower levels as well / Do not duplicate", the value in the "Duplicate all lower levels as well / Do not duplicate" column will be set to "-", excluding them from the selection. In the example in Figure 15, the values ​​in the "Duplicate as well / Do not duplicate" column for all block names "A", "B", and "C" are set to "Do not duplicate", and the value in the "Duplicate all lower levels as well / Do not duplicate" column is set to "-". Block C is an example of excluding the lowest-level block from the "Do not make all lower levels N-level" specification. In other words, no lower-level blocks are connected to Block C, and Block C is the lowest-level block in its sequence. The value in the "Do not make all lower levels N-level" column for the block named "C" is "-".

[0065] In the "Placement Method" column, "No. 1" can be specified for any block. Furthermore, for blocks below a block that has "No.1" specified in the "Placement Method" column, "No.2" can be specified. On the other hand, for blocks below a block that has "No. 2" specified in the "Placement Method" column, "No. 1" cannot be specified.

[0066] Figure 16 shows a fifth example of multiplexed circuit information. Figure 16 shows an example where block C of the circuit shown in Figure 6 is triple-redundant. Block C in Figure 6 is triple-redundant in Figure 16 as blocks C-1, C-2, and C-3. In addition, Figure 16 includes a majority voting circuit that takes a majority vote of the outputs of blocks C-1, C-2, and C-3. Blocks C-1, C-2, C-3, and the majority voting circuit are all connected to block A.

[0067] Figure 16 shows an example where a lower-level block is subject to triple redundancy than in the example in Figure 4. In the example in Figure 4, the top-level block, Block A, is triple-redundant, whereas in the example in Figure 16, the second-level block, Block C, is triple-redundant.

[0068] Figure 17 shows a fifth example of assigning a multiplexed circuit to an FPGA. Figure 17 shows an example of assigning the triple-redundant circuit shown in Figure 16 to an FPGA. The design support device 100 divides the region of block C in the FPGA into four parts and assigns the triple-redundant blocks C-1, C-2, and C-3 to one of the four divided regions. The design support device 100 also assigns the majority voting circuit to the remaining of the four divided regions. Furthermore, the design support device 100 allocates the areas of blocks A and B, which are not triple-redundant blocks, in such a way that they do not overlap with the area of ​​the triple-redundant block C. In the example in Figure 17, the region of block C within the FPGA is divided into four parts, resulting in a shorter distance between the tripled blocks compared to the example in Figure 5, where the FPGA region is divided into four parts. This is expected to improve the operating frequency of the circuit implemented on the FPGA.

[0069] Figure 18 shows a second example of a specification for multiplexing. Figure 18 shows an example of how the design support device 100 specifies the multiplexing of the circuit information blocks in Figure 6. Similar to the example in Figure 15, the example in Figure 18 shows the specification information indicating the multiplexing specification as tabular data. The display unit 120 may display the table showing the specification information, and the operation input unit 130 may accept user operations to input values ​​into each column of the table showing the specification information. The specification information shown in Figure 18 indicates the specifications for each of the block names "TOP", "A", "B", and "C", for the following items: "N-level redundancy / not redundancy", "all lower levels also N-level redundancy / not redundancy", "placement method", "placement location", and "N-level redundancy priority".

[0070] The columns for "N-level duplication / not duplication," "N-level duplication for all lower levels / not duplication," "Placement method," and "Placement location" are explained in the same way as in Figure 15. The "N-Duplicate Priority" column indicates the priority (priority) for duplicating the corresponding block. A smaller number in the "N-Duplicate Priority" column indicates a higher priority. The design support device 100 performs redundancy on the blocks designated for redundancy, in order of highest redundancy priority.

[0071] As explained with reference to Figure 15, the value "-" in the column indicates that it is not a target. For the block name "TOP," the value in all fields is "-". In other words, none of the items for TOP are applicable. As explained with reference to Figure 15, if you select "Yes" for the "Do not duplicate N levels" item, you will then be able to select either "Yes" or "No" for the "Do not duplicate all lower levels" item. However, for the lowest-level block, even if "Yes" is selected in the "Do not make N-level blocks" column, the value in the "Do not make all lower levels N-level blocks N-level" column will be set to "-" and it will be excluded from the specification. In the example in Figure 18, the value in the "Do not make N-level blocks N-level" column is "Yes" for both block names "B" and "C", but since both blocks B and C are the lowest-level blocks, the value in the "Do not make all lower levels N-level blocks N-level" column is set to "-".

[0072] Furthermore, if "Do not duplicate" is selected for the item "Duplicate all lower levels as well / Do not duplicate", the value in the "Duplicate all lower levels as well / Do not duplicate" column will be set to "-", excluding it from the selection. In the example in Figure 18, the value in the "Duplicate / Do not duplicate" column for block name "A" is "Do not duplicate", and the value in the "Duplicate all lower levels as well / Do not duplicate" column is "-".

[0073] As explained with reference to Figure 15, in the "Placement Method" column, "No. 1" can be specified for any block. Furthermore, for blocks below a block that has "No.1" specified in the "Placement Method" column, "No.2" can be specified. On the other hand, for blocks below a block that has "No. 2" specified in the "Placement Method" column, "No. 1" cannot be specified.

[0074] If N=3 is specified, the design support device 100 performs triple redundancy on block B, which has a redundancy priority of "1" in the specified information in Figure 18. As a result, the design support device 100 triple-reduces block B of the circuit shown in Figure 6 and generates the circuit information shown in Figure 7. Then, the design support device 100 assigns the triple-redundant circuit shown in Figure 7 to the FPGA as in the example in Figure 8.

[0075] The design support device 100 then determines whether the circuit assigned to the FPGA, as shown in the example in Figure 8, satisfies the target performance. If it determines that the circuit satisfies the target performance, the design support device 100 generates ROM code for implementing this circuit on the FPGA.

[0076] On the other hand, if the design support device 100 determines that the circuit assigned to the FPGA does not satisfy the target performance, as in the example in Figure 8, it performs triple redundancy on block C, which has a redundancy priority of "2" in the specified information in Figure 18, for the circuit information shown in Figure 6. As a result, the design support device 100 generates the circuit information shown in Figure 16. Then, the design support device 100 assigns the triple-redundant circuit shown in Figure 16 to the FPGA as in the example in Figure 17.

[0077] The design support device 100 then determines whether the circuit assigned to the FPGA, as shown in the example in Figure 17, satisfies the target performance. If it determines that the circuit satisfies the target performance, the design support device 100 generates ROM code for implementing this circuit on the FPGA.

[0078] On the other hand, if the design support device 100 determines that the circuit assigned to the FPGA does not satisfy the target performance, as in the example in Figure 17, it notifies the user that it has failed to design a circuit that satisfies the target performance. For example, the display unit 120 may display a message indicating that it has failed to design a circuit that satisfies the target performance.

[0079] Figure 19 shows a sixth example of multiplexed circuit information. Figure 19 shows an example where block B of the circuit shown in Figure 6 is duplicated five times. Block B in Figure 6 is duplicated five times in Figure 19 into blocks B-1, B-2, B-3, B-4, and B-5. In addition, Figure 19 includes a majority voting circuit that takes a majority vote of the outputs of blocks B-1, B-2, B-3, B-4, and B-5. Blocks B-1, B-2, B-3, B-4, B-5, and the majority voting circuit are all connected to Block A.

[0080] Figure 19 shows an example where blocks at a lower hierarchical level than those in Figure 4 are subject to redundancy. In the example in Figure 4, the top-level block, Block A, is triple-redundant, whereas in the example in Figure 19, the second-level block, Block B, is quintuple-redundant.

[0081] Figure 20 shows a sixth example of assigning a multiplexed circuit to an FPGA. Figure 20 shows an example of assigning the quintuple redundant circuit shown in Figure 19 to an FPGA. The design support device 100 divides the region of block B in the FPGA into six parts and assigns the five-redundant blocks B-1, B-2, B-3, B-4, and B-5 to one of the six divided regions. The design support device 100 also assigns the majority voting circuit to the remaining of the six divided regions. Furthermore, the design support device 100 allocates the areas of blocks A and C, which are not quintuplely redundant, so that they do not overlap with the area of ​​block B, which is quintuplely redundant. In the example in Figure 20, the region of Block B within the FPGA area is divided into six parts, resulting in closer distances between the five redundant blocks compared to the example in Figure 5, where the FPGA area is divided into four parts. This is expected to improve the operating frequency of the circuits implemented on the FPGA.

[0082] Figure 21 shows a seventh example of multiplexed circuit information. Figure 21 shows an example where block C of the circuit shown in Figure 6 is redundantly duplicated five times. Block C in Figure 6 is redundantly duplicated five times in Figure 21 into blocks C-1, C-2, C-3, C-4, and C-5. In addition, Figure 21 includes a majority voting circuit that takes a majority vote of the outputs of blocks C-1, C-2, C-3, C-4, and C-5. Blocks C-1, C-2, C-3, C-4, C-5, and the majority voting circuit are all connected to Block A.

[0083] Figure 21 shows an example where blocks at a lower hierarchical level than those in Figure 4 are subject to redundancy. In the example in Figure 4, the top-level block, Block A, is triple-redundant, whereas in the example in Figure 21, the second-level block, Block C, is quintuple-redundant.

[0084] Figure 22 shows a seventh example of assigning a multiplexed circuit to an FPGA. Figure 22 shows an example of assigning the quintuple redundant circuit shown in Figure 21 to an FPGA. The design support device 100 divides the region of block C in the FPGA into six parts and assigns the quintuple-redundant blocks C-1, C-2, C-3, C-4, and C-5 to one of the six divided regions. The design support device 100 also assigns the majority voting circuit to the remaining of the six divided regions. Furthermore, the design support device 100 allocates the areas of blocks A and B, which are not quintuplely redundant, so that they do not overlap with the area of ​​block C, which is quintuplely redundant. In the example in Figure 22, the region of block C within the FPGA is divided into six parts, resulting in closer distances between the five redundant blocks compared to the example in Figure 5, where the FPGA region is divided into four parts. This is expected to improve the operating frequency of the circuits implemented on the FPGA.

[0085] For example, if the design support device 100 redundancies the circuit shown in Figure 6 fivefold based on the specified information shown in Figure 18, the design support device 100 redundancies block B, which has a redundancy priority of "1" in the specified information in Figure 18, fivefold. As a result, the design support device 100 redundancies block B of the circuit shown in Figure 6 fivefold and generates the circuit information shown in Figure 19. Then, the design support device 100 assigns the fivefold redundant circuit shown in Figure 19 to the FPGA as in the example in Figure 20.

[0086] The design support device 100 then determines whether the circuit assigned to the FPGA, as shown in the example in Figure 20, satisfies the target performance. If it determines that the circuit satisfies the target performance, the design support device 100 generates ROM code for implementing the circuit on the FPGA.

[0087] On the other hand, if the design support device 100 determines that the circuit assigned to the FPGA does not satisfy the target performance, as in the example in Figure 20, it performs quintuple redundancy on block C, which has a redundancy priority of "2" in the specified information in Figure 18, for the circuit information shown in Figure 6. As a result, the design support device 100 generates the circuit information shown in Figure 21. Then, the design support device 100 assigns the quintuple redundant circuit shown in Figure 21 to the FPGA as in the example in Figure 22.

[0088] The design support device 100 then determines whether the circuit assigned to the FPGA, as shown in the example in Figure 22, satisfies the target performance. If it determines that the circuit satisfies the target performance, the design support device 100 generates ROM code for implementing this circuit on the FPGA.

[0089] On the other hand, if the design support device 100 determines that the circuit assigned to the FPGA does not satisfy the target performance, as in the example in Figure 22, it notifies the user that it has failed to design a circuit that satisfies the target performance. For example, the display unit 120 may display a message indicating that it has failed to design a circuit that satisfies the target performance.

[0090] Figure 23 shows an example of the configuration of an implementation system according to at least one embodiment. In the configuration shown in Figure 23, the implementation system 1 comprises a design support device 100 and an implementation device 200. In the implementation system 1, the design support device 100 transmits the generated ROM code to the implementation device 200. The mounting device 200 mounts the circuit onto the FPGA according to the ROM code received from the design support device 100. The mounting device 200 may perform the circuit mounting onto the FPGA automatically or semi-automatically.

[0091] As described above, the multiplexing unit 192 multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to make it a target for multiplexing.

[0092] The placement unit 193 determines the placement of the multiplexed circuit, which is a circuit in which blocks have been multiplexed, on the mounting target. The performance determination unit 194 determines whether the implemented circuit satisfies the specified target performance, assuming that the multiplexed circuit is implemented on the implementation target according to the determined arrangement.

[0093] If the performance determination unit 194 determines that the implemented circuit does not satisfy the target performance, the repeating control unit 195 changes the blocks to be multiplexed based on the specified information and causes the multiplexing unit 192, the arrangement unit 193 to determine the arrangement, and the performance determination unit 194 to perform the determination again.

[0094] According to the design support device 100, when designing a partially redundant circuit, if the resulting circuit does not satisfy the target performance, the burden on the designer to redesign it can be relatively reduced. In particular, the design support device 100 can automatically redesign the circuit by changing the redundant blocks.

[0095] Let's consider the case where the designer manually performs block multiplexing and incorporates majority voting circuits. In this case, the designer needs to design and verify the block multiplexing and majority voting circuits. For example, errors may occur when creating connection circuits for multiple signals. Also, when incorporating block multiplexing and majority voting circuits, the circuit size becomes larger compared to circuits without block multiplexing, which can make timing compliance more difficult during the logic synthesis / place-and-route design phase. In that case, it becomes necessary to change the blocks to be multiplexed, change the majority voting circuit, and re-verify the circuit changes to facilitate timing compliance. Furthermore, logic synthesis / place-and-route must be performed again, increasing the design effort. In this context, "timing met" refers to, for example, satisfying the constraints on the operating frequency of the clock in the design.

[0096] In contrast, the design support device 100, with its function to automatically perform block multiplexing and majority voting circuit design, can process the data more efficiently compared to when a designer manually performs block multiplexing and majority voting circuit design. Furthermore, the design support device 100 can reduce circuit defects and improve circuit quality compared to when a designer manually performs block multiplexing and majority voting circuit design.

[0097] Furthermore, the design support device 100 can feed back the results of block multiplexing and logic synthesis / place-and-route of majority voting circuits, change the options / parameters used during logic synthesis / place-and-route, and repeat the logic synthesis / place-and-route until the timing is met. For example, in step S111 or S122 of Figure 2, the condition acquisition unit 191 may change the options / parameters used during logic synthesis / place-and-route.

[0098] Furthermore, according to the design support device 100, if the target performance set by the designer is not satisfied, such as not timing correctly, the design support device 100 can automatically change the hierarchy of the blocks to be duplicated and the method of placement and routing, according to the priority specification of block duplication made by the designer. If the target performance is still not satisfied, the design support device 100 can reduce the number of duplicated blocks and perform logic synthesis / placement and routing again. For example, if the target performance such as circuit size is not satisfied, in step S111 or S122 of Figure 2, the condition acquisition unit 191 may reduce the number of duplicated blocks by decreasing the value of the number of duplicated blocks N (for example, changing from 5-fold to 3-fold duplication).

[0099] As a result, the design support device 100 can streamline the design process compared to when a designer manually changes options / parameters and the blocks to be multiplexed and the majority voting circuit based on the results of logic synthesis / placement and routing. Furthermore, the design support device 100 can improve reliability by performing block multiplexing and incorporating majority voting circuits as much as possible within the range that satisfies the target performance, depending on the circuit size and operating frequency of the FPGA target device. For example, within the range that satisfies the target performance such as circuit size, the condition acquisition unit 191 may increase the number of multiplexed blocks by increasing the value of the number of multiplexed blocks N (for example, changing from 3x to 5x) in step S111 or S122 of Figure 2.

[0100] Furthermore, the multiplexing unit 192 multiplexes the blocks to be multiplexed into an odd number of blocks. The placement unit 193 divides the area to be implemented where the multiplexed blocks are to be placed into areas that are one more than the number of multiplexed blocks, and assigns an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. According to the design support device 100, multiplexed blocks and majority voting circuits can be placed relatively close together. In this respect, the design support device 100 is expected to improve the operating frequency of the circuits implemented on the FPGA and make timing easier.

[0101] Furthermore, the placement unit 193 determines the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. According to the design support device 100, the distance between the redundant blocks can be increased, and it is expected that this will prevent soft errors from occurring when multiple blocks are simultaneously affected by radiation such as cosmic rays.

[0102] <Second Embodiment> Figure 24 shows an example of the configuration of a design support device according to at least one embodiment. In the configuration shown in Figure 24, the design support device 610 comprises a multiplexing unit 611, an arrangement unit 612, a performance determination unit 613, and a repeat control unit 614.

[0103] In this configuration, the multiplexing unit 611 multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to make it a target for multiplexing.

[0104] The placement unit 612 determines the placement of the multiplexed circuit, which is a circuit in which blocks have been multiplexed, on the mounting target. The performance determination unit 613 determines whether the implemented circuit satisfies the specified target performance, assuming that the multiplexed circuit is implemented on the target according to the determined arrangement.

[0105] If the repeating control unit 614 determines that the implemented circuit does not satisfy the target performance, it changes the blocks to be multiplexed based on the specified information and causes the multiplexing unit 611, the placement unit 612, and the performance determination unit 613 to perform the multiplexing, placement determination, and performance determination again. The multiplexing unit 611 is an example of multiplexing means. The arrangement unit 612 is an example of arrangement means. The performance determination unit 613 is an example of performance determination means. The repeat control unit 614 is an example of repeat control means.

[0106] According to the design support device 610, when designing a partially redundant circuit, if the resulting circuit does not satisfy the target performance, the burden on the designer to redesign it can be relatively reduced. In particular, the design support device 610 can automatically redesign the circuit by changing the redundant blocks.

[0107] <Third Embodiment> Figure 25 shows an example of the configuration of an implementation system according to at least one embodiment. In the configuration shown in Figure 25, the implementation system 620 comprises a design support device 621 and an implementation device 626. The design support device 621 comprises a multiplexing unit 622, a placement unit 623, a performance determination unit 624, and a repeat control unit 625.

[0108] In this configuration, the multiplexing unit 622 multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to make it a target for multiplexing.

[0109] The placement unit 623 determines the placement of the multiplexed circuit, which is a circuit in which blocks have been multiplexed, on the mounting target. The performance determination unit 624 determines whether the implemented circuit satisfies the specified target performance, assuming that the multiplexed circuit is implemented on the implementation target according to the determined arrangement.

[0110] If the repeating control unit 625 determines that the implemented circuit does not satisfy the target performance, it changes the blocks to be multiplexed based on the specified information and causes the multiplexing unit 622, the placement unit 623 to determine the placement, and the performance determination unit 624 to perform the determination again. The mounting device 626 mounts the circuit with multiplexed blocks onto the mounting target according to the design by the design support device 621. The multiplexing unit 622 is an example of a multiplexing means. The arrangement unit 623 is an example of an arrangement means. The performance determination unit 624 is an example of a performance determination means. The repeat control unit 625 is an example of a repeat control means.

[0111] According to the implementation system 620, when designing a partially redundant circuit, if the resulting circuit does not meet the target performance, the burden on the designer to redesign it can be relatively reduced. In particular, the implementation system 620 allows for automatic redesign by changing the redundant blocks.

[0112] <Fourth Embodiment> Figure 26 shows an example of the processing steps in a design support method according to at least one embodiment. The design support method shown in Figure 26 includes performing multiplexing (step S611), determining the arrangement (step S12), performing performance determination (step S613), and repeating the process (step S614).

[0113] In performing multiplexing (step S611), the computer multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is partially to be multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing. In determining the placement (step S612), the computer determines the placement of the multiplexed circuit, which is a circuit in which blocks have been multiplexed, on the implementation target. In the performance determination step (step S613), the computer determines whether the implemented circuit satisfies the specified target performance, assuming that the multiplexed circuit is implemented on the target according to the determined arrangement. In the repeated processing (step S614), if the computer determines that the implemented circuit does not satisfy the target performance, it changes the blocks to be duplicated based on the specified information and performs the multiplexing, placement determination, and determination again.

[0114] According to the design support method shown in Figure 26, when designing a partially redundant circuit, if the resulting circuit does not satisfy the target performance, the burden on the designer to redesign it can be relatively reduced. In particular, according to the design support method shown in Figure 26, redesign by changing the redundant blocks can be performed automatically.

[0115] Figure 27 shows an example of a computer configuration according to at least one embodiment. As shown in Figure 27, the computer 700 comprises a CPU 710, a main memory 720, an auxiliary memory 730, an interface 740, and a non-volatile recording medium 750.

[0116] One or more of the above-described design support devices 100, 610, and 621, or parts thereof, may be implemented in the computer 700. In that case, the operation of each of the above-described processing units is stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, expands it into the main memory 720, and executes the above-described processing according to the program. The CPU 710 also reserves memory areas in the main memory 720 corresponding to each of the above-described storage units according to the program. Communication between each device and other devices is performed by the interface 740 having a communication function and performing communication according to the control of the CPU 710. The interface 740 also has a port for the non-volatile recording medium 750 and reads information from and writes information to the non-volatile recording medium 750.

[0117] When the design support device 100 is implemented in a computer 700, the operation of the processing unit 190 and each of its parts is stored in auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, loads it into the main memory 720, and executes the above processing according to the program.

[0118] Furthermore, the CPU 710 reserves a memory area for the memory unit 180 in the main memory 720 according to the program. Communication with other devices by the communication unit 110 is performed by the interface 740 having a communication function and operating under the control of the CPU 710. Display of images by the display unit 120 is performed by the interface 740 having a display screen and displaying images under the control of the CPU 710. Acceptance of user operations by the operation input unit 130 is performed by the interface 740 having an input device and accepting user operations under the control of the CPU 710.

[0119] When the design support device 610 is implemented in the computer 700, the operations of the multiplexing unit 611, the placement unit 612, the performance determination unit 613, and the repeat control unit 614 are stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, loads it into the main memory 720, and executes the above processes according to the program.

[0120] Furthermore, the CPU 710 reserves memory in the main memory 720 for the design support device 610 to process according to the program. Communication between the design support device 610 and other devices is performed by the interface 740 having a communication function and operating under the control of the CPU 710. Interaction between the design support device 610 and the user is performed by the interface 740 having input and output devices, presenting information to the user via the output device and accepting user operations via the input device under the control of the CPU 710.

[0121] When the design support device 621 is implemented in the computer 700, the operations of the multiplexing unit 622, the placement unit 623, the performance determination unit 624, and the repeat control unit 625 are stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, loads it into the main memory 720, and executes the above processes according to the program.

[0122] Furthermore, the CPU 710 reserves memory in the main memory 720 for the design support device 621 to process according to the program. Communication between the design support device 621 and other devices is performed by the interface 740 having a communication function and operating under the control of the CPU 710. Interaction between the design support device 621 and the user is performed by the interface 740 having input and output devices, presenting information to the user via the output device and accepting user operations via the input device under the control of the CPU 710.

[0123] One or more of the above-mentioned programs may be recorded on the non-volatile recording medium 750. In this case, the interface 740 may read the program from the non-volatile recording medium 750. The CPU 710 may then either directly execute the program read by the interface 740, or temporarily save it in the main memory 720 or auxiliary memory 730 before executing it.

[0124] Alternatively, a program for executing all or part of the processing performed by the design support devices 100, 610, and 621 may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be loaded into a computer system and executed to perform the processing of each part. The term "computer system" here includes hardware such as the operating system (OS) and peripheral devices. Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, magneto-optical disks, ROMs (Read Only Memory), CD-ROMs (Compact Disc Read Only Memory), and storage devices such as hard disks built into computer systems. The above-mentioned program may be intended to implement only a part of the functions described above, and may also be able to implement the above-mentioned functions in combination with programs already recorded in the computer system.

[0125] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure are possible, as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, the embodiments described above may be combined with other embodiments as appropriate.

[0126] Some or all of the above embodiments may also be described as follows, but are not limited to these.

[0127] (Note 1) A multiplexing means that multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to be made a target for multiplexing, The aforementioned block is a multiplexed circuit, and the arrangement means determines the placement of the multiplexed circuit on the implementation target. A performance determination means for determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement, If it is determined that the implemented circuit does not satisfy the target performance, the repeating control means changes the blocks to be multiplexed based on the specified information and causes the multiplexing by the multiplexing means, the arrangement determination by the arrangement means, and the determination by the performance determination means to be performed again. A design support device equipped with the following features.

[0128] (Note 2) The multiplexing means multiplexes the blocks to be multiplexed into an odd number of blocks, The arrangement means divides the area of ​​the area to be implemented in which the multiplexed blocks are arranged into areas of one greater number than the number of multiplexed blocks, and assigns an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. The design support device described in Appendix 1.

[0129] (Note 3) The arrangement means determines the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. Design support device as described in Appendix 1 or Appendix 2.

[0130] (Note 4) It comprises a design support device and an implementation device, The design support device, A multiplexing means that multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to be made a target for multiplexing, The aforementioned block is a multiplexed circuit, and the arrangement means determines the placement of the multiplexed circuit on the implementation target. A performance determination means for determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement, If it is determined that the implemented circuit does not satisfy the target performance, the repeating control means changes the blocks to be multiplexed based on the specified information and causes the multiplexing by the multiplexing means, the arrangement determination by the arrangement means, and the determination by the performance determination means to be performed again. Equipped with, The mounting device mounts the circuit with multiplexed blocks onto the mounting target according to the design by the design support device. Implementation system.

[0131] (Note 5) The multiplexing means multiplexes the blocks to be multiplexed into an odd number of blocks, The arrangement means divides the area of ​​the area to be implemented in which the multiplexed blocks are arranged into areas of one greater number than the number of multiplexed blocks, and assigns an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. The implementation system described in Appendix 4.

[0132] (Note 6) The arrangement means determines the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. The implementation system described in Appendix 4 or Appendix 5.

[0133] (Note 7) Computers Based on circuit information in which the pre-multiplexing circuit, which is a circuit that is partially to be multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing, at least some of the blocks subject to multiplexing are multiplexed. The placement of the multiplexed circuit, which is a multiplexed circuit of the aforementioned block, on the implementation target is determined. Assuming that the multiplexed circuit is implemented on the target device according to the determined arrangement, it is determined whether the implemented circuit satisfies the specified target performance. If it is determined that the implemented circuit does not satisfy the target performance, the blocks to be multiplexed are changed based on the specified information, and the multiplexing, arrangement determination, and determination are repeated. A design support method that includes the following.

[0134] (Note 8) In performing the aforementioned multiplexing, the computer multiplexes the blocks to be multiplexed into an odd number of blocks, In determining the arrangement, the computer divides the area of ​​the implementation target where the multiplexed blocks are to be placed into an area of ​​one greater than the number of multiplexed blocks, and assigns an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. The design support method described in Appendix 7.

[0135] (Note 9) In determining the arrangement, the computer determines the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. The design support method described in Appendix 7 or Appendix 8.

[0136] (Note 10) On the computer, Based on circuit information in which the pre-multiplexing circuit, which is a circuit that is partially to be multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing, at least a portion of the blocks subject to multiplexing are to be multiplexed. The block is a multiplexed circuit, and the placement of the multiplexed circuit on the implementation target is determined. The process involves determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement. If it is determined that the implemented circuit does not satisfy the target performance, the blocks to be multiplexed are changed based on the specified information, and the multiplexing, arrangement determination, and determination are repeated. A program that executes the command.

[0137] (Note 11) The aforementioned multiplexing involves causing the computer to perform the multiplexing of the blocks to be multiplexed into an odd number of blocks. In determining the arrangement, the computer is instructed to divide the area of ​​the implementation target where the multiplexed blocks are to be placed into an area of ​​one greater than the number of multiplexed blocks, and to assign an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. The program described in Appendix 10.

[0138] (Note 12) In determining the arrangement, the computer is instructed to determine the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. The program described in Appendix 10 or Appendix 11. [Explanation of symbols]

[0139] 1,620 Implementation Systems 100, 610, 621 Design support equipment 110 Communications Department 120 Display section 130 Operation Input Section 180 Storage section 190 Processing Unit 191 Condition Acquisition Unit 192, 611, 622 Multiplexer 193, 612, 623 placement section 194, 613, 624 Performance judgment section 195, 614, 625 Repeat Control Unit 200, 626 mounting equipment 700 Computers 710 CPU 720 Main storage 730 Auxiliary storage 740 Interfaces 750 Non-volatile recording media

Claims

1. A multiplexing means that multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to be made a target for multiplexing, The aforementioned block is a circuit that has been duplicated, and the arrangement means for determining the placement of the duplicated circuit on the implementation target, A performance determination means for determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement, If it is determined that the implemented circuit does not satisfy the target performance, the repeating control means changes the blocks to be multiplexed based on the specified information and causes the multiplexing by the multiplexing means, the arrangement determination by the arrangement means, and the determination by the performance determination means to be performed again. A design support device equipped with the following features.

2. The multiplexing means multiplexes the blocks to be multiplexed into an odd number of blocks, The arrangement means divides the area of ​​the area to be implemented in which the multiplexed blocks are arranged into areas of one greater number than the number of multiplexed blocks, and assigns an odd number of multiplexed blocks and a majority voting circuit that takes a majority vote of the outputs of those odd number of blocks to the divided areas. The design support device according to claim 1.

3. The arrangement means determines the placement of at least some of the multiplexed blocks in the area to be implemented using simulated annealing, which includes an evaluation function that shows a reliability evaluation based on the distance between the blocks to be placed. A design support device according to claim 1 or claim 2.

4. It comprises a design support device and an implementation device, The design support device, A multiplexing means that multiplexes at least some of the blocks that are to be multiplexed, based on circuit information in which the pre-multiplexing circuit, which is a circuit that is to be partially multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit a target for multiplexing, and the priority if it is to be made a target for multiplexing, The aforementioned block is a circuit that has been duplicated, and the arrangement means for determining the placement of the duplicated circuit on the implementation target, A performance determination means for determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement, If it is determined that the implemented circuit does not satisfy the target performance, the repeating control means changes the blocks to be multiplexed based on the specified information and causes the multiplexing by the multiplexing means, the arrangement determination by the arrangement means, and the determination by the performance determination means to be performed again. Equipped with, The mounting device mounts the circuit with multiplexed blocks onto the mounting target according to the design by the design support device. Implementation system.

5. Computers Based on circuit information in which the pre-multiplexing circuit, which is a circuit that is partially to be multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing, at least some of the blocks subject to multiplexing are multiplexed. The placement of the multiplexed circuit, which is a multiplexed circuit of the aforementioned block, on the implementation target is determined. Assuming that the multiplexed circuit is implemented on the target device according to the determined arrangement, it is determined whether the implemented circuit satisfies the specified target performance. If it is determined that the implemented circuit does not satisfy the target performance, the blocks to be multiplexed are changed based on the specified information, and the multiplexing, arrangement determination, and determination are repeated. A design support method that includes the following.

6. On the computer, Based on circuit information in which the pre-multiplexing circuit, which is a circuit that is partially to be multiplexed, is divided into blocks, and designation information indicating whether or not to make each block of the pre-multiplexing circuit subject to multiplexing, and the priority if it is subject to multiplexing, at least a portion of the blocks subject to multiplexing are to be multiplexed. The block is a multiplexed circuit, and the placement of the multiplexed circuit, which is the circuit after the multiplexing, on the implementation target is determined. The process involves determining whether the implemented circuit satisfies the specified target performance when the multiplexed circuit is implemented on the target according to the determined arrangement. If it is determined that the implemented circuit does not satisfy the target performance, the blocks to be multiplexed are changed based on the specified information, and the multiplexing, arrangement determination, and determination are repeated. A program that executes the command.

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