Indication device

Abstract

To provide a display device that minimizes unevenness. [Solution] A display device according to one embodiment of the present invention includes a subpixel, which includes a light-emitting element, connected to a data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line; a gate driver that supplies a first sub-light emission control signal to the first sub-light emission control line and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line; and a data driver that supplies a data voltage to the data line. The length of the period during which the second sub-gate signal is supplied during a display scan interval is different from the length of the period during which the second sub-gate signal is supplied during a self-scan interval, and the second sub-gate signal can control the timing of initializing one electrode of the light-emitting element.

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] With the development of information technology, the importance of display devices, which are the connection medium between users and information, has been increasing. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices has been increasing.

[0003] A display device can include a plurality of pixels. One pixel column can be connected to the same data line. When the data voltage changes abruptly, it may affect other pixel rows to which the data voltage is not written. As a result, mura may occur in some areas of the display panel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] One object of the present invention is to provide a display device that minimizes mura.

Means for Solving the Problems

[0006] A display device according to one embodiment of the present invention includes a subpixel, which includes a light-emitting element, connected to a data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line; a gate driver that supplies a first sub-light emission control signal to the first sub-light emission control line and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line; and a data driver that supplies a data voltage to the data line. The length of the period during which the second sub-gate signal is supplied during a display scan interval differs from the length of the period during which the second sub-gate signal is supplied during a self-scan interval, and the second sub-gate signal controls the timing of initializing one electrode of the light-emitting element.

[0007] In one embodiment of the present invention, the subpixel includes a first transistor that generates a drive current and is connected between a first node and a second node that receive a first power supply voltage and is connected to a third node, and includes a gate electrode; a second transistor that is connected between the data line and the third node and includes a gate electrode connected to the first subgate line; a third transistor that is connected between the second node and a fourth node and includes a gate electrode connected to the first sub-light emission control line; and a fourth transistor that is connected between a node that provides an initialization voltage and the fourth node and includes a gate electrode connected to the second subgate line, wherein the light-emitting element may be connected between the fourth node and a node that receives a second power supply voltage.

[0008] In one embodiment of the present invention, the data voltage may be written to the subpixel during the display scan interval, but the data voltage may not be written to the subpixel during the self-scan interval.

[0009] In one embodiment of the present invention, the gate driver may supply the second subgate signal during the first period while the display scan interval is in progress, and the gate driver may supply the second subgate signal during the second period while the self-scan interval is in progress.

[0010] In one embodiment of the present invention, the length of the first period may be longer than the length of the second period.

[0011] In one embodiment of the present invention, the length between the end of the non-luminescent period including the first period and the end of the first period may be the same as the length between the end of the non-luminescent period including the second period and the end of the second period.

[0012] In one embodiment of the present invention, the length between the start of the non-luminescence period including the first period and the start of the first period may be shorter than the length between the start of the non-luminescence period including the second period and the start of the second period.

[0013] In one embodiment of the present invention, the length of the first period may be shorter than the length of the second period.

[0014] In one embodiment of the present invention, the length between the end of the non-luminescent period including the first period and the end of the first period may be the same as the length between the end of the non-luminescent period including the second period and the end of the second period.

[0015] In one embodiment of the present invention, the length between the start of the non-luminescence period including the first period and the start of the first period may be longer than the length between the start of the non-luminescence period including the second period and the start of the second period.

[0016] In one embodiment of the present invention, the subpixel further includes a fifth transistor connected between a node receiving the first power supply voltage and the first node and including a gate electrode connected to a second sub-light emission control line, and a sixth transistor connected between a node receiving a reference voltage and the third node and including a gate electrode connected to a third sub-gate line, wherein the gate driver may supply a second sub-light emission control signal to the second sub-light emission control line and a third sub-gate signal to the third sub-gate line.

[0017] A display device according to one embodiment of the present invention includes a subpixel, which includes a light-emitting element, connected to a data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line; a gate driver that supplies a first sub-light emission control signal to the first sub-light emission control line and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line; and a data driver that supplies a data voltage to the data line. The number of times the second sub-gate signal is supplied during a display scan interval and the number of times the second sub-gate signal is supplied during a self-scan interval are different, and the second sub-gate signal controls the timing of initializing one electrode of the light-emitting element.

[0018] In one embodiment of the present invention, the subpixel includes a first transistor that generates a drive current and is connected between a first node and a second node that receive a first power supply voltage and is connected to a third node, and includes a gate electrode; a second transistor that is connected between the data line and the third node and includes a gate electrode connected to the first subgate line; a third transistor that is connected between the second node and a fourth node and includes a gate electrode connected to the first sub-light emission control line; and a fourth transistor that is connected between a node that provides an initialization voltage and the fourth node and includes a gate electrode connected to the second subgate line, wherein the light-emitting element may be connected between the fourth node and a node that receives a second power supply voltage.

[0019] In one embodiment of the present invention, the data voltage may be written to the subpixel during the display scan interval, but the data voltage may not be written to the subpixel during the self-scan interval.

[0020] In one embodiment of the present invention, the number of times the gate driver supplies the second subgate signal during the display scan interval may be less than the number of times the gate driver supplies the second subgate signal during the self-scan interval.

[0021] In one embodiment of the present invention, during the display scan interval, the number of toggles of the second sub-gate signal may be smaller than the number of toggles of the second sub-gate signal during the self-scan interval.

[0022] In one embodiment of the present invention, the number of toggles may be the number of times the logic level of the second sub-gate signal changes.

[0023] In one embodiment of the present invention, during the display scan interval, the number of times the gate driver supplies the second sub-gate signal may be more than the number of times the gate driver supplies the second sub-gate signal during the self-scan interval.

[0024] In one embodiment of the present invention, during the display scan interval, the number of toggles of the second sub-gate signal may be more than the number of toggles of the second sub-gate signal during the self-scan interval.

[0025] In one embodiment of the present invention, the sub-pixel further includes a fifth transistor connected between a node receiving the first power supply voltage and the first node and including a gate electrode connected to a second sub-light emission control line, and a sixth transistor connected between a node receiving a reference voltage and the third node and including a gate electrode connected to a third sub-gate line, and the gate driver may supply a second sub-light emission control signal to the second sub-light emission control line and supply a third sub-gate signal to the third sub-gate line.

[0026] An electronic device according to one embodiment of the present invention includes a processor and a display device configured to display an image on the pixels according to the control of the processor, the display device including a subpixel having a light-emitting element connected to a data line, a first sub-light-emitting control line, a first sub-gate line, and a second sub-gate line, a gate driver that supplies a first sub-light-emitting control signal to the first sub-light-emitting control line and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line, and a data driver that supplies a data voltage to the data line, wherein the length of the period during which the second sub-gate signal is supplied during a display scan interval is different from the length of the period during which the second sub-gate signal is supplied during a self-scan interval, and the second sub-gate signal controls the timing of initializing one electrode of the light-emitting element. [Effects of the Invention]

[0027] A display device according to one embodiment of the present invention can minimize unevenness by making the waveform of the subgate signal supplied during the display scan section and the waveform of the subgate signal supplied during the self-scan section different.

[0028] However, the effects of the present invention are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawing]

[0029] [Figure 1] This is a block diagram showing one embodiment of a display device. [Figure 2] This is a block diagram showing one of the subpixels in Figure 1. [Figure 3] Figure 2 is a circuit diagram showing one embodiment of a subpixel. [Figure 4] This is a conceptual diagram illustrating the driving operation of the display device shown in Figure 1. [Figure 5] Figure 1 is a timing diagram illustrating an example of a display device performing a display scan operation. [Figure 6] Figure 1 is a timing diagram showing an example of a display device performing a self-scan operation. [Figure 7] This diagram illustrates the phenomenon where a pattern displayed in one area of ​​a display panel is copied and displayed in other areas. [Figure 8] This timing diagram shows one embodiment of the third subgate signal supplied to the display scan section and the self-scan section. [Figure 9] This timing diagram shows one embodiment of the third subgate signal supplied to the display scan section and the self-scan section. [Figure 10] This timing diagram shows one embodiment of the third subgate signal supplied to the display scan section and the self-scan section. [Figure 11] This timing diagram shows one embodiment of the third subgate signal supplied to the display scan section and the self-scan section. [Figure 12] A block diagram showing an electronic device according to one embodiment of the present invention. [Figure 13] Figure 12 shows an example of how the electronic device shown in Figure 12 can be realized in a smartphone. [Modes for carrying out the invention]

[0030] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following description, only the parts necessary to understand the operation of the present invention will be described, and descriptions of other parts may be omitted without departing from the spirit of the invention. Furthermore, the present invention is not limited to the embodiments described herein and can be embodied in other forms. The embodiments described herein are provided in enough detail to enable a person with ordinary skill in the art to easily implement the technical idea of ​​the present invention.

[0031] Throughout the specification, when a part is said to be “connected” to another part, this includes not only cases where it is “directly connected” but also cases where it is “indirectly connected” with other elements in between. The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the invention. Throughout the specification, when a part is said to “include” a component, this means that it may include other components rather than excluding them, unless otherwise stated. “At least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, “and / or” includes all combinations of one or more of the applicable components.

[0032] Here, terms such as "first," "second," etc., may be used to describe various components, but such components are not limited to these terms. Such terms are used to distinguish one component from another. Thus, the first component may refer to the second component insofar as it does not deviate from what is disclosed herein.

[0033] Spatially relative terms such as "down" and "up" may be used for descriptive purposes to explain the relationship between one element or feature and another, as shown in the drawing. Spatially relative terms are intended to include different directions during use, operation, and / or manufacturing, in addition to the directions depicted in the drawing. For example, if the device shown in the drawing is inverted, an element depicted as being located "down" of another element or feature will be located "up" of the other element or feature. Thus, in one embodiment, the term "down" may include both up and down directions. Moreover, the device may be oriented in other directions (e.g., rotated 90 degrees or in any other direction), and the spatially relative terms used herein will be interpreted accordingly.

[0034] Various embodiments are described with reference to diagrams illustrating ideal embodiments. It will be anticipated that, for example, tolerances and / or manufacturing techniques may cause variations in their shape. Therefore, the embodiments disclosed herein should not be construed as being limited to specific illustrated shapes, but rather as including, for example, variations in shape resulting from manufacturing. Thus, the shapes shown in the drawings do not necessarily represent the actual shapes of the areas of the apparatus, and these embodiments are not limited to the examples shown herein.

[0035] Figure 1 is a block diagram showing one embodiment of a display device.

[0036] Referring to Figure 1, the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0037] The display panel 110 includes sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 via the first to the mth gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 via the first to the nth data lines DL1 to DLn.

[0038] Each subpixel SP may contain at least one light-emitting element configured to generate light. This allows each subpixel SP to generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels SP can constitute a single pixel PXL. For example, as shown in Figure 1, three subpixels can constitute a single pixel PXL.

[0039] The gate driver 120 is connected to subpixels SP arranged in the row direction via the first to m gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m gate lines GL1 to GLm in response to the gate control signal GCS. In one embodiment of the present invention, the gate control signal GCS may include a start signal that indicates the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with the timing at which data signals are applied, and the like.

[0040] In one embodiment of the present invention, first to m-th light emission control lines EL1 to ELm connected to row-direction sub-pixels SP can be further provided. In such a case, the gate driver 120 may include a light emission control driver configured to control the first to m-th light emission control lines EL1 to ELm, and the light emission control driver can operate according to the control of the controller 150.

[0041] The gate driver 120 can be located on one side of the display panel 110. However, one embodiment of the present invention is not limited to the example shown herein. For example, the gate driver 120 can be divided into two or more physically and / or logically separated drivers, and such drivers may be located on one side of the display panel 110 and on the other side of the display panel 110 opposite to the first side. Thus, the gate driver 120 can be located around the display panel 110 in various forms according to one embodiment of the present invention.

[0042] The data driver 130 is connected to sub-pixels SP arranged in a column direction via the first to nth data lines DL1 to DLn. The data driver 130 receives video data DATA and data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In one embodiment of the present invention, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0043] The data driver 130 can use the voltage from the voltage generator 140 to apply data signals having a gradation voltage corresponding to the video data DATA to the first to nth data lines DL1 to DLn. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, data signals corresponding to the video data DATA can be applied to the data lines DL1 to DLm. As a result, the corresponding subpixel SP can generate light corresponding to the data signal. This causes the video to be displayed on the display panel 110.

[0044] In one embodiment of the present invention, the gate driver 120 and the data driver 130 may include CMOS (complementary metal-oxide semiconductor) circuit elements.

[0045] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 may be configured to generate multiple voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0046] The voltage generator 140 can generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS can be supplied to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a lower voltage level than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be supplied by an external device of the display device 100.

[0047] In addition, the voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to a sub-pixel SP. For instance, during a sensing operation to sense the electrical characteristics of the transistor and / or light-emitting element of the sub-pixel SP, a predetermined reference voltage can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate such a reference voltage.

[0048] The controller 150 controls the various operations of the display device 100. The controller 150 receives input video data IMG and a control signal CTRL for controlling its display from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0049] The controller 150 can convert the input video data IMG to be compatible with the display device 100 or display panel 110 and output video data DATA. In one embodiment of the present invention, the controller 150 can align the input video data IMG to be compatible with row-level subpixels SP and output video data DATA.

[0050] Two or more of the data driver 130, voltage generator 140, and controller 150 can be implemented in a single integrated circuit. As shown in Figure 1, the data driver 130, voltage generator 140, and controller 150 can be included in a driver integrated circuit DIC. In such a case, the data driver 130, voltage generator 140, and controller 150 can be functionally separated components within a single driver integrated circuit DIC. In another embodiment, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0051] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP representing the sensed temperature. In one embodiment of the present invention, the temperature sensor 160 may be positioned adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0052] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In one embodiment of the present invention, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to temperature data TEP. For example, the controller 150 can adjust the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0053] Figure 2 is a block diagram showing one embodiment of the subpixels in Figure 1. In Figure 2, the subpixel SPij arranged in the i-th row (where i is an integer between 1 and m) and the j-th column (where j is an integer between 1 and n) of the subpixel SP in Figure 1 is shown as an example.

[0054] Referring to Figure 2, the sub-pixel SPij may include the sub-pixel circuit SPC and the light-emitting element LD.

[0055] The light-emitting element LD is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. In this case, the first power supply voltage node VDDN is the node that transmits the first power supply voltage VDD in Figure 1, and the second power supply voltage node VSSN is the node that transmits the second power supply voltage VSS in Figure 1.

[0056] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via a sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0057] The sub-pixel circuit SPC can be connected to the i-th gate line GLi among the first to m-th gate lines GL1 to GLm in Figure 1, the i-th light emission control line ELi among the first to m-th light emission control lines EL1 to ELm in Figure 1, and the j-th data line DLj among the first to n-th data lines DL1 to DLn in Figure 1. The sub-pixel circuit SPC is configured to control the light-emitting element LD in response to signals received through such signal lines.

[0058] The sub-pixel circuit SPC can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In one embodiment of the present invention, as shown in Figure 2, the i-th gate line GLi may include first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC can operate in response to a gate signal received via the first and second sub-gate lines SGL1 and SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to a gate signal received via the relevant sub-gate lines.

[0059] The sub-pixel circuit SPC can operate in response to a light emission control signal received via the i-th light emission control line ELi. In one embodiment of the present invention, the i-th light emission control line ELi may include one or more sub-light emission control lines. If the i-th light emission control line ELi includes two or more sub-light emission control lines, the sub-pixel circuit SPC can operate in response to a light emission control signal received via the sub-light emission control lines.

[0060] The sub-pixel circuit SPC can receive data signals via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first and second sub-gate lines SGL1 and SGL2. In response to a light emission control signal received via the i-th light emission control line ELi, the sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN according to the stored voltage. This allows the light-emitting element LD to generate light with a brightness corresponding to the data signal.

[0061] Figure 3 is a circuit diagram showing one embodiment of the subpixels in Figure 2.

[0062] Referring to Figure 3, the subpixel SPij may include the subpixel circuit SPC and the light-emitting element LD.

[0063] The sub-pixel circuit SPC can be connected to the i-th gate line GLi', the i-th light emission control line ELi', and the j-th data line DLj. Compared to the i-th gate line GLi in Figure 2, the i-th gate line GLi' may further include a third sub-gate line SGL3. Compared to the i-th light emission control line ELi in Figure 2, the i-th light emission control line ELi' may include a first sub-light emission control line SEL1 and a second sub-light emission control line SEL2.

[0064] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6, a first capacitor C1, and a second capacitor C2.

[0065] The first transistor T1 is connected between the first node N1 and the second node N2, which receive the first power supply voltage. The gate electrode of the first transistor T1 is connected to the third node N3, thereby allowing the first transistor T1 to be turned on in accordance with the voltage level of the third node N3. The first transistor T1 can be referred to as the driver transistor.

[0066] The second transistor T2 is connected between the j-th data line DLj and the third node N3. The gate electrode of the second transistor T2 is connected to the first subgate line SGL1, so that the second transistor T2 can be turned on in response to the subgate signal of the first subgate line SGL1. When the second transistor T2 is turned on, it can provide a data voltage to the third node N3. The second transistor T2 can be referred to as a switching transistor.

[0067] A third transistor T3 is connected between the reference voltage node VRFN and the third node N3. The reference voltage node VRFN is configured to transmit a reference voltage. In one embodiment of the present invention, the reference voltage can be provided by the voltage generator 140 in Figure 1. The reference voltage can have a value between the first power supply voltage and the second power supply voltage.

[0068] The gate electrode of the third transistor T3 is connected to the second subgate line SGL2, thereby allowing the third transistor T3 to be turned on in response to the subgate signal of the second subgate line SGL2. When the third transistor T3 is turned on, a reference voltage can be provided to the third node N3.

[0069] The fourth transistor T4 is connected between the fourth node N4 and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. In one embodiment of the present invention, the initialization voltage can be provided by the voltage generator 140 in Figure 1. The initialization voltage can have a value between the first power supply voltage and the second power supply voltage.

[0070] The gate electrode of the fourth transistor T4 is connected to the third subgate line SGL3, thereby allowing the fourth transistor T4 to be turned on in response to the subgate signal of the third subgate line SGL3.

[0071] The fifth transistor T5 is connected between the first power supply voltage node VDDN and the first node N1. The gate electrode of the fifth transistor T5 is connected to the first sub-light emission control line SEL1, so that the fifth transistor T5 can be turned on in response to the first sub-light emission control signal of the first sub-light emission control line SEL1. The first node N1 can receive the first power supply voltage via the fifth transistor T5.

[0072] The sixth transistor T6 is connected between the second node N2 and the fourth node N4 (i.e., the anode electrode of the light-emitting element LD). The gate electrode of the sixth transistor T6 is connected to the second sub-light emission control line SEL2, so that the sixth transistor T6 can be turned on in response to the second sub-light emission control signal of the second sub-light emission control line SEL2.

[0073] The first capacitor C1 can be connected between the second node N2 and the third node N3. The first capacitor C1 can store a voltage corresponding to the data signal.

[0074] The second capacitor C2 can be connected between the first power supply voltage VDDN and the second node N2. The second capacitor C2 can stabilize the voltage at the second node N2.

[0075] Thus, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6, a first capacitor C1, and a second capacitor C2. However, the embodiment of the present invention is not limited to the example shown herein.

[0076] A sub-pixel circuit SPC can be implemented in any one of various forms of circuitry, including multiple transistors and one or more capacitors. For example, a sub-pixel circuit SPC may include two transistors and one capacitor. According to one embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light emission control lines included in the i-th light emission control line ELi' can be variable.

[0077] Each of the first to sixth transistors T1 to T6 can be a MOSFET (Metal Oxide Silicon Field Effect Transistor).

[0078] Each of the first to sixth transistors T1 to T6 can be an N-type transistor. In this case, the turn-on level can be a high voltage level, and the turn-off level can be a low voltage level. When the signal applied to the gate electrode of an N-type transistor has a low voltage level, the N-type transistor can be turned off. For example, when the signal applied to the gate electrode of an N-type transistor has a high voltage level, the N-type transistor can be turned on.

[0079] However, the present invention is not limited to the examples shown herein. For example, some of the first to sixth transistors T1 to T6 may be P-type transistors. In this case, the turn-on level can be a low voltage level, and the turn-off level can be a high voltage level. For example, when the signal applied to the gate electrode of a P-type transistor has a low voltage level, the P-type transistor can be turned on. For example, when the signal applied to the gate electrode of a P-type transistor has a high voltage level, the P-type transistor can be turned off.

[0080] In the following, "the subgate signal is supplied" can be understood as the subgate signal being supplied to a logic level that turns on the transistor it controls. Similarly, "the subgate signal supply is interrupted" can be understood as the subgate signal being supplied to a logic level that turns off the transistor it controls.

[0081] Furthermore, the phrase "the light emission control signal is supplied" can be understood as the light emission control signal being supplied to a logic level that turns on the transistor controlled by it. Similarly, the phrase "the supply of the light emission control signal is interrupted" can be understood as the light emission control signal being supplied to a logic level that turns off the transistor controlled by it.

[0082] The light-emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be placed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted via the j-th data line DLj is reflected in the voltage of the third node N3, the fifth and sixth transistors T5 and T6 can be turned on when the first light-emitting control signal applied to the first sub-light-emitting control line SEL1 and the second light-emitting control signal applied to the second sub-light-emitting control line SEL2 are enabled to a high voltage level.

[0083] Furthermore, the first transistor T1 can be turned on in response to the voltage at the third node N3, thereby allowing current to flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light-emitting element LD can emit light in response to the amount of current flowing through it.

[0084] Figure 4 is a conceptual diagram illustrating the driving operation of the display device shown in Figure 1, Figure 5 is a timing diagram showing an example of the display device shown in Figure 1 performing a display scan operation, and Figure 6 is a timing diagram showing an example of the display device shown in Figure 1 performing a self-scan operation.

[0085] Referring to Figures 1 and 4, a single frame can include a display scan section or a self-scan section.

[0086] During the display scan section (DISPLAY SCAN), a display scan operation is performed in which the data voltage VDATA is written. During the self scan section (SELF SCAN), a self scan operation can be performed in which the light-emitting element illuminates without writing the data voltage VDATA.

[0087] At the maximum drive frequency of the display panel 110 (for example, when the drive frequency is 240Hz), the display scan section DISPLAY SCAN can be continuously repeated for one frame.

[0088] At drive frequencies other than the maximum drive frequency of the display panel 110 (i.e., assuming the maximum drive frequency is 240 Hz in Figure 4) (i.e., 120 Hz, 80 Hz, 60 Hz, 48 Hz), one frame may contain a display scan section (DISPLAY SCAN) and at least one frame may contain a self-scan section (SELF SCAN).

[0089] Specifically, when the drive frequency is 120Hz, the display scan section (DISPLAY SCAN) and the self scan section (SELF SCAN) of one frame are repeated, and the display scan section (DISPLAY SCAN) and the self scan section (SELF SCAN) of one frame constitute one drive frame (i.e., the same image can be displayed for the duration of one drive frame).

[0090] When the drive frequency is 80Hz, a display scan section of one frame and a self-scan section of two frames are repeated, and a display scan section of one frame and a self-scan section of two frames can constitute a single drive frame.

[0091] When the drive frequency is 60Hz, a display scan section of one frame and a self-scan section of three frames are repeated, and a display scan section of one frame and a self-scan section of three frames can constitute a single drive frame.

[0092] When the drive frequency is 48Hz, a display scan section of one frame and a self-scan section of four frames are repeated, and a display scan section of one frame and a self-scan section of four frames can constitute a single drive frame.

[0093] In this way, the drive control unit 200 can vary the drive frequency by adjusting the length of the self-scan section (SELF SCAN).

[0094] Referring to Figure 5, a frame containing a display scan interval (DISPLAY SCAN) can include a non-emission interval (NEP) and an emission interval (EP).

[0095] The non-emitting period NEP may include the first initialization period IP1, the compensation period CP, the data writing period WP, ​​and the second initialization period IP2.

[0096] The first initialization period IP1 may be the period for initializing the first capacitor C1. The compensation period CP may be the period for compensating the threshold voltage of the first transistor T1. The data writing period WP may be the period for storing the voltage of the data signal in the sub-pixel SPij. The second initialization period IP2 may be the period for initializing the light-emitting element LD.

[0097] During the first initialization period IP1, the second subgate signal GR may be supplied to the second subgate line SGL2, the third subgate signal GI to the third subgate line SGL3, and the second sublight emission control signal EMB to the second sublight emission control line SEL2. The first subgate signal GW may not be supplied to the first subgate line SGL1, and the first sublight emission control signal EM may not be supplied to the first sublight emission control line SEL1.

[0098] If the first sub-light emission control signal EM is not supplied to the first sub-light emission control line SEL1, the fifth transistor T5 can be turned off. When the fifth transistor T5 is turned off, the electrical connection between the first power supply voltage node VDDN and the first transistor T1 is interrupted, thereby setting the light-emitting element LD to a non-light-emitting state.

[0099] When the second subgate signal GR is supplied to the second subgate line SGL2, the third transistor T3 is turned on. When the third transistor T3 is turned on, a reference voltage is supplied to the third node N3.

[0100] When the third subgate signal GI is supplied to the third subgate line SGL3, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, an initialization voltage can be supplied to the fourth node N4. In other words, the third subgate signal GI can control the timing of the initialization of the fourth node N4.

[0101] When the second sub-light emission control signal EMB is supplied to the second sub-light emission control line SEL2, the sixth transistor T6 is turned on. When the sixth transistor T6 is turned on, the initialization voltage of the fourth node N4 can be supplied to the second node N2.

[0102] When a reference voltage is supplied to the third node N3 and an initialization voltage is supplied to the second node N2, the first capacitor C1 and the second capacitor C2 can be initialized. That is, the first initialization period IP1 can be a period for initializing sub-pixels SPij so as not to be affected by the data signals supplied in the previous frame period.

[0103] During the compensation period CP, the second subgate signal GR can be supplied to the second subgate line SGL2, and the third subgate signal GI can be supplied to the third subgate line SGL3. In addition, the supply of the second sublight emission control signal EMB to the second sublight emission control line SEL2 is interrupted, and the first sublight emission control signal EM can be supplied to the first sublight emission control line SEL1.

[0104] If the supply of the second sub-light emission control signal EMB to the second sub-light emission control line SEL2 is interrupted, the sixth transistor T6 can be turned off. When the sixth transistor T6 is turned off, the electrical connection between the second power supply voltage node VSSN and the first transistor T1 is severed, thereby setting the light-emitting element LD to a non-light-emitting state.

[0105] When the first sub-light emission control signal EM is supplied to the first sub-light emission control line SEL1, the fifth transistor T5 can be turned on. When the fifth transistor T5 is turned on, the first power supply voltage can be supplied to the first node N1.

[0106] When the second subgate signal GR is supplied to the second subgate line SGL2, the third transistor T3 is turned on. When the third transistor T3 is turned on, a reference voltage is supplied to the third node N3.

[0107] Here, the reference voltage is set so that the first transistor T1 can be turned on, thereby allowing the voltage at the second node N2 to be raised in accordance with the current supplied by the first transistor T1. The voltage at the second node N2 can be raised to a value obtained by subtracting the absolute threshold voltage of the first transistor T1 from the reference voltage. That is, during the compensation period CP, the first capacitor C1 can store a voltage corresponding to the threshold voltage of the first transistor T1.

[0108] When the third subgate signal GI is supplied to the third subgate line SGL3, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, an initialization voltage can be supplied to the fourth node N4.

[0109] During the data writing period WP, ​​the first subgate signal GW can be supplied to the first subgate line SGL1 and the third subgate signal GI can be supplied to the third subgate line SGL3. In addition, the supply of the second subgate signal GR to the second subgate line SGL2 can be interrupted, and the supply of the first sublight emission control signal EM to the first sublight emission control line SEL1 can be interrupted.

[0110] When the supply of the first sub-light emission control signal EM and the second sub-light emission control signal EMB is interrupted, the fifth and sixth transistors T5 and T6 can be turned off. This disconnects the electrical connection between the first power supply voltage node VDDN and the second power supply voltage node VSSN and the first transistor T1, thereby setting the light-emitting element LD to a non-light-emitting state.

[0111] When the first subgate signal GW is supplied to the first subgate line SGL1, the second transistor T2 is turned on. When the second transistor T2 is turned on, the data voltage from the data line DLj can be supplied to the third node N3.

[0112] This allows a data voltage to be written to the first capacitor C1. At this time, the data voltage written to the first capacitor C1 is a voltage that reflects the decrease in the threshold voltage of the first transistor T1.

[0113] During the second initialization period IP2, the supply of the first light emission control signal GW to the first subgate line SGL1 may be interrupted, while the supply of the third light emission control signal GI to the third subgate line SGL3 may be maintained.

[0114] When the third subgate signal GI is supplied to the third subgate line SGL3, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, an initialization voltage can be supplied to the fourth node N4. When the initialization voltage is supplied to the fourth node N4, the anode electrode AE ​​of the light-emitting element LD (or the parasitic capacitor of the light-emitting element LD) can be initialized to the initialization voltage.

[0115] During the light emission period EP, a first sub-light emission control signal EM can be supplied to the first sub-light emission control line SEL1, and a second sub-light emission control signal EMB can be supplied to the second sub-light emission control line SEL2.

[0116] When the first sub-light control signal EM is supplied, the fifth transistor T5 can be turned on. This allows the first power supply voltage node VDDN and the first transistor T1 to be electrically connected.

[0117] At this time, the first transistor T1 can supply a drive current corresponding to the voltage at the third node N3 from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN. As a result, during the light emission period EP, the light-emitting element LD can generate light with a brightness corresponding to the drive current.

[0118] Referring to Figure 5, the third subgate signal GI can be supplied to the third subgate line SGL3 during the first period P1 between the first time point t1 and the second time point t2.

[0119] Referring to Figure 6, a frame containing a self-scan interval (SELF SCAN) can include a non-emission interval (NEP) and an emission interval (EP).

[0120] The non-emitting period NEP may include a second period P2 in which the third subgate signal GI is supplied to the third subgate line SGL3.

[0121] During the non-emitting period NEP, the second sub-emitting control signal EMB can be supplied to the second sub-emitting control line SEL2. When the second sub-emitting control signal EMB is supplied to the second sub-emitting control line SEL2, the second node N2 and the fourth node N4 can be connected as the sixth transistor T6 is turned on.

[0122] During the non-emission period NEP, the first sub-emission control signal EM may not be supplied to the first sub-emission control line SEL1, the first sub-gate signal GW may not be supplied to the first sub-gate line SGL1, and the second sub-gate signal GR may not be supplied to the second sub-gate line SGL2.

[0123] If the first sub-light emission control signal EM is not supplied to the first sub-light emission control line SEL1, the fifth transistor T5 can be turned off. When the fifth transistor T5 is turned off, the electrical connection between the first power supply voltage node VDDN and the first transistor T1 is interrupted, thereby setting the light-emitting element LD to a non-light-emitting state.

[0124] During the second period PL2 between the third time point t3 and the second time point t2, the third subgate signal GI can be supplied to the third subgate line SGL3. When the third subgate signal GI is supplied to the third subgate line SGL3, the fourth transistor T4 is turned on, thereby initializing the anode electrode AE ​​of the light-emitting element LD to the initialization voltage.

[0125] During the light emission period EP, a first sub-light emission control signal EM can be supplied to the first sub-light emission control line SEL1, and a second sub-light emission control signal EMB can be supplied to the second sub-light emission control line SEL2.

[0126] When the first sub-light control signal EM is supplied, the fifth transistor T5 can be turned on. This allows the first power supply voltage node VDDN and the first transistor T1 to be electrically connected.

[0127] At this time, the first transistor T1 can supply a drive current corresponding to the voltage at the third node N3 from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN. As a result, during the light emission period EP, the light-emitting element LD can generate light with a brightness corresponding to the drive current.

[0128] During the self-scan section, the subgate signals GW and GR that control the second and third transistors T2 and T3, which affect the voltage level of the gate electrode of the first transistor T1, are kept in a low-level, inactive state. In other words, the supply of the first subgate signal GW and the second subgate signal GR is interrupted during the self-scan section.

[0129] Furthermore, during the self-scan interval (SELF SCAN), the third subgate signal GI, which controls the fourth transistor T4, can be activated to initialize the anode electrode AE ​​of the light-emitting element LD.

[0130] Thus, during the self-scan section (SELF SCAN), in order to initialize the anode electrode AE ​​of the light-emitting element LD, only the third subgate signal GI can be supplied from the first to third subgate signals GW, GR, and GI.

[0131] This ensures that the data voltage written to the first capacitor C1 remains constant during the self-scan interval (SELF SCAN). Therefore, the sub-pixel SPij can display the same image during the display scan interval (DISPLAY SCAN) and the self-scan interval (SELF SCAN) based on the data voltage supplied during the data writing period (WP).

[0132] Referring to Figure 6, the third subgate signal GI can be supplied to the third subgate line SGL3 during the second period P2 between the third time point t3 and the second time point t2.

[0133] During the self-scan section, the third subgate signal GI is supplied during the second period P2, and during the display scan section in Figure 5, the third subgate signal GI can be supplied during the first period P1.

[0134] In other words, the length of time during which the third subgate signal GI is supplied during the self-scan interval (SELF SCAN) can differ from the length of time during which the third subgate signal GI is supplied during the display scan interval (DISPLAY SCAN).

[0135] For example, the length of the second period P2 during which the third subgate signal GI is supplied during the self-scan section (SELF SCAN) can be shorter than the length of the first period P1 during which the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN). More detailed embodiments of this will be described later with reference to Figures 8 to 11.

[0136] During the self-scan section, the period for which the third subgate signal GI is supplied differs from the period for which the third subgate signal GI is supplied during the display scan section. This prevents the phenomenon in which patterns displayed in one area of ​​the display panel are copied and displayed unevenly in other areas.

[0137] Figure 7 illustrates the phenomenon in which a pattern displayed in one area of ​​a display panel is copied and displayed in other areas.

[0138] Referring to Figure 7, we can see the first region A1 where the pattern is displayed and the second region A2 where unevenness has occurred due to the pattern in the first region A1.

[0139] The following explanation, shown in Figure 7, describes a case where the display device drives the display panel in two cycles and displays a pattern with a large difference in grayscale between adjacent areas in the first area A1. Here, two-cycle driving means that the two areas of the display panel display different subframes. However, this disclosure is not limited to the example shown herein, and the display device may drive the display panel in more than two cycles.

[0140] The difference between the tonal range of the first region A1 and the tonal range of a region different from the first region A1 can be greater than the reference tone. The reference tone can have a pre-set value. For example, the tonal difference between the first region A1 and a region adjacent to it can be greater than the reference tone.

[0141] For example, as shown in Figure 3, if the first transistor T1 is an N-type transistor, the lower the grayscale level, the smaller the data voltage VDATA corresponding to the grayscale level can be.

[0142] For the sake of explanation, as shown in Figure 7, we assume that the gradation of the first region A1 is lower than that of regions other than the first region A1. In this case, the data voltage VDATA may increase at the end of the first region A1. Furthermore, as the data voltage VDATA increases, the voltage of the anode electrode AE ​​of the light-emitting element LD may increase due to coupling by a parasitic capacitor between the anode electrode AE ​​and the data line DLj. For example, some of the subpixels of the second region A2 are connected to the data line DLj along with the subpixels of the first region A1, and the voltage of the anode electrode AE ​​of the light-emitting element LD of the subpixels of the second region A2 can increase as the data voltage VDATA increases. As the voltage of the anode electrode AE ​​of the light-emitting element LD increases, the voltage difference between the anode electrode AE ​​and the cathode electrode CE of the light-emitting element LD increases, which causes the subpixels of the second region A2 to emit unintended light. In this way, the pattern of the first region A1 may cause unintended images, such as unevenness, to appear in the second region A2.

[0143] The voltage coupling between the anode electrode AE ​​and the data line DLj, as described above, allows the first region A1 to induce grayscale changes in the second region A2 in various aspects. When a display scan operation (see Figure 5) is performed on a sub-pixel SP (hereinafter referred to as a sub-pixel row) of a row corresponding to the second region A2, a self-scan operation (see Figure 6) can be performed on the sub-pixel row corresponding to the first region A1. In other words, the display scan operation on a sub-pixel row corresponding to the second region A2 can be temporally superimposed on the self-scan operation on a sub-pixel row corresponding to the first region A1. In such a case, a third sub-gate signal GI is supplied to the sub-pixel row corresponding to the first region A1, thereby supplying the initialization voltage of the initialization voltage node VINTN to the anode electrode AE ​​of the corresponding sub-pixel. The third sub-gate signal GI is also supplied to the sub-pixel row corresponding to the second region A2, thereby supplying the initialization voltage of the initialization voltage node VINTN to the anode electrode AE ​​of the corresponding sub-pixel.

[0144] Voltage coupling between the anode electrode AE ​​and the data line DLj can cause a change in the voltage of the anode electrode AE ​​to trigger a change in the data voltage VDATA of the data line DLj. In response to the supply of the third subgate signal GI, the voltage of the anode electrode AE ​​of a subpixel corresponding to the first region A1 can change from the voltage corresponding to the grayscale emitted during the previous display scan operation of that subpixel to the initialization voltage of the initialization voltage node VINTN. Voltage changes in the anode electrode AE ​​of a subpixel in the first region A1 can cause an undesirable change in the data voltage VDATA due to voltage coupling between the anode electrode AE ​​and the data line DLj. The changed data voltage VDATA can be supplied to a subpixel in the second region A2 where the display scan operation is performed, thereby causing the corresponding subpixel in the second region A2 to display an undesirable grayscale. Thus, the grayscale of the first region A1 can affect the grayscale of the second region A2, thereby causing unevenness in the second region A2 to be displayed in the second region A2 that is associated with the first region A1.

[0145] To prevent this phenomenon, the duration for which the third subgate signal GI is supplied in the self-scan section (SELF SCAN) can be reduced, as explained in Figure 6. This reduces the voltage change of the anode electrode AE ​​of the subpixels in the first region A1, and prevents or at least reduces the change in the data voltage VDATA of the data line DLj. Thus, the second region A2 can display the desired image.

[0146] Furthermore, the duration for which the third subgate signal GI is supplied during the display scan interval (DISPLAY SCAN) can be reduced. This reduces the voltage change of the anode electrode AE ​​of the subpixels in the second region A2, and reduces the change in the data voltage VDATA of the data line DLj. Thus, the second region A2 can display the desired image.

[0147] As described in Figure 6, the period during which the third subgate signal GI is supplied during the self-scan section (SELF SCAN) and the period during which the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN) can be set to be different. Various embodiments of the third subgate signal GI supplied during the display scan section (DISPLAY SCAN) and the self-scan section (SELF SCAN) are described below.

[0148] Figures 8 to 11 are timing diagrams showing one embodiment of the third subgate signal supplied to the display scan section and the self-scan section.

[0149] Referring to Figure 8, during the display scan section (DISPLAY SCAN), the third subgate signal GI is supplied during the first period P1, and during the self scan section (SELF SCAN), the third subgate signal GI is supplied during the second period P2.

[0150] The non-luminescence period can be the period between the fifth time point t5 and the sixth time point t6. The first period P1 can be the period between the first time point t1 and the second time point t2. The second period P2 can be the period between the third time point t3 and the second time point t2.

[0151] In Figure 8, for illustrative purposes, the first period P1 and the second period P2 are shown to be included in the same non-emission period NEP. However, in one embodiment of the present invention, the non-emission periods NEP in which the first period P1 and the second period P2 are included may be different from each other. For example, the non-emission period NEP in which the first period P1 is included may precede the non-emission period NEP in which the second period P2 is included.

[0152] The second period P2 during which the third subgate signal GI is supplied during the self-scan section can be shorter than the first period P1 during which the third subgate signal GI is supplied during the display scan section.

[0153] The start time t1 of the first period P1 can be earlier than the start time t3 of the second period P2. That is, the length of period P3 between the start time t1 of the first period P1 and the start time t5 of the non-emission period can be shorter than the length of period P4 between the start time t3 of the second period P2 and the start time t5 of the non-emission period.

[0154] The end time t2 of the first period P1 can be the same as the end time t2 of the second period P2. That is, the length of period P5 between the end time t2 of the first period P1 and the end time t6 of the non-emission period that includes the first period P1 can be the same as the length of period P6 between the end time t2 of the second period P2 and the end time t6 of the non-emission period that includes the second period P2.

[0155] Referring to Figure 9, during the display scan section (DISPLAY SCAN), the third subgate signal GI is supplied during the first period P1, and during the self scan section (SELF SCAN), the third subgate signal GI is supplied during the second period P2.

[0156] The non-luminescence period can be the period between the fifth time point t5 and the sixth time point t6. The first period P1 can be the period between the first time point t1 and the second time point t2. The second period P2 can be the period between the third time point t3 and the second time point t2.

[0157] In Figure 9, for illustrative purposes, the first period P1 and the second period P2 are shown to be included in the same non-emission period NEP. However, in one embodiment of the present invention, the non-emission periods NEP in which the first period P1 and the second period P2 are included may be different from each other. For example, the non-emission period NEP in which the first period P1 is included may precede the non-emission period NEP in which the second period P2 is included.

[0158] During the self-scan section, the second period P2 in which the third subgate signal GI is supplied can be longer than the first period P1 in which the third subgate signal GI is supplied during the display scan section.

[0159] The start time t1 of the first period P1 can be later than the start time t3 of the second period P2. That is, the length of period P3 between the start time t1 of the first period P1 and the start time t5 of the non-emission period can be longer than the length of period P4 between the start time t3 of the second period P2 and the start time t5 of the non-emission period.

[0160] The end time t2 of the first period P1 can be the same as the end time t2 of the second period P2. That is, the length of period P5 between the end time t2 of the first period P1 and the end time t6 of the non-emission period that includes the first period P1 can be the same as the length of period P6 between the end time t2 of the second period P2 and the end time t6 of the non-emission period that includes the second period P2.

[0161] As explained in Figures 8 and 9, the phenomenon described in Figure 7 can be prevented by having a different period during which the third subgate signal GI is supplied during the self-scan section (SELF SCAN) and the display scan section (DISPLAY SCAN).

[0162] Referring to Figure 10, during the display scan section, the third subgate signal GI is supplied during the first period P1, and during the self scan section, the third subgate signal GI is supplied during the seventh period P7 and the eighth period P8.

[0163] The non-luminescence period can be the period between the 5th time point t5 and the 6th time point t6. The 1st period P1 can be the period between the 1st time point t1 and the 2nd time point t2. The 7th period P7 can be the period between the 1st time point t1 and the 7th time point t7. The 8th period P8 can be the period between the 8th time point t8 and the 2nd time point t2.

[0164] In Figure 10, for illustrative purposes, the first period P1, the seventh period P7, and the eighth period P8 are shown to be included in the same non-emission period NEP. However, in one embodiment of the present invention, the non-emission periods NEP in which the first period P1, the seventh period P7, and the eighth period P8 are included may be different from each other. For example, the non-emission period NEP in which the first period P1 is included may precede the non-emission periods NEP in which the seventh period P7 and the eighth period P8 are included.

[0165] The number of times the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN) may differ from the number of times the third subgate signal GI is supplied during the self scan section (SELF SCAN).

[0166] In one embodiment of the present invention, the number of times the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN) can be less than the number of times the third subgate signal GI is supplied during the self scan section (SELF SCAN).

[0167] For example, during the display scan interval (DISPLAY SCAN), the third subgate signal GI may be supplied once, and during the self scan interval (SELF SCAN), the third subgate signal GI may be supplied twice.

[0168] Referring to Figure 10, the number of toggles of the third subgate signal GI during the display scan interval (DISPLAY SCAN) can differ from the number of toggles of the third subgate signal GI during the self scan interval (SELF SCAN). The number of toggles can refer to the number of times the logic level of the signal changes.

[0169] For example, during the display scan section, the third subgate signal GI is toggled at the first time point t1 and the second time point t2, so the number of toggles is 2. On the other hand, during the self scan section, the third subgate signal GI is toggled at the first time point t1, the seventh time point t7, the eighth time point t8, and the second time point t2, so the number of toggles is 4.

[0170] The start time t1 of the first period P1 can be the same as the start time t1 of the seventh period P7. Also, the first toggle time t1 of the third subgate signal GI in the display scan section can be the same as the first toggle time t1 of the third subgate signal GI in the self scan section.

[0171] In other words, the length of period P3 between the start time t1 of the first period P1 and the start time t5 of the non-luminescent period in which the first period P1 is included can be the same as the length of period P4 between the start time t1 of the seventh period P7 and the start time t5 of the non-luminescent period in which the seventh period P7 is included.

[0172] The end time t2 of the first period P1 can be the same as the end time t2 of the eighth period P8. Also, the last toggle time t2 of the third subgate signal GI in the display scan section DISPLAY SCAN can be the same as the last toggle time t2 of the third subgate signal GI in the self scan section SELF SCAN.

[0173] In other words, the length of period P5 between the end time t2 of the first period P1 and the end time t6 of the non-luminescent period that includes the first period P1 can be the same as the length of period P6 between the end time t2 of the eighth period P8 and the end time t6 of the non-luminescent period that includes the eighth period P8.

[0174] The lengths of the seventh period P7 and the eighth period P8 can be freely set, as long as the sum of their lengths is less than the length of the first period P1. For example, the lengths of the seventh period P7 and the eighth period P8 may be the same or different.

[0175] Furthermore, while Figure 10 illustrates that the third subgate signal GI is supplied once during the display scan section (DISPLAY SCAN) and twice during the self scan section (SELF SCAN), this disclosure is not limited to the examples shown herein.

[0176] Referring to Figure 11, during the display scan section, the third subgate signal GI is supplied between the seventh period P7 and the eighth period P8, and during the self scan section, the third subgate signal GI is supplied during the first period P1.

[0177] The non-luminescence period can be the period between the 5th time point t5 and the 6th time point t6. The 1st period P1 can be the period between the 1st time point t1 and the 2nd time point t2. The 7th period P7 can be the period between the 1st time point t1 and the 7th time point t7. The 8th period P8 can be the period between the 8th time point t8 and the 2nd time point t2.

[0178] In Figure 11, for illustrative purposes, the first period P1, the seventh period P7, and the eighth period P8 are shown to be included in the same non-emission period NEP. However, in one embodiment of the present invention, the non-emission periods NEP in which the first period P1, the seventh period P7, and the eighth period P8 are included may be different from each other. For example, the non-emission period NEP in which the first period P1 is included may occur after the non-emission periods NEP in which the seventh period P7 and the eighth period P8 are included.

[0179] The number of times the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN) may differ from the number of times the third subgate signal GI is supplied during the self scan section (SELF SCAN).

[0180] In one embodiment of the present invention, the number of times the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN) can be greater than the number of times the third subgate signal GI is supplied during the self scan section (SELF SCAN).

[0181] For example, during the display scan interval (DISPLAY SCAN), the third subgate signal GI may be supplied twice, and during the self-scan interval (SELF SCAN), the third subgate signal GI may be supplied once.

[0182] During the display scan section, the number of toggles of the third subgate signal GI may differ from the number of toggles of the third subgate signal GI during the self scan section. The number of toggles can refer to the number of times the logic level of the signal changes.

[0183] For example, during the display scan section, the third subgate signal GI is toggled at the first time point t1, the seventh time point t7, the eighth time point t8, and the second time point t2, so there are four toggles. On the other hand, during the self scan section, the third subgate signal GI is toggled at the first time point t1 and the second time point t2, so there are two toggles.

[0184] The start time t1 of the first period P1 can be the same as the start time t1 of the seventh period P7. Also, the first toggle time t1 of the third subgate signal GI in the display scan section can be the same as the first toggle time t1 of the third subgate signal GI in the self scan section.

[0185] In other words, the length of period P3 between the start time t1 of the first period P1 and the start time t5 of the non-luminescent period in which the first period P1 is included can be the same as the length of period P4 between the start time t1 of the seventh period P7 and the start time t5 of the non-luminescent period in which the seventh period P7 is included.

[0186] The end time t2 of the first period P1 can be the same as the end time t2 of the eighth period P8. Also, the last toggle time t2 of the third subgate signal GI in the display scan section DISPLAY SCAN can be the same as the last toggle time t2 of the third subgate signal GI in the self scan section SELF SCAN.

[0187] In other words, the length of period P5 between the end time t2 of the first period P1 and the end time t6 of the non-luminescent period that includes the first period P1 can be the same as the length of period P6 between the end time t2 of the eighth period P8 and the end time t6 of the non-luminescent period that includes the eighth period P8.

[0188] Furthermore, while Figure 11 illustrates that the third subgate signal GI is supplied twice during the display scan section (DISPLAY SCAN) and once during the self-scan section (SELF SCAN), this disclosure is not limited to the examples shown herein.

[0189] As explained in Figures 10 and 11, the phenomenon described in Figure 7 can be prevented by having a different number of times the third subgate signal GI is supplied during the self-scan section (SELF SCAN) and the number of times the third subgate signal GI is supplied during the display scan section (DISPLAY SCAN).

[0190] Figure 12 is a block diagram showing an electronic device according to one embodiment of the present invention, and Figure 13 is a diagram showing an example in which the electronic device of Figure 12 is realized as a smartphone.

[0191] Referring to Figures 12 and 13, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply device 1050, and a display device 1060. In this case, the display device 1060 may be the display device shown in Figure 1. The electronic device 1000 may also further include various ports that can communicate with video cards, sound cards, memory cards, USB devices, etc., or with other systems. In one embodiment of the present invention, as shown in Figure 13, the electronic device 1000 can be implemented as a smartphone. However, this is illustrative, and the electronic device 1000 is not limited to the examples shown herein. For example, the electronic device 1000 may be implemented as a mobile phone, video phone, smart pad, smartwatch, tablet PC, vehicle navigation system, computer monitor, notebook computer, head-mounted display device, etc.

[0192] The processor 1010 can perform specific calculations or tasks. According to one embodiment of the present invention, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. According to one embodiment of the present invention, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0193] The display device 1060 can display images on pixels according to the control of the processor 1010. In one embodiment of the present invention, the processor 1010 can generate the image data IMG shown in Figure 1 and the control signal CTRL for controlling its display.

[0194] The memory device 1020 can store data necessary for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as EPROM (Erasable Programmable Read-Only Memory) devices, EEPROM (Electrically Erasable Programmable Read-Only Memory) devices, flash memory devices, PRAM (Phase Change Random Access Memory) devices, RRAM (Resistance Random Access Memory) devices, NFGM (Nano Floating Gate Memory) devices, PoRAM (Polymer Random Access Memory) devices, MRAM (Magnetic Random Access Memory), FRAM® (Ferroelectric Random Access Memory) devices, and / or volatile memory devices such as DRAM (Dynamic Random Access Memory) devices, SRAM (Static Random Access Memory) devices, and mobile DRAM devices.

[0195] The storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0196] The input / output device 1040 may include input means such as a keyboard, keypad, touchpad, touchscreen, or mouse, and output means such as a speaker or printer. According to one embodiment of the present invention, a display device 1060 may also be included in the input / output device 1040.

[0197] The power supply device 1050 can supply the power necessary for the operation of the electronic device 1000. For example, the power supply device 1050 may be a power management integrated circuit (PMIC).

[0198] The display device 1060 can display images corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 may be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited to the examples shown herein. The display device 1060 may be connected to other components via the bus or other communication links.

[0199] The scope of the present invention is not limited to what is described in the detailed description of the specification, but should be defined by the claims. The meaning and scope of the claims, and all modifications or alterations derived from the concept of equivalents thereof, should be interpreted as being included within the scope of the present invention. [Explanation of symbols]

[0200] 100 display device 110 Display Panel 120 Gate Driver 130 Data Drivers 140 Voltage Generator 150 controllers 160 Temperature Sensor

Claims

1. A data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line are connected to a subpixel including a light-emitting element, A gate driver that supplies a first sub-light emission control signal to the first sub-light emission control line, and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line, Includes a data driver that supplies data voltage to the data line, During the display scan interval, the length of the period during which the second subgate signal is supplied differs from the length of the period during the self-scan interval. The second subgate signal is a display device that controls the timing for initializing one electrode of the light-emitting element.

2. The aforementioned subpixel is, A first transistor is connected between a first node and a second node that receive a first power supply voltage, and includes a gate electrode connected to a third node, which generates a drive current. A second transistor is connected between the data line and the third node and includes a gate electrode connected to the first subgate line, A third transistor, which includes a gate electrode connected between the second node and the fourth node and connected to the first sub-light emission control line, A fourth transistor is connected between the node providing the initialization voltage and the fourth node and includes a gate electrode connected to the second subgate line, The display device according to claim 1, wherein the light-emitting element is connected between the fourth node and the node that receives the second power supply voltage.

3. During the display scan interval, the gate driver supplies the second subgate signal during the first period. The display device according to claim 2, wherein the gate driver supplies the second subgate signal during the second period during the self-scan interval.

4. The display device according to claim 3, wherein the length of the first period is longer than the length of the second period.

5. The display device according to claim 3, wherein the length of the first period is shorter than the length of the second period.

6. A data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line are connected to a subpixel including a light-emitting element, A gate driver that supplies a first sub-light emission control signal to the first sub-light emission control line, and supplies a first sub-gate signal to the first sub-gate line and a second sub-gate signal to the second sub-gate line, Includes a data driver that supplies data voltage to the data line, The number of times the second subgate signal is supplied during the display scan interval is different from the number of times the second subgate signal is supplied during the self-scan interval. The second subgate signal is a display device that controls the timing for initializing one electrode of the light-emitting element.

7. The aforementioned subpixel is, A first transistor is connected between a first node and a second node that receive a first power supply voltage, and includes a gate electrode connected to a third node, which generates a drive current. A second transistor is connected between the data line and the third node and includes a gate electrode connected to the first subgate line, A third transistor, which includes a gate electrode connected between the second node and the fourth node and connected to the first sub-light emission control line, A fourth transistor is connected between the node providing the initialization voltage and the fourth node and includes a gate electrode connected to the second subgate line, The display device according to claim 6, wherein the light-emitting element is connected between the fourth node and the node that receives the second power supply voltage.

8. The display device according to claim 7, wherein the number of times the gate driver supplies the second subgate signal during the display scan interval is less than the number of times the gate driver supplies the second subgate signal during the self-scan interval.

9. The display device according to claim 7, wherein the number of toggles of the second subgate signal during the display scan interval is less than the number of toggles of the second subgate signal during the self scan interval.

10. The display device according to claim 9, wherein the number of toggles is the number of times the logic level of the second subgate signal changes.

Images