Semiconductor device and data storage system including the same

Abstract

We provide semiconductor devices that enable highly reliable quality inspection. [Solution] The semiconductor device 10 includes a first semiconductor structure S1 including a first substrate 101, a circuit element 120, a lower wiring structure 130 and a lower bonding structure 180; a laminated structure GS1, GS2 including an upper bonding structure 280, conductive layers 201, 202, a laminated interlayer insulating layer 220 and a gate electrode 230; and a second semiconductor structure S2 including a separation region that penetrates the laminated structure and extends in the X direction perpendicular to the Z direction and is separated from each other in the Y direction perpendicular to the Z and X directions, a channel structure CH that penetrates the laminated structure in the Z direction, an address stud 275 disposed below the separation region at a first separation distance along the X direction, a channel stud 272 disposed below the channel structure, and upper wiring structures 271, 273, 274 disposed below the laminated structure, connected to the channel stud and separated from the address stud.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a data storage system including the same.

Background Art

[0002] In a data storage system that requires data storage, a semiconductor device capable of storing a large amount of data is required. Accordingly, a scheme for increasing the data storage capacity of the semiconductor device has been studied. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor device capable of performing a highly reliable quality inspection.

[0004] Another object of the present invention is to provide a data storage system including a semiconductor device capable of performing a highly reliable operation error inspection.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present invention made to achieve the above objective includes a first semiconductor structure comprising a first substrate, a circuit element on the first substrate, a lower wiring structure electrically connected to the circuit element, and a lower bonding structure connected to the lower wiring structure, and a second semiconductor structure comprising an upper bonding structure bonded to the lower bonding structure on the first semiconductor structure, wherein the second semiconductor structure comprises a conductive layer and a laminated structure below the conductive layer, comprising an interlayer insulating layer and a gate electrode laminated in a first direction perpendicular to the upper surface of the conductive layer. The structure includes: a separation region that penetrates the laminated structure and extends in a second direction perpendicular to the first direction, and is separated from each other in a third direction perpendicular to the first and second directions; a channel structure that includes a channel layer and penetrates the laminated structure in the first direction; an address stud disposed below at least one of the separation regions at a first separation distance along the second direction; a channel stud disposed below the channel structure; and an upper wiring structure disposed below the laminated structure, connected to the channel stud, and separated from the address stud.

[0006] To achieve the above objective, another aspect of the present invention provides a semiconductor device comprising: a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure; and a second semiconductor structure including an upper bonding structure bonded to the lower bonding structure on the first semiconductor structure, wherein the second semiconductor structure comprises a conductive layer, a laminated structure including an interlayer insulating layer and a gate electrode laminated below the conductive layer in a first direction perpendicular to the upper surface of the conductive layer, and a channel layer. The structure includes a channel structure penetrating the stacked structure in the first direction; an address separation region penetrating the stacked structure, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first and second directions, and including a first address separation region and a second address separation region adjacent to the first address separation region in the third direction; address studs arranged below the first and second address separation regions at distances of 1 and r (where r is a natural number greater than or equal to 2) of the unit separation distance along the second direction; and a channel stud arranged below the channel structure.

[0007] A data storage system according to one aspect of the present invention, made to achieve the above objective, includes: a first semiconductor structure including a substrate and circuit elements on the substrate; a second semiconductor structure including a laminated structure including interlayer insulating layers and gate electrodes stacked in a first direction and a channel structure penetrating the laminated structure; a semiconductor storage device including input / output pads electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device via the input / output pads and controlling the semiconductor storage device, wherein the first semiconductor structure further includes a lower wiring structure electrically connected to the circuit elements and a lower bonding structure connected to the lower wiring structure. The second semiconductor structure includes an upper wiring structure disposed below the laminated structure, an upper bonding structure connected to the upper wiring structure and joined to the lower bonding structure, isolation regions penetrating the laminated structure and extending in a second direction perpendicular to the first direction and separated from each other in a third direction perpendicular to the first and second directions, address studs disposed at a first separation distance along the second direction below at least one of the isolation regions, and channel studs disposed below the channel structure, wherein the upper wiring structure is connected to the channel studs and separated from the address studs. [Effects of the Invention]

[0008] In a structure where two or more semiconductor structures are joined together, when performing operational error testing, the joined structure is cut again and an image is taken to confirm the location of the error point. At this time, the cell structure imaged from the cut surface captures repeating circuit patterns, such as bit lines and channel structure studs, making it difficult to pinpoint the location of the error point. Therefore, according to the present invention, by arranging address studs for identifying the location of the error point according to a predetermined rule, the location of the error point can be calculated according to the arrangement of the address studs.

[0009] Furthermore, according to the present invention, by arranging the address studs on the isolation region, they can be positioned in a location clearly distinct from the studs on the channel structure, and can be used as an indicator of the error point location through various arrangements. In addition, by regularly changing the arrangement of the address studs according to the position of the isolation region, the block address can also be confirmed.

[0010] Therefore, according to the present invention, a highly reliable semiconductor device and a data storage system including the same can be provided by improved error checking reliability.

[0011] The diverse yet beneficial advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic plan view of a semiconductor device according to an exemplary embodiment. [Figure 2] This is a partially enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 3] This is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment. [Figure 4a] This is an enlarged cross-sectional view of a portion of Figure 3. [Figure 4b] This is an enlarged cross-sectional view of a portion of Figure 3. [Figure 5] This is an enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 6] This is an enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 7] This is an enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 8] This is a plan view of a semiconductor device according to an exemplary embodiment. [Figure 9] This is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment. [Figure 10] This is a schematic partial enlargement view of a semiconductor device according to an exemplary embodiment. [Figure 11] It is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 12] It is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 13] It is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment. [Figure 14a] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14b] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14c] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14d] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14e] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14f] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14g] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15] It is a diagram schematically showing a data storage system including a semiconductor device according to an exemplary embodiment. [Figure 16] It is a perspective view schematically showing a data storage system including a semiconductor device according to an exemplary embodiment.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the drawings. Hereinafter, terms such as "upper", "upper part", "upper surface", "above", "lower", "lower part", "lower surface", "below", "side surface", etc. are represented by reference numerals and are referred to based on the drawings unless otherwise mentioned.

[0014] Below, a semiconductor device according to an exemplary embodiment will be described with reference to Figures 1 to 4b. Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment, and Figure 2 is an enlarged plan view of area "A" in Figure 1.

[0015] The semiconductor device 10 includes a first semiconductor structure S1 and a second semiconductor structure S2, wherein the first semiconductor structure S1 is stacked in the Z direction, which is perpendicular to the second semiconductor structure S2. Specifically, the first semiconductor structure S1 is positioned below the second semiconductor structure S2 in the Z direction. In an exemplary embodiment, the opposite may be true, with the second semiconductor structure S2 positioned below the first semiconductor structure S1.

[0016] In an exemplary embodiment, the semiconductor device 10 includes a peripheral circuit structure which is a first semiconductor structure S1 on which a peripheral circuit region is formed, and a memory cell structure which is a second semiconductor structure S2 including a common source line CSL, on a first substrate 101.

[0017] The first semiconductor structure S1 forms peripheral circuits by forming transistors and metal patterns for wiring transistors on the first substrate 101. The second semiconductor structure S2 of the semiconductor device 10 includes a memory block BLK which is a collection of multiple channel structures CH.

[0018] The semiconductor device 10 includes a first region R1 along the X direction and a second region R2 on both sides of the first region R1.

[0019] The first region R1 is a memory cell region where memory cells are arranged, and is the region where the channel structure CH is arranged. The second region R2 corresponds to a region for electrically connecting the memory cell to the peripheral circuit structure PERI, and is a region in which the gate electrode layer 130 extends at different lengths, but is not limited to this.

[0020] Referring to Figure 1, edge regions EA are located on each side. The edge regions EA are located outside the second region R2, above and below the first region R1, and are areas where mold structures remain. The edge regions EA are defined as areas where externally connected pad regions are located, or where external contact vias connected to pad regions are located, or where various through vias connected to the first semiconductor structure S1 are located. The semiconductor device 10 is shown as having a frame shape with edge regions EA located on each side, but is not limited to this.

[0021] The semiconductor device 10 has isolation regions MS extending in the X direction within a first region R1 and a second region R2. The isolation regions MS are spaced apart from each other in the Y direction, and the first region R1 between adjacent isolation regions MS is defined as a single memory block BLK. The memory block BLK is used, but is not limited to, as the operating unit and signal application unit of the channel structure CH.

[0022] Multiple memory blocks BLK are arranged within a first region R1 of the semiconductor device 10, with tens to hundreds of memory blocks BLK being placed within the first region R1. Address studs 275 are placed corresponding to at least a portion of the isolation region MS that separates the memory blocks BLK.

[0023] The isolation region MS where the address stud 275 is located is defined as the address isolation region MSc. Address isolation region MSc is located every nth isolation region MS in the Y direction out of all isolation regions MS, and the nth, 2nth, 3nth, and so on isolation regions MS are defined as address isolation region MSc. The remaining isolation regions MS that are not address isolation region MSc are general isolation regions MSg, which are isolation regions MS where the address stud 275 is not located at the bottom.

[0024] Address isolation regions MSc are arranged in pairs, forming groups. That is, adjacent isolation regions MS located above and below a single memory block BLK are address isolation regions MSc. Specifically, n is a predetermined number such as 50 or 100. For example, when n is 50, the 50th and 51st address isolation regions MSc form one pair, and the 100th and 101st address isolation regions MSc form another pair.

[0025] The address studs 275, located on a pair of address isolation areas MSc, are arranged regularly according to an arrangement rule. The address studs 275 are arranged in two rows on the pair of address isolation areas MSc. One row of address studs 275 is arranged on each of the address isolation areas MSc that make up the pair of address isolation areas MSc.

[0026] In a pair of address isolation regions MSc, the address studs 275 in each row are arranged in different numbers. The first row has at least a number of address studs 275, and the second row has b-(a-1) number of address studs 275. Here, b is the number of stud positions n1, n2, n3, n4, n5 within the array group AG, which is the set of address studs 275 to which the array rule applies. Stud positions n1, n2, n3, n4, n5 are defined as positions separated by the same separation distance I1, for example, the sum of the pitches (multiples of the pitch) of a predetermined number (k) bit lines BL. Stud positions n1, n2, n3, n4, n5 are defined as the positions where the address studs 275 are arranged within the array group AG, and the same stud positions n1, n2, n3, n4, n5 are set for each row, aligned in the Y direction. Therefore, the address studs 275 are placed on the address isolation region MSc at intervals of an integer multiple of the separation distance (r, r=1, 2, 3, ...).

[0027] Preferably, k is 50, 100, etc. For example, when the number of stud positions n1, n2, n3, n4, n5 in the array group AG, b, is 5, then the number of address studs 275 in the first row, a, is 2, and the number of address studs 275 in the second row is 4.

[0028] The array group AG is repeatedly arranged along the extension direction (X direction) of the pair of address isolation regions MSc. The arrangement rule is the same for each array group AG, and the same array of address studs 275 following the same arrangement rule are repeatedly placed on the pair of address isolation regions MSc. The same arrangement rule can also be applied to other pairs of address isolation regions MSc.

[0029] As shown in Figures 1 and 2, when five stud positions (n1, n2, n3, n4, n5) are set in one row within one array group AG, the first row has address studs 275 at the first and second stud positions (n1, n2), and the second row has address studs 275 at the first, third, fourth, and fifth stud positions (n1, n3, n4, n5). That is, the stud position n2 of the second row has address stud 275 from the first row, and the distance between the starting address stud 275 of the second row and the next address stud 275 is a second separation distance I2, which is twice the first separation distance I1.

[0030] Specifically, the position where address stud 275 is placed in both rows is the first stud position n1, and address stud 275 placed in both rows is defined as the starting address stud 275. The position where address stud 275 is placed only in the first row is the second stud position n2, and the case where address stud 275 adjacent to stud position n2 in the second row is located in the second row is called the third stud position n3, the position of address stud 275 in the second row located to the left of the starting address stud 275 of adjacent array group AG2 is called the fifth position n5, and the position of stud 275 in the second row between the third and fifth stud positions n3 and n5 is called the fourth stud position n4. Furthermore, by regularly arranging the address isolation region MSc within the entire isolation region MS, the positions of the address isolation region MSc can be counted.

[0031] Therefore, during error checking, the arrangement of the address studs 275 and the location of the address isolation area MSc where the address studs 275 are located can be confirmed, and the location where the error occurred, i.e., the location of the error point, can be determined as to which memory block BLK in the Y direction and which bit line BL in the X direction.

[0032] In the following, exemplary embodiments of the present invention will be described in more detail with reference to Figures 2 to 4b.

[0033] Figure 2 is a partially enlarged view of a semiconductor device according to an exemplary embodiment, Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment, and Figures 4a and 4b are partially enlarged views of a semiconductor device according to an exemplary embodiment. Figure 2 is an enlarged view of portion "A" of Figure 1, and Figure 3 is a view of a cross-section along the cutting line I-I' of Figure 2. Figures 4a and 4b are enlarged views of portions "B" and "C" of Figure 3, respectively.

[0034] Referring to Figures 2 to 4b, the semiconductor device 10 includes a first semiconductor structure S1 defined as a peripheral circuit structure PERI, and a second semiconductor structure S2 defined as a memory cell structure CELL on the first semiconductor structure S1. The first semiconductor structure S1 and the second semiconductor structure S2 are joined to each other via bonding structures 180 and 280.

[0035] The first semiconductor structure S1 includes a first substrate 101, circuit elements 120 on the first substrate 101, a lower wiring structure 130, a lower bonding structure 180, and a lower capping layer 190.

[0036] The first substrate 101 comprises a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 101 may be provided as a bulk wafer or an epitaxial layer. An active region is defined in the first substrate 101 by an element isolation layer 110. A source / drain region 105 containing impurities is located within a portion of the active region.

[0037] The circuit element 120 includes a transistor. Each circuit element 120 includes a circuit gate dielectric layer 124, a circuit gate electrode 122, a spacer layer 126, and a source / drain region 105. The source / drain region 105 containing impurities is located within the first substrate 101 on both sides of the circuit gate electrode 122. The spacer layer 126 is located on both sides of the circuit gate electrode 122. The circuit gate dielectric layer 124 includes silicon oxide, silicon nitride, or a high-dielectric constant (high-k) material. The circuit gate electrode 122 includes at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), and ruthenium (Ru). For example, the circuit gate electrode 122 includes a doped polycrystalline silicon layer. According to an exemplary embodiment, the circuit gate electrode 122 may be composed of two or more multilayers.

[0038] The lower wiring structure 130 is electrically connected to the circuit gate electrode 122 and the source / drain region 105 of the circuit element 120. The lower wiring structure 130 includes a lower contact plug 135 and a lower wiring line 137, at least one of which is linear. Part of the lower contact plug 135 is connected to the source / drain region 105, and another part of the lower contact plug 135, not shown, is connected to the gate electrode 122. The lower contact plug 135 electrically connects the lower wiring lines 137, which are arranged at different levels from the upper surface of the first substrate 101. The lower wiring structure 130 contains a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each configuration may further include a diffusion barrier containing at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tantalum nitride (WN). According to exemplary embodiments, the number of layers and arrangement of the lower contact plugs 135 and lower wiring lines 137 constituting the lower wiring structure 130 may be varied.

[0039] The lower bonding structure 180 is connected to the lower wiring structure 130. The lower bonding structure 180 includes lower bonding vias 182, lower bonding pads 184, and a lower bonding insulating layer 186. The lower bonding vias 182 are connected to the lower wiring structure 130. The lower bonding pads 184 are connected to the lower bonding vias 182. The lower bonding vias 182 and the lower bonding pads 184 contain a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each component may further include a diffusion barrier. The lower bonding insulating layer 186 also functions as a diffusion barrier for the lower bonding pads 184 and contains at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The lower bonding insulating layer 186 has a thickness thinner than, but is not limited to, the thickness of the lower bonding pads 184. The lower bonding structure 180 is joined or connected to the upper bonding structure 280 by direct contact through hybrid bonding. For example, the lower bonding pad 184 is bonded to the upper bonding pad 284 by copper-to-copper bonding in contact with each other, and the lower bonding insulating layer 186 is bonded to the upper bonding insulating layer 286 by dielectric-to-dielectric bonding in contact with each other. Together with the upper bonding structure 280, the lower bonding structure 180 provides an electrical connection path between the peripheral circuit structure PERI (S1) and the memory cell structure CELL (S2).

[0040] The lower capping layer 190 is placed on the first substrate 101 and covers the circuit elements 120 and the lower wiring structure 130. The lower capping layer 190 may include a plurality of insulating layers. The lower capping layer 190 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0041] The second semiconductor structure S2, which is a memory cell structure, includes a first conductive layer 201 in a first region R1 which is a memory cell region, a second conductive layer 202 on the upper surface of the first conductive layer 201, a gate electrode 230 stacked on the lower surface of the first conductive layer 201 within the first region R1 and the second region R2, an interlayer insulating layer 220 stacked alternately with the gate electrode 230, a channel structure CH positioned to penetrate the gate electrode 230, an isolation region MS extending in one direction through the gate electrode 230, and an insulating region SS penetrating a portion of the gate electrode 230. The second semiconductor structure S2 includes an edge region EA surrounding the first region R1 and the second region R2. It further includes an upper capping layer 290 covering the gate electrode 230. The gate electrode 230 is stacked vertically separated on the lower surface of the first conductive layer 201 and, together with the interlayer insulating layer 220, forms stacked structures GS1 and GS2.

[0042] The second semiconductor structure S2 includes a channel stud 272 for electrical connection with the first semiconductor structure S1, upper wiring structures 271, 273, and 274 below the stacked structures GS1 and GS2, and an upper bonding structure 280 connected to the upper wiring structures 271, 273, and 274. The second semiconductor structure S2 includes an address stud 275 located at substantially the same level as the channel stud 272 and positioned on the address isolation region MSc of the isolation region MS.

[0043] The second semiconductor structure S2 further includes a contact plug in the second region R2 and an external contact via in the edge region EA.

[0044] As shown in Figure 3, the first region R1 is a region where gate electrodes 230 are stacked spaced apart from each other in the vertical direction, for example, in the Z direction, and where the channel structure CH is located. The second region R2 is located on both sides of the first region R1 in the X direction, as shown in Figure 1, and is connected to the gate electrodes 230, and is a region where contact plugs for electrically connecting the memory cell to the first semiconductor structure S1 are located.

[0045] The laminated structures GS1 and GS2 include multiple vertically stacked laminated structures GS1 and GS2. Although Figure 3 shows the lower and upper laminated structures GS1 and GS2 included, it is not limited to this and may include 3 to 5 layers of laminated structures GS1-GSd. However, depending on the embodiment, the laminated structures GS1-GSd may be formed as a single laminated structure.

[0046] The gate electrode 230 includes at least one lower gate electrode 230L forming the gate of a ground selection transistor, a plurality of memory gate electrodes 230M forming memory cells, and an upper gate electrode 230U forming the gate of a string selection transistor. Here, the lower gate electrode 230L and the upper gate electrode 230U are referred to as "lower" and "upper" with respect to the direction during the manufacturing process. The number of memory gate electrodes 230M forming memory cells can be determined according to the capacity of the semiconductor device 10. Depending on the embodiment, the upper and lower gate electrodes 230U, 230L may each be one or more, and may have the same or different structure as the memory gate electrodes 230M. In an exemplary embodiment, an erase gate electrode may be further arranged below the upper gate electrode 230U. In addition, some gate electrodes 230, for example, memory gate electrodes 230M adjacent to the upper or lower gate electrodes 230U, 230L may be dummy gate electrodes, but are not limited thereto.

[0047] The gate electrodes 230 are separated from each other in the Y direction by isolation regions MS that extend continuously within the first region R1 and the second region R2. The gate electrodes 230 between the pair of isolation regions MS form one memory block BLK. A portion of the gate electrodes 230, for example, the memory gate electrodes 230M, each forms one layer within one memory block BLK.

[0048] The gate electrodes 230 are stacked vertically spaced apart within the first region R1 and the second region R2, extending from the first region R1 to the second region R2 at different lengths, forming a stepped structure in a part of the second region R2, for example. Due to the stepped structure, the lower gate electrode 230 extends longer than the upper gate electrode 230, and each has a region where its upper surface is exposed above the interlayer insulating layer 220 and the other gate electrodes 230, and this region is referred to as the pad region. In each gate electrode 230, the pad region is the region including the end of the gate electrode 230 along the X direction. Each gate electrode 230 is connected to a contact plug in the pad region.

[0049] The gate electrode 230 comprises a metallic material, such as tungsten (W). Depending on the embodiment, the gate electrode 230 may comprise polycrystalline silicon or a metallic silicide material. According to an exemplary embodiment, the gate electrode 230 further comprises a diffusion prevention layer 231, which may comprise, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0050] The interlayer insulating layer 220 is positioned between the gate electrodes 230 to form the laminated structures GS1 and GS2. Like the gate electrodes 230, the interlayer insulating layer 220 is positioned spaced apart from each other in a direction perpendicular to the lower surface of the first conductive layer 201 and extends in the X direction. The interlayer insulating layer 220 extends to the edge region EA and is positioned between the sacrificial insulating layers 218 to form the molded structure. The interlayer insulating layer 220 contains an insulating material such as silicon oxide or silicon nitride.

[0051] In the embodiment, the thickness of all interlayer insulating layers 220 does not have to be the same. For example, among the interlayer insulating layers 220, the uppermost interlayer insulating layer 223, the lowermost interlayer insulating layer 222, and the intermediate interlayer insulating layer 225 have a greater thickness than the other interlayer insulating layers 220, but are not limited to this. The intermediate interlayer insulating layer 225 is defined as the interlayer insulating layer between the laminated structures GS1 and GS2.

[0052] As described above, the isolation region MS is arranged to extend along the X direction, penetrating the gate electrode 230. The isolation region MS is arranged parallel to each other and spaced apart in the Y direction. The isolation region MS penetrates the entire stacked gate electrode 230 and is connected to the upper capping layer 290. The isolation region MS extends as a single unit along the X direction, but may extend intermittently in some parts, or may be arranged only in some areas.

[0053] A separation insulating layer 264 is placed in the separation region MS. The separation insulating layer 264 has a shape in which its width increases toward the first substrate 101 due to a high aspect ratio, but is not limited to this. The lower surface Sa of the separation insulating layer 264 is in contact with the upper capping layer 290, and the upper surface is in contact with the lower surface of the first conductive layer 201. The separation insulating layer 264 does not have to extend to the edge region EA.

[0054] As shown in Figure 2, the separation region MS may be formed with flat sides, but it may also have a structure in which curved surfaces with a convex curvature toward the outside are continuously formed. Such a curved surface structure on the sides is derived by forming a channel hole and, simultaneously with forming a plurality of separation holes that are separated from each other, and then expanding the plurality of separation holes so that they connect to each other through a washing process, thereby forming the separation region MS.

[0055] The insulating region SS extends in the X direction between adjacent isolation regions MS. The insulating region SS is located within a portion of the second region R2 and within the first region R1. The insulating region SS penetrates the upper gate electrode 230U, which is located at the uppermost end of the gate electrode 230. The insulating region SS divides the upper gate electrode 230U in the Y direction, as shown in Figure 2. However, the number of upper gate electrode 230U separated by the insulating region SS may vary depending on the embodiment.

[0056] The insulating region SS is positioned across a portion of the channel structure CH. The insulating region SS has a predetermined width in the Y direction and extends across the X direction between multiple channel structures CH arranged in a zigzag matrix. Therefore, when multiple channel structures CH are arranged to have the same separation distance, the insulating region SS extends across one row of channel structures CH simultaneously. The insulating region SS retracts into the upper end of the channel structure CH, for example, a portion of the channel structure CH facing one upper gate electrode 230U, thereby removing a portion of the channel structure CH. In this case, the channel structure CH retracts by a length smaller than the radius of the channel structure CH from the channel central axis to the inner wall of the channel hole. Therefore, the insulating region SS is positioned so as not to pass through the channel central axis of the channel structure CH, and so as to leave more than half of the channel structure CH remaining on its upper surface. Each insulating region SS includes an upper separating insulating layer 266. The upper separating insulating layer 266 contains an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0057] The channel structures CH are arranged spaced apart from each other on the lower surface of the first conductive layer 201 in the first region R1, forming rows and columns. The channel structures CH are arranged in a zigzag pattern in one direction in the XY plane. The channel structures CH penetrate the gate electrode 230 and extend in a vertical direction perpendicular to the lower surface of the first conductive layer 201, for example, in the Z direction, and have a columnar shape with inclined sides that become narrower closer to the first conductive layer 201 depending on the aspect ratio.

[0058] Each of the channel structures CH has a configuration in which a first channel structure CH1 and a second channel structure CH2 are connected, each penetrating the lower laminated structure GS1 and upper laminated structure GS2 of the gate electrode 230, respectively, and has a bent portion in the connecting region due to a difference or change in width.

[0059] As shown in the enlarged view of Figure 4a, each channel structure CH includes a first portion within the laminated structures GS1 and GS2, and a second portion projecting above the laminated structures GS1 and GS2.

[0060] The channel layer 240 is positioned throughout the first and second portions of the channel structure CH, extending up to the upper end of the second portion. The channel layer 240 includes a projection 240a positioned in the second portion of the channel structure CH and exposed above the laminated structures GS1 and GS2, and a non-projecting portion 240b positioned in the first portion of the channel structure CH. The lengths of the projections 240a of the second portion of the channel structure CH, i.e., the projections 240a of the channel layer 240, do not have to be the same, but are not limited to this. The channel layer 240 is formed in an annular shape with its sides surrounding the internal embedded insulating layer 247, but depending on the embodiment, it may have a columnar shape such as a cylinder or prism without the embedded insulating layer 247. The projection 240a of the channel layer 240 is covered by the first conductive layer 201 and is in direct contact with the first conductive layer 201. The protruding portion 240a is formed to have a gentle slope with the non-protruding portion 240b so as to maintain its annular shape, as shown in Figure 4a. The channel layer 240 contains a semiconductor material such as polycrystalline silicon or single-crystal silicon, and the semiconductor material may be an undoped material or a material containing P-type or N-type impurities.

[0061] In the channel structure CH, a channel pad 249 is positioned below the channel layer 240. The channel pad 249 covers the lower surface of the embedded insulating layer 247 and is positioned to be electrically connected to the channel layer 240. The channel pad 249 includes, for example, doped polycrystalline silicon.

[0062] The information storage structure 245 is positioned between the gate electrode 230 and the channel layer 240. The information storage structure 245 includes a tunneling layer 241, a charge storage layer 242, and a blocking layer 243, which are sequentially stacked from the channel layer 240. The tunneling layer 241 can tunnel charges to the charge storage layer 242 and includes, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer 242 is a charge trap layer or a floating gate conductive layer. The blocking layer 243 includes silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. According to an exemplary embodiment, at least a portion of the information storage structure 245 forms a channel dielectric layer extending horizontally along the gate electrode 230.

[0063] The information storage structure 245 is removed from the upper part of the laminated structures GS1 and GS2 in the second part such that the protruding portion 240a of the channel layer 240 is exposed to the outside. Thus, the upper end of the information storage structure 245 is in contact with the first conductive layer 201, and in the first part, the side surface of the information storage structure 245 is positioned to surround the non-protruding portion 240b of the channel layer 240.

[0064] The channel layer 240, the information storage structure 245, and the embedded insulating layer 247 are connected to each other between the second channel structure CH2 and the first channel structure CH1. As described above, a relatively thick intermediate interlayer insulating layer 225 is placed between the second channel structure CH2 and the first channel structure CH1.

[0065] The external contact vias are connected in the edge region EA to the first semiconductor structure S1 via the pad region 258 exposed to the outside and the upper wiring structure 272 of the second semiconductor structure S2 to transmit external signals.

[0066] In the first region R1, the semiconductor device 10 includes a first conductive layer 201 between the lower surface of the second conductive layer 202 and the laminated structures GS1 and GS2. The first conductive layer 201 includes a semiconductor material. For example, the first conductive layer 201 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor includes silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first conductive layer 201 functions as a common source line (CSL) of the semiconductor device 10. The first conductive layer 201 includes a silicon layer, such as a silicon layer having an N-type conductivity. For example, the first conductive layer 201 is provided as a crystalline semiconductor layer such as an impurity-doped single-crystal silicon layer or a polycrystalline silicon layer, or as an epitaxial layer. As shown in the enlarged view of Figure 4a, the first conductive layer 201 covers the second portion of the channel structure CH and is in direct contact with the protruding portion 240a of the channel layer 240.

[0067] The first conductive layer 201 is a plate layer that covers the entire laminated structures GS1 and GS2, and is arranged so that its upper surface is flat. The first conductive layer 201 has a thickness greater than the length of the protrusion 240a of the channel layer 240 and is conformally formed to the shape of the channel structure CH.

[0068] A second conductive layer 202 is positioned along the first conductive layer 201. The second conductive layer 202 has a smaller thickness than the first conductive layer 201 and is a conductive layer in contact with the first conductive layer 201. The second conductive layer 202 contains at least one of metal-semiconductor compounds, metal-nitrides, and metals (e.g., tungsten (W), copper (Cu), aluminum (Al)). The second conductive layer 202 is aligned perpendicularly to the first conductive layer 201.

[0069] The first and second conductive layers 201 and 202 are source layers and together form a source structure. The source structure functions as a common source line (CSL) of the semiconductor device 10.

[0070] A buffer layer (not shown) may be further formed on the second conductive layer 202. The buffer layer is an oxide that conformally covers the second conductive layer 202 and includes silicon oxide, silicon oxynitride, and the like.

[0071] The upper wiring structures 271, 273, and 274 electrically connect the gate electrode 230 and the channel structure CH to the circuit element 120 within the upper capping layer 290. The upper wiring structures 271, 273, and 274 are connected to channel studs 272 which are connected to the channel structure CH. The channel studs 272 located below the channel structure CH are connected to the channel pads 249 of the channel structure CH. The channel studs 272 connected to the channel structure CH are electrically connected to the channel layer 240 via the channel pads 249 of the channel structure CH in the first region R1. In the second region R2, a stud (not shown) is connected to a contact plug which is connected to the gate electrode 230. The channel stud 272 contains a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and the channel stud 272 may further include a diffusion prevention layer 272b containing at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tantalum nitride (WN).

[0072] The first upper wiring line 271 is electrically connected to the channel stud 272 and includes a plurality of bit lines BL that extend in the Y direction and are spaced apart in the X direction at a predetermined pitch. A second upper wiring line 274 is positioned below the first upper wiring line 271, and connecting vias 273 are positioned between the second upper wiring line 274 and the first upper wiring line 271, and between the channel stud 272 and the first upper wiring line 271. The upper wiring structures 271, 273, and 274 also contain conductive material, such as tungsten (W), copper (Cu), aluminum (Al), and the respective components may further include a diffusion-blocking layer containing at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to exemplary embodiments, the number of layers and arrangement of the upper wiring lines 271, 274 that constitute the upper wiring structures 271, 273, 274 may be varied.

[0073] The address stud 275 is positioned in the address isolation area MSc within the isolation area MS, and is located below the lower surface Sa of the address isolation area MSc.

[0074] Each address stud 275 includes a top surface Sb, a bottom surface, and a side surface between the top surface Sb and the bottom surface. Each address stud 275 has a top surface Sb width smaller than the bottom surface width W2, and its width increases towards the bottom. The side surface has a slope due to the difference in width between the top surface Sb and the bottom surface, but is not limited to this. The size and form of each address stud 275 are substantially the same as those of the channel stud 272. The channel stud 272 also includes a top surface, a bottom surface, and a side surface between the top surface and the bottom surface. Each channel stud 272 has a top surface width smaller than the bottom surface width W3, and its width increases towards the bottom surface. The side surface has a slope due to the difference in width between the top surface and the bottom surface, but is not limited to this. Specifically, when the bottom surface width W2 of each address stud 275 is at its largest, the bottom surface width W3 of the channel stud 272 is also at its largest, and the bottom surface width W2 of the address stud 275 and the bottom surface width W3 of the channel stud 272 are substantially the same. The length h1 of each address stud 275, i.e., the length h1 in the Z direction, is substantially the same as that of the channel stud 272 and is greater than the length of the connecting via 273 in the Z direction. The lower surface of the address stud 275 and the lower surface of the channel stud 272 are located at substantially the same level. The distance between an address stud 275 and the nearest channel stud 272 satisfies the minimum distance d1. The minimum distance d1 is greater than the distance between the channel studs 272.

[0075] The upper capping layer 290 includes, but is not limited to, a plurality of capping insulating layers 291, 295, and 296, including a first capping insulating layer 291, a second capping insulating layer 295, and a third capping insulating layer 295.

[0076] The first to third capping insulating layers 291, 295, and 296 are laminated in different orders during the manufacturing process and contain substantially the same material. The first to third capping insulating layers 291, 295, and 296 contain at least one of SiCN, SiO, SiN, SiOC, SiON, and SiCN.

[0077] The isolation region MS has a lower surface width W1 that is greater than the upper surface width, and the lower surface Sa of the isolation region MS has a first width W1 in the Y direction. The lower surface Sa of the address isolation region MSc and the lower surface of the channel structure CH are substantially coplanar with the lower surface of the uppermost interlayer insulating layer 223.

[0078] A first capping insulating layer 291 is positioned to cover the lower surface Sa of the address isolation region MSc and the lower surface of the channel structure CH. Address studs 275 and channel studs 272 are positioned penetrating the first capping insulating layer 291. The upper surface Sb of the address studs 275 is in contact with the lower surface Sa of the address isolation region MSc, but is not limited to this, and may also be positioned within the first capping insulating layer 291.

[0079] When the center line of the width W1 in the Y direction of the lower surface Sa of the address isolation region MSc is defined as the reference line l0, and the center line of the width of the upper surface Sb of the address stud 275 below it is defined as the first line l1, then the reference line l0 and the first line l1 are arranged to be coaxial. Therefore, the address stud 275 is aligned in the Z direction so that it is located in the center on the lower surface Sa of the address isolation region MSc.

[0080] A second capping insulating layer 295 is placed below the first capping insulating layer 291. The first upper via 273a of the connecting vias 273 is placed through the second capping insulating layer 295. The first upper via 273a is not connected to the address stud 275, but is connected to the channel stud 272.

[0081] The first upper via 273a is connected to the first wiring line 271. The first upper via 273a is connected to the first wiring line 271, for example, to the bit line BL, to apply an electrical signal to the channel structure CH. The address stud 275 is separated in the Z direction from the first wiring line 271, including the bit line BL. A second capping insulating layer 295 is placed between the address stud 275 and the first wiring line 271, including the bit line BL.

[0082] A third capping insulating layer 296 is placed on the second capping insulating layer 295, and a second upper via 273b and a second wiring line 274 are placed within the third capping insulating layer 296 and connected to the first wiring line 271.

[0083] The upper bonding structure 280 is connected to the upper wiring structures 271, 273, and 274. For example, the channel stud 272 is electrically connected to the upper bonding structure 280. The upper bonding structure 280 includes upper bonding vias 281, upper bonding pads 284, and an upper bonding insulating layer 286. The upper bonding vias 281 are connected to the upper wiring structure 270. The upper bonding pads 284 are connected to the upper bonding vias 281. The upper bonding vias 281 and upper bonding pads 284 contain a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each component may further include a diffusion barrier. The upper bonding insulating layer 286 also functions as a diffusion barrier for the upper bonding pads 284 and contains at least one of SiCN, SiO, SiN, SiOC, SiON, and SiCN. The upper bonding insulating layer 286 has a thickness that is thinner than the thickness of the upper bonding pad 284, but is not limited to this.

[0084] In the following, exemplary embodiments of the present invention will be described with reference to Figures 5 to 13. Figures 5 to 7 are enlarged views of a semiconductor device according to an exemplary embodiment, and are enlarged views of the area corresponding to Figure 4b.

[0085] Referring to Figure 5, the semiconductor device 10a is the same as in Figure 4b, except that it further includes a base layer 298.

[0086] Specifically, the semiconductor device 10a further includes a base layer 298 on the channel structure CH and the lower surface Sa of the isolation region MS. The base layer 298 is an insulating material different from the upper capping layer 290; for example, when the upper capping layer 290 contains silicon oxide, the base layer 298 contains a material such as silicon nitride. The base layer 298 is an etching-blocking layer that prevents via holes from being formed from the lower surface Sa of the address isolation region MSc into the interior when forming the address studs 275. Depending on the size of the isolation region MS, some metallic material may remain in the isolation region MS after the gate electrode 230 replacement process. If etching occurs into the interior of the isolation region MS when forming via holes for the address studs 275, the address studs 275 may be formed to extend into the interior of the isolation region MS, forming parasitic capacitance and potentially causing a short circuit between the gate electrodes 230 of adjacent memory blocks BLK.

[0087] Therefore, in order to prevent via holes from being formed inside the isolation region MS when via holes are formed, by further forming a capping insulating layer 290 and an etching-selective base layer 298, via holes for the address studs 275 are formed only on the underside of the base layer 298, thereby protecting the upper address isolation region MSc.

[0088] Therefore, a first capping insulating layer 291 is placed on the lower surface of the base layer 298, and studs 275 and 272 are placed penetrating the first capping insulating layer 291. At this time, a third upper via 297 is further placed for electrical connection between the channel structure CH and the channel stud 272. The third upper via 297 contains a conductive material, the same material as the first and second upper vias 273a and 273b, and has a smaller area and length than the channel stud 272. The third upper via 297 has the same length as the thickness of the base layer 298.

[0089] In this way, the base layer 298 is placed between the upper surface Sb of the address stud 275 and the lower surface Sa of the address isolation region MSc, physically separating the address isolation region MSc and the address stud 275 by a second distance d2.

[0090] Referring to Figure 6, the semiconductor device 10b is identical to that in Figure 4b, except for the size of the address stud 275.

[0091] Each address stud 275 includes a top surface Sb, a bottom surface, and a side surface between the top surface Sb and the bottom surface. Each address stud 275 has a top surface Sb width smaller than the bottom surface width W4, and its width increases towards the bottom. The side surface has a slope due to the difference in width between the top surface Sb and the bottom surface, but is not limited to this. The size and shape of each address stud 275 differ from the size and shape of the channel stud 272. The channel stud 272 also includes a top surface, a bottom surface, and a side surface between the top surface and the bottom surface. Each channel stud 272 has a top surface width smaller than the bottom surface width, and its width increases towards the bottom surface. The side surface has a slope due to the difference in width between the top surface and the bottom surface, but is not limited to this. Specifically, when the bottom surface width W4 of each address stud 275 is at its largest, the bottom surface width W3 of the channel stud 272 is also at its largest, and the bottom surface width W4 of the address stud 275 is smaller than the bottom surface width W3 of the channel stud 272. The width of the upper surface Sb of the address stud 275 is smaller than the width of the upper surface of the channel stud 272, and the length h2 of the address stud 275, i.e., the length h2 in the Z direction, is smaller than the length h1 of the channel stud 272 but larger than the length of the upper via 273.

[0092] Therefore, the address stud 275 is positioned within the first capping insulating layer 291, and the lower surface of the address stud 275 is coplane with the lower surface of the channel stud 272 and coplane with the lower surface of the first capping insulating layer 291. However, the upper surface Sb of the address stud 275 is physically separated from the lower surface Sa of the address isolation region MSc by a third distance d3 in the Z direction, and a portion of the first capping insulating layer 291 is positioned in the separated space.

[0093] Referring to Figure 7, the semiconductor device 10c is identical to that in Figure 4b, except for the alignment of the address studs 275.

[0094] The first capping insulating layer 291 is positioned to cover the isolation region MS and the lower surface of the channel structure CH. The address stud 275 and channel stud 272 are positioned penetrating the first capping insulating layer 291. The upper surface Sb of the address stud 275 is in contact with the upper surface Sa of the address isolation region MSc, but is not limited to this, and may be positioned within the first capping insulating layer 291.

[0095] When the center line of the width W1 of the lower surface Sa of the address isolation region MSc is defined as the reference line l0, and the center line of the width of the upper surface Sb of the address stud 275 below it is defined as the first line l1, the address stud 275 is positioned such that the first line l1 is offset from the reference line l0 by a fourth distance d4. Therefore, the address stud 275 is positioned below the lower surface Sa of the address isolation region MSc, offset from the center and close to one side. At least a portion of the upper surface Sb of the address stud 275 is in contact with the uppermost interlayer insulating layer 223, but is not limited to this.

[0096] The semiconductor device 10d in Figure 8 is the same as the semiconductor devices in Figures 1 to 4b, except for the arrangement rule of the address studs 275.

[0097] Referring to Figure 8, the isolation region MS where the address stud 275 is located is defined as the address isolation region MSc. Address isolation regions MSc are arranged every n isolation region MS in the Y direction. Address isolation regions MSc are arranged in pairs. That is, adjacent isolation regions MS located above and below a single memory block BLK constitute a pair of address isolation regions MSc. For example, when n is 50, the 50th (n)th and 51st (n+1)th isolation regions MS form a pair of address isolation regions MSc, the 100th (2n)th and 101st (2n+1)th isolation regions MS form another pair of address isolation regions MSc, and the 150th (3n)th and 151st (3n+1)th isolation regions MS form yet another pair of address isolation regions MSc. In this case, the arrangement rules are applied differently to each of the multiple pairs of address isolation regions MSc.

[0098] In a pair of address isolation regions MSc, one row of address studs 275 is arranged on each address isolation region MSc, spaced apart in the X direction. The two rows of address studs 275 on the pair of address isolation regions MSc form an array group AG arranged according to an array rule, and as shown in Figures 1 and 2, the array rule determines that the address studs 275 are selectively positioned for stud positions n1, n2, n3, n4, and n5 in the X direction.

[0099] As an example, when there are five stud positions (n1, n2, n3, n4, n5) in each row of a single array group AG, the array rule is set such that the address stud 275 on the first pair of address isolation regions (MSc:MSn, MSn+1) has its starting address stud 275i located at the first stud position n1 of the first and second rows, and the address stud 275 at the second stud position n2 is located in the first row. Therefore, the first separation distance I1 is satisfied between the starting address stud 275i of the first row and the adjacent address stud 275.

[0100] The address studs 275 on the second pair of address isolation regions (MSc:MS2n, MS2n+1) are arranged such that the starting address stud 275i is located at the first stud position n1 of the first and second rows, and the address stud 275 at the third stud position n3 is located in the first row. Thus, the distance between the starting address stud 275i of the first row and the adjacent address stud 275 satisfies the second separation distance I2, i.e., twice the first separation distance I1.

[0101] The address studs 275 on the third pair of address isolation regions (MSc:MS3n, MS3n+1) are arranged such that the starting address stud 275i is located at the first stud position n1 of the first and second rows, and the address stud 275 at the fourth stud position n4 is located in the first row. Therefore, the distance between the starting address stud 275i of the first row and the adjacent address stud 275 satisfies the third separation distance I3, i.e., three times the first separation distance I1.

[0102] In this way, by setting different arrangement rules for the arrangement group AG depending on the position of the address isolation area MSc, the arrangement of the address stud 275 can be checked during error checking, and the position in the Y direction, i.e., the position of the memory block BLK, can be quickly confirmed as well as the position in the X direction.

[0103] Various semiconductor devices will be described with reference to Figures 9 and 13.

[0104] Figure 9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment, and Figure 10 is an enlarged cross-sectional view of region "D" in Figure 9.

[0105] Referring to Figures 9 and 10, the semiconductor device 10e is the same as in Figures 3 to 4b, except that the upper channel structure CH3 is arranged on the first and second channel structures CH1 and CH2 to form a single channel structure CH.

[0106] The upper channel structure CH3 extends in the z-direction through the upper gate electrode 293 and is connected to the first and second channel structures CH1 and CH2, respectively. The upper channel structure CH3 is positioned on the first and second channel structures CH1 and CH2, respectively, and is positioned shifted horizontally from the first and second channel structures CH1 and CH2, but is not limited to this arrangement.

[0107] As shown in Figures 9 and 10, each of the upper channel structures CH3 includes an upper channel layer 240c, an upper gate dielectric layer 245a, an upper channel embedding insulating layer 247a, and an upper channel pad 249a, all located within the upper channel hole. The upper channel layer 240c is formed in an annular shape, surrounding the internal upper channel embedding insulating layer 247a. The upper channel layer 240c is connected at the top to a connecting pad 299 and is electrically connected to the channel layer 240 of the upper first and second channel structures CH1 and CH2 via the connecting pad 299.

[0108] The descriptions of the materials of the upper channel layer 240c, upper gate dielectric layer 245a, upper channel embedding insulating layer 247a, and upper channel pad 249a can be similarly applied to the descriptions of the lower channel layer 240, information storage structure 245, channel embedding insulating layer 247, and channel pad layer 249 described above.

[0109] The horizontal insulating layer 292 is positioned between the upper first and second channel structures CH1 and CH2 and the upper channel structure CH3, and extends horizontally. The horizontal insulating layer 292 is positioned between the upper gate electrode 293 and the uppermost interlayer insulating layer 223. The horizontal insulating layer 292 is used as an etching stop layer when forming the upper channel structure CH3 and is also used when forming the connecting pad 299.

[0110] The horizontal insulating layer 292 contains an insulating material, which is different from the uppermost interlayer insulating layer 223. The horizontal insulating layer 292 is a hydrogen blocking layer and contains a material that prevents or reduces the diffusion of hydrogen (H). The horizontal insulating layer 292 contains a nitride, for example, at least one of SiN, SiON, SiCN, and SiOCN.

[0111] The connecting pad 299 penetrates the horizontal insulating layer 292 between the upper first and second channel structures CH1 and CH2 and the upper channel structure CH3, electrically connecting the lower channel layer 240 and the upper channel layer 240c. The connecting pad 299 is formed by partially removing the horizontal insulating layer 292 and has an upper surface that is coplane with the upper surface of the horizontal insulating layer 292. The connecting pad 299 is arranged in a form in which the upper channel pad layer 249 is partially recessed. However, the specific arrangement of the connecting pad 299 may be changed in various ways depending on the embodiment. The connecting pad 299 contains a conductive material, which may include, for example, polycrystalline silicon.

[0112] The upper gate electrode 293 is positioned on the XY plane and contains a conductive material. The upper gate electrode 293 contains the same material as the gate electrode 230, but unlike that, it may contain doped polysilicon.

[0113] The insulating region SS extends in the X direction between adjacent isolation regions MS. The insulating region SS penetrates the upper gate electrode 293, which is located at the top of the gate electrode 230. The insulating region SS divides the upper gate electrode 293 in the Y direction. A portion of the insulating region SS is located on the isolation region MS. Therefore, the insulating region SS is not formed by indenting a portion of the channel structure CH as shown in Figure 3, but is positioned to isolate only the upper gate electrode 293.

[0114] Each insulating region SS includes an upper separating insulating layer 266. The upper separating insulating layer 266 contains an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0115] The second horizontal insulating layer 294 is positioned to cover the upper gate electrode 293. The second horizontal insulating layer 294 is positioned on the horizontal insulating layer 292 and covers the top and sides of the upper gate electrode 293. The first capping insulating layer 291 is positioned below the second horizontal insulating layer 294, and both the first capping insulating layer 291 and the second horizontal insulating layer 294 are made of an insulating material and consist of multiple insulating layers.

[0116] The channel stud 272 and address stud 275 are positioned through the first capping insulating layer 291. The address stud 275 is positioned below the address isolation region MSc, and the channel stud 272 is positioned below the upper channel pad 249a of the upper channel structure CH3. The shape and position of the channel stud 272 are the same as in Figure 4b, and are identical except that the channel pad 249 has been changed to the upper channel pad 249a.

[0117] The shape of the address stud 275 is the same as that shown in Figure 4b. When the center line of the width in the Y direction of the address isolation region MSc is defined as the reference line l0, the center line of the width of the address stud 275 is defined as the first line l1, and the center line of the width in the Y direction of the insulation region SS is defined as the second line l2.

[0118] In Figure 10, the reference line l0 and the second line l2 are coaxial and aligned in the Z direction, with the first line l1 being offset from the reference line l0. It is explained that at least a portion of the upper surface Sb of the address stud 275 is not located on the lower surface Sc of the insulating region SS, but is located on the upper horizontal insulating layer 294.

[0119] In this case, the second horizontal insulating layer 294 is positioned between the upper gate electrode 293 and the address stud 275, and the insulating region SS and the address stud 275 are offset, thereby preventing a short circuit from occurring between the insulating region SS and the upper gate electrode 293 when a via hole for the address stud 275 is formed.

[0120] The semiconductor device 10f in Figure 11 is the same as the semiconductor device 10e in Figure 10, except that it includes a base layer 298.

[0121] Specifically, the semiconductor device 10f further includes a base layer 298 on the upper channel structure CH3 and the lower surface Sc of the insulating region SS. The base layer 298 is an insulating material different from the upper capping layer 290; for example, when the upper capping layer 290 contains silicon oxide, the base layer 298 contains a material such as silicon nitride. The base layer 298 is an etching-blocking layer, which prevents the address studs 275 from protruding inward from the lower surface Sc of the insulating region SS when forming them.

[0122] To prevent via holes from forming inside the insulating region SS during via hole formation, a capping insulating layer 290 and an etching-selective base layer 298 are further formed. This ensures that when via holes for the address studs 275 are formed, via holes are formed only up to the underside of the base layer 298, protecting the upper insulating region SS.

[0123] Therefore, a first capping insulating layer 291 is placed on the lower surface of the base layer 298, and an address stud 275 is placed penetrating the first capping insulating layer 291. At this time, a third upper via 297 is further placed for electrical connection between the upper channel structure CH3 and the channel stud 272. The third upper via 297 contains a conductive material, the same material as the first and second upper vias 293, and has a smaller area and length than the studs 272 and 275. The third upper via 297 has the same length as the thickness of the base layer 298.

[0124] The base layer 298 causes the reference line l0, the first line l1, and the second line I2 to be coaxial, and the address stud 275 and the insulating area SS to be aligned in the Z direction, but the base layer 298 is placed between them, physically separating the insulating area SS and the address stud 275.

[0125] Referring to Figure 12, the semiconductor device 10g is identical to that in Figure 10, except for the size of the address stud 275.

[0126] Each address stud 275 includes an upper surface Sb, a lower surface, and a side surface between the upper and lower surfaces. Each address stud 275 has a width on its upper surface Sb that is smaller than the width of its lower surface, and its width increases towards the bottom. The side surface has a slope due to the difference in width between the upper surface Sb and the lower surface, but is not limited to this. The size and form of each address stud 275 differ from the size and form of the channel stud 272. The channel stud 272 also includes an upper surface, a lower surface, and a side surface between the upper and lower surfaces. Each channel stud 272 has a width on its upper surface that is smaller than the width of its lower surface, and its width increases towards the bottom. The side surface has a slope due to the difference in width between the upper and lower surfaces, but is not limited to this. Specifically, when the width of the lower surface of each address stud 275 is at its largest, the width of the lower surface of the channel stud 272 is also at its largest, and the width of the lower surface of the address stud 275 is smaller than the width of the lower surface of the channel stud 272. The width of the upper surface Sb of the address stud 275 is smaller than the width of the upper surface of the channel stud 272, and the length h2 of the address stud 275, i.e., the length h2 in the Z direction, is smaller than the length h1 of the channel stud 272 but larger than the length of the upper via 273.

[0127] Therefore, the address stud 275 is positioned within the first capping insulating layer 291, and the lower surface of the address stud 275 is coplane with the lower surface of the channel stud 272 and the lower surface of the first capping insulating layer 294. However, the upper surface Sb of the address stud 275 is physically separated in the Z direction from the lower surface of the insulating region SS, and a portion of the first capping insulating layer 294 is positioned in the separated space. Due to the miniaturization of the address stud 275, the reference line l0, the first line l1 and the second line I2 are coaxial, and the insulating region SS and the address stud 275 are physically separated.

[0128] Referring to Figure 13, the semiconductor device 10h is identical to that in Figure 10, except for the alignment of the address studs 275 and the insulating region SS.

[0129] The first line l1 of address stud 275 is coaxial with the reference line l0 of address isolation region MSc, and the second line I2 of isolation region SS is offset in the Z direction from the reference line l0 of isolation region MS.

[0130] Specifically, the insulating region SS is offset to one side below the address isolation region MSc and positioned so as not to overlap in the Z direction. Therefore, even if the via hole of the address stud 275 penetrates to the upper horizontal insulating layer 294, it will still contact the upper gate electrode 293, but the insulating region SS will physically and electrically separate it from the adjacent upper gate electrode 293. Thus, over-etching of the address stud 275 can prevent a short circuit between the upper gate electrodes 293.

[0131] Figures 14a to 14g are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 14a to 14g show the regions corresponding to Figure 3.

[0132] Referring to Figure 14a, a first semiconductor structure (S1:PERI) is formed on the first substrate 101, including a circuit element 120 forming a peripheral circuit region (PERI), a lower wiring structure 130, a lower bonding structure 180, and a lower capping layer 190.

[0133] First, an element isolation layer 110 is formed within the first substrate 101, and then a circuit gate dielectric layer 124 and a circuit gate electrode 122 are sequentially formed on the first substrate 101. The element isolation layer 110 is formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 124 is formed on the first substrate 101, and the circuit gate electrode 122 is formed on the circuit gate dielectric layer 124. The circuit gate dielectric layer 124 and the circuit gate electrode 122 are formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 124 is formed of silicon oxide, and the circuit gate electrode 122 is formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited to these. Next, spacer layers 126 are formed on both side walls of the circuit gate dielectric layer 124 and the circuit gate electrode 122, and impurities are injected into the active region of the first substrate 101 on both sides of the circuit gate electrode 122 to form source / drain regions 105.

[0134] The lower contact plug 135 of the lower wiring structure 130 is formed by first forming a portion of the lower capping layer 190, then etching and removing a portion of it, and finally embedding a conductive material. The lower wiring line 137 is formed, for example, by depositing a conductive material and then patterning it.

[0135] The lower bonding vias 182 of the lower bonding structure 180 are formed by first forming a portion of the lower capping layer 190, then etching and removing a portion of it, and finally filling it with a conductive material. The lower bonding pads 184 are formed, for example, by vapor deposition of a conductive material and then patterning it. The lower bonding structure 180 is formed, for example, by a vapor deposition process or a plating process. The lower bonding insulating layer 186 is formed so as to cover a portion of the upper and side surfaces of the lower bonding pads 184, and then a planarization process is performed until the upper surface of the lower bonding pads 184 is exposed.

[0136] The lower capping layer 190 consists of multiple insulating layers. The lower capping layer 190 is part of each step in forming the lower wiring structure 130 and the lower bonding structure 180. This forms the first semiconductor structure S1, which is the peripheral circuit region PERI.

[0137] Referring to Figure 14b, the manufacturing process for the second semiconductor structure (S2:CELL) is initiated.

[0138] A molded structure is formed by alternately stacking sacrificial insulating layers 218 and interlayer insulating layers 220 on a base substrate 300 (SUB), and sacrificial vertical structures 216a, 216b, 217a, and 217b are formed at the positions where each vertical structure is to be formed.

[0139] The lower mold structure is formed on the base substrate 300 at the height in which the first channel structure CH1 (see Figure 3) is positioned. The base substrate 300 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0140] The sacrificial insulating layer 218 is a layer that, in a subsequent process, is replaced by at least a portion of the gate electrode 230 (see Figure 3). The sacrificial insulating layer 218 is made of a different material from the interlayer insulating layer 220. For example, the interlayer insulating layer 220 and the uppermost, middle, and lowermost interlayer insulating layers 222, 223, and 225 are made of at least one of silicon oxide and silicon nitride, while the sacrificial insulating layer 218 is made of a different material from the interlayer insulating layer 220, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In this embodiment, the thickness of the interlayer insulating layers 220 does not have to be the same. Also, the thickness of the interlayer insulating layer 220 and the sacrificial insulating layer 218 and the number of constituent films may be changed in various ways from those shown.

[0141] An interlayer insulating layer 220 and a sacrificial insulating layer 218, which form the lower mold structure, are alternately laminated on the base substrate 300.

[0142] When forming a gate pad region in the second region R2, the photolithography process and etching process are repeatedly performed on the sacrificial insulating layer 218 and the interlayer insulating layer 220. However, in the embodiment, the specific shape of the gate pad region may be changed in various ways.

[0143] The first vertical sacrificial layer 216a is formed in the first region R1 at a position corresponding to the lower part of the first channel structure CH1. The first vertical sacrificial layer 216a is formed by forming a hole that penetrates the lower mold structure MS1, then depositing a sacrificial layer material into the hole and performing a planarization process. When forming the hole, a plurality of separation holes that are spaced apart from each other are formed in the region corresponding to the separation region MS, and together with the first separation sacrificial layer 217a that fills the plurality of separation holes is formed. The vertical sacrificial layer, including the first vertical sacrificial layer 216a and the first separation sacrificial layer 217a, includes, for example, at least one of TiN and polycrystalline silicon.

[0144] Next, sacrificial insulating layers 218 and interlayer insulating layers 220 that form the upper mold structure are alternately stacked on the lower mold structure to form a second vertical sacrificial layer 216b and a second separation sacrificial layer 217b.

[0145] Each component of the upper mold structure MS2 is formed in the same manner as the lower mold structure MS1. The second vertical sacrificial layer 216b is formed so as to be connected to the first vertical sacrificial layer 216a. The second separation sacrificial layer 217b is formed so as to be connected to the first separation sacrificial layer 217a. The second vertical sacrificial layer 216b and the second separation sacrificial layer 217b are formed by depositing the same material as the first vertical sacrificial layer 216a, for example, polycrystalline silicon.

[0146] Therefore, all of the vertical structures, channel structures CH, and multiple vertical sacrificial layers 216a, 216b, 217a, and 217b that make up the separation region MS in Figure 3 are formed simultaneously.

[0147] As shown in Figure 14c, a channel structure CH is formed on the base substrate 300, penetrating the molded structure of the sacrificial insulating layer 218 and the interlayer insulating layer 220.

[0148] The channel structure CH is formed by first forming an upper hole on vertical sacrificial layers 216a and 216b, then removing the vertical sacrificial layers 216a and 216b to form a hole-shaped channel hole, and finally filling the channel hole with multiple layers. The multiple layers include an information storage structure 245, a channel layer 240, an embedded insulating layer 247, and a channel pad 249. The upper channel hole of the channel hole is formed by anisotropically etching the upper laminated structure of the sacrificial insulating layer 218 and the interlayer insulating layer 220 using a separate mask layer. The lower channel hole of the channel hole is formed by removing the vertical sacrificial layer exposed through the upper channel hole.

[0149] Depending on the height of the molded structure, the side walls of the channel structure CH may not be perpendicular to the upper surface of the base substrate 300. The channel structure CH is formed to recess a portion of the base substrate 300 depending on the depth of the channel hole.

[0150] The information storage structure 245 is formed to have a uniform thickness. At this stage, all or part of the information storage structure 245 is formed, and the portion extending perpendicularly to the base substrate 300 along the channel structure CH is formed at this stage. The channel layer 240 is formed on the information storage structure 245 within the channel structure CH. The embedded insulating layer 247 is formed to fill the channel structure CH and is an insulating material. The channel pad 249 is made of a conductive material, for example, polycrystalline silicon. After the channel structure CH is formed, a contact plug is formed in the second region R2.

[0151] Referring to Figure 14d, the gate electrode 230 is formed. By removing the separation sacrificial layers 217a and 217b that fill the separation holes formed at the location of the separation region MS, and expanding the separation holes by cleaning or the like to connect them to each other, openings are formed that are connected to each other in the X direction as shown in Figure 2. As the multiple separation holes expand in the circumferential direction and connect to each other, the side surface forming the separation region MS has a shape in which curves are continuously convex outwards, but is not limited to this. Within these expanded openings, the sacrificial insulating layer 218 is selectively removed from the interlayer insulating layer 220 by wet etching to form the gate electrode 230.

[0152] The gate electrode 230 is formed by depositing a conductive material in the region where the sacrificial insulating layer 218 has been removed. The conductive material includes a metal, polycrystalline silicon, or a metal silicide. In some embodiments, a portion of the gate dielectric layer is formed before forming the gate electrode 230.

[0153] After forming the gate electrode 230, a gate isolation insulating layer 264 (see Figure 3) is formed within an opening that corresponds to the isolation region MS. At this time, an insulating region SS is also formed that crosses the upper gate electrode 230U.

[0154] Referring to Figure 14e, channel studs 272 and address studs 275 are formed.

[0155] A first capping insulating layer 291 is formed on the uppermost interlayer insulating layer 223, covering both the upper surface of the separation region MS and the upper surface of the channel structure CH.

[0156] Within the first capping insulating layer 291, channel stud holes that expose the channel pads 249 of each channel structure CH, and address stud holes that expose the upper surface of the address isolation region MSc among the isolation regions MS are simultaneously formed.

[0157] The stud holes are formed by removing the corresponding region of the first capping insulating layer 291 by etching, and the size and depth of the channel stud holes and address stud holes are substantially the same.

[0158] Diffusion-blocking layers 272b and 275b are laminated along the sides of the channel stud holes and address stud holes, the channel stud holes and address stud holes are embedded within the diffusion-blocking layers 272b and 275b, and a conductive material is laminated to form the channel studs 272 and address studs 275. Depending on the shape of the channel stud holes and address stud holes, the width of the upper end is greater than the width of the lower end, and the sides are inclined. This forms the address stud holes on the address separation region MSc, which is part of the separation region MS.

[0159] Referring to Figure 14f, upper wiring structures 271, 273, and 274 are formed on the channel stud 272 and address stud 275.

[0160] First, a second capping insulating layer 295 is formed by covering the channel stud 272 and address stud 275, and a portion of the second capping insulating layer 295 is removed to form a first upper via hole that exposes the upper surface of the channel stud 272. The first upper via hole is formed to be smaller than the channel stud hole and is not formed on the address stud 275.

[0161] A diffusion barrier and conductive material are formed within the first upper via hole to form the first upper via 273a, which is connected to the channel stud 272.

[0162] Next, a third capping insulating layer 296 is formed to cover the first upper via 273a, and upper wiring structures 271, 273, and 274 are formed, including a first upper wiring line 271, a second upper via 273b, and a second upper wiring line 274, which are connected to the first upper via 273a. The third capping insulating layer 296 is implemented in multiple layers, and the upper wiring structures 271, 273, and 274 are formed by laminating a diffusion barrier and conductive material, similar to the first upper via 273a.

[0163] An upper bonding structure 280 is formed on the upper wiring structures 271, 273, and 274.

[0164] The upper bonding structure 280 is formed in a manner similar to that used to form the lower bonding structure 180. This forms the second semiconductor structure S2, which is a memory cell structure CELL. However, in the manufacturing process of the semiconductor device 10, the second semiconductor structure S2 further includes a base substrate 300.

[0165] Referring to Figure 14g, the first semiconductor structure S1, which is a peripheral circuit structure PERI, and the second semiconductor structure S2, which is a memory cell structure CELL, are joined together.

[0166] The first semiconductor structure S1 and the second semiconductor structure S2 are connected by bonding the lower bonding pad 184 and the upper bonding pad 284 under pressure. The lower bonding insulating layer 186 and the upper bonding insulating layer 286 are connected by bonding under pressure. On the first semiconductor structure S1, the second semiconductor structure S2 is bonded such that the upper bonding pad 284 faces downward. The first semiconductor structure S1 and the second semiconductor structure S2 are directly bonded together without the use of an adhesive such as a separate adhesive layer.

[0167] With the first semiconductor structure S1 and the second semiconductor structure S2 joined together, the base substrate 300 exposed on the upper part of the second semiconductor structure S2 is removed, exposing the lower end of the channel structure CH. At this time, the information storage structure 245 on the second part of the exposed channel structure CH is removed. The information storage structure 245 is removed by a photolithography process and an etching process such as wet etching and / or dry etching. As a result, the channel layer 240 is exposed on the second part of the channel structure CH protruding onto the laminated structures GS1 and GS2, and the protruding portion 240a is positioned. Therefore, the channel layer 240 of the second part is in direct contact with the first conductive layer 201.

[0168] Next, as shown in Figure 3, a first conductive layer 201 is formed to cover the entire cell region R1. The first conductive layer 201 is formed by depositing a semiconductor layer, specifically a crystalline silicon layer, for example, a polycrystalline silicon layer. The first conductive layer 201 may be formed to have an inflection along the protruding channel structure CH, or it may be formed to a predetermined thickness with a flat upper surface. A second conductive layer 202 is formed on the first conductive layer 201. Specifically, the second conductive layer 202 can be formed in multiple layers. A buffer layer is conformally formed to cover the entire second conductive layer 202, and an oxide film, for example, a silicon oxide film, may be formed as the buffer layer.

[0169] Figure 15 is a schematic diagram showing a data storage system including a semiconductor device according to an exemplary embodiment.

[0170] Referring to Figure 15, the data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may also be a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the data storage system 1000 may be an SSD (solid state drive device), a USB (Universal Serial Bus), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0171] The semiconductor device 1100 is a non-volatile memory device, for example, the NAND flash memory device described above with reference to Figures 1 to 13. The semiconductor device 1100 includes a first semiconductor structure 1100F and a second semiconductor structure 1100S on the first semiconductor structure 1100F. According to an exemplary embodiment, the first semiconductor structure 1100F may be located next to the second semiconductor structure 1100S. The first semiconductor structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second semiconductor structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0172] In the second semiconductor structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0173] According to an exemplary embodiment, the upper transistors UT1 and UT2 include string selection transistors, and the lower transistors LT1 and LT2 include ground selection transistors. The lower gate lines LL1 and LL2 are the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 are the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0174] According to an exemplary embodiment, the lower transistors LT1, LT2 include ground selection transistors LT1, LT2 connected in series. The upper transistors UT1, UT2 include string selection transistors UT1, UT2 connected in series.

[0175] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 are electrically connected to the decoder circuit 1110 via a first connecting wire 1115 that extends from within the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connecting wire 1125 that extends from within the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0176] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors MCTs. The decoder circuit 1110 and the page buffer 1120 are controlled by the logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 via input / output pads 1101 which are electrically connected to the logic circuit 1130. The input / output pads 1101 are electrically connected to the logic circuit 1130 via input / output coupling wiring 1135 which extends from within the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0177] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. According to one embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, in which case the controller 1200 controls the plurality of semiconductor devices 1000.

[0178] The processor 1210 controls the operation of the entire data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, and so on are transmitted. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. When the processor 1210 receives a control command from an external host via the host interface 1230, it controls the semiconductor device 1100 in response to the control command.

[0179] Figure 16 is a schematic perspective view showing a data storage system including a semiconductor device according to an exemplary embodiment.

[0180] Referring to Figure 16, an exemplary embodiment of the present invention, a data storage system 2000, includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001.

[0181] The main board 2001 includes a connector 2006 which includes a plurality of pins that connect to an external host. The number and arrangement of the plurality of pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. According to an exemplary embodiment, the data storage system 2000 communicates with the external host via one of the following interfaces: USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), or M-Phy for UFS (Universal Flash Storage). According to an exemplary embodiment, the data storage system 2000 is powered by a power supply provided by the external host via the connector 2006. The data storage system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied by the external host to a controller 2002 and a semiconductor package 2003.

[0182] The controller 2002 can write data to or read data from the semiconductor package 2003, thereby improving the operating speed of the data storage system 2000.

[0183] DRAM2004 is a buffer memory that mitigates the speed difference between the semiconductor package 2003, which is the data storage space, and the external host. DRAM2004 included in the data storage system 2000 also operates as a type of cache memory, providing space for temporarily storing data during control operations on the semiconductor package 2003. When DRAM2004 is included in the data storage system 2000, the controller 2002 further includes a DRAM controller for controlling DRAM2004, in addition to the NAND controller for controlling the semiconductor package 2003.

[0184] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b, which are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b are each semiconductor packages containing a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 disposed on the lower surface of each semiconductor chip 2200, connecting structures 2400 that electrically connect the semiconductor chips 2000 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chips 2200 and the connecting structures 2400 on the package substrate 2100.

[0185] The package substrate 2100 is a printed circuit board including the package upper pad 2130. Each semiconductor chip 2200 includes an input / output pad 2210. The input / output pad 2210 corresponds to the input / output pad 1101 in Figure 15. Each semiconductor chip 2200 includes a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 includes the semiconductor device described above with reference to Figures 1 to 13.

[0186] According to an exemplary embodiment, the connecting structure 2400 is a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130. Thus, in the first and second semiconductor packages 2003a and 2003b, respectively, the semiconductor chips 2200 are electrically connected to each other by bonding wires and electrically connected to the package top pads 2130 of the package substrate 2100. Depending on the embodiment, in the first and second semiconductor packages 2003a and 2003b, respectively, the semiconductor chips 2200 are electrically connected to each other by a connecting structure including through silicon vias (TSVs) instead of the bonding wire connecting structure 2400.

[0187] According to an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be contained in a single package. According to an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer board.

[0188] The present invention is not limited by the embodiments and drawings described above. Therefore, within the scope of the technical spirit of the present invention, various forms of substitution, modification, and alteration and combination of embodiments are possible by those with ordinary skill in the art, and these also fall within the technical scope of the present invention. [Explanation of symbols]

[0189] 10 Semiconductor Devices 101 First board 105 Source / Drain Area 110-element isolation layer 120 circuit elements 130 Lower wiring structure 180 Lower bonding structure 190 Lower capping layer CH channel structure MSc Address Isolation Area GS1, GS2 laminated structures MS separation area SS Insulation Area 201 First conductive layer 202 Second conductive layer CSL Common Sourceline 220 Interlayer insulating layer 230 gates 240 channel layer 245 Information storage structure 272 Channel Stud 275 Address Stud 280 Upper bonding structure 290 Upper capping layer

Claims

1. A first semiconductor structure comprising a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure, A second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure on the first semiconductor structure, The second semiconductor structure is A conductive layer, A laminated structure including an interlayer insulating layer and a gate electrode, which are laminated below the conductive layer in a first direction perpendicular to the upper surface of the conductive layer, A separation region that penetrates the laminated structure, extends in a second direction perpendicular to the first direction, and is separated from each other in a third direction perpendicular to the first and second directions, A channel structure including a channel layer and penetrating the laminated structure in the first direction, An address stud is positioned below at least one of the separation regions at a distance of a first separation distance along the second direction, A channel stud positioned below the channel structure, A semiconductor device comprising an upper wiring structure disposed below the laminated structure, connected to the channel studs, and spaced apart from the address studs.

2. Each of the address studs includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. Each of the channel studs includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface. The semiconductor device according to claim 1, characterized in that the lower surface of each of the address studs is located at the same level as the lower surface of each of the channel studs.

3. The upper surfaces of each of the address studs are located below the lower surface of at least one of the separation regions. Each of the address studs has a top surface width smaller than the bottom surface width. The semiconductor device according to claim 2, characterized in that the width of the lower surface of at least one of the isolation regions is greater than the width of the lower surface of each of the address studs.

4. The semiconductor device according to claim 3, characterized in that the lower surface of the at least one separation region is spaced apart in the first direction from the upper surfaces of each of the address studs.

5. The lower surface of the address stud and the upper wiring structure further include an upper insulating layer, The semiconductor device according to claim 2, characterized in that the address stud is electrically isolated from the upper wiring structure by the upper insulating layer.

6. The semiconductor device according to claim 1, characterized in that the length of each of the address studs in the first direction is the same as the length of each of the channel studs in the first direction.

7. The upper wiring structure is connected to the channel stud and includes a bit line extending in the third direction and spaced apart in the second direction. The semiconductor device according to claim 1, characterized in that the first separation distance is a multiple of the pitch of the bit line.

8. A first semiconductor structure comprising a first substrate, circuit elements on the first substrate, a lower wiring structure electrically connected to the circuit elements, and a lower bonding structure connected to the lower wiring structure, A second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure on the first semiconductor structure, The second semiconductor structure is A conductive layer, A laminated structure including an interlayer insulating layer and a gate electrode, which are laminated below the conductive layer in a first direction perpendicular to the upper surface of the conductive layer, A channel structure including a channel layer and penetrating the laminated structure in the first direction, The separation region includes an address separation group that extends through the laminated structure in a second direction perpendicular to the first direction, is separated from each other in a third direction perpendicular to the first and second directions, and includes a first address separation region and a second address separation region adjacent to the first address separation region in the third direction, Address studs are arranged below the first and second address separation regions at distances of 1 and r (where r is a natural number of 2 or more) of the unit separation distance along the second direction, A semiconductor device comprising a channel stud disposed below the channel structure.

9. The semiconductor device according to claim 8, characterized in that the address isolation group defines the isolation region arranged every nth in the third direction as the first address isolation region, and the isolation region following the first address isolation region as the second address isolation region.

10. A semiconductor storage device comprising a substrate and a first semiconductor structure including circuit elements on the substrate, a second semiconductor structure including a laminated structure including interlayer insulating layers and gate electrodes stacked in a first direction and a channel structure penetrating the laminated structure, and input / output pads electrically connected to the circuit elements, A controller is electrically connected to the semiconductor storage device via the input / output pads and controls the semiconductor storage device, The first semiconductor structure is A lower wiring structure electrically connected to the aforementioned circuit element, The lower bonding structure is further connected to the lower wiring structure, The second semiconductor structure is An upper wiring structure positioned below the aforementioned laminated structure, The upper bonding structure is connected to the upper wiring structure and joined to the lower bonding structure, A separation region extending through the laminated structure in a second direction perpendicular to the first direction, and separated from each other in a third direction perpendicular to the first and second directions, An address stud is positioned below at least one of the separation regions at a distance of a first separation distance along the second direction, Includes a channel stud disposed below the channel structure, A data storage system characterized in that the upper wiring structure is connected to the channel stud and separated from the address stud.

Images