Overhang reduction using pulse bias

Abstract

This provides a method for physical gas-phase deposition. [Solution] Embodiments of the present disclosure relate to a method for increasing the aperture width of a substrate feature by reducing the overhang of the deposited film. Some embodiments of the present disclosure utilize a high-energy bias pulse to etch the deposited film near the aperture of the substrate feature. Some embodiments of the present disclosure etch the deposited film without damaging the underlying substrate.

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to methods for physical vapor deposition. More specifically, embodiments of this disclosure relate to methods for reducing overhangs and improving the aperture width of PVD films deposited within features. [Background technology]

[0002] The miniaturization of semiconductor circuit elements has reached the point where feature sizes of 45nm, 32nm, 28nm, 20nm, and even smaller are being manufactured on a commercial scale. As dimensions continue to shrink, new challenges arise regarding process steps such as filling the gaps between circuit elements. As the width between elements continues to decrease, the gaps between elements are often higher and narrower, making it more difficult for gap-filling materials to fill the gaps without creating voids and weak seams.

[0003] In the manufacturing of semiconductor integrated circuits, sputtering, also known as physical vapor deposition (PVD), is used for depositing metals and other materials. The use of sputtering extends to the deposition of material layers onto the sidewalls of high aspect ratio holes or gaps, such as vias or other vertical interconnect structures.

[0004] In PVD techniques, material overgrowth or overhangs often occur at the top of the void before it is completely filled. When such overhangs occur, voids or seams can form in the void where the deposited material is separated by the overhang. This is sometimes referred to as breadloafing.

[0005] Current methods for reducing overhang utilize a continuous-wave (CW) bias applied to the substrate. However, these methods have a limited power range. Furthermore, CW bias can cause damage to the underlying substrate when operating at high power levels.

[0006] Accordingly, there is a need for a physical vapor deposition method that prevents or eliminates the formation of overhangs at the top of substrate features or gaps without damaging the underlying substrate. [Overview of the project]

[0007] One or more embodiments of this disclosure relate to a physical vapor deposition (PVD) method. This method involves sputtering a material target in a physical vapor deposition (PVD) chamber to form a material layer on a substrate surface having a feature that extends in depth from top to bottom. The feature has an opening width on the substrate surface defined by a first sidewall and a second sidewall. The transverse thickness at the top of the material layer is greater than the thickness on the first or second sidewall in the feature. An additional material layer is deposited on the substrate surface by biasing the substrate surface with a low-energy DC bias. The material layer is etched from the substrate surface by biasing the substrate surface with a high-energy DC bias. The difference between the transverse thickness on the substrate surface and the transverse thickness in the feature is reduced by alternating low and high energies at a predetermined frequency.

[0008] Additional embodiments of the present disclosure relate to a method for reducing overhang. This method involves biasing a substrate containing a material layer with a DC bias in a physical vapor deposition (PVD) chamber having a material target. The substrate includes a feature that extends in depth from the substrate surface to the bottom surface. The feature has an opening width on the substrate surface defined by a first sidewall and a second sidewall. The transverse thickness of the material layer on the substrate surface is greater than the transverse thickness within the feature. Low-energy and high-energy biases are alternately repeated at a predetermined frequency to reduce the difference between the transverse thickness on the substrate surface and the transverse thickness within the feature.

[0009] Further embodiments of the present disclosure relate to a method for depositing a copper liner. This method involves sputtering a copper target in a physical vapor deposition (PVD) chamber to form a copper layer on a substrate surface including a feature that extends to a depth from the substrate surface to the bottom surface. The feature has an opening width on the substrate surface defined by a first sidewall and a second sidewall. The transverse thickness of the copper layer on the substrate surface is greater than the transverse thickness in the feature. An additional copper layer is deposited on the substrate surface by biasing the substrate surface with a low-energy DC bias in the range of about 50 W to about 100 W. The copper layer is etched from the substrate surface by biasing the substrate surface with a high-energy DC bias in the range of about 1000 W to about 1500 W. The difference between the transverse thickness on the substrate surface and the transverse thickness in the feature is reduced by alternating between low and high energies at a predetermined frequency of about 1 kHz.

[0010] To allow for a more detailed understanding of the features of this disclosure described above, a more specific description of this disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that this disclosure may also permit other equally valid embodiments, and therefore the accompanying drawings only illustrate typical embodiments of this disclosure and should not be considered to limit the scope of this disclosure. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of an exemplary substrate having features according to one or more embodiments of the present disclosure. [Figure 2] This is an illustrative flowchart of a processing method according to one or more embodiments of the present disclosure. [Figure 3] This is a cross-sectional view of an exemplary substrate including a material layer having an overhang according to one or more embodiments of the present disclosure. [Figure 4] This is a waveform diagram of a DC bias applied to a substrate according to one or more embodiments of the present disclosure. [Figure 5]This is a cross-sectional view of an exemplary substrate including a material layer having a reduced overhang according to one or more embodiments of the present disclosure. [Figure 6] This is a schematic cross-sectional view of a physical vapor deposition (PVD) chamber according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0012] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the structural or process step details described below. Other embodiments of this disclosure are possible and can be carried out or implemented in various ways.

[0013] As used herein and in the appended claims, the term “substrate” refers to the surface or portion of a surface on which the process acts. Those skilled in the art will understand that unless otherwise explicitly indicated by the context, a reference to a substrate may also refer to only a portion of the substrate. In addition, a reference to depositing on a substrate can mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0014] In this specification, “substrate” means any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment can be performed include, depending on the application field, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or firing of the substrate surface. In addition to direct film treatment of the surface of the substrate itself, the disclosure may also perform any of the disclosed film treatment steps on an underlying layer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as indicated by the context. Therefore, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015] One or more embodiments of the present disclosure relate to methods for reducing overhangs formed by physical vapor deposition. Some embodiments of the present disclosure are advantageous in providing a deposition-etching cycle that removes overhangs without damaging the underlying substrate. Some embodiments of the present disclosure are advantageous in facilitating subsequent metallization by providing larger feature openings.

[0016] An exemplary substrate 82 for processing according to one or more embodiments is shown in Figure 1. In some embodiments, the substrate 84 includes a base material 15 having an exposed surface also called a substrate surface 18. The substrate surface 18 includes a feature 20 extending to a depth D from the top 22 to the bottom 26. The feature has an opening width W defined by a first side wall 24 and a second side wall 25. OIt has. In some embodiments, the first sidewall 24 and the second sidewall 25 are opposite surfaces of a continuous sidewall (e.g., a circular via).

[0017] In some embodiments, the opening width W O is within the range of about 8 nm to about 25 nm or within the range of about 10 nm to about 20 nm. In some embodiments, the opening width W O is about 10 nm, about 14 nm, about 16 nm, about 20 nm, or about 22 nm.

[0018] In some embodiments, the base material 15 includes a dielectric. In some embodiments, the base material 15 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, or silicon oxycarbide. In some embodiments, the base material 15 consists essentially of silicon oxide. When used in this context, a material consisting essentially of the recited material includes about 95% or more, about 98% or more, about 99% or more, or about 99.5% or more of the recited material on a molar basis.

[0019] Referring to FIGS. 2 and 3, an exemplary method 100 for processing a substrate 82 begins with an optional operation 110 and sputters a material target in a physical vapor deposition (PVD) chamber to form a material layer 30 having an overhang 40 on the substrate surface 18. The lateral thickness T1 at the top 22 of the feature 20 of the material layer 30 is greater than the thickness T S on the sidewall 24 within the feature 20. The difference between T1 and T S is referred to as the overhang 40. In the deposited state of the material layer 30, the opening W O of the feature at the top of the feature is smaller than the width of the feature between the sidewalls 24, 25.

[0020] In some embodiments, the sputtering process forms a material layer 30 having a thickness within the range of about 10 nm to about 20 nm or within the range of about 12 nm to about 18 nm on the substrate surface 18 outside the feature 20. In some embodiments, the sputtering process forms a material layer 30 having a thickness of about 15 nm on the substrate surface 18 outside the feature 20.

[0021] The material target and the material layer 30 include the same material. In some embodiments, the material includes a conductor. In some embodiments, the material includes one or more of copper, tungsten, cobalt, ruthenium, molybdenum, indium, iridium, or rhodium. In some embodiments, the material includes a dielectric. In some embodiments, the material includes one or more of titanium nitride, tantalum nitride, ruthenium nitride, aluminum nitride, silicon oxide, aluminum oxide, or aluminum oxynitride.

[0022] The method 100 continues by reducing the overhang 40 by a deposition-etch cycle, also referred to as the dep-etch cycle 120. The dep-etch cycle 120 includes one deposition stage 122 and one etching stage 124. Although FIGS. 2 and 4 show the deposition stage 122 preceding the etching stage 124, this order is not limiting and those skilled in the art will understand that any stage may be executed first during any dep-etch cycle 120. The dep-etch cycle 120 may begin with either the deposition stage 122 or the etching stage 124.

[0023] The deposition stage 122 deposits an additional material layer 30 on the substrate surface 18 by applying a bias to the substrate surface 18 with a low energy DC bias. In some embodiments, the low energy is within the range of about 10 W to about 100 W, within the range of about 20 W to about 100 W, within the range of about 50 W to about 100 W, or within the range of about 50 W to about 75 W. In some embodiments, the low energy is about 70 W.

[0024] The etching step 124 etches the material layer 30 from the substrate surface 18 by biasing the substrate surface 18 with a high-energy DC bias. In some embodiments, the high energy is in the range of about 200W to about 3000W, about 500W to about 2500W, or about 1000W to about 2000W. In some embodiments, the high energy is about 1400W.

[0025] While not bound by theory, it is considered that high-energy biases cannot be applied to the substrate surface 18 for extended periods. If a high-energy bias is applied for too long, the base material 15 may be damaged by the bias, or this energy may generate an electric arc from the substrate to other parts of the processing chamber. Accordingly, the inventors have surprisingly found that by using short bursts of high-energy and low-energy biases, the material layer 30 can be etched without damaging the underlying base material 15. In some embodiments, the substrate is substantially undamaged. Substrate damage can be evaluated physically in the case of physical layer damage (layer separation, adhesion), by TEM in the case of structural damage, by EELS analysis in the case of chemical damage, or by electroanalysis in the case of complex damage.

[0026] During the dep-etch cycle 120, the deposition stage 122 and the etching stage 124 are repeated alternately. In some embodiments, the time between the deposition stage 122 and the etching stage 124 is minimized. Figure 4 shows the waveform 200 of the bias power over time during the dep-etch cycle 120. The deposition stage 122 is performed during period t D In region 210 having the following characteristics, it is shown that the energy is low. The etching step 124 is performed during period t E In region 220, which contains [the specified element], it has been shown that the energy level is high.

[0027] The waveform 200 shown in FIG. 4 is different from a continuous wave (CW) waveform. In a CW waveform, the bias energy increases and decreases gently, forming a sine-type wave with peaks and valleys at high and low energies. The inventors have found that in a CW-type bias waveform, the high-energy bias is much lower than that which can be applied to the substrate surface 18 without damaging the base material 15. In contrast, the waveform 200 of the present invention rapidly transitions from the low-energy bias in region 210 to the high-energy bias in region 220.

[0028] The frequency of the bias power is controlled. In some embodiments, this frequency is within the range of about 1 Hz to about 10 kHz or within the range of about 100 Hz to about 5 kHz. In some embodiments, the frequency is about 1 kHz.

[0029] The duty cycle is the ratio of the time spent applying the high-energy bias to the substrate surface within one cycle. In some embodiments, the duty cycle is within the range of about 5% to about 95%, within the range of about 10% to about 90%, within the range of about 20% to about 80%, within the range of about 30% to about 70%, within the range of about 40% to about 60%, or within the range of about 45% to about 55%. In some embodiments, the duty cycle is about 50%.

[0030] The dep-etch cycle 120 is repeated until a sufficient thickness of the overhang 40 is removed. As shown in FIG. 5, after a plurality of dep-etch cycles, the substrate 82 has a material layer 30 including a reduced overhang 40. In other words, the difference between the reduced lateral thickness T2 at the top 22 of the feature 20 and the thickness T on the sidewall 24 within the feature 20 is reduced. In some embodiments, the thickness T within the feature does not substantially change by the dep-etch cycle 120. In some embodiments, the thickness T within the feature is increased by the dep-etch cycle 120. S and is reduced. In some embodiments, the thickness T within the feature S does not substantially change by the dep-etch cycle 120. In some embodiments, the thickness T within the feature S is increased by the dep-etch cycle 120.

[0031] In some embodiments, the dep-etch cycle 120 deposits an additional material layer on the outer substrate surface 18 of the feature 20. In some embodiments, the dep-etch cycle 120 deposits a material layer of about 2 nm or more, about 4 nm or more, about 6 nm or more, or about 8 nm or more on the outer substrate surface 18 of the feature. In some embodiments, the dep-etch cycle 120 deposits a material layer of about 6 nm on the outer substrate surface 18 of the feature 20.

[0032] At decision point 130, the opening width W of feature 20. O It is determined whether it is sufficient. Opening width W O If this is insufficient, method 100 returns to perform an additional dep-etch cycle 120. Aperture width W O If sufficient, the board can undergo further processing in operation 140.

[0033] In some embodiments, a further process of operation 140 includes depositing a conductive filler material within feature 20. In some embodiments, the conductive filler material comprises a material different from that of material layer 30. In some embodiments, the conductive filler material comprises a metal or a metallic alloy. In some embodiments, the conductive filler material comprises one or more of copper, tungsten, cobalt, ruthenium, molybdenum, indium, iridium, or rhodium.

[0034] In some embodiments, before sputtering the material target, the aperture width of feature 20 is in the range of approximately 10 nm to approximately 20 nm. By sputtering the material target, a material layer 30 having a thickness of approximately 15 nm is formed on the outer substrate surface 18 of feature 20. By alternately repeating low and high energies, an additional material layer having a thickness of approximately 6 nm is formed on the outer substrate surface 18 of feature 20. In this embodiment, after sputtering the material target and alternately repeating low and high energies, the aperture width of feature 20 is approximately 7 nm or more.

[0035] An exemplary physical vapor deposition chamber 50 useful for one or more embodiments of the method is shown in Figure 6. The physical vapor deposition chamber 50 includes a vacuum chamber 52 arranged around a central axis 54, on which a target 56 is supported by an insulator 58, the insulator 58 vacuum-sealing the target 56 to the vacuum chamber 52 and electrically isolating the target 56 from the electrically grounded vacuum chamber 52. A vacuum pump system (not shown) pumps air into the vacuum chamber 52 to a low milliliter range pressure.

[0036] In one or more embodiments, the front surface of the target 56 can be flat, or it can be substantially concave, with its outer edge being thicker than the inner diameter portion. The target 56 includes a material layer facing the inside of the vacuum chamber 52, which typically contains 5 atomic percent or less of elements other than the material deposited to provide the sputtering material source.

[0037] The DC power supply 60 applies a negative bias to the target of a grounded vacuum chamber 52 or a grounded sidewall shield (not shown) to excite the plasma gas into plasma. In some embodiments, the plasma gas is supplied from a gas source 62 into the vacuum chamber 52 through a mass flow controller 64.

[0038] In one or more embodiments, the plasma gas includes one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe). In some embodiments, the plasma gas includes one or more of helium (He), neon (Ne), or argon (Ar).

[0039] In one or more embodiments, target power supplied by a DC power supply 60 excites a plasma processing gas into a plasma, and the positively charged ions of the plasma are accelerated toward the target 56, sputtering the material from the target 56. The plasma density is increased by positioning a magnetron 66 behind the back of the target 56, with an inner pole 68 of one magnetic polarity surrounded by an outer pole 70 of the opposite magnetic polarity. The poles 68, 70 project a magnetic field parallel to the plane of the target 56 into the vacuum chamber 52 to confine electrons, thus increasing the plasma density and the resulting sputtering rate. To improve sputtering uniformity and target utilization, the poles 68, 70 are asymmetrical about the central axis 54 but are supported by arms 72 connected to a shaft 74 extending along the central axis 54. A motor 76 rotates the shaft 74, and therefore the magnetron 66, about the central axis 54 to provide at least directional uniformity.

[0040] The substrate 82 is supported in a position facing the target 56 so that the pedestal 80 in the vacuum chamber 52 is covered with material to be sputtered from the target 56. The signal generator 86 includes a DC power supply 84 and a waveform generator 67 to bias the pedestal 80. The pedestal 80 is conductive and therefore acts as an electrode. The DC bias, with plasma present in the vacuum chamber 52, creates a negative DC self-bias on the pedestal 80, so that the sputtered metal ions are accelerated toward the substrate 82, and the orbits of such ions enter deep into high aspect ratio holes or features formed in the substrate 82.

[0041] The operation of the physical vapor deposition chamber 50 is controlled by a controller 40. The controller 40 is coupled to one or more of the motor 76, DC power supply 60, signal generator 86, or mass flow controller 64. In some embodiments, two or more controllers 40 are connected to individual components, and a primary control processor is coupled to each of separate processors to control the physical vapor deposition chamber 50. The controller 40 can be one of any form of general-purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial environment to control various chambers and subprocessors.

[0042] At least one controller 40 may have a processor 42, memory 44 coupled to the processor 42, input / output devices 46 coupled to the processor 42, and support circuits 48 for communication between different electronic components. The memory 44 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0043] The processor's memory 44 or computer-readable medium can be one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. Memory 44 can hold a set of instructions operable by the processor 42 to control the parameters and components of the physical vapor deposition chamber 50. Support circuitry 48 is coupled to the processor 42 to conventionally support the processor. The circuitry may include, for example, a cache, power supply, clock circuitry, input / output circuitry, subsystems, and the like.

[0044] In general, a process can be stored in memory as a software routine, and such a software routine, when executed by a processor, causes the process of the present disclosure to run in a process chamber. The software routine can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Thus, a process can be implemented in software and executed using a computer system in hardware, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into a purpose-specific computer (controller) that controls the chamber operation so that the process can run.

[0045] In some embodiments, the controller 40 has one or more configurations for executing individual processes or subprocesses to carry out the method. The controller 40 can be connected to intermediate components and can be configured to operate the intermediate components to carry out the function of the method. For example, the controller 40 can be connected to one or more of the following and can be configured to control them: gas valves, actuators, motors, slit valves, vacuum control devices, etc.

[0046] In some embodiments, the controller 40 has one or more configurations selected from configurations for rotating the shaft 74, for biasing the target 56, for biasing the substrate 82, for adding a waveform to the substrate bias, or for controlling the flow of plasma gas.

[0047] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that the specific features, structures, materials, or properties described in relation to that embodiment are included in at least one embodiment of this disclosure. Therefore, any mention of phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, specific features, structures, materials, or properties can be combined in any preferred manner.

[0048] While the disclosures herein have been described with reference to specific embodiments, it will be understood by those skilled in the art that the embodiments described are merely illustrative examples of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of physical gas-phase deposition, The method involves sputtering a material target in a physical vapor deposition (PVD) chamber to form a material layer on a substrate surface that includes a feature extending in depth from the top to the bottom, wherein the feature has an opening width defined by a first sidewall and a second sidewall on the substrate surface, and the lateral thickness of the material layer at the top surface is greater than the thickness on the first sidewall or the second sidewall within the feature. By applying a bias to the substrate surface with a low-energy DC bias, an additional material layer is deposited on the substrate surface. By applying a high-energy DC bias to the substrate surface, the material layer is etched from the substrate surface. A method comprising alternating between the low energy and the high energy at a predetermined frequency to reduce the difference between the lateral thickness on the substrate surface and the lateral thickness within the feature.

2. The method according to claim 1, wherein the substrate is not substantially damaged.

3. The method according to claim 2, wherein the duty cycle of the DC bias is approximately 50%.

4. The method according to claim 1, wherein the material target comprises copper.

5. The method according to claim 1, wherein the low energy is in the range of about 50W to about 100W.

6. The method according to claim 1, wherein the high energy is in the range of about 1000W to about 3000W.

7. The method according to claim 1, wherein the predetermined frequency is in the range of about 1 Hz to about 10 kHz.

8. The method according to claim 1, wherein sputtering the material target forms a material layer having a thickness of about 15 nm on the substrate surface.

9. The method according to claim 1, wherein alternating between the low energy and the high energy forms a material layer having a thickness of approximately 6 nm on the substrate surface.

10. The method according to claim 1, wherein, before sputtering the material target, the aperture width of the feature is in the range of about 10 nm to about 20 nm.

11. The method according to claim 1, wherein, before sputtering the material target, the aperture width of the feature is in the range of about 10 nm to about 20 nm, as a result of sputtering the material target, a material layer having a thickness of about 15 nm is formed on the substrate surface, a material layer having a thickness of about 6 nm is formed on the substrate surface by alternately repeating the low energy and the high energy, the material target is sputtered, and after alternately repeating the low energy and the high energy, the aperture width of the feature is about 7 nm or more.

12. The method according to claim 1, further comprising reducing the difference between the lateral thickness on the substrate surface and the lateral thickness within the feature, and then depositing a conductive filler material within the feature.

13. A method for reducing overhang, The bias is applied to a substrate containing a material layer with a DC bias in a physical vapor deposition (PVD) chamber having a material target, wherein the substrate includes a feature that extends in depth from the substrate surface to the bottom surface, the feature has an opening width defined by a first side wall and a second side wall on the substrate surface, and the lateral thickness of the material layer on the substrate surface is greater than the lateral thickness within the feature, and the bias is applied accordingly. A method comprising alternating between low-energy bias and high-energy bias at a predetermined frequency to reduce the difference between the lateral thickness on the substrate surface and the lateral thickness within the feature.

14. The method according to claim 13, wherein the substrate is not substantially damaged by applying a bias to the substrate and alternating between a low-energy bias and a high-energy bias.

15. The method according to claim 14, wherein the duty cycle of the DC bias is approximately 50%.

16. The method according to claim 13, wherein the material layer contains copper.

17. The method according to claim 13, wherein the low-energy bias is in the range of about 50W to about 100W.

18. The method according to claim 13, wherein the high-energy bias is in the range of about 1000W to about 3000W.

19. The method according to claim 13, wherein the predetermined frequency is in the range of about 1 Hz to about 10 kHz.

20. A method for depositing a copper liner, The method involves sputtering a copper target within a physical vapor deposition (PVD) chamber to form a copper layer on the substrate surface, characterized in that the layer extends to a depth from the substrate surface to the bottom surface, wherein the layer has an opening width defined by a first side wall and a second side wall on the substrate surface, and the lateral thickness of the copper layer on the substrate surface is greater than the lateral thickness within the characteristic. By applying a DC bias of low energy in the range of approximately 50W to approximately 100W to the substrate surface, an additional copper layer is deposited on the substrate surface. By applying a DC bias of high energy in the range of approximately 1000W to approximately 1500W to the substrate surface, the copper layer is etched from the substrate surface. A method comprising alternating between the low energy and the high energy at a predetermined frequency of approximately 1 kHz to reduce the difference between the lateral thickness on the substrate surface and the lateral thickness within the feature.

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