Semiconductor equipment

Abstract

To provide a semiconductor device with a novel configuration. To provide a semiconductor device with reduced power consumption. To provide. [Solution] In a transistor having a gate and a back gate, in the first state the gate The input terminals are applied to both the gate and the back gate, and in the second state, the input is only applied to the gate. The configuration includes a circuit for supplying signals from the power terminals. The current supply capacity of the inverter can be switched for each operation, and the back gate can be charged. This can reduce power consumption.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a display module, and electronic equipment.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Or, one aspect of the present invention. This refers to a process, machine, manufacture, or composition. This relates to (a). Therefore, one aspect of the present invention disclosed more specifically herein In terms of technology fields, semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, and related Driving methods, or methods for manufacturing them, can be given as examples.

[0003] In this specification, a semiconductor device is defined as an element that can function by utilizing semiconductor properties. This refers to a component, circuit, or device. Examples include semiconductor elements such as transistors and diodes. It is a semiconductor device. Another example is a circuit having semiconductor elements, which is a semiconductor device. Yes. Another example is a device equipped with a circuit having semiconductor elements, which is a semiconductor device. ru. [Background technology]

[0004] Display devices are trending toward higher performance, such as narrower bezels, multi-level color depth, and higher resolution. The drive circuit, which is designed to achieve high performance, has high dynamic characteristics (on-response and frequency characteristics (f-response) and A call is required.

[0005] For example, in Patent Documents 1 to 3, in order to improve the dynamic characteristics, a part of the transistor in the drive circuit A transistor (hereinafter referred to as a dual-gate transistor) has gate electrodes on both the top and bottom of the semiconductor layer. A semiconductor device with a configuration called an "energister" is disclosed. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2010 / 0102313 [Patent Document 2] U.S. Patent Application Publication No. 2010 / 0102314 [Patent Document 3] U.S. Patent Application Publication No. 2010 / 0301326 [Overview of the project] [Problems that the invention aims to solve]

[0007] As mentioned above, there are many configurations for semiconductor devices. Each configuration has one Each has its advantages and disadvantages, and the appropriate configuration is selected depending on the situation. Therefore, a novel semiconductor device configuration... If we can propose this, it will lead to an increase in the degree of freedom of choice.

[0008] Therefore, one aspect of the present invention relates to a novel semiconductor device having a configuration different from existing semiconductor devices. One of the objectives is to provide novel display modules, novel electronic devices, etc.

[0009] In a dual-gate transistor, one gate electrode (hereinafter referred to as the gate) and By applying voltage from both sides of the other gate electrode (hereinafter referred to as the back gate), the dynamic characteristics are improved. However, when displaying information that does not require improved dynamic characteristics, one of the semiconductor layers A transistor with a gate on one side (hereinafter referred to as a single-gate transistor) In some cases, this is better in terms of power consumption. In other words, with a dual-gate transistor, the dynamics The sexual capacity becomes excessive, requiring extra power to operate. .

[0010] Therefore, one aspect of the present invention is a state in which it operates as a dual gate and a single gate traction This invention provides a novel semiconductor device with a configuration that allows switching between operating as an inverter and other functions. One of the challenges is to achieve this. Another aspect of the present invention involves charging and discharging the back gate depending on the state. One of the objectives is to provide a semiconductor device with a novel configuration that can reduce the power consumption required. do.

[0011] The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Issues not mentioned in this section can be found in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention addresses at least of the above-listed issues and / or other issues. It solves one problem. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first transistor, a second transistor, and a circuit, The gate of the first transistor is electrically connected to the first input terminal, and the first transistor Either the source or drain of the transistor is electrically connected to the first wiring, and the first transistor The source or drain of the transistor is electrically connected to the output terminal, and the second transistor The gate of the transistor is electrically connected to the second input terminal, and the source of the second transistor is also One side of the drain is electrically connected to the second wiring, and the source of the second transistor is also The other end of the drain is electrically connected to the output terminal, and the circuit, according to the control signal, A first state in which the input terminal 1 and the back gate of the first transistor are electrically connected, A second state in which the output terminal and the back gate of the first transistor are electrically connected, and a closed state It is a semiconductor device that has a replacement function.

[0013] In one embodiment of the present invention, the circuit has a first switch and a second switch, and controls The signal is obtained by alternately turning the first switch and the second switch on and off. A semiconductor device is preferred, which is a signal that switches between state 1 and state 2.

[0014] In one embodiment of the present invention, the first switch and the second switch are transistors. A semiconductor device is preferred.

[0015] In one embodiment of the present invention, the second transistor is electrically connected to the second input terminal. A semiconductor device having a back gate is preferred.

[0016] In one embodiment of the present invention, a third transistor is provided, wherein the third transistor is at the input terminal It is placed between the child and the gate of the first transistor, and the gate of the third transistor is A semiconductor device that is electrically connected to wiring that provides a high potential is preferred.

[0017] Further aspects of the present invention will be described in the following embodiments, and It is shown in the drawing. [Effects of the Invention]

[0018] One aspect of the present invention proposes a novel semiconductor device, a novel display module, a novel electronic device, etc. It can be provided.

[0019] Alternatively, one aspect of the present invention is a state in which it operates as a dual-gate transistor and a single A novel semiconductor configuration that can switch between operating as a glugate transistor and another state. The present invention can provide devices and the like. In another aspect of the present invention, depending on the state, the back gate We can provide a semiconductor device with a novel configuration that can reduce the power consumption required for charging and discharging. ru.

[0020] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention includes, among the effects listed above and / or other effects, at least It has one effect. Therefore, one aspect of the present invention may, in some cases, be the one enumerated above. It may not always have the desired effect. [Brief explanation of the drawing]

[0021] [Figure 1] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 2] A circuit diagram illustrating one aspect of the present invention. [Figure 3] A circuit diagram illustrating one aspect of the present invention. [Figure 4] A circuit diagram and timing chart illustrating one aspect of the present invention. [Figure 5] A circuit diagram illustrating one aspect of the present invention. [Figure 6] A top view illustrating one aspect of the present invention. [Figure 7] A top view illustrating one aspect of the present invention. [Figure 8] A circuit diagram illustrating one aspect of the present invention. [Figure 9] A circuit diagram illustrating one aspect of the present invention. [Figure 10] A circuit diagram illustrating one aspect of the present invention. [Figure 11] A timing chart illustrating one aspect of the present invention. [Figure 12] A circuit diagram illustrating one aspect of the present invention. [Figure 13] A top view and a cross-sectional view illustrating one aspect of the present invention. [Figure 14] A cross-sectional view illustrating one aspect of the present invention. [Figure 15] A cross-sectional view illustrating one aspect of the present invention. [Figure 16] A cross-sectional view illustrating one aspect of the present invention. [Figure 17] A top view illustrating one aspect of the present invention. [Figure 18] A cross-sectional view illustrating one aspect of the present invention. [Figure 19] A projection drawing illustrating one aspect of the present invention. [Figure 20] A cross-sectional view illustrating one aspect of the present invention. [Figure 21] A diagram illustrating an electronic device according to one aspect of the present invention. [Figure 22] A diagram illustrating the measurement results of the XRD spectrum of a sample. [Figure 23] A diagram illustrating the TEM image and electron diffraction pattern of the sample. [Figure 24] A diagram illustrating the EDX mapping of a sample. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, many of the embodiments differ. It is possible to implement it in any manner, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, the present invention The following embodiments are not to be interpreted as being limited to their contents.

[0023] In this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to the constituent elements. This is added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the constituent elements.

[0024] In the drawings, elements that are identical or have similar functions, elements made of the same material, etc. In some cases, elements formed simultaneously may be given the same symbol, and the explanation for this repetition is as follows: It may be omitted in some cases.

[0025] (Embodiment 1) This embodiment describes an example of a semiconductor device.

[0026] Figure 1(A) is a circuit diagram illustrating the semiconductor device 100. The semiconductor device 100 is It can be used as part of the drive circuit of a display device.

[0027] The semiconductor device 100 shown in Figure 1(A) includes transistor 101, transistor 102, and It also has a switching circuit 103. In Figure 1(A), input terminals IN and INB The output terminal OUT, wiring 104, and wiring 105 are shown in the diagram.

[0028] Transistor 101 is in a conductive state between its source and drain, i.e., between the wiring 104 and the drain. It controls the conduction state between the power terminal OUT. Transistor 101 controls the gate and back gate. This is a dual-gate transistor having a gate. The conduction state of transistor 101 is gate The voltage applied to the input terminal IN and the voltage applied to the back gate control the signal. It is controlled. Hereafter, transistor 101 will be described as an n-channel transistor.

[0029] Transistor 102 has a conductive state between its source and drain, i.e., it is connected to wiring 105. It controls the conduction state between the power terminal OUT. Transistor 102 has a gate. This is a gate transistor. The conduction state of transistor 102 is given to the gate. It is controlled by the voltage of the input terminal INB. Hereinafter, transistor 102 is an n-channel transistor. Let's explain it as a type of transistor.

[0030] The switching circuit 103 controls the back gate of transistor 101 by the control signal φ. Connect the power terminal IN, or the back gate of transistor 101 to the output terminal OU. It is possible to connect to T or to switch between them. The switching circuit 103 is simply a circuit Sometimes.

[0031] The input signal applied to input terminal INB is, for example, the input signal applied to input terminal IN. This corresponds to the inverted signal. Wiring 104 is, for example, a constant potential (V) corresponding to a high potential. DD ) A constant potential (V) corresponding to a low potential is given. Wiring 105 is, for example, a constant potential (V) corresponding to a low potential. SS , GND etc. A clock signal or reset signal, etc., is given to wiring 104 or wiring 105. It is acceptable to have a configuration that can be obtained.

[0032] Figure 1(B) shows the timing to explain the operation of the semiconductor device 100 shown in Figure 1(A). This is a chart. Figure 1(B) shows the waveform of input terminal IN, the waveform of input terminal INB, and the control signal. The waveform of terminal φ and the waveform of the output terminal OUT are shown. In Figure 1(B), the waveform of the signal is Accordingly, it can be explained by dividing it into a first period P1 and a second period P2.

[0033] As shown in Figure 1(B), the waveform of input terminal IN and the waveform of input terminal INB are inverted. The relationship is as follows: During the first period P1, the control signal φ is at the H level. During the second period P2, The control signal φ is set to L level. The waveform of the output terminal OUT is as follows: It varies depending on the potential or signal, but for example, if a constant potential corresponding to a high potential is applied to wiring 104 Therefore, if a constant potential equivalent to a low potential is applied to wiring 105, the waveform at input terminal IN will The waveform will be determined accordingly.

[0034] As described above, the switching circuit 103 switches the connection state according to the control signal φ. During the first period P1, the back gate of transistor 101 is connected to the input terminal IN. In other words, the circuit diagram shown in Figure 1(C) is in a state where transistor 1 is present. Also, during the second period P2, transistor 1 Connect the back gate of 01 to the output terminal OUT. In other words, the circuit diagram is as shown in Figure 1(D). To become.

[0035] In the circuit diagram shown in Figure 1(C), transistor 101 is a dual-gate transistor and Because it operates in this manner, it has high dynamic characteristics (on-response and frequency characteristics (called f-response)). This becomes possible. Therefore, as shown in the first period P1 of Figure 1(B), the output terminal OUT The waveform can be made to be similar to the waveform of the input terminal IN. On the other hand, as shown in Figure 1(D) In the circuit diagram, transistor 101 operates as a single-gate transistor, This enables operation with suppressed dynamic characteristics. Therefore, as shown in the second period P2 in Figure 1(B) As shown, the waveform of the output terminal OUT is a blunted waveform (solid line) compared to the waveform of the input terminal IN (dotted line). It is possible.

[0036] The difference between the operation in Figure 1(C) and the operation in Figure 1(D) is shown in Figures 2(A), (B), and Figure 2(A, B, and D). This can be explained using the circuit diagrams shown in 2(C) and (D). In Figures 2(A) to (D), the input The high level of the signal potential applied to the power terminals IN and INB and the output terminal OUT is designated as 'H', and the low level is designated as 'H'. Bell is represented as 'L'. Also, in Figures 2(A) to (D), high level or low By applying a level to the transistor, positive charges accumulate on the gate and back gate. A negative charge is schematically illustrated. In Figures 2(A) to (D), wiring 104 is V D D And wiring 105 is V SS That is what they say.

[0037] Figures 2(A) and (B) schematically illustrate the operation of a dual-gate transistor. They are doing it.

[0038] In Figure 2(A), the potential of input terminal IN is set to high level, and the potential of input terminal INB is set to low level. The positive and negative charges accumulated on the gate and back gate when the gate is closed are schematically illustrated. Transistor 101 is charged with a positive charge by the potential of the input terminal IN. Since converter 101 becomes conductive, current I D1 A current flows through transistor 102. A negative charge is charged by the potential of terminal INB. Transistor 102 becomes non-conductive. The potential of the output terminal OUT will be high level.

[0039] In Figure 2(B), the potential of input terminal IN is set to low level, and the potential of input terminal INB is set to high level. The positive and negative charges accumulated on the gate and back gate when the gate is closed are schematically illustrated. Transistor 101 is charged with a negative charge by the potential of the input terminal IN. Transistor 101 becomes non-conductive. Transistor 102 is at the potential of input terminal INB. Therefore, a positive charge is accumulated. Transistor 102 becomes conductive. The rank will be low.

[0040] As shown in Figures 2(A) and (B), in dual-gate operation, transistor 101 Therefore, both the gate and the back gate are charged with either a positive or negative charge, An electric field is easily applied to the Nell formation region, and current I D1 It can be made larger. This allows for operation with improved dynamic characteristics.

[0041] On the other hand, Figures 2(C) and (D) schematically show the operation when it is a single-gate transistor. It represents it accurately.

[0042] In Figure 2(C), the potential of input terminal IN is set to high level, and the potential of input terminal INB is set to low level. This diagram schematically illustrates the positive and negative charges accumulated at the gate when a transistor is in operation. Transistor 101 is charged with a positive charge by the potential of the input terminal IN. Transistor 101 is led Since it is in a flow state, current I D2 The current flows. Transistor 102 is at the potential of input terminal INB. Negative charge is charged by this. Transistor 102 becomes non-conductive. Output terminal OUT The potential becomes high.

[0043] In FIG. 2(D), the positive and negative charges accumulated in the gate when the potential of the input terminal IN is at a low level and the potential of the input terminal INB is at a high level are schematically illustrated. The transistor 101 is charged with negative charges by the potential of the input terminal IN. The transistor 101 is in a non-conducting state. The transistor 102 is charged with positive charges by the potential of the input terminal INB. The transistor 102 is in a conducting state. The potential of the output terminal OUT becomes a low level. In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In FIG. 2(D), the positive and negative charges accumulated in the gate when the potential of the input terminal IN is at a low level and the potential of the input terminal INB is at a high level are schematically illustrated. The transistor 101 is charged with negative charges by the potential of the input terminal IN. The transistor 101 is in a non-conducting state. The transistor 102 is charged with positive charges by the potential of the input terminal INB. The transistor 102 is in a conducting state. The potential of the output terminal OUT becomes a low level. In FIG. 2(D), the positive and negative charges accumulated in the gate when the potential of the input terminal IN is at a low level and the potential of the input terminal INB is at a high level are schematically illustrated. The transistor 101 is charged with negative charges by the potential of the input terminal IN. The transistor 101 is in a non-conducting state. The transistor 102 is charged with positive charges by the potential of the input terminal INB. The transistor 102 is in a conducting state. The potential of the output terminal OUT becomes a low level. In FIG. 2(D), the positive and negative charges accumulated in the gate when the potential of the input terminal IN is at a low level and the potential of the input terminal INB is at a high level are schematically illustrated. The transistor 101 is charged with negative charges by the potential of the input terminal IN. The transistor 101 is in a non-conducting state. The transistor 102 is charged with positive charges by the potential of the input terminal INB. The transistor 102 is in a conducting state. The potential of the output terminal OUT becomes a low level.

[0044] In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. D2 as current I D1 In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. In the single-gate operation as shown in FIGS. 2(C) and (D), in the transistor 101, since positive or negative charges from the input terminal IN are charged on one side of the gate, an electric field is less likely to be applied to the channel formation region compared to the case of a dual gate, and the current I can be made smaller than the current I. As a result, an operation with suppressed dynamic characteristics can be performed. In FIG. 2(D), the positive and negative charges accumulated in the gate when the potential of the input terminal IN is at a low level and the potential of the input terminal INB is at a high level are schematically illustrated. The transistor 101 is charged with negative charges by the potential of the input terminal IN. The transistor

[0045] In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor. In the semiconductor device according to one aspect of the present invention described above, it is possible to switch between a state of operating as a dual-gate transistor and a state of operating as a single-gate transistor. Therefore, when performing a display that does not require enhanced dynamic characteristics, it can be operated as a single-gate transistor, and when performing a display that requires enhanced dynamic characteristics, it can be operated as a dual-gate transistor. The single-gate transistor can reduce the power consumption required for charging and discharging the back gate compared to the dual-gate transistor.

[0046] Furthermore, when displaying information that does not require improved dynamic characteristics, the frame frequency of the display device should be set to constant speed. There are cases where it is operated at 60Hz or lower. Also, displays that require improved dynamic characteristics If you choose to do so, operate it at double speed (120Hz) or quadruple speed (240Hz), etc. There are cases where the display changes, such as when watching sports or browsing websites. Switching the frame frequency is effective in reducing power consumption. Depending on the circumstances, switching the charging and discharging of the back gate as in one aspect of the present invention consumes power This is effective in further reducing [the amount].

[0047] The semiconductor device 100 shown in Figure 1(A) can be modified in various ways. Figure 3(A) Examples of modified forms are shown in (C).

[0048] The semiconductor device 100A in Figure 3(A) has an input terminal IN and the gate of transistor 101. This is a modified example in which transistor 106 is placed between them. The gate of transistor 106 is Wiring 107 is connected. Wiring 107 is preferably at a constant potential equivalent to a high potential. i. By using the configuration shown in Figure 3(A), the signal from input terminal IN is sent to the gate of transistor 106. This can provide the potential of the gate of transistor 101 to be equal to the potential of the output terminal OUT. When capacitive coupling occurs due to parasitic capacitance between the terminals, causing a rise in voltage, the potential of the input terminal IN rises. This can suppress that.

[0049] Furthermore, the semiconductor device 100B in Figure 3(B) has a dual gate transistor 102. This is a modified example using transistor 108. With this configuration, transistor 108 It can improve dynamic characteristics.

[0050] It is also possible to combine the modified examples described in Figure 3(A) and Figure 3(B). This results in semiconductor device 100C as shown in Figure 3(C). In Figure 3(C), the transistors in Figure 3(A) Transistor 106 is made into a dual-gate transistor 109, and transistor 102 is made into a dual gate This is a modified example in which transistor 108 is a dual-gate transistor. By adopting this configuration, The dynamic characteristics of transistor 109 and transistor 108 can be improved.

[0051] In Figure 4(A), the switching circuit 103 is based on the semiconductor device 100C shown in Figure 3(C). Let's explain an example of a specific circuit configuration.

[0052] The switching circuit 103 has transistors 110 and 111. Transistors 110 and 111 are both shown as dual-gate transistors in the diagram. This indicates that transistor 110 is in a conductive state between its source and drain, i.e., a transistor Controls the conductivity between the back gate of transistor 101 and the input terminal IN. Transistor 111 is in a conductive state between its source and drain, i.e., the back of transistor 101. The transistor 110 controls the conduction state between the gate and the output terminal OUT. The conduction state is controlled by φ. Transistor 111 receives the inverted signal of the control signal φ. The conduction state is controlled by the control signal φB. Note that transistor 110 and transistor STA111 will both be described as n-channel transistors.

[0053] Figure 4(B) illustrates the operation of the switching circuit 103 of the semiconductor device 100C shown in Figure 4(A). This is a timing chart to clarify. Figure 4(B) shows the waveform of the input terminal IN, input terminal The waveforms of child INB, control signal φ, control signal φB, and output terminal OUT are shown. In Figure 4(B), similar to Figure 1(B), the period is divided into a first period P1 and a second period P2. It can be explained in detail.

[0054] As shown in Figure 4(B), the waveform of control signal φ and the waveform of control signal φB are inverted. This is the result. During the first period P1, the control signal φ is at the H level and the control signal φB is at the L level. In the second period P2, the control signal φ is at the L level and the control signal φB is at the H level.

[0055] As shown in Figure 4(B), by controlling the control signal φ and control signal φB, the switching cycle The path 103 switches the connection state. In the first period P1, the back of transistor 101 The gate and the input terminal IN can be connected. In other words, transistor 101 can be dual It can be operated as a gate transistor. Also, in the second period P2, the transistor The back gate and output terminal OUT of the ST101 can be connected. The 101 can be operated as a single-gate transistor. Therefore, Because the dynamic characteristics of the transistor 101 can be switched, the second period P2 in Figure 4(B) As shown, the waveform of the output terminal OUT is a blunted waveform (actual) compared to the waveform of the input terminal IN (dotted line). It can be represented as a line.

[0056] The switching circuit 103 shown in Figure 4(A) can be modified in various ways. (B) and (A) illustrate an example of a modified form.

[0057] The switching circuit 103A of the semiconductor device 100C in Figure 5(A) is a transistor 11 In a modified version, 0 and transistor 111 are replaced with switches 110SW and 111SW. Yes, that is, transistors 110 and 111 can alternately enter a conductive state. It can be transformed into a different element.

[0058] Furthermore, the switching circuit 103B of the semiconductor device 100C in Figure 5(B) is a transistor This is a variation where 111 is replaced with a single-gate transistor 111S. Transistors 110 and 111 can be converted to either dual-gate or single-gate. It is possible to create a shape.

[0059] Figure 6 shows the semiconductor device 100C based on the semiconductor device 100C shown in Figure 4(A), and the upper part of the semiconductor device 100C. An example of a surface view is explained. Figure 6 shows conductive layer 121, conductive layer 122, semiconductor layer 123, and an opening. Layers 124 and 125 are formed sequentially and shown in the diagram, representing transistors and wiring. For the sake of simplicity, the insulating layers between conductive layers have been omitted.

[0060] In Figure 6, transistors 101, 108, and 108, as shown in Figure 4(A), are shown. Transistors 109, 110, and 111 are shown. The transistor is also a dual-gate transistor. Furthermore, Figure 6 shows the wiring shown in Figure 4(A). 104, Wiring 105, Wiring 107, Input terminal IN, Input terminal INB, Output terminal OUT, Control The wiring diagram shows how to supply signals φ and φB.

[0061] In transistor 101 in Figure 6, the conductive layer corresponding to the back gate is conductive layer 121. The conductive layer corresponding to the gate is conductive layer 125. The layer is wider in the channel length direction than the conductive layer corresponding to the gate. This is due to the charging and discharging of charge when switching between single-gate and dual-gate structures. The effect can be enhanced. Also, the transistor 110 that constitutes the switching circuit 103 Transistor 111 has a smaller transistor size compared to transistors 101 and 108. It is preferable that transistors 110 and 111 function as switches. Therefore, by adopting this configuration, the circuit area occupied by the transistors in the semiconductor device 100C can be reduced. It can be transformed.

[0062] In Figure 6, the conductive layer corresponding to the back gate is the conductive layer corresponding to the gate. Although it was described as a conductive layer 121 located below layer 125, the top-bottom relationship can be reversed. For example... As shown in Figure 7, the conductive layer corresponding to the back gate is the conductive layer 125, and the gate The corresponding conductive layer may be conductive layer 121. With this configuration, the back gate The corresponding conductive layer has a narrower width in the channel length direction than the conductive layer corresponding to the gate. This suppresses the deterioration of dynamic characteristics when using a single gate.

[0063] Next, in Figures 8 to 11, based on the semiconductor device 100C shown in Figure 4(A), input terminal I The diagram shows a circuit 200 that supplies a signal to input terminal INB, and a semiconductor device that drives a display device. This section describes an example configuration when applied to a circuit.

[0064] The circuit 200 shown in Figure 8(A) is connected to input terminals IN and INB. Device 100C amplifies the signals applied to input terminals IN and INB and outputs a buffer. It can function as a.

[0065] Note that the semiconductor device 100C, which functions as a buffer, is not limited to one per circuit 200. i. Multiple terminals may be provided as shown in Figure 8(B). In this case, the output terminal OUT is the output terminal It is preferable to provide separate terminals, designated as SROUT and OUT, depending on the connected circuit. i. By using this configuration, the buffer is configured according to the load of the connected circuit. Because the size of the transistor can be changed, the size can be reduced or adjusted to match the load. It is possible to design the model.

[0066] Next, we will explain a specific example of circuit 200, which is shown in Figures 8(A) and (B). Input terminal A circuit 200 controls the timing of the signals supplied to the child IN and input terminal INB, and a buffer and By combining it with a semiconductor device 100C that functions in this way, one stage of a shift register is formed. It can be made to function as a circuit.

[0067] Figure 9(A) shows an example of a circuit configuration for a shift register capable of outputting n+2 stages of pulses. Circuit SR and Circuit SR DUM This combines circuit 200 and semiconductor device 100C. This corresponds to the circuit shown. The shift register in Figure 9(A) receives a start pulse and a clock signal from an external source. Signals CLK1 to CLK4, pulse width control signals PWC1 to PWC4, reset signal RE S, control signals φ and φB, output terminals OUT_1 to OUT_n+2 (n is a natural number) It can output pulses. Although not shown in the diagram, there is a reset signal RES and a control signal. Signals φ and φB are signals applied to separate wiring.

[0068] The following signals are applied to circuit SR, as shown in Figure 9(B). DUM Figure 9(C) The following signals are given: Circuit SR and Circuit SR DUM In which, The clock signals CLK1 to CLK4 and pulse width control signals PWC1 to PWC4 differ for each stage. LIN is a signal supplied from the upper side of the shift direction in the shift register. RIN is a signal supplied from the lower side of the shift direction in the shift register. UT is the signal supplied to the next stage shift register. OUT is supplied to the wiring that will be the load. It is a signal that can be obtained.

[0069] An example of the circuit configuration of circuit SR is shown in Figure 10(A). The circuit 200 shown in Figure 10(A) is It has transistors 201 to 209. Transistors 201 to 209 are dual gates Although it is shown as a gate transistor, a single-gate transistor will suffice. Similarly, the circuit SR DUM An example of the circuit configuration is shown in Figure 10(B).

[0070] Figure 11 also shows pulse width control signals PWC1 to PWC4 and clock signals CLK1 to CLK4, control signals φ, φB, start pulse SP, and output terminals OUT_1 to OU The timing chart shown in Figure 11 represents the waveform of T_n+2. As can be seen from the waveforms of the control signals φ and φB, the first half of the period is as explained in Figure 1(B). This corresponds to period P1, and the latter half of this period corresponds to the second period P2, as explained in Figure 1(B).

[0071] During the first period P1, pulse width control signals PWC1 to PWC4 and clock signal CLK1 are used. The frequency of CLK4 is high, and high dynamic characteristics are required for the shift register buffer. Therefore, in a buffer circuit, the transistor functions as a dual-gate transistor. Control signals φ and φB are given to do so. Meanwhile, in the second period P2, pulse width control signals The frequencies of PWC1 to PWC4 and the clock signals CLK1 to CLK4 are small and shifted. Register buffers do not require high dynamic performance, and their capacity is excessive. Therefore, buffer In the circuit, the control signal is used so that the transistor functions as a single-gate transistor. Given φ and φB.

[0072] Thus, not only changes in frame frequency, but also in response to the frequency of clock signals, etc., By switching between the dual-gate and single-gate functions of the transistors that make up the system This reduces the power consumption required to charge and discharge the back gate.

[0073] (Embodiment 2) In this embodiment, a display device to which a semiconductor device according to one aspect of the present invention can be applied is described. explain.

[0074] The display device illustrated in Figure 12(A) has a circuit 300 and a pixel section 130. Pixel section 1 30 has N wirings GL (where N is a natural number greater than or equal to 3) (also known as GL[1] to GL[N]). ) and M (M is a natural number) wires SL (also referred to as wires SL[1] to SL[M]) are provided. And pixels 131 are provided corresponding to N wirings GL and M wirings SL. Circuit 300 is a gate driver (gate line drive circuit, gate signal line drive circuit, scan line drive). It functions as a dynamic circuit (also called a dynamic circuit). The N wires GL are gate wires (gate signal wires, It functions as a scan line (also called a scan line). The M wiring SL has the function of transmitting video signals. It has. In other words, the M wiring SL is the source line (also called the source signal line or signal line) It has the function of M. Also, the wiring SL of the M line is the source driver (source line drive circuit, source). It is connected to a circuit that functions as a signal line drive circuit (also called a signal line drive circuit). .

[0075] Furthermore, the circuit 300 is the shift register shown in Figure 9, which was described in Embodiment 1. It is possible. In that case, the N wires GL are output terminals OUT_1 to OUT_ This corresponds to n. Also, the N circuits 301 (circuits 301[1] to 30) that the circuit 300 has As shown in 1[N], the circuits SR and SR described in Embodiment 1 are examples of the same circuit. D UM It is possible to use this.

[0076] The selection or deselection of pixel 131 is controlled based on the potential of the wiring GL. In other words, pixel 1 The selection or deselection of 31 is controlled by circuit 300. When pixel 131 is selected, The audio signal is written from wiring SL to pixel 131. Then the video signal is written to pixel 131. The image is held, and the pixel 131 displays according to the video signal. After that, the pixel 131 When the selection is disabled, pixel 131 continues to display according to the held video signal.

[0077] Next, we will explain a specific example of the configuration of pixel 131.

[0078] The pixel 131 illustrated in Figure 12(B) consists of a transistor 132, a liquid crystal element 133, and a capacitor. It has element 134. Transistor 132 has a first terminal connected to wiring SL and a second terminal The terminals are the first electrode (also called the pixel electrode) of the liquid crystal element 133 and the first electrode of the capacitive element 134 The pole is connected, and the gate is connected to the wiring GL. The second electrode of the liquid crystal element 133 (common electric) The pole (also called the pole) is common to all or two or more of the multiple pixels 131. In other words, the A conductor having a region that becomes the second electrode of the liquid crystal element 133 of pixel 131 is the second pixel It has a region that will become the second electrode of the liquid crystal element 133. The second electrode of the capacitive element 134 It is connected to wiring that functions as a capacitance line. The second electrode of the capacitance element 134 is multi All or more of the 131 pixels are connected to the same wiring. However, capacitive element 1 The second electrode of 34 may be connected to the second electrode of the liquid crystal element 133. Transistor 1 32 is controlled to be on or off by the potential of the wiring GL. Transistor 132 is on. At this point, the video signal from wiring SL is input to pixel 131. The liquid crystal element 133 is made of liquid crystal material It has a material. The orientation of the liquid crystal material is such that the first electrode of the liquid crystal element 133 and the second electrode of the liquid crystal element 133 It is controlled by the potential difference with respect to the electrodes. The capacitive element 134 stores charge according to the video signal. It has the function of doing so. In other words, the capacitive element 134 controls the potential of the first electrode of the liquid crystal element 133. It has a function to maintain a value corresponding to the audio signal.

[0079] The pixel 131 illustrated in Figure 12(C) is composed of transistors 135, 136, and E It has an L element 137. Transistor 135 has a first terminal connected to wiring SL and a second terminal The terminal is connected to the gate of transistor 136, and the gate is connected to wiring GL. The inverter 136 has a first terminal that has the function of supplying current to the EL element 137. The wire is connected, and the second terminal is connected to the first electrode (also called the pixel electrode) of the EL element 137. The second electrode (also called the common electrode) of the EL element 137 is connected to all of the multiple pixels 131. This is common to two or more. That is, the second electric element of the EL element 137 of the first pixel 131 The conductor having a region that forms a pole becomes the second electrode of the EL element 137 of the second pixel 131. It has a region. Transistor 135 is controlled to be on or off by the potential of the wiring GL. When transistor 135 is turned on, the video signal from wiring SL is input to pixel 131. Transistor 136 has the function of supplying current to EL element 137. The current supplied by terminal 136 to the EL element 137 will be a value corresponding to the video signal. EL element 1 37 has the function of emitting light in response to the current supplied from transistor 136.

[0080] The configuration of pixel 131 is not limited to those shown in Figures 12(B) and 12(C). Pixel 131 is, A transistor whose gate is connected to wiring GL and whose first terminal is connected to wiring SL, and A display element that performs a display based on a video signal input via a transistor, It is sufficient if it is present. Alternatively, pixel 131 has its gate connected to wiring GL and the first terminal connected to wiring S A transistor connected to L, and based on the video signal input through said transistor It is sufficient to have a pixel electrode to which a potential or current is supplied. Alternatively, pixel 131 is A transistor whose gate is connected to wiring GL and whose first terminal is connected to wiring SL, and A current based on the video signal input via the transistor is supplied to the display element or pixel electrode. It is sufficient to have a supply transistor. Also, the transistors that the pixels have are thin It can be a Glugate or a Dualgate.

[0081] (Embodiment 3) In this embodiment, the transistors in each semiconductor device described in Embodiment 1 above are Examples of applicable transistor configurations will be explained with reference to the drawings.

[0082] <Example of transistor configuration> Figure 13(A) shows a schematic top view of the transistor 600, which is illustrated below. (B) shows a schematic cross-sectional view of transistor 600 at the cutting line AB shown in Figure 13(A). show.

[0083] The transistor 600 has a gate 602 provided on the substrate 601, and the substrate 601 and the gate An insulating layer 603 is provided on the gate 602, and the insulating layer 603 is positioned so as to overlap with the gate 602. An oxide semiconductor layer 604 is provided therein, and a pair of electrodes are in contact with the upper surface of the oxide semiconductor layer 604. It has 605a and 605b. It also has an insulating layer 603, an oxide semiconductor layer 604, and a pair of electric An insulating layer 606 covers electrodes 605a and 605b, and an insulating layer 607 is provided on top of the insulating layer 606. Furthermore, a back gate 608 is provided on the insulating layer 607.

[0084] There are no major restrictions on the material of the substrate 601, but it should at least be able to withstand subsequent heat treatment. A material with heat resistance is used. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a saffron. Using a flame substrate, a YSZ (yttria-stabilized zirconia) substrate, etc., as substrate 601 This is also acceptable. In addition, single-crystal semiconductor substrates and polycrystalline semiconductor substrates made of silicon or silicon carbide are also acceptable. Applying plates, compound semiconductor substrates made of silicon germanium, SOI substrates, etc. This is also possible. Furthermore, a substrate on which semiconductor elements are provided may be referred to as substrate 601. It may also be used in this way.

[0085] Furthermore, a flexible substrate such as plastic may be used as the substrate 601, and the flexible substrate may be directly A transistor 600 may be formed in contact with the substrate 601. Alternatively, the substrate 601 and the transistor 600 may be formed A delamination layer may be provided in between. The delamination layer forms part or all of the transistor on its upper layer. After completion, it can be separated from substrate 601 and used to transfer to other substrates. As a result, the transistor 600 can be mounted on substrates with poor heat resistance or flexible substrates.

[0086] Gate 602 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. A metal selected from stainless steel, or an alloy containing the aforementioned metals, or a combination of the aforementioned metals It can be formed using a combination of alloys, etc. Also, either manganese or zirconium Alternatively, one or more metals may be used. Also, the gate 602 has a single-layer structure. However, a laminated structure of two or more layers is also possible. For example, a single layer structure of an aluminum film containing silicon. Two-layer structure with a titanium film laminated on an aluminum film, and a titanium film laminated on a titanium nitride film. A two-layer structure, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film Alternatively, a two-layer structure in which a tungsten film is laminated on a tungsten nitride film, a titanium film, and its titanium There are three-layer structures, such as one in which an aluminum film is laminated on top of a titanium film, and then a titanium film is formed on top of that. In addition, aluminum is combined with titanium, tantalum, tungsten, molybdenum, chromium, and neo A composite film of one or more metals selected from zinc, scandium, or nitrogen. A film coating may also be used.

[0087] Furthermore, gate 602 and back gate 608 are made of indium tin oxide and tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, By applying a light-transmitting conductive material such as indium tin oxide with added silicon oxide... It is also possible to use a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal. can.

[0088] Furthermore, between the gate 602 and the insulating layer 603, an In-Ga-Zn oxynitride semiconductor film is provided. In-Sn-based oxynitride semiconductor films, In-Ga-based oxynitride semiconductor films, In-Zn-based oxynitride Semiconductor films, Sn-based oxynitride semiconductor films, In-based oxynitride semiconductor films, metal nitride films (InN, Z These materials may have a rating of 5 eV or higher, preferably 5.5 eV or higher. It is a function that can make the threshold voltage of the transistor positive, so-called normally Off-switching elements can be realized. For example, an In-Ga-Zn oxynitride semiconductor film If used, the nitrogen concentration must be at least higher than that of the oxide semiconductor layer 604, specifically 7 atomic percent or less. The above In-Ga-Zn oxynitride semiconductor film is used.

[0089] The insulating layer 603 functions as a gate insulating film. It is in contact with the lower surface of the oxide semiconductor layer 604. The insulating layer 603 is preferably an oxide insulating film.

[0090] The insulating layer 603 is made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride Ricon, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn metal oxides. Any material can be used, and it can be constructed in layers or as a single layer.

[0091] Furthermore, as the insulating layer 603, hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z), Nitrogen-added hafnium aluminum (HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this material, gate leakage in transistors can be reduced.

[0092] The pair of electrodes 605a and 605b are connected to the source or drain electrode of the transistor. It functions in this way.

[0093] The pair of electrodes 605a and 605b are made of conductive material such as aluminum, titanium, chromium, Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tung Using metals such as stainless steel, or alloys with stainless steel as the main component, in a single-layer or laminated structure. This is possible. For example, a single-layer structure of an aluminum film containing silicon, on an aluminum film A two-layer structure in which a titanium film is laminated on top of a tungsten film, a two-layer structure in which a titanium film is laminated on top of a tungsten film, copper- A two-layer structure consisting of a copper film laminated on a magnesium-aluminum alloy film, a titanium film, or a nitride film. A tan film is layered with an aluminum film or copper film on top of the titanium film or titanium nitride film. Furthermore, a three-layer structure is formed by forming a titanium film or titanium nitride film on top of that, or a molybdenum film or This consists of a molybdenum nitride film and aluminum layered on top of the molybdenum film or molybdenum nitride film. A molybdenum film or copper film is laminated, and then a molybdenum film or molybdenum nitride film is formed on top of it. There are three-layer structures, etc. Furthermore, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide. You may also use [this].

[0094] The insulating layer 606 is an oxide insulating film containing more oxygen than satisfies the stoichiometric composition. It is preferable to use an oxide insulating material containing more oxygen than the oxygen that satisfies the stoichiometric composition. When heated, some oxygen is removed from the membrane. Oxide insulating films containing these materials are analyzed by thermal desorption gas spectroscopy (TDS). In ion spectroscopy analysis, the amount of oxygen desorption when converted to oxygen atoms was determined. 1.0 × 10 18 atoms / cm 3 Preferably 3.0 × 10 20 ate / c m 3 The above describes the oxide insulating film. Note that the surface temperature of the film during the above TDS analysis was A range of 100°C to 700°C, or 100°C to 500°C, is preferred.

[0095] For the insulating layer 606, silicon oxide, silicon oxide nitride, etc., can be used.

[0096] Furthermore, the insulating layer 606 is used when forming the insulating layer 607 which will be formed later, and the oxide semiconductor layer 6 It also functions as a damage mitigation layer for 04.

[0097] Furthermore, an oxygen-permeable oxide film is provided between the insulating layer 606 and the oxide semiconductor layer 604. That's good too.

[0098] For oxide films that permeate oxygen, silicon oxide, silicon oxide-nitride, etc., can be used. Yes, it is possible. In this specification, a silicon oxidizride film is defined as having a composition of nitrogen. It refers to a film with a higher oxygen content than a film, and silicon nitride oxide film, in terms of its composition, has a higher oxygen content than a film. This also refers to a membrane with a high nitrogen content.

[0099] The insulating layer 607 may use an insulating film that has a blocking effect on oxygen, hydrogen, water, etc. This is possible. By providing the insulating layer 607 on the insulating layer 606, it is possible to prevent the diffusion of oxygen from the oxide semiconductor layer 604 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor layer 604. This is possible. As the insulating film having a blocking effect on oxygen, hydrogen, water, etc., there are silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc.

[0100] <Example of manufacturing method of transistor> Subsequently, an example of the manufacturing method of the transistor 600 illustrated in FIG. 13 will be described.

[0101] First, as shown in FIG. 14(A), a gate 602 is formed on the substrate 601, and an insulating layer 603 is formed on the gate 602.

[0102] Here, a glass substrate is used as the substrate 601.

[0103] The method of forming the gate 602 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a resist mask is formed on the conductive film by a photolithography process using a first photomask. Next, a part of the conductive film is etched using the resist mask to form the gate 602. Then, the resist mask is removed.

[0104] Note that the gate 602 may be formed by an electroplating method, a printing method, an inkjet method, etc. instead of the above forming method.

[0105] The insulating layer 603 is formed by a sputtering method, a PECVD method, an evaporation method, etc.

[0106] ​​​​​​The insulating layer 603 is a silicon oxide film, a silicon oxide nitride film, or a silicon nitride oxide film. When forming it, silicon-containing sedimentary gases and oxidizing gases are used as raw material gases. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and tri Examples include silanes and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and dinitrate. Examples include nitric oxide.

[0107] Furthermore, when forming a silicon nitride film as the insulating layer 603, a two-step formation method is used. This is preferable. First, a mixed gas of silane, nitrogen, and ammonia is used as the raw material gas. A first silicon nitride film with few defects is formed using the plasma CVD method. Next, The raw material gas is switched to a mixed gas of silane and nitrogen, resulting in a lower hydrogen concentration and a lower hydrogen content. A second silicon nitride film capable of locking is formed. Furthermore, silicon nitride, which has few defects and hydrogen blocking properties, is used as the insulating layer 603. It can form a film.

[0108] Furthermore, when forming a gallium oxide film as the insulating layer 603, MOCVD (Metal Using the Organic Chemical Vapor Deposition method, the shape It is possible.

[0109] Next, as shown in Figure 14(B), an oxide semiconductor layer 604 is formed on the insulating layer 603. .

[0110] The method for forming the oxide semiconductor layer 604 is shown below. First, the oxide semiconductor film is formed. Next, a photolithography process is performed on the oxide semiconductor film using a second photomask. A resist mask is formed. Next, a part of the oxide semiconductor film is etched using the resist mask to form an oxide semiconductor layer 604. After that, the resist mask is removed .

[0111] After this, a heat treatment may be performed. When performing the heat treatment, it is preferably performed in an atmosphere containing oxygen . Also, as the temperature of the above heat treatment, for example, it may be 150°C or higher and 600°C or lower, preferably 200°C or higher and 500°C or lower.

[0112] Next, as shown in FIG. 14(C), a pair of electrodes 605a and 605b are formed.

[0113] The method for forming the pair of electrodes 605a and 605b is shown below. First, a conductive film is formed by a sputtering method , PECVD method, evaporation method, etc. Next, a resist mask is formed on the conductive film by a photolithography process using a third photomask . Next, a part of the conductive film is etched using the resist mask to form a pair of electrodes 605a and 605b . After that, the resist mask is removed.

[0114] Note that, as shown in FIG. 14(C), when etching the conductive film, a part of the upper portion of the oxide semiconductor layer 604 may be etched and thinned. Therefore, when forming the oxide semiconductor layer 604 , it is preferable to set the thickness of the oxide semiconductor film to be thick in advance.

[0115] Next, as shown in FIG. 14(D), an insulating layer 606 is formed on the oxide semiconductor layer 604 and the pair of electrodes 605a and 6 05b, and then an insulating layer 607 is formed on the insulating layer 606, and then a back gate 608 is formed on the insulating layer 607.

[0116] When forming a silicon oxide film or silicon oxidiznitride film as the insulating layer 606, the raw material gas As the gas, it is preferable to use a depositing gas and an oxidizing gas containing silicon. Typical examples of sedimentary gases containing silanes include silanes, disilanes, trisilanes, and silane fluorides. These include oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0117] For example, a substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 180°C or higher. Maintain the temperature at 260°C or lower, more preferably 200°C to 240°C, and place the raw material gas in the processing chamber. By introducing a suction device, the pressure inside the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably. The pressure should be between 100 Pa and 200 Pa, and 0.17 W / cm² should be applied to the electrode installed in the processing chamber. 2 Below Upper 0.5W / cm 2 More preferably, 0.25 W / cm² 2 More than 0.35W / cm 2 Under the following conditions for supplying high-frequency power, a silicon oxide film or silicon oxide nitride film is formed. To accomplish.

[0118] As a film deposition condition, high-frequency power of the above power density is supplied in the processing chamber at the above pressure. As a result, the decomposition efficiency of the raw material gas in the plasma increases, oxygen radicals increase, and the acid of the raw material gas As the chemical reaction progresses, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is at the above temperature, the bonding force between silicon and oxygen is weak, so heating Some of the oxygen is eliminated. As a result, it contains more oxygen than the oxygen required to satisfy the stoichiometric composition. Furthermore, an oxide insulating film can be formed in which some of the oxygen is desorbed by heating.

[0119] Furthermore, if an oxide insulating film is provided between the oxide semiconductor layer 604 and the insulating layer 606, In the process of forming the edge layer 606, the oxide insulating film becomes a protective film for the oxide semiconductor layer 604. As a result, damage to the oxide semiconductor layer 604 is reduced, while high power density and high frequency are achieved. The insulating layer 606 can be formed using electricity.

[0120] For example, a substrate placed in the vacuum-evacuated processing chamber of a PECVD apparatus is subjected to temperatures above 180°C for 4 hours. Maintain the temperature below 0°C, more preferably between 200°C and 370°C, and introduce the raw material gas into the processing chamber. The pressure inside the processing chamber is set to 20 Pa or more and 250 Pa or less, more preferably 100 Pa. The pressure is set to be between Pa and 250 Pa, and the conditions for supplying high-frequency power to electrodes installed in the processing chamber are as follows: Therefore, a silicon oxide film or silicon oxidnitride film can be formed as an oxide insulating film. Furthermore, by setting the pressure in the processing chamber to between 100 Pa and 250 Pa, the oxide insulation can be improved. When forming the film, it is possible to reduce damage to the oxide semiconductor layer 604.

[0121] As raw material gases for oxide insulating films, silicon-containing depositing gases and oxidizing gases are used. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and tri Examples include silanes and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and dinitrate. Examples include nitric oxide.

[0122] The insulating layer 607 can be formed by sputtering, PECVD, or other methods.

[0123] When forming a silicon nitride film or silicon nitride oxide film as the insulating layer 607, raw materials The gases used include silicon-containing sedimentary gases, oxidizing gases, and nitrogen-containing gases. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and trisyl Examples include ores and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and diacitates. Examples include nitrogen dioxide. Gases containing nitrogen include nitrogen and ammonia.

[0124] The methods for forming the back gate 608 are shown below. First, the sputtering method and the CVD method. A conductive film is formed by vapor deposition or the like, and a fourth photomask is used to photolithograph the conductive film. A resist mask is formed by a roughing process. Next, a conductive film is formed using the resist mask. A portion is etched to form the back gate 608. Then the resist mask is removed. do.

[0125] The back gate 608 can be formed by electrolytic plating, printing, or injection molding instead of the above-mentioned formation method. It may also be formed by methods such as the cgetting method.

[0126] By following the above steps, the transistor 600 can be formed.

[0127] The following describes an example of a transistor configuration that differs in some respects from transistor 600. .

[0128] Figure 15(A) shows a schematic cross-sectional view of transistor 610, which is illustrated below. The TA610 differs from the transistor 600 in that it has a different oxide semiconductor layer configuration.

[0129] The oxide semiconductor layer 614 of transistor 610 is composed of oxide semiconductor layer 614a and oxide It is constructed by stacking a monocrystalline semiconductor layer 614b.

[0130] Furthermore, the boundary between oxide semiconductor layer 614a and oxide semiconductor layer 614b may be unclear. Therefore, these boundaries are shown with dashed lines in diagrams such as Figure 15(A).

[0131] The oxide semiconductor layer 614a is typically In-Ga oxide, In-Zn oxide, In- M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) It is used. Also, when the oxide semiconductor layer 614a is In-M-Zn oxide, Zn and The atomic ratio of In and M excluding O is preferably less than 50 atomic% for In. M is 50 atomic % or more, more preferably In is less than 25 atomic %, M The amount is set to 75 atomic% or more. Also, for example, the oxide semiconductor layer 614a has an energy A material having a gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Use a ration.

[0132] The oxide semiconductor layer 614b contains either In or Ga, and is typically an In-Ga oxide. In-Zn oxide, In-M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, La, C) (e, Nd or Hf), and the energy at the lower end of the conduction band is greater than that of the oxide semiconductor layer 614a. The energy level is close to the vacuum level, and typically, it is the energy at the lower end of the conduction band of the oxide semiconductor layer 614b. - The difference between this energy and the energy at the lower end of the conduction band of the oxide semiconductor layer 614a is 0.05 eV or more. , 0.07eV or higher, 0.1eV or higher, or 0.15eV or higher and 2eV or lower, 1e It is preferable to have a voltage of V or less, 0.5 eV or less, or 0.4 eV or less.

[0133] Furthermore, when the oxide semiconductor layer 614b is an In-M-Zn oxide, excluding Zn and O The atomic ratio of In to M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than 34 atomic%, more preferably In is 34 atomic% or more and M is 66 atomic% It should be less than mic%.

[0134] For example, in oxide semiconductor layer 614a, In:Ga:Zn=1:1:1, In:Ga: In-Ga- Zn oxide can be used. Also, In:Ga:Z can be used as the oxide semiconductor layer 614b. In-Ga-Zn oxides with atomic ratios n=1:3:2, 1:6:4, or 1:9:6 It can be used. Each atom ratio includes a margin of error of plus or minus 20% from the atom ratios mentioned above.

[0135] The oxide semiconductor layer 614b provided on the upper layer contains Ga, which functions as a stabilizer. By using an oxide with a high amount of oxide, the oxide semiconductor layer 614a and the oxide semiconductor layer 6 This can suppress the release of oxygen from 14b.

[0136] Furthermore, this is not limited to the semiconductor characteristics and electrical characteristics (field effect) of the transistor as needed. A suitable composition should be used depending on the required torque (e.g., fruit mobility, threshold voltage). To obtain the semiconductor properties of the lampistor, oxide semiconductor layer 614a, oxide semiconductor layer 614 b's carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree and other parameters appropriately.

[0137] In the above description, the oxide semiconductor layer 614 is a configuration in which two oxide semiconductor layers are stacked. While the above is an example, a configuration in which three or more oxide semiconductor layers are stacked is also possible.

[0138] Figure 15(B) shows a schematic cross-sectional view of transistor 620, which is illustrated below. The TA620 differs from the transistor 600 and the transistor 620 in that the oxide semiconductor layer configuration is different. It differs from 610.

[0139] The oxide semiconductor layer 624 of transistor 620 consists of oxide semiconductor layer 624a and oxide The material is constructed by sequentially stacking a monocrystalline semiconductor layer 624b and an oxide semiconductor layer 624c.

[0140] The oxide semiconductor layer 624a and the oxide semiconductor layer 624b are laminated on the insulating layer 603. It can be kicked. Also, the oxide semiconductor layer 624c is on the upper surface of the oxide semiconductor layer 624b, and a pair It is provided in contact with the upper and side surfaces of electrodes 605a and 605b.

[0141] For example, as the oxide semiconductor layer 624b, the acid exemplified in the <Modified Transistor> above A configuration similar to that of the oxide semiconductor layer 614a can be used. Also, for example, an oxide semiconductor layer 624a and 624c are the oxide semiconductor layers 6 exemplified in the above <Modified Transistor>. A configuration similar to 14b can be used.

[0142] For example, an oxide semiconductor layer 624a provided below the oxide semiconductor layer 624b, and above The oxide semiconductor layer 624c provided in the layer contains Ga, which functions as a stabilizer. By using an oxide with a high concentration, oxide semiconductor layer 624a, oxide semiconductor layer 624b, Furthermore, the release of oxygen from the oxide semiconductor layer 624c can be suppressed.

[0143] Furthermore, for example, when channels are mainly formed in the oxide semiconductor layer 624b, An oxide with a high In content is used for the semiconductor layer 624b, and in contact with the oxide semiconductor layer 624b By providing a pair of electrodes 605a and 605b, the on-current of transistor 620 is increased. It can be made larger.

[0144] <Other transistor configurations> The following describes other configurations to which oxide semiconductor films can be applied.

[0145] Furthermore, in the following, for components with the same configuration or function as described above, The same symbols are used, and redundant explanations are omitted.

[0146] Figure 16(A) shows a schematic cross-sectional view of the transistor 650, which is illustrated below.

[0147] The transistor 650 has a back gate 608 provided on the substrate 601 and an insulating layer 65 1 an oxide semiconductor layer 604 provided on top of and a pair in contact with the upper surface of the oxide semiconductor layer 604 On electrodes 605a and 605b, oxide semiconductor layer 604, and on the pair of electrodes 605a and 605b An insulating layer 603 is provided, and an oxide semiconductor layer 604 is provided on the insulating layer 603 so as to overlap with it. It has a gate 602 that can be used. Furthermore, an insulating layer 6 covers the insulating layer 603 and the gate 602. 52 is provided.

[0148] The insulating layer 651 suppresses the diffusion of impurities from the substrate 601 to the oxide semiconductor layer 604. It has the ability. For example, the same configuration as the insulating layer 607 can be used. Layer 651 may be omitted if it is not needed.

[0149] The insulating layer 652, like the insulating layer 607, provides a blocking effect against oxygen, hydrogen, water, etc. An insulating film can be applied. Note that the insulating layer 607 may be omitted if it is not needed. good.

[0150] The following describes an example of a transistor configuration that differs in some respects from the 650 transistor. .

[0151] Figure 16(B) shows a schematic cross-sectional view of transistor 660, which is illustrated below. The TA660 differs from the transistor 650 in that it has a different oxide semiconductor layer configuration.

[0152] The oxide semiconductor layer 664 of transistor 660 consists of oxide semiconductor layer 664a and oxide The device is constructed by sequentially stacking a monocrystalline semiconductor layer 664b and an oxide semiconductor layer 664c.

[0153] Of the oxide semiconductor layer 664a, oxide semiconductor layer 664b, and oxide semiconductor layer 664c, Apply the oxide semiconductor film described above to one, two, or all of them. It is possible.

[0154] For example, as the oxide semiconductor layer 664b, the acid exemplified in the <Modified Transistor> above A configuration similar to that of the oxide semiconductor layer 614a can be used. Also, for example, an oxide semiconductor layer 664a and 664c are the oxide semiconductor layers 6 exemplified in the above <Modified Transistor>. A configuration similar to 14b can be used.

[0155] Furthermore, the oxide semiconductor layer 664a provided below the oxide semiconductor layer 664b, and the upper layer The oxide semiconductor layer 664c provided therein has a Ga content that functions as a stabilizer. By using a large amount of oxide, oxide semiconductor layer 664a, oxide semiconductor layer 664b, acid This can suppress the release of oxygen from the ionized semiconductor layer 664c.

[0156] The following describes an example of a transistor configuration that differs in some respects from the 650 transistor. .

[0157] Figure 16(C) shows a schematic cross-sectional view of transistor 670, which is illustrated below. TA 670 is the shape of a pair of electrodes 605a and 605b that are in contact with the oxide semiconductor layer 604, and The gate 602 differs from transistor 650 in its shape and other characteristics.

[0158] The transistor 670 has a back gate 608 provided on the substrate 601 and an insulating layer 65 1 an oxide semiconductor layer 604 provided on and an insulating layer 603 on the oxide semiconductor layer 604, The gate 602 on the insulating layer 603, and the insulating layer 651 and the insulating layer 6 on the oxide semiconductor layer 604 54, the insulating layer 656 on the insulating layer 654, and the openings provided in the insulating layers 654 and 656 A pair of electrodes 605a and 605b are electrically connected to the oxide semiconductor layer 604 via an insulating film, It has an edge layer 656 and an insulating layer 652 on a pair of electrodes 605a and 605b.

[0159] The insulating layer 654 is formed, for example, with an insulating film containing hydrogen. Examples include silicon nitride films. The hydrogen contained in the insulating layer 654 is an oxide semiconductor. By bonding with oxygen vacancies in layer 604, it becomes a carrier in the oxide semiconductor layer 604. Therefore, in the configuration shown in Figure 16(C), the oxide semiconductor layer 604 and the insulating layer 654 The touching regions are represented as n-type region 604b and n-type region 604c. The region sandwiched between the 604b and the n-type region 604c becomes the channel region 604a.

[0160] By providing the n-type regions 604b and 604c in the oxide semiconductor layer 604, the contact resistance with the pair of electrodes 6 05a and 605b can be reduced. Note that as the n-type regions 604b and 6 04c, during the formation of the gate 602, they can be formed self-alignedly using the insulating layer 654 covering the gate 602. The transistor 670 shown in FIG. 16(C) is a so-called self aligned top-gate type transistor. By adopting the self-aligned top-gate type transistor structure, there is no overlap between the gate 602 and the pair of electrodes 605a and 605b that function as the source electrode and the drain electrode, so the parasitic capacitance generated between the electrodes can be reduced. Moreover, as the insulating layer 656 included in the transistor 670, for example, it can be formed of a silicon oxynitride film or the like.

[0161] Also, as the insulating layer 656 that the transistor 670 has, for example, it can be formed by a silicon oxynitride film or the like.

[0162] (Embodiment 4) In this embodiment, a transistor (OS transistor) having an oxide semiconductor in the channel formation region will be described. The OS transistor can be applied to the transistors included in the semiconductor device described in the above embodiment.

[0163] The OS transistor can reduce the impurity concentration in the oxide semiconductor and make the oxide semiconductor intrinsic or substantially intrinsic to lower the off-current. Here, substantially intrinsic means that the carrier density in the oxide semiconductor is less than 1×10 17 / cm 3 and less than 1×10 ​15 / cm 3 Being less than, or 1 × 10 13 / cm 3 It refers to being less than the acid. In ionized semiconductors, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are impurities. They become matter. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing carrier density. It will cause it to happen.

[0164] Transistors using intrinsic or substantially intrinsic oxide semiconductors have a carrier density of Because it is low, it rarely exhibits electrical characteristics where the threshold voltage is negative. Transistors using conductors have fewer carrier traps in oxide semiconductors, resulting in better electrical characteristics. The fluctuations are small, resulting in a highly reliable transistor. Furthermore, transistors using this oxide semiconductor... The transistor allows for extremely low off-currents.

[0165] Furthermore, with an OS transistor with a low off-current, the channel width is 1 at room temperature (around 25°C). Off-current per μm is 1 × 10 -18 Below A, 1×10 -21 A or less, or 1 x 1 0 -24 A or less, or 1 x 10 at 85°C -15 Below A, 1×10 -18 A or below, or is 1 x 10 -21 It can be less than or equal to A.

[0166] <Off-current> In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state (non- This refers to the drain current when the circuit is in a conductive state or an interrupted state. The off state is particularly... Unless otherwise specified, in an n-channel transistor, the voltage Vgs between the gate and source is the threshold. When the voltage value is lower than Vth, in a p-channel transistor, the voltage between the gate and source is lower. This refers to a state where the voltage Vgs is higher than the threshold voltage Vth. For example, an n-channel transistor. The off-current is the voltage between the gate and source (Vgs) when the voltage between the gate and source (Vgs) is lower than the threshold voltage (Vth). Sometimes it's referred to as rain current.

[0167] The off-current of a transistor may depend on Vgs. Therefore, the off-current of a transistor The statement that the off-current is less than or equal to I means that there exists a Vgs value such that the transistor's off-current is less than or equal to I. It is sometimes said that the off-current of a transistor is the off-state at a given Vgs. This results in an off state at a Vgs within a predetermined range, or an off current that is sufficiently reduced. This may refer to the off-state in Vgs, or the off-current in such states.

[0168] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, the drain voltage Flow is 1 x 10 -9 A is such that the drain current at Vgs = 0.1V is 1 × 10⁻¹⁰ -13 A Therefore, the drain current at Vgs = -0.5V is 1 × 10⁻⁶ -19 A and Vgs The drain current at -0.8V is 1 × 10⁻⁶ -22 n-channel transient such that A Assume a transistor. The drain current of the transistor is such that when Vgs is -0.5V, Alternatively, in the range where Vgs is -0.5V to -0.8V, 1 × 10 -19 A or less Therefore, the off-current of the transistor is 1 × 10⁻⁶. -19 Sometimes it is said that it is less than or equal to A. The drain current of the transistor is 1 × 10⁻⁶ -22 Since there exists a Vgs that is less than or equal to A, The off-current of the transistor is 1 × 10⁻⁶ -22 Sometimes it is said that it is less than or equal to A.

[0169] In this specification, the off-current of a transistor having a channel width W is defined as per channel width W. It is sometimes expressed as the current value flowing through it. Also, it is expressed as the current flowing per predetermined channel width (e.g., 1 μm). It may be expressed as a current value. In the latter case, the unit of the off-current has the dimension of current / length. It may be expressed in units (for example, A / μm).

[0170] The off-current of a transistor may be temperature-dependent. In this specification, the off-current Unless otherwise specified, the device is turned off at room temperature, 60°C, 85°C, 95°C, or 125°C. It may represent electric current. Alternatively, it may indicate that the reliability of the semiconductor device containing the transistor is maintained. The temperature at which the transistor is proven, or the temperature at which the semiconductor device containing the transistor is used (e.g.) For example, it may represent the off-current at any one temperature between 5°C and 35°C. The off-current of the inverter is less than or equal to I, meaning that at room temperature, 60°C, 85°C, 95°C, and 125°C, The temperature at which the reliability of the semiconductor device containing the transistor is guaranteed, or the transistor The temperature at which semiconductor devices containing DISTROs are used (for example, any one temperature between 5°C and 35°C) At a given temperature, there exists a value of Vgs such that the transistor's off-current is less than or equal to I. It may refer to something.

[0171] The off-current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-current is defined as Vds = 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, and This may represent the off-current at 20V. Or, the semiconductor containing the transistor in question. The reliability of the device, etc., is guaranteed by Vds, or the semiconductor device containing the transistor in question. It may represent the off-current at Vds used in applications such as transistor off-voltage. The current is less than or equal to I, meaning that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, the transistor in question The reliability of the semiconductor device is guaranteed by Vds, or the semiconductor device containing the transistor. In devices such as body equipment, the off-current of the transistor at Vds is less than or equal to I. This can sometimes refer to the existence of a value for gs.

[0172] In the above explanation of off-current, drain may be read as source. The term "current" can also refer to the current flowing through the source of a transistor when it is in the off state.

[0173] In this specification, the term "leakage current" may be used interchangeably with "off current."

[0174] In this specification, off-current refers to, for example, the current when a transistor is in the off state. It can sometimes refer to the current flowing between the drain and the outlet.

[0175] <Composition of oxide semiconductors> Furthermore, as an oxide semiconductor used in the semiconductor layer of an OS transistor, at least indi- It is preferable to contain in (In) or zinc (Zn). It is particularly preferable to contain both In and Zn. In addition, it is preferable to have a stabilizer that strongly binds to oxygen. It is suitable as a stabilizer. Gallium (Ga), tin (Sn), zirconium (Zr ), and at least one of hafnium (Hf) and aluminum (Al) is sufficient. .

[0176] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europieu Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Ho Lumium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more types of lutetium (Lu).

[0177] Examples of oxide semiconductors used in the semiconductor layer of transistors include indium oxide and acid Tin oxide, zinc oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Z n-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, I n-Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides, In- Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides, In-Ti -Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Z n-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides Oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn acids In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides Materials, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga- Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, I Examples include n-Sn-Hf-Zn oxides and In-Hf-Al-Zn oxides.

[0178] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or I In-Ga-Zn oxides with an atomic ratio of n:Ga:Zn = 2:1:3, and their compositions in the vicinity. Oxides are preferable. In particular, In:Ga:Zn = 4:2:3 or a similar number of atoms. It is best to use an In-Ga-Zn oxide with a specific ratio. In:Ga:Zn = 4:2:3 or To obtain an In-Ga-Zn oxide with a nearby atomic ratio, In:Ga:Zn = 4 A 2:4.1 target is used to deposit an oxide semiconductor film.

[0179] <Impurities in oxide semiconductors> When hydrogen is present in the oxide semiconductor film that makes up the semiconductor layer, it bonds with the oxide semiconductor. As a result, some of the hydrogen becomes a donor, generating electrons, which act as carriers. This causes the transistor's threshold voltage to shift in the negative direction. Therefore, oxide semiconductors... After the film is formed, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen from the oxide semiconductor film, It is preferable to remove moisture and purify the material to the highest possible degree to minimize the presence of impurities.

[0180] Furthermore, by dehydrating (dehydrogenating) the oxide semiconductor film, Oxygen levels may decrease. Therefore, dehydration treatment (dehydrogenation treatment) of oxide semiconductor films is necessary. To compensate for the increased oxygen deficiency caused by the process, oxygen is added to the oxide semiconductor film. It is preferable.

[0181] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. It is removed and the oxygen deficiency is compensated for by oxygenation treatment, resulting in type i (true) or i It is possible to create an oxide semiconductor film that is very close to the original type and is essentially type i (intrinsic).

[0182] <Oxide semiconductor structure> The structure of oxide semiconductors will be explained.

[0183] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Approximately parallel" refers to a state where two lines are positioned at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two lines are positioned at an angle of 80° to 100°. It refers to a state. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" This refers to a state in which two straight lines are positioned at an angle between 60° and 120°.

[0184] Furthermore, in this specification, if the crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0185] Oxide semiconductor films are divided into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. It can be done.

[0186] Furthermore, as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligne d Crystalline Oxide Semiconductor), polycrystalline oxide These include crystalline semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. As conductors, single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides are used. Examples include semiconductors.

[0187] First, let's explain the CAAC-OS membrane.

[0188] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions. .

[0189] Transmission Electron Microscope (TEM) A composite image of the bright-field image and diffraction pattern of the CAAC-OS film was obtained using an optical scope. By observing (also known as high-resolution TEM images), multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between crystal parts, i.e., grain boundaries. It is not possible to confirm the boundary (also called the boundary). Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0190] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction approximately parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is This reflects the unevenness of the surface (also called the surface to be formed) or the upper surface of the CAAC-OS film. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0191] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction approximately perpendicular to the sample surface. Then, it was confirmed that the metal atoms in the crystalline region are arranged in a triangular or hexagonal shape. Yes, it is possible. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0192] X-ray diffraction (XRD) of CAAC-OS film When structural analysis is performed using the instrument, for example, CAAC-OS having InGaZnO4 crystals is found. Out-of-plane analysis of the film showed a peak at a diffraction angle (2θ) of around 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is on the surface to be formed or on the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0193] Furthermore, the out-of-plane CAAC-OS film having InGaZnO4 crystals Analysis using this method revealed that in addition to the peak near 2θ = 31°, there is also a peak near 2θ = 36°. In some cases, this may occur. Peaks near 2θ of 36° indicate c-axis orientation in a portion of the CAAC-OS film. This indicates the presence of crystals that do not possess properties. The CAAC-OS film has a 2θ of approximately 31°. It is preferable that a peak is shown and that no peak is shown near 36° for 2θ.

[0194] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen and carbon. These are elements other than the main components of oxide semiconductor films, such as silicon and transition metal elements. In particular, silicon Elements such as condensate, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, are acidic. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a high atomic ratio. Because of its large diameter (or molecular radius), when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Pure substances can act as carrier traps or carrier sources.

[0195] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxidation Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. This can sometimes become a source of carrier transmission.

[0196] A low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic. Because membranes have fewer carrier sources, they can have lower carrier densities. Therefore The transistor using the oxide semiconductor film exhibits electrical characteristics such as a negative threshold voltage ( - Also called Marieion.) It rarely becomes high purity genuine or substantially high purity. Intrinsic oxide semiconductor films have few carrier traps. Therefore, the oxide semiconductor... Transistors using film have small variations in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can last for a long time and behave as if it were a fixed charge. Therefore, when the impurity concentration is high... Furthermore, transistors using oxide semiconductor films with a high defect level density exhibit unstable electrical properties. There are cases where this occurs.

[0197] Furthermore, transistors using CAAC-OS films exhibit electrical properties when irradiated with visible light or ultraviolet light. Sexual variation is small.

[0198] Next, we will explain microcrystalline oxide semiconductor films.

[0199] Microcrystalline oxide semiconductor films allow for the confirmation of crystalline regions in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor The crystalline portion contained in the film is between 1 nm and 100 nm, or between 1 nm and 10 nm. They are often small in size. In particular, between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are microcrystalline, c-OS(nanocrystalline oxide semiconductor It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. It may not be possible to confirm this.

[0200] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not the case. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film... When structural analysis is performed using an RD instrument, out-of-plane analysis shows that crystals No peaks indicating a plane are detected. Also, for the nc-OS film, a probe larger than the crystalline region is detected. Electron diffraction using an electron beam with a diameter (e.g., 50 nm or more) (also called limited-field electron diffraction). When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, when applied to an nc-OS film... Furthermore, nanobeam electron beams with a probe diameter close to or smaller than the size of the crystal region are used. When nanobeam diffraction is performed, spots are observed. Furthermore, nanobeam electron diffraction is used on nc-OS films. When this is done, a region of high brightness may be observed in a circular (ring-shaped) pattern. When nanobeam electron diffraction is performed on an nc-OS film, multiple spots are observed within a ring-shaped region. This can sometimes be observed.

[0201] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, Furthermore, the nc-OS film does not show any regularity in crystal orientation between different crystalline regions. Therefore, nc- OS films have a higher defect level density compared to CAAC-OS films.

[0202] Next, we will explain amorphous oxide semiconductor films.

[0203] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are oxide semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0204] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images. .

[0205] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of- Analysis using the plane method does not detect peaks indicating crystal planes. Furthermore, amorphous oxides are present. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. Also, amorphous oxides... When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is formed. This is observed.

[0206] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have a structure. Oxide semiconductor films having such a structure are particularly amorphous lycoated. Amorphous-like Oxide Semiconductor (a-like OS) It is called a conductor film.

[0207] a-like OS films exhibit porosity (also called voids) in high-resolution TEM images. In some cases, this may occur. Also, in high-resolution TEM images, the crystalline portion can be clearly identified. The a-like OS film has regions where crystals can be observed and regions where crystals cannot be observed. Crystallization occurs and the growth of the crystal portion is observed by minute electron irradiation, such as that observed by TEM. This can sometimes be the case. On the other hand, with a high-quality nc-OS film, even trace amounts that can be observed by TEM are not visible. Crystallization due to electron irradiation is hardly observed.

[0208] Furthermore, the measurement of the crystal size of a-like OS films and nc-OS films is performed using high resolution. This can be done using TEM imaging. For example, the crystal of InGaZnO4 has a layered structure. It has two Ga-Zn-O layers between the In-O layers. Unit size of InGaZnO4 crystal The child has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. It has a layered structure. Therefore, the spacing between these adjacent layers is the (009) plane. It is approximately the same as the lattice plane spacing (also called the d value), and from crystal structure analysis, its value is 0.29n m has been determined. Therefore, we focused on the lattice fringes in the high-resolution TEM image, and between the lattice fringes In areas where the interval is between 0.28 nm and 0.30 nm, each lattice fringe is In This corresponds to the ab-plane of the GaZnO4 crystal.

[0209] Furthermore, oxide semiconductor films may have different densities depending on their structure. For example, a certain oxide semiconductor... If the composition of the conductive film is known, it can be compared with the density of a single crystal with the same composition. This allows us to estimate the structure of the oxide semiconductor film. For example, with respect to the density of a single crystal, a -The density of the OS film is between 78.6% and 92.3%. Also, for example, single-layer The density of the nc-OS film and the CAAC-OS film is 92.3% or higher relative to the density of the crystal. It will be less than 00%. Note that oxide semiconductor films with a density of less than 78% of the density of a single crystal are Furthermore, forming the film itself is difficult.

[0210] The above will be explained using a concrete example. For example, In:Ga:Zn=1:1:1[original In an oxide semiconductor film satisfying the [number of particles ratio], a single crystal InGaZnO having a rhombohedral crystal structure is used. The density of 4 is 6.357 g / cm³ 3 Therefore, for example, In:Ga:Zn=1:1: In an oxide semiconductor film satisfying 1 [atomic ratio], the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 It becomes less than. Also, for example, In:Ga:Zn=1:1 In an oxide semiconductor film satisfying :1 [atomic ratio], the density of the nc-OS film and CAAC -The density of the OS film is 5.9 g / cm³ 3 More than 6.3g / cm 3 It will be less than.

[0211] Note that single crystals with the same composition may not exist. In that case, a mixture of crystals with different compositions in any proportion may be used. By combining single crystals, the density corresponding to a single crystal with a desired composition can be calculated. This can be done. The density of a single crystal of the desired composition depends on the ratio of single crystals of different compositions that are combined. Then, it may be calculated using a weighted average. However, the density is preferably calculated by combining as few types of single crystals as possible.

[0212] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0213] As described above, the OS transistor can realize extremely excellent off-current characteristics.

[0214] (Embodiment 5) <Configuration of CAC-OS> Hereinafter, the configuration of CAC (Cloud Aligned Complementary)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0215] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also simply referred to as Oxide Semiconductor or OS), and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS FET, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor. In this specification, when a metal oxide has a region having a conductor function and a region having a dielectric function mixed, and the entire metal oxide functions as a semiconductor, CAC (Cloud

[0216] In this specification, when a metal oxide has a region having a conductor function and a region having a dielectric function mixed, and the entire metal oxide functions as a semiconductor, CAC (Cloud Aligned Complementary)-OS is formed. ​​​​​​​​Aligned Complementary)-OS(Oxide Semicon Defined as a ductor, or CAC-metal oxide.

[0217] In other words, CAC-OS means that, for example, the elements constituting the oxide semiconductor are 0.5 nm or larger. The size is 10 nm or less, preferably 0.5 nm to 3 nm, or close to that size, and is unevenly distributed. This is one component of the material. In the following, in oxide semiconductors, one or more The above elements are unevenly distributed, and the region containing the elements is 0.5 nm to 10 nm, preferably, A state in which particles with a size of 0.5 nm to 3 nm, or close to that size, are mixed is called a mosaic pattern. This is also called a patchy pattern.

[0218] In regions where a particular element is concentrated, the physical properties are determined by the properties of that element. For example... If, among the elements that make up metal oxides, elements that tend to be relatively insulators are concentrated in certain areas. The region becomes the dielectric region. On the other hand, among the elements that make up metal oxides, those that are relatively conductive... Regions where elements that tend to be conductive are concentrated become conductive regions. The mosaic-like mixing of body regions allows the material to function as a semiconductor.

[0219] In other words, the metal oxide in one aspect of the present invention is a mixture of materials with different physical properties. Trix composite, or metal matrix composite It is a type of material (metal matrix composite).

[0220] Furthermore, the oxide semiconductor preferably contains at least indium, particularly indium. It is preferable that it also contains zinc. In addition to these, element M (where M is gallium, a Aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One of the following, selected from luminous, hafnium, tantalum, tungsten, or magnesium. (Or multiple types) may be included.

[0221] For example, CAC-OS in In-Ga-Zn oxide (In- Ga-Zn oxide may also be specifically referred to as CAC-IGZO. ) is indium oxide (hereinafter referred to as InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc Oxides (hereinafter, In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0) ) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, oyo Let Z4 be a real number greater than 0. The material separates into parts, creating a mosaic pattern. It becomes a mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is uniformly distributed within the membrane. This configuration (hereinafter also referred to as cloud-based) is as follows.

[0222] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region is the main component and a region is mixed. It is a body. In this specification, for example, the number of atoms of In relative to element M in the first region. The first region indicates that the ratio is greater than the atomic ratio of In to element M in the second region. Assume that the concentration of In is higher in this region compared to the second region.

[0223] Note that IGZO is a common name and refers to a single compound composed of In, Ga, Zn, and O. There are cases where this occurs. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is any number) Examples of crystalline compounds are shown.

[0224] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. CAAC structure refers to a structure in which multiple IGZO nanocrystals have c-axis orientation and ab-plane orientation This is a crystal structure in which the elements are linked without orientation.

[0225] On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is In, In a material composition containing Ga, Zn, and O, a portion of the material consists of nanoparticles with Ga as the main component. A region was observed, and in part, a nanoparticle-like region mainly composed of In was observed, each forming a mosaic. This refers to a configuration in which particles are randomly dispersed. Therefore, in CAC-OS, the crystal structure is secondary. It is a secondary element.

[0226] Furthermore, CAC-OS does not include a layered structure of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, includes No.

[0227] Note that GaOX3 The region where X3 is the main component and In X2 Zn Y2 O Z2 or InO X1 The region where is the main component may not have a clear boundary observable. [[ID=…]]<Analysis of CAC-OS> Subsequently, the results of measurements performed on the oxide semiconductor formed on the substrate using various measurement methods will be described.

[0230] ≪Composition and Fabrication Method of Samples≫ Hereinafter, nine samples according to one aspect of the present invention will be described. Each sample is fabricated under different conditions of the substrate temperature and the oxygen gas flow rate ratio when forming the oxide semiconductor. Note that the sample has a structure including a substrate and an oxide semiconductor on the substrate.

[0231] The fabrication method of each sample will be described.

[0232] First, a glass substrate is used as the substrate. Subsequently, using a sputtering apparatus, an In-Ga-Zn oxide with a thickness of 100 nm is formed as the oxide semiconductor on the glass substrate. It should be noted that the content you provided contains some incomplete or unclear tags (such as the ellipsis in the middle). I have translated it as accurately as possible based on the existing content. If you have any further questions or need more detailed translation, please feel free to let me know.​​​​​​​​​​​​​​The film deposition conditions were: chamber pressure of 0.6 Pa, and oxide target. (In:Ga:Zn=4:2:4.1 [atomic ratio]) is used. Also, sputtering equipment It supplies 2500W of AC power to the oxide target installed inside the unit.

[0233] Furthermore, as a condition for depositing oxide films, the substrate temperature should not be intentionally heated (see below). The temperature was set to room temperature (also called RT), 130°C, or 170°C. Also, Ar and acid The flow rate ratio of oxygen gas to the raw gas mixture (hereinafter also referred to as the oxygen gas flow rate ratio) is 10% Nine samples are prepared by using either 30% or 100% of the solution.

[0234] <<Analysis by X-ray diffraction>> In this section, X-ray diffraction (XRD) was performed on nine samples. The results of the measurement (on) will be explained. The XRD device used was manufactured by Bruker. D8 ADVANCE was used. The conditions were θ / by the Out-of-plane method. In 2θ scanning, the scanning range is 15 to 50 degrees, and the step size is 0.02d. For example, the scanning speed was set to 3.0 degrees / minute.

[0235] Figure 22 shows the results of measuring the XRD spectrum using the out-of-plane method. In Figure 22, the upper section shows the measurements for a sample where the substrate temperature during film formation was 170°C. As a result, the middle section shows the measurement results for a sample where the substrate temperature during film deposition was 130°C, and the bottom section shows the film deposition results. The measurement results for the sample under substrate temperature conditions RT are shown. The left column also shows the oxygen gas Measurement results for samples with a flow rate ratio of 10%, the central column shows the oxygen gas flow rate ratio conditions. The measurement results for 30% of the samples are shown in the right column, where the oxygen gas flow rate ratio conditions are the same as for the 100% sample. The measurement results are shown.

[0236] The XRD spectrum shown in Figure 22 indicates that increasing the substrate temperature during film deposition, or the acidity during film deposition, may affect the outcome. Increasing the ratio of the primary gas flow rate increases the peak intensity around 2θ = 31°. Oh, the peak around 2θ=31° is oriented along the c-axis with respect to the direction approximately perpendicular to the surface being formed or the upper surface. A crystalline IGZO compound (CAAC(c-axis aligned crystal)) It is known to originate from the fact that it is (line)-IGZO.

[0237] Furthermore, the XRD spectrum shown in Figure 22 indicates that the substrate temperature during film deposition was low, or that oxygen gas was present. The smaller the flow rate ratio, the less pronounced the peak. Therefore, when the substrate temperature during film deposition is low, Alternatively, for samples with a small oxygen gas flow rate ratio, the measurement area is measured in the ab-plane direction and the c-axis direction. It becomes clear that the direction cannot be seen.

[0238] ≪Analysis using an electron microscope≫ This section describes samples prepared with a substrate temperature RT during film deposition and an oxygen gas flow rate ratio of 10%. HAADF (High-Angle Annular Dark Field)-S TEM(Scanning Transmission Electron Micro The results of observation and analysis using the scope (hereinafter referred to as HAADF-) will be explained below. Images acquired by STEM are also called TEM images.

[0239] Planar images acquired by HAADF-STEM (hereinafter also referred to as planar TEM images), This section explains the results of image analysis performed on cross-sectional images (hereinafter also referred to as cross-sectional TEM images). The TEM images were observed using spherical aberration correction. (Note: HAADF-STEM) For image capture, we used the JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd. The procedure involved irradiating the sample with an electron beam having an acceleration voltage of 200kV and a beam diameter of approximately 0.1nmφ.

[0240] Figure 23(A) shows the results obtained when the substrate temperature RT and oxygen gas flow rate ratio 10% were used during film deposition. This is a planar TEM image of the sample. Figure 23(B) shows the substrate temperature RT and oxygen gas during film deposition. This is a cross-sectional TEM image of a sample prepared with a flow rate ratio of 10%.

[0241] Analysis of electron diffraction patterns This section describes samples prepared with a substrate temperature RT during film deposition and an oxygen gas flow rate ratio of 10%. By irradiating it with an electron beam (also called a nanobeam electron beam) with a probe diameter of 1 nm, We will now explain the results obtained from acquiring the sub-ray diffraction patterns.

[0242] The film was fabricated using the substrate temperature RT and oxygen gas flow rate ratio of 10% shown in Figure 23(A). In the planar TEM image of the sample, black spots a1, a2, a3, a4, and black Observe the electron diffraction pattern indicated by point a5. Note that the observation of the electron diffraction pattern is performed by electron Perform the operation while illuminating the line, moving it at a constant speed from the 0-second position to the 35-second position. The result for point a1 is shown in Figure 23(C), the result for sunpoint a2 is shown in Figure 23(D), and the result for sunpoint a3 is shown in Figure 23. (E) The results for sunspot a4 are shown in Figure 23(F), and the results for sunspot a5 are shown in Figure 23(G).

[0243] From Figures 23(C), 23(D), 23(E), 23(F), and 23(G) A region of high brightness can be observed in a circular (ring-shaped) pattern. In addition, in the ring-shaped region... Multiple spots can be observed.

[0244] Also, as shown in Figure 23(B), the substrate temperature RT during film formation and the oxygen gas flow rate ratio of 10% In the cross-sectional TEM image of the sample prepared by [method], black dots b1, b2, b3, b4, and Observe the electron diffraction pattern shown by sunspot b5. The result for sunspot b1 is shown in Figure 23(H), black The result for point b2 is shown in Figure 23(I), the result for sunspot b3 is shown in Figure 23(J), and the result for sunspot b4 is shown in Figure 23. The results for (K) and sunspot b5 are shown in Figure 23(L).

[0245] From Figures 23(H), 23(I), 23(J), 23(K), and 23(L) A ring-shaped area of ​​high brightness can be observed. In addition, multiple spots can be observed within the ring-shaped area. It can be measured.

[0246] Here, for example, with respect to CAAC-OS having InGaZnO4 crystals, the sample surface is flat When an electron beam with a probe diameter of 300 nm is incident on the row, the (00) of the InGaZnO4 crystal 9) A diffraction pattern containing spots originating from the plane is observed. In other words, CAAC-OS It is found that it has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface to be formed or the upper surface. On the other hand, when an electron beam with a probe diameter of 300 nm is incident on the same sample perpendicular to the sample surface... When this is done, a ring-shaped diffraction pattern is observed. In other words, CAAC-OS is a-axis and It can be seen that the b-axis does not have any orientation.

[0247] Furthermore, nanocrystalline oxide semiconductors semiconductor. (Hereinafter referred to as nc-OS.) with a larger probe diameter When electron diffraction is performed using an electron beam (for example, 50 nm or more), a halo pattern can be observed. Diffraction patterns are observed. Also, for nc-OS, a small probe diameter electron beam (for example) When nanobeam electron diffraction is performed using a beam of less than 50 nm, bright spots are observed. Furthermore, when nanobeam electron diffraction is performed on nc-OS, it forms a circular pattern (ring shape). In some cases, areas of high brightness may be observed. Furthermore, multiple bright spots may be observed within a ring-shaped region. It may be measured.

[0248] Electron diffraction of samples prepared with substrate temperature RT and oxygen gas flow rate ratio of 10% during film deposition. The pattern has a ring-shaped area of ​​high brightness, and multiple bright spots within that ring-shaped area. Samples prepared with a substrate temperature RT during film deposition and an oxygen gas flow rate ratio of 10% showed the following electron beam activity: The folding pattern is nc-OS, and there is no orientation in the planar and cross-sectional directions. stomach.

[0249] Based on the above, oxide semiconductors with a low substrate temperature during film formation or a small oxygen gas flow rate ratio are It is clearly different from both amorphous oxide semiconductor films and single-crystal oxide semiconductor films. It can be presumed that it possesses such properties.

[0250] ≪Elemental analysis≫ This section discusses energy-dispersive X-ray spectroscopy (EDX). Using X-ray spectroscopy, EDX mapping is obtained and evaluated. By performing this evaluation, the film was fabricated at a substrate temperature RT during deposition and an oxygen gas flow rate ratio of 10%. The results of the elemental analysis of the sample are described below. Note that the EDX measurement was performed using an elemental analyzer. The JED-2300T energy-dispersive X-ray analyzer manufactured by JEOL Ltd. will be used. A Si drift detector is used to detect the X-rays emitted from the sample.

[0251] In EDX measurement, electron beam irradiation is performed on each point in the analyte region of the sample, and this generates The energy and number of characteristic X-rays emitted from the sample were measured, and the corresponding EDX spectrum was obtained for each point. In this embodiment, the peaks of the EDX spectrum at each point are determined by the electron transition of the In atom to the L shell. Electronic transitions, including electron transitions of Ga atoms to the K shell, electron transitions of Zn atoms to the K shell, and electron transitions of O atoms to the K shell. The data is attributed to the child transitions, and the ratio of each atom at each point is calculated. This is then used as the analysis target for the sample. By performing this operation on the morphological region, we obtain an EDX mapping that shows the distribution of the ratios of each atom. It is possible.

[0252] Figure 24 shows samples prepared with a substrate temperature RT and an oxygen gas flow rate ratio of 10% during film deposition. Figure 24(A) shows the EDX mapping in the cross-section. (The ratio of Ga atoms to total atoms is in the range of 1.18 to 18.64 [atomic%]) Figure 24(B) shows the EDX mapping of In atoms (In atoms relative to all atoms). The ratio of offspring is in the range of 9.28 to 33.74 [atomic%]. (Figure 24) (C) shows the EDX mapping of Zn atoms (the ratio of Zn atoms to all atoms is 6.69 to The range is 24.99 [atomic%]. Also, Figure 24(A), Figure 24( Figures B) and 24(C) show the substrate temperature RT and oxygen gas flow rate ratio of 10% during film deposition. The cross-section of the sample prepared by shows the same range. Note that EDX mapping is Within the range, the more elements measured, the brighter the image becomes, and the fewer elements measured, the dimmer the image becomes. The light and dark areas indicate the proportion of elements. Also, the magnification of the EDX mapping shown in Figure 24 is 720. It's ten thousand times more.

[0253] In the EDX mapping shown in Figures 24(A), 24(B), and 24(C), the image A relative distribution of light and dark is observed, and the substrate temperature RT and oxygen gas flow rate ratio 10 during film deposition are also observed. In the sample prepared using %, it can be observed that each atom is distributed in a specific way. Then, the areas enclosed by solid lines and dashed lines shown in Figures 24(A), 24(B), and 24(C) Focus on the range.

[0254] In Figure 24(A), the area enclosed by the solid line contains a relatively large amount of dark areas, while the area enclosed by the dashed line... This includes a relatively large number of bright areas. Also, in Figure 24(B), the area enclosed by the solid line is relatively The area enclosed by the dashed line contains many bright regions, while the area enclosed by the dashed line contains relatively many dark regions.

[0255] In other words, the area enclosed by the solid line is a region with a relatively high concentration of In atoms, and the area enclosed by the dashed line is a region with a relatively high concentration of In atoms. This is a region with relatively few atoms. Here, in Figure 24(C), in the area enclosed by the solid line The right side is a relatively bright area, and the left side is a relatively dark area. Therefore, it is enclosed by a solid line. The range is, In X2 Zn Y2 O Z2 , or InO X1 These are the regions whose main components are these elements.

[0256] Furthermore, the area enclosed by the solid line is a region with relatively few Ga atoms, and the area enclosed by the dashed line is a region with Ga This is a region with a relatively high concentration of atoms. In Figure 24(C), the area enclosed by the dashed line is the upper left region. The area is relatively bright, while the area in the lower right is relatively dark. Therefore, The area enclosed by the dashed line is GaO X3、 or Ga X4 Zn Y4 O Z4 and other regions where the main component is is.

[0257] Also, from FIGS. 24(A), 24(B), and 24(C), the distribution of In atoms is relatively uniformly distributed compared to G a atoms, and the region where InO X1 is the main component is In X 2Zn Y2 O Z2 appears to be connected to each other through the region where it is the main component and is formed. Thus, In X2 Zn Y2 O Z2 , or the region where InO X1 is the main component is formed by spreading in a cloud shape.

[0258] Thus, the region where GaO X3 and other substances are the main components, and In X2 Zn Y2 O Z2 , or InO X1 is the main component, and the In-Ga-Z n oxide having a structure in which they are unevenly distributed and mixed can be referred to as CAC-OS.

[0259] Also, the crystal structure in CAC-OS has an nc structure. The nc structure of CAC-OS has several bright spots (spots) in addition to the bright spots (spots) caused by single crystal, polycrystal, or CAAC structure in the electron diffraction image. Or the crystal <00XXXXX>structure is defined as having several bright spots (spots) or, in addition to several bright spots (spots), a region with high brightness appears in a ring shape. is.

[0260] Also, from FIGS. 24(A), 24(B), and 24(C), GaO X3 ​etc. The region is a fraction, and In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component Iz is observed at wavelengths between 0.5 nm and 10 nm, or between 1 nm and 3 nm. Preferably, in EDX mapping, the diameter of the region where each element is the main component is 1 nm or less. The upper limit should be 2nm or less.

[0261] Based on the above, CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed. It has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Na Regions where such is the main component, and In X2 Zn Y2 O Z2 , or InO X1 The main component is It has a mosaic-like structure in which regions are phase-separated from each other, with each region being the main component of a particular element.

[0262] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X This region has higher conductivity compared to regions where 3 is the main component. X2 Zn Y2 O Z2 , or InO X1 As the carrier flows through the region where acid is the main component, Conductivity as a semiconductor is exhibited. Therefore, In X2 Zn Y2 O Z2 , or InO X1 Regions where this is the main component are distributed in a cloud-like manner within the oxide semiconductor, resulting in a high field effect. Fruit mobility (μ) can be achieved.

[0263] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties compared to the region where GaO is the main component. X3 etc. The distribution of regions where this is the main component within the oxide semiconductor suppresses leakage current and improves performance. Switching operation can be achieved.

[0264] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation caused by factors such as In X2 Zn Y2 O Z2 , or InO X1 The conductivity resulting from this works in a complementary manner. This results in a high on-current (I on ), and achieving high field effect mobility (μ) It is possible.

[0265] Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is, It is ideal for various semiconductor devices, including displays.

[0266] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0267] (Embodiment 6) In this embodiment, a display device to which the semiconductor device described in the above embodiment is applied is The display module is described below. The semiconductor device, as an example, includes a gate driver circuit. Applicable to the path section, source driver circuit section, or part of the pixel section. An example of Joule will be explained below using Figures 17 and 18.

[0268] <Top view of the display module> Figure 17 is a top view showing an example of a display module. The display module 7 shown in Figure 17 00 is a pixel portion 702 provided on the first substrate 701 and provided on the first substrate 701 The source driver circuit section 704 and the gate driver circuit section 706, and the pixel section 702, A screen is arranged to surround the screw driver circuit section 704 and the gate driver circuit section 706. The material 712 and the second substrate 705 provided opposite the first substrate 701 are The first substrate 701 and the second substrate 705 are sealed with a sealing material 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit The passage 706 is sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in Figure 17, between the first substrate 701 and the second substrate 705 there is A display element is provided.

[0269] Furthermore, the display module 700 is surrounded by a sealing material 712 on the first substrate 701. In a region different from the region where the pixel section 702, source driver circuit section 704, and gate are located, The driver circuit section 706 and the FPC terminal section 708 (FPC: Fl) are electrically connected to each other. An exible printed circuit (FPC) is provided. Also, the FPC terminal section 7 FPC716 is connected to 08, and FPC716 controls the pixel unit 702 and the source dry Various signals are supplied to the circuit section 704 and the gate driver circuit section 706. The element section 702, the source driver circuit section 704, the gate driver circuit section 706, and the FPC terminal Each sub-unit 708 is connected to a signal line 710. Each supplied by FPC716 The seed signal, etc., is transmitted via the signal line 710 to the pixel unit 702, the source driver circuit unit 704, and the gateway. This is supplied to the driver circuit section 706 and the FPC terminal section 708.

[0270] Furthermore, the display module 700 may be provided with multiple gate driver circuit sections 706. The display module 700 includes a source driver circuit section 704 and a gate driver circuit section 704. This example shows the path portion 706 formed on the same first substrate 701 as the pixel portion 702, but The configuration is not limited to this. For example, only the gate driver circuit section 706 may be placed on the first substrate 701. Alternatively, the source driver circuit section 704 may be formed on the first substrate 701. This is also good. In this case, a substrate on which a source driver circuit or gate driver circuit etc. is formed ( For example, a drive circuit substrate (formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) is placed on the first substrate 7 This configuration can also be implemented in 01. Note that the method for connecting the separately formed drive circuit board is particularly important. It is not limited to the COG (Chip On Glass) method, wire bonding Methods such as rigging can be used.

[0271] Furthermore, the pixel section 702, source driver circuit section 704 and The gate driver circuit section 706 has multiple transistors. As for the transistor, the transistor described in the previous embodiment can be used.

[0272] Furthermore, the display module 700 can have various elements. These elements may include, for example, , liquid crystal elements, EL (electroluminescent) elements (EL elements including organic and inorganic materials) Organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) LEDs, transistors (transistors that emit light in response to current), electron emission elements, electric Ink cartridges, electrophoretic elements, grating light bulbs (GLVs), plasma displays Using iPanel (PDP) and MEMS (Micro-Electro-Mechanical Systems) Display elements, digital micromirror devices (DMDs), DMSs (digital micro • Shutter), IMOD (Interferometric Modulation) element, MEMS display elements using the tamper method, MEMS display elements using the optical interference method, electrowet Display elements, piezoelectric ceramic displays, display elements using carbon nanotubes, etc. It has at least one. In addition to these, it can control through electrical or magnetic action. The display medium may have properties such as brightness, reflectance, and transmittance that change. An example of a display device used is an EL display. Examples of display devices include field emission displays (FEDs) or SEDs. Flat-panel display (SED: Surface-conduction Electron) Examples include n-emitter displays. For example, liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays) These include LCD displays, direct-view LCD displays, and projection LCD displays. An example of a display device using electronic ink or electrophoretic elements is electronic paper. Furthermore, when realizing a transflective liquid crystal display or a reflective liquid crystal display, pixels The electrodes can be made to function as reflective electrodes, either partially or entirely. The pixel electrodes may be made of aluminum, silver, or the like, either partially or entirely. Furthermore, in that case, it is also possible to install memory circuits such as SRAM below the reflective electrode. This further reduces power consumption. Next, we will explain the configuration using liquid crystal elements as display elements.

[0273] The display method in the display module 700 is either progressive or interlaced. The S method and other methods can be used. Also, when displaying in color, the color elements controlled by pixels can be used. This is not limited to the three colors RGB (R stands for red, G for green, and B for blue). For example, a pixel with red (R) It may consist of four pixels: a G pixel, a B pixel, and a W (white) pixel. Alternatively, a penta Like an RGB array, one color element is composed of two of the RGB colors, and different colors are produced depending on the color element. You can also choose two colors to create the color scheme. Alternatively, you can add yellow, cyan, magenta, etc. to RGB. You may add one or more colors. Note that the size of the display area differs for each dot of the color element. It may also be done. However, the disclosed invention is not limited to a color display device, and may also be a color display device. It can also be applied to display devices with a black display.

[0274] Also, white light is used for backlights (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.) In order to display full color on a display device using W), a color layer (also called a color filter) is used. .) may be used. The colored layer may be, for example, red (R), green (G), and blue (B). Yellow (Y) and other colors can be used in appropriate combinations. By using a colored layer, Compared to not using a colored layer, the color reproduction can be improved. In this case, the colored layer By arranging regions that have a colored layer and regions that do not have a colored layer, the region that does not have a colored layer White light in the area may be used directly for display. A portion of the area may be placed without a colored layer. This reduces the decrease in brightness caused by the colored layer when displaying bright content, and reduces power consumption by 20%. In some cases, this can be reduced by about 30%. However, this is not possible with self-emissive elements such as organic EL elements and inorganic EL elements. When using elements for full-color display, R, G, B, Y, and white (W) are used in each case. It is also acceptable to emit light from an element that has a light-emitting color. By using a self-luminescent element, a colored layer can be used. In some cases, power consumption can be reduced even further than in the case where it was used. The following explanation concerns a so-called reflective liquid crystal display module, which does not have a backlight or similar component. To perform the task.

[0275] <Cross-section of the display module> Figure 18 shows a cross-sectional view of the dashed-dotted line QR shown in Figure 17. Details about the rule will be explained below.

[0276] The display module 700 shown in Figure 18 comprises a wiring section 711, a pixel section 702, and a sensor It has a driver circuit section 704 and an FPC terminal section 708. It also has a wiring section 711 has a signal line 710. The pixel section 702 has a transistor 750 and a capacitor. It has element 790. Furthermore, the source driver circuit section 704 has transistor 752. ru.

[0277] Transistors 750 and 752 can use the transistors shown above. can.

[0278] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor reduces the current value in the off state (off current value). This allows for longer holding times of electrical signals such as image signals, and power supply When enabled, the write interval can also be set to a longer duration. Therefore, the frequency of refresh operations can be reduced. This allows for reduced power consumption.

[0279] Furthermore, the transistor used in this embodiment is capable of obtaining a relatively high field-effect mobility. Therefore, high-speed operation is possible. For example, a transistor capable of such high-speed operation can be used in a display device. By using it in the pixel section, the switching transistor and the drive circuit used in the drive circuit are used. The transistors can be formed on the same substrate. That is, as a separate drive circuit, Since it is not necessary to use semiconductor devices formed from silicon wafers, etc., the semiconductor device part The number of parts can be reduced. Also, in the pixel section, high-speed drive transistors By using this method, high-quality images can be provided.

[0280] Capacitive element 790 has a structure in which a dielectric is located between a pair of electrodes. More specifically, capacitive element One electrode of sub-electrode 790 is the same conductive film that functions as the gate of transistor 750. Using a conductive film formed in a single process, the other electrode of the capacitive element 790 is a transistor. A conductive film is used that functions as both a source electrode and a drain electrode. Additionally, a pair of electrodes are used. The dielectric sandwiched in between functions as an insulator, which acts as the gate insulating film of transistor 750. A membrane is used.

[0281] Also, in Figure 18, transistor 750, transistor 752, and capacitive element 79 Insulating films 764, 768 and a planarizing insulating film 770 are provided on the surface.

[0282] For example, the insulating film 764 can be formed using a PECVD apparatus to create a silicon oxide film and an oxidized nitride film. A silicon film or the like can be formed. Furthermore, as the insulating film 768, for example, a PECVD apparatus... A silicon nitride film or the like can be formed using this. Furthermore, as the planarizing insulating film 770, Liimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, poly Heat-resistant organic materials such as mid-resins and epoxy resins can be used. Even when a planar insulating film 770 is formed by stacking multiple insulating films made of these materials, That's fine. Alternatively, the planar insulating film 770 may be omitted.

[0283] Furthermore, signal line 710 is connected to the source and drain electrodes of transistors 750 and 752. It is formed using the same process as the conductive film that functions as a transistor 75. A conductive film formed in a different process from the source and drain electrodes, for example, a g A conductive film may be formed in the same process as a conductive film that functions as a signal line. For example, when using materials containing copper, signal delays caused by wiring resistance are reduced. This allows for display on a large screen.

[0284] Furthermore, the FPC terminal section 708 includes a connecting electrode 760, an anisotropic conductive film 780, and FPC 71 It has 6. The connecting electrode 760 is the source electrode of transistors 750 and 752 and It is formed using the same process as the conductive film that functions as a rain electrode. Also, the connecting electrode 760 is F The terminals on the PC716 are electrically connected via the anisotropic conductive film 780.

[0285] Furthermore, for example, glass substrates can be used as the first substrate 701 and the second substrate 705. This is possible. Also, the first substrate 701 and the second substrate 705 are flexible substrates. A flexible substrate may be used. Examples of such flexible substrates include plastic substrates. ru.

[0286] Furthermore, a structure 778 is provided between the first substrate 701 and the second substrate 705. The fabricated body 778 is a columnar spacer obtained by selectively etching an insulating film. It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. This is possible. Furthermore, a spherical spacer may be used as structure 778. In this configuration, we have provided an example of a setup in which the structure 778 is provided on the first substrate 701 side. However, it is not limited to this. For example, a configuration in which the structure 778 is provided on the second substrate 705 side, Alternatively, the structure 778 may be provided on both the first substrate 701 and the second substrate 705. .

[0287] Furthermore, the second substrate 705 side has a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, and a light-shielding film 738 and a film in contact with the colored film 736 An insulating film 734 is provided.

[0288] Figure 18 shows a cross-sectional view of a display module 700 as an example, which has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. For 776, a liquid crystal material with a dielectric anisotropy of 2 or more and 3.8 or less is used. Conductive film 7 74 is provided on the second substrate 705 side and functions as a counter electrode. (See Figure 18) The display module 700 uses a voltage applied to the conductive film 772 and the conductive film 774 to generate liquid crystals. The orientation of layer 776 changes, controlling the transmission and opacity of light, thereby displaying an image. It is possible.

[0289] Furthermore, the conductive film 772 serves as the source electrode and drain electrode of the transistor 750. It is connected to a conductive film that functions as a pixel. The conductive film 772 is formed on the planar insulating film 770 and is connected to the pixel. It functions as an electrode, that is, one of the electrodes of the display element. Furthermore, the conductive film 772 acts as a reflective electrode. It has the function of being a conductive film 77, which utilizes ambient light. The display module 700 shown in Figure 18 uses ambient light to display a conductive film 77 This is a so-called reflective type color liquid crystal display device that reflects light at point 2 and displays it through a colored film 736. ru.

[0290] The conductive film 772 is a conductive film that is transparent in visible light, or a conductive film that is transparent in visible light. A conductive film with light-transmitting properties can be used. Examples of conductive films that are transparent in visible light include: For example, a material containing one element selected from indium (In), zinc (Zn), and tin (Sn). It is advisable to use a material. Examples of conductive films that are reflective in visible light include aluminum. Alternatively, a material containing silver may be used. In this embodiment, the conductive film 772 is, A reflective conductive film is used in the visible light spectrum.

[0291] Furthermore, when a conductive film that is reflective in visible light is used as the conductive film 772, The film may also be in a layered structure. For example, an aluminum film with a thickness of 100 nm may be formed as the lower layer. A 30nm thick silver alloy film (for example, an alloy film containing silver, palladium, and copper) is formed on the upper layer. The above structure provides the following excellent effects.

[0292] (1) The adhesion between the base film and the conductive film 772 can be improved. (2) By using a chemical solution It is possible to etch both the aluminum film and the silver alloy film at the same time. (3) Conductive The cross-sectional shape of the film 772 can be made into a good shape (for example, a tapered shape). (3) The reason for this is that aluminum films have a slower etching rate with chemicals than silver alloy films. Alternatively, if the lower aluminum film is exposed after etching of the upper silver alloy film, the silver alloy Electrons are drawn from aluminum, a metal that is less noble than the film, or in other words, a metal with a high ionization tendency. To achieve this, etching of the silver alloy film is suppressed, and etching of the underlying aluminum film progresses. This is because it speeds up the writing process.

[0293] Furthermore, in the display module 700 shown in Figure 18, the planar insulating film 7 of the pixel section 702 A portion of 70 is provided with irregularities. These irregularities are, for example, formed by organic resin on the planar insulating film 770. It can be formed by creating a film or the like, and then providing irregularities on the surface of the organic resin film. The conductive film 772, which functions as a reflective electrode, is formed along the above irregularities. Therefore, the outer When light is incident on the conductive film 772, the light is diffusely reflected on the surface of the conductive film 772. This makes it possible to improve visibility. As shown in Figure 18, reflective color liquid By using a crystal display device, it becomes possible to display without using a backlight, thus reducing consumption It can reduce power consumption.

[0294] The display module 700 shown in Figure 18 is a reflective color liquid crystal display module. The examples given are not limited to these. For example, the conductive film 772 may be transparent in visible light. A transparent color liquid crystal display module may also be used by employing a certain conductive film. In the case of a liquid crystal display module, the irregularities provided on the planar insulating film 770 are provided It is also acceptable to omit this configuration.

[0295] Note that although not shown in Figure 18, the side of the conductive films 772 and 774 that contacts the liquid crystal layer 776. Alternatively, an orientation film may be provided in each of them. Also, although not shown in Figure 18, Optical components (optical substrates) such as optical members, phase difference members, and anti-reflective members may be provided as appropriate. For example, circular polarization using a polarizing substrate and a phase difference substrate may be used. Also, a transmissive display module For Joule or transflective display modules, the light source is a backlight, siding You may also provide threads or other means.

[0296] Examples of liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, and polymer dispersion liquids. Crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials are subject to the conditions This leads to the cholesteric phase, smectic phase, cubic phase, chiral nematic phase, It shows isotropic equality.

[0297] Furthermore, when employing a transverse electric field method, it is also possible to use a liquid crystal that exhibits a blue phase without using an alignment layer. The blue phase is one of the liquid crystal phases, and as the temperature of cholesteric liquid crystal is increased, the cholesteric phase This phase appears just before the transition from the blue phase to the isotropic phase. The blue phase only appears within a narrow temperature range. To improve the temperature range, a liquid crystal assembly containing several weight percent or more of chiral agent was mixed in. The resulting material is used in the liquid crystal layer. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent provides a fast response. Because it has a short angle and is optically isotropic, orientation processing is unnecessary, and it has low dependence on the viewing angle. Furthermore, since an alignment film does not need to be applied, rubbing treatment is also unnecessary. This can prevent electrostatic discharge damage caused by electrostatic discharge, and can also prevent defects and breakage of liquid crystal display devices during the manufacturing process. This can reduce losses.

[0298] Furthermore, when using liquid crystal elements as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin (Field Switching) mode, ASM (Axially Symmetry) tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferroe) lectric Liquid Crystal) mode, AFLC (AntiFerr Features such as the (electric Liquid Crystal) mode can be used. .

[0299] Furthermore, a normally black type liquid crystal display device, for example, one that employs vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes can be listed. For example, MVA (Multi-Domain Vertical Alignment) ) Mode, PVA (Patterned Vertical Alignment) Mode You can use modes such as ASV mode.

[0300] (Embodiment 7) In this embodiment, the display module described in the previous embodiment is equipped with a touch sensor By installing a (contact detection device), it can function as an input / output device (also called a touch panel). A configuration that allows this will be explained using Figures 19 and 20. The above will be described below. In some cases, explanations of parts that overlap with the embodiments may be omitted.

[0301] Figure 19 is a projection diagram illustrating the configuration of the input / output device.

[0302] Figure 19(A) is a projection view of the input / output device 800, and Figure 19(B) is a projection view of the input / output device 800. This is a projection diagram illustrating the configuration of the detection unit 820U equipped with the device.

[0303] Figure 20 is a cross-sectional view of the input / output device 800 shown in Figure 19(A) at the Z1-Z2 point.

[0304] The input / output device 800 described in this embodiment is equipped with a window portion 834 that transmits visible light and Multiple detection units 820U are arranged in a matrix, in the row direction (indicated by arrow Rx in the figure). Multiple detection units 820U arranged in (su) are electrically connected to scan lines G1, in the column direction ( Multiple detection units 820U located at the points indicated by arrows Ry in the diagram are electrically connected to the signal The first line DL, and the detection unit 820U, scan line G1 and signal line DL support each other. An input device 850 comprising a base material 836 and a window portion 834 that overlaps and is arranged in a matrix A display module comprising a plurality of pixels 802 and a second substrate 810 supporting the pixels 802. It has a 801 (see Figures 19(A) to 19(C)).

[0305] The detection unit 820U has a detection element Ca that overlaps the window portion 834 and an electrical connection between the detection element Ca and the window portion 834. It includes a detection circuit 839 that is connected to the target (see Figure 19(B)).

[0306] The sensing element Ca sandwiches an insulating layer 823, an insulating layer 823 (not shown in Figure 19(B)). It comprises a first electrode 821 and a second electrode 822 (see Figure 19(B)).

[0307] The detection circuit 839 is supplied with a selection signal and detects based on the change in capacitance of the detection element Ca. It supplies signal data.

[0308] Scan line G1 can supply the selection signal, and signal line DL can supply the detection signal DATA. The detection circuit 839 is positioned to overlap the gaps between the multiple window sections 834. ru.

[0309] Furthermore, the input / output device 800 described in this embodiment includes a detection unit 820U and a detection unit. A colored layer is provided between the window portion 834 of unit 820U and the pixel 802 that overlaps with it.

[0310] The input / output device 800 described in this embodiment is equipped with a window portion 834 that transmits visible light. An input device 850 equipped with multiple detection units 820U, and pixels 802 that overlap the window portion 834 It has multiple display modules 801, and includes a colored layer between the window portion 834 and the pixels 802. It is composed of n.

[0311] As a result, the input / output device provides a detection signal based on the change in capacitance and a detection unit that supplies it. To supply location information of the detector, and the image associated with the location information of the detection unit. Information can be displayed. As a result, a novel input / output device with superior convenience or reliability. We can provide this.

[0312] Furthermore, the input / output device 800 is a flexible cable that receives signals supplied by the input device 850. A frame that supplies signals containing the substrate FPC1 and / or image information to the display module 801. It may also be equipped with a flexible printed circuit board (FPC2).

[0313] Furthermore, a protective substrate 837 and a protective layer 837 protect the input / output device 800 by preventing damage. p and / or an anti-reflective layer 867p that reduces the intensity of ambient light reflected by the input / output device 800 It's a good idea to be prepared.

[0314] Furthermore, the input / output device 800 supplies selection signals to the scan lines of the display module 801. Line drive circuit 803g, signal supply wiring 811 and flexible circuit board FPC2 and electrical It has terminals 819 that are connected to each other.

[0315] The individual elements that make up the input / output device 800 are described below. The components cannot be clearly separated, and one component may also serve as part of another component or include a part of another component. For example, an input device 850 having a colored layer in a position that overlaps with multiple window sections 834 is an input device. It is both a force device 850 and a color filter.

[0316] The input / output device 800 includes an input device 850 and a display module 801 (Figure 19). (See (A)).

[0317] The input device 850 supports a plurality of detection units 820U and detection units 820U. It comprises a first substrate 836. For example, multiple detection units are arranged in a matrix of 40 rows and 15 columns. The 820U is placed on the first base material 836.

[0318] The window section 834 transmits visible light.

[0319] A colored layer that transmits light of a predetermined color is provided in a position overlapping the window portion 834. For example, blue light A colored layer CFB that transmits light, a colored layer CFG that transmits green light, or a colored layer that transmits red light It features a color layer CFR (see Figure 19(B)).

[0320] In addition to blue, green, and / or red, there is also a colored layer that transmits white light or yellow light. It can be equipped with a colored layer that transmits light of various colors, such as a colored layer that transmits light of a certain color.

[0321] Metal materials, pigments, or dyes can be used in the colored layer.

[0322] A light-blocking layer BM is provided to surround the window portion 834. The light-blocking layer BM blocks light from the window portion 834. It is difficult for light to pass through.

[0323] Carbon black, metal oxides, and composite oxides containing solid solutions of multiple metal oxides are used for light shielding. It can be used in the sexual layer BM.

[0324] Scan line G1, signal line DL, wiring VPI, wiring RES are located in positions that overlap with the light-shielding layer BM. It is equipped with wiring VRES and a detection circuit 839.

[0325] Furthermore, a translucent overcoat layer can be provided to cover the colored layer and the light-shielding layer BM. Cut.

[0326] The sensing element Ca consists of a first electrode 821, a second electrode 822, and the first electrode 821 and the second An insulating layer 823 is provided between the electrodes 822 (see Figure 20).

[0327] The first electrode 821 is formed, for example, in an island-like shape, so as to be separated from other regions. In particular, To prevent the user of the input / output device 800 from identifying the first electrode 821, the first electrode 821 A configuration in which a layer that can be fabricated in the same process is placed close to the first electrode 821 is preferred. It is preferable to place the first electrode 821 and the first electrode 821 in close proximity to it. It is desirable to minimize the number of window sections 834 placed in the gaps between layers. In particular, the window section 834 in the gaps should be minimized. A configuration without section 834 is preferred.

[0328] For example, the first electrode 821 or the second electrode 822 of the sensing element Ca placed in the atmosphere When something with a dielectric constant different from that of the atmosphere approaches, the capacitance of the sensing element Ca changes. When an object such as a finger approaches the sensing element Ca, the capacitance of the sensing element Ca changes. Therefore, it can be used in proximity detectors.

[0329] The first electrode 821 and the second electrode 822 include a conductive material.

[0330] For example, inorganic conductive materials, organic conductive materials, metals or conductive ceramics, etc. It can be used for the electrode 821 and the second electrode 822.

[0331] Specifically, the first electrode 821 and the second electrode 822 are made of aluminum, chromium, Choose from copper, tantalum, titanium, molybdenum, tungsten, nickel, silver, or manganese. The identified metal element, an alloy containing the above-mentioned metal element, or a combination of the above-mentioned metal elements A metal alloy can be used.

[0332] Alternatively, the first electrode 821 and the second electrode 822 may be indium oxide, indium Conductive materials such as tin oxide, indium zinc oxide, zinc oxide, and zinc oxide with added gallium Oxides can be used.

[0333] Alternatively, graphene or graphite may be used as the first electrode 821 and the second electrode 822. A graphene-containing film can be used, for example, a film-like graphene oxide film. A film containing ions can be formed by reduction. Methods of reduction include applying heat or Methods using reducing agents can be cited.

[0334] Alternatively, conductive polymers may be used as the first electrode 821 and the second electrode 822. can.

[0335] The detection circuit 839 includes, for example, transistors M1 to M3. Circuit 839 includes wiring that supplies power potential and signals. For example, signal line DL, wiring VPI. This includes wiring CS, scan line G1, wiring RES, and wiring VRES, etc.

[0336] The detection circuit 839 may be placed in an area that does not overlap with the window portion 834.

[0337] Conductive materials are used for wiring (e.g., signal line DL, wiring VPI, wiring CS, scan line G1) It can be applied to wiring RES and wiring VRES, etc. For example, inorganic conductive materials, organic Conductive materials, metals, or conductive ceramics can be used for wiring. Alternatively, The same material that can be used for the first electrode 821 and the second electrode 822 is used for wiring. It may be applied as follows.

[0338] Also, aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum Metallic materials such as butene, iron, cobalt, copper, or palladium, or alloy materials containing such metallic materials This can be used for scan line G1, signal line DL, wiring VPI, wiring RES, and wiring VRES. can.

[0339] Alternatively, the detection circuit 839 may be formed on the first substrate 836. Or, it may be formed on another substrate. The detection circuit 839 may be transferred to the first substrate 836.

[0340] The first substrate 836 and the second substrate 810 are glass substrates or flexible materials ( For example, resin, resin film, or plastic film can be used.

[0341] More specifically, the first substrate 836 and the second substrate 810 are alkali-free glass. Soda-lime glass, potash glass, or crystal glass can be used. Alternatively, the first base material 836 may be polyester, polyolefin, polyamide, poly Using resin films or resin sheets such as mido, polycarbonate, or acrylic resin. It is possible.

[0342] Examples of protective substrates 837 and / or protective layers 837p include glass, polyester, etc. Polyolefin, polyamide, polyimide, polycarbonate, or acrylic resin Resin films, resin plates, or laminates such as these can be used.

[0343] For example, a hard coat layer or a ceramic coat layer can be used as the protective layer 837p. This can be done. Specifically, a layer containing UV-curing resin or aluminum oxide is placed on the second electrode. It may be formed in a position that overlaps with 822.

[0344] The display module 801 includes a plurality of pixels 802 arranged in a matrix (Figure 1). 9(C)).

[0345] For example, pixel 802 includes sub-pixels 802B, 802G, and 802R. Each sub-pixel is equipped with a display element and a pixel circuit that drives the display element.

[0346] Furthermore, sub-pixel 802B of pixel 802 is positioned to overlap with the colored layer CFB, and sub-pixel 8 02G is positioned to overlap with the colored layer CFG, and sub-pixel 802R overlaps with the colored layer CFR. It is positioned.

[0347] The colored layer CFR is located in a position that overlaps with the liquid crystal element 880. Note that the liquid crystal element 880 is located on one side. It has a reflective electrode 872 as an electrode (see Figure 20). As a result, reflection occurs at the reflective electrode 872. A portion of the ambient light is transmitted through the colored CFR layer and emitted in the direction of the arrow shown in the figure. The electrode 872 is the same as the conductive film 772 that functions as a reflective electrode as shown in the previous embodiment. The configuration can be as follows. In addition, the liquid crystal element 880 has a dielectric anisotropy of 2 or more and 3.8 or less. It has a liquid crystal layer underneath.

[0348] Furthermore, there is a light-shielding layer BM surrounding the colored layer (for example, the colored layer CFR).

[0349] The scan line driver circuit 803g includes transistor 803t and capacitor 803c (Figure 20). reference).

[0350] The detection signal DATA supplied by the detection unit 820U is converted and used for flexible circuit board (FPC) Various circuits that can supply power to 1 can be used in the converter CONV (Figure See 19(A) and Figure 20).

[0351] For example, transistor M4 can be used in the converter CONV.

[0352] The display module 801 is equipped with an anti-reflective layer 867p in a position that overlaps with the pixels. For layer 867p, for example, a circular polarizer can be used.

[0353] As shown in Figure 19(A), the display module 801 is capable of supplying signals. It is equipped with wire 811, and terminal 819 is provided on wire 811. Note that the image signal and synchronization A flexible circuit board (FPC2) capable of supplying signals such as signals is electrically connected to terminal 819. It is connected.

[0354] Note that a printed circuit board (PWB) is attached to the flexible circuit board FPC2. You can.

[0355] The display module 801 has wiring such as scan lines, signal lines, and power lines. The membrane can be used for wiring.

[0356] The wiring of the display module 801 may include, for example, aluminum, chromium, copper, and Tal, titanium, molybdenum, tungsten, nickel, yttrium, zirconium, A metallic element selected from silver or manganese, an alloy containing the aforementioned metallic elements, or the above Alloys and the like, which combine the metal elements, can be used. In particular, aluminum, chromium One or more elements selected from the following: luminous iron, copper, tantalum, titanium, molybdenum, and tungsten. It is preferable that it contains a copper-manganese alloy. In particular, a copper-manganese alloy is suitable for microfabrication using the wet etching method. It is suitable for.

[0357] The specific wiring configuration of the display module 801 is as follows: Titanium on an aluminum film A two-layer structure in which a titanium film is stacked on top of a titanium nitride film, a two-layer structure in which a titanium film is stacked on top of a titanium nitride film, titanium nitride film A two-layer structure with a tungsten film laminated on top, or a tantalum nitride film or tungsten nitride film on top A two-layer structure consisting of stacked tungsten films, a titanium film, and an aluminum film stacked on top of the titanium film. A three-layer structure can be used, which involves layering and then forming a titanium film on top of it. Alternatively, Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and sulfite are present on the luminium film. A layered alloy film or nitride film made of one or more candium-selected alloy films or nitride films. A layered structure can be used. Alternatively, a permeable containing indium oxide, tin oxide, or zinc oxide can be used. A conductive material with photocatalytic properties may also be used.

[0358] (Embodiment 8) In this embodiment, an electronic device manufactured using the liquid crystal display device described in the above embodiment is A specific example of a vessel will be explained using Figure 21.

[0359] An example of an electronic device to which the present invention can be applied is a television device (television, or television). (also called a John receiver), monitors for computers, digital cameras, digital video cameras Cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, music Examples include playback devices, amusement machines (pachinko machines, slot machines, etc.), and game cabinets. A specific example of such an electronic device is shown in Figure 21.

[0360] Figure 21(A) shows a portable information terminal 1400 having a display unit. Portable information terminal 1 In the 400 model, the display unit 1402 and the operation buttons 1403 are integrated into the housing 1401. A liquid crystal display device according to one aspect of the present invention can be used in the display unit 1402.

[0361] Figure 21(B) shows the mobile phone 1410. The mobile phone 1410 has a housing 14 11 has a display unit 1412, operation buttons 1413, a speaker 1414, and a microphone 1415. It is incorporated. One embodiment of the present invention is a liquid crystal display device that is used in the display unit 1412. can.

[0362] Figure 21(C) shows the music playback device 1420. The music playback device 1420 has a housing. Unit 1421 incorporates the display unit 1422, the operation buttons 1423, and the antenna 1424. Furthermore, information can be transmitted and received via wireless signals from antenna 1424. (This invention) One embodiment of the liquid crystal display device can be used in the display unit 1422.

[0363] Display units 1402, 1412, and 1422 have a touch input function. , Display buttons displayed on display unit 1402, display unit 1412 and display unit 1422 (not shown) By touching the screen with your finger, you can operate the screen and input information.

[0364] The liquid crystal display device shown in the previous embodiment includes display unit 1402, display unit 1412 and display unit 1 By using 422, the display quality of the display unit 1402, display unit 1412 and This can be a display unit 1422.

[0365] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below.

[0366] <Notes relating to one aspect of the present invention described in the embodiments> The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to represent the present invention. This can be one embodiment. Furthermore, multiple configuration examples may be shown within a single embodiment. The combination allows for the appropriate arrangement of the configuration examples.

[0367] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other content (even partial content) described in form, and / or one or more other facts The content described in the form of implementation (even if only a part of it) may be applied, combined, or replaced. It is possible to perform tasks such as drawing.

[0368] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0369] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. , other figures (even partial ones) described in the embodiment, and / or one or more In the diagram (or even just a part of it) described in another embodiment of the number, by combining them... This allows for the creation of even more diagrams.

[0370] <Notes regarding descriptions of drawings> In this specification, phrases indicating placement such as "above" and "below" refer to the positional relationship between components. The terms are used for convenience when explaining with reference to the diagrams. The positional relationships between the components are as follows: It changes appropriately depending on the direction in which the formation is depicted. Therefore, the terms indicating the arrangement are explained in the specification. This description is not limited to the above; it can be appropriately rephrased depending on the situation.

[0371] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly It does not necessarily mean that they are in contact. For example, the expression "electrode B on insulating layer A" is also acceptable. However, it is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B This does not exclude those that include other components in between.

[0372] Furthermore, in this specification, etc., block diagrams classify components according to their function and treat them as independent of each other. It is shown as a block. However, in actual circuits, the components are divided by function. It is difficult to separate the functions, and when multiple functions are involved in a single circuit, or when multiple circuits are involved... In some cases, one function may be involved. Therefore, the blocks in the block diagram are specified in the specification. It is not limited to the components described.

[0373] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are made with clarity in mind. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings. For example... , variations in signals, voltages, or currents due to noise, or signals due to timing discrepancies This can include variations in voltage, current, and other parameters.

[0374] Furthermore, in drawings, such as top views (also called plan views or layout drawings) and perspective views... In order to ensure clarity in the drawings, some components may be omitted from the description.

[0375] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, the source and drain are referred to as one The side is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source The other side of the source and drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is indicated that the source and drain of a transistor are related to the structure or movement of the transistor. This is because it varies depending on the operating conditions, etc. Regarding the terminology for the source and drain of a transistor... Depending on the situation, you can use appropriate terms such as source (drain) terminal or source (drain) electrode. It can be replaced.

[0376] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0377] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from the reference potential; for example, the reference potential is the ground potential (earth potential). If we consider it as electric potential, then voltage can be rephrased as electric potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0378] In this specification, the terms "membrane," "layer," etc. may be used in some cases, or in a manner. Depending on the situation, they can be interchanged. For example, the term "conductive layer" can be replaced with " In some cases, the term can be changed to "conductive film." Or, for example, "insulating film." In some cases, it is possible to change the term "insulating layer" to "insulating layer."

[0379] <Notes regarding the definition of terms> The following sections will explain the definitions of terms not mentioned in the above embodiments.

[0380] <<About the switch>> In this specification, a switch means a conductive state (on state) or a non-conductive state (off state). It refers to a device that enters a state (F) and has the function of controlling whether or not to allow current to flow. Or, A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0381] For example, an electrical switch or a mechanical switch can be used. Furthermore, any switch that can control the current will suffice, and is not limited to any particular type.

[0382] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is.

[0383] Furthermore, when using a transistor as a switch, the "conductive state" of the transistor refers to: This refers to a state in which the source and drain of a transistor can be considered to be electrically short-circuited. The "non-conductive state" of a transistor means that the source and drain of the transistor are electrically disconnected. This refers to a state in which it can be considered to be in operation. Note that this also applies to operating a transistor as a simple switch. In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0384] One example of a mechanical switch is a digital micromirror device (DMD). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are Yes, it exists. The switch has electrodes that can be moved mechanically, and when those electrodes move... Therefore, it operates by controlling the states of conduction and non-conductivity.

[0385] <<Regarding channel length>> In this specification, channel length refers, for example, to the length of a semiconductor in a top view of a transistor. The body (or the part of the semiconductor through which current flows when the transistor is ON) and the gate The distance between the source and drain in the region where they overlap, or in the region where a channel is formed. It means separation.

[0386] Note that the channel length in a single transistor is not necessarily the same across all regions. No. In other words, the channel length of a single transistor may not be fixed to a single value. Therefore, in this specification, the channel length is any one of the regions in which the channel is formed. This value is the maximum, minimum, or average value.

[0387] <<Regarding channel width>> In this specification, channel width refers to, for example, the state in which a semiconductor (or transistor) is ON. The region where the part of the semiconductor through which current flows and the gate overlap when in a certain state, or the channel This refers to the length of the portion where the source and drain face each other within the formed region.

[0388] Note that the channel width in a single transistor is not necessarily the same across all regions. In other words, the channel width of a single transistor may not be fixed to a single value. Therefore, in this specification, the channel width is any of the regions in which the channel is formed. This can be defined as a single value, maximum value, minimum value, or average value.

[0389] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is the top surface of the transistor. The apparent channel width shown in the figure becomes larger, and its effect cannot be ignored. This can occur. For example, in transistors with a fine and three-dimensional structure, the side of the semiconductor... In some cases, the proportion of the channel region formed in the top view may be large. The effective channel width in which the channel is actually formed is greater than the apparent channel width shown. It will be larger.

[0390] By the way, in transistors with a three-dimensional structure, the effective channel width is Estimation by measurement can sometimes be difficult. For example, it can be difficult to determine the effective channel width from the design value. For accumulation to occur, it is necessary to assume that the shape of the semiconductor is known. Therefore, the shape of the semiconductor When the exact condition is unknown, it is difficult to accurately measure the effective channel width. .

[0391] Therefore, in this specification, in the top view of a transistor, the region where the semiconductor and the gate overlap is shown. The apparent channel is the length of the portion where the source and drain face each other in the region. Channel width is referred to as "Surrounded Channel Width (SCW)". It is sometimes referred to as "dth)". Also, in this specification, when simply referred to as channel width, it means This may refer to the enclosed channel width or apparent channel width. Or, as specified herein. Therefore, when simply referring to "channel width," it may sometimes mean the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The width of the channel, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. It is possible to make a decision.

[0392] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine the value. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The result may differ from the value obtained when calculating using the channel width.

[0393] <<About pixels>> In this specification, a pixel refers to, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and that color element Brightness is expressed using only the R (red), G (green), and B (blue) color elements. In the case of a color display device, the smallest unit of an image is a three-part image consisting of a red pixel, a green pixel, and a blue pixel. It is assumed to be composed of pixels.

[0394] Note that the color elements are not limited to three colors; there can be more, for example, RGBW (W is white). Other variations include those that add yellow, cyan, and magenta to RGB.

[0395] <<About Connection>> In this specification, etc., "A and B are connected" means that A and B are not directly connected. This includes things that are electrically connected, in addition to things that are not connected. Here, A and B are electrically connected To be connected means that there is an object between A and B that has some kind of electrical interaction with it. This refers to a device that enables the exchange of electrical signals between A and B.

[0396] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (or Without an intermediary, X is electrically connected, and the drain of the transistor (or the second terminal, etc.) is connected. If Y is electrically connected via (or without) Z2, or if the transistor's saw A part of Z1 (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are indirectly connected, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When they are connected and another part of Z2 is directly connected to Y, the following table It can be expressed.

[0397] For example, "X and Y and the source (or first terminal, etc.) and drain (or the first terminal) of the transistor" Terminals 2, etc., are electrically connected to each other, and X is the source of the transistor (or The electrical components are connected in the following order: the first terminal (or the second terminal), the transistor's drain (or the second terminal), and Y. It can be expressed as "connected to the source of the transistor (or The first terminal (or the second terminal) is electrically connected to X, and the drain of the transistor (or the second terminal) (etc.) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, and the trap Transistor source (or first terminal, etc.), transistor drain (or second terminal, etc.) It can be expressed as, "Y is provided in this connection order." By specifying the order of connections in a circuit configuration using various methods of expression, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the inverter are separated. Separately, the technical scope can be determined.

[0398] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." ) is electrically connected to X via at least a first connection path, and the first connection path It does not have a second connection path, and the second connection path is via a transistor. The source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal) The path between (etc.), and the first connection path is a path via Z1, and the transit The drain of the sta (or a second terminal, etc.) is connected to Y and the electric field via at least a third connection path. They are electrically connected, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "trans The source of the ZISTA (or the first terminal, etc.) is connected to Z1 by at least the first connection path. The first connection path is electrically connected to X via the first connection path, and the first connection path does not have a second connection path. The second connection path has a connection path via a transistor, and the transistor's Dray The terminal (or second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path is electrically connected and does not have the second connection path. It can be expressed. Or, "the source (or first terminal, etc.) of the transistor is small." However, through the first electrical path, X is electrically connected via Z1, and the first electrical The pneumatic path does not have a second electrical path, and the second electrical path is a transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The electrical path is such that the drain (or second terminal, etc.) of the transistor is at least the The third electrical path is electrically connected to Y via Z2, and the third electrical path It does not have a fourth electrical path, and the said fourth electrical path is a transistor drain. Electrical current from the source (or second terminal, etc.) of the transistor (or first terminal, etc.) It can be expressed as "It is a path." Using similar expressions to these examples, the circuit structure By defining the connection path in the configuration, the source (or first terminal) of the transistor is defined. The technical scope is determined by distinguishing between the drain (or second terminal, etc.) and the child (or second terminal, etc.). It is possible.

[0399] These methods of expression are merely examples and are not limited to them. X, Y, Z1, and Z2 represent the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film). Let's assume it is a layer, etc. [Explanation of Symbols]

[0400] CLK1 clock signal CLK2 clock signal CLK3 clock signal CLK4 clock signal G1 scan line ID1 current ID2 current M1 Transistor M2 Transistor M3 Transistor M4 Transistor OUT_n output terminal OUT_1 Output terminal P1 Period P2 Period PWC1 pulse width control signal PWC2 pulse width control signal PWC3 pulse width control signal PWC4 pulse width control signal 100 Semiconductor Equipment 100A Semiconductor Equipment 100B Semiconductor Equipment 100C Semiconductor Equipment 101 Transistors 102 transistors 103 Switching Circuit 103A Switching Circuit 103B Switching Circuit 104 Wiring 105 Wiring 106 transistors 107 Wiring 108 transistors 109 transistors 110 transistors 111 transistors 111S Transistor 121 Conductive layer 122 Conductive layer 123 Semiconductor layer 124 Aperture 125 Conductive layer 130 pixel section 131 pixels 132 transistors 133 liquid crystal elements 134 Capacitive elements 135 transistors 136 transistors 137 EL elements 200 circuits 201 Transistors 209 transistors 300 circuits 301 Circuit 600 transistors 601 circuit board Gate 602 603 Insulating layer 604 oxide semiconductor layer 604a channel region 604b n-type region 604c n-type region 605a electrode 605b electrode 606 Insulating layer 607 Insulating layer 608 Back gate 610 transistors 614 Oxide semiconductor layer 614a Oxide semiconductor layer 614b oxide semiconductor layer 620 transistors 624 oxide semiconductor layer 624a Oxide Semiconductor Layer 624b oxide semiconductor layer 624c oxide semiconductor layer 650 transistors 651 Insulating layer 652 Insulating layer 654 Insulating layer 656 Insulating layer 660 transistors 664 Oxide semiconductor layer 664a Oxide semiconductor layer 664b oxide semiconductor layer 664c oxide semiconductor layer 670 transistors 700 Display Module 701 circuit board 702 pixel section 704 Source Driver Circuit 705 circuit board 706 Gate Driver Circuit Section 708 FPC terminal section 710 signal line 711 Wiring section 712 Sealant 716 FPC 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrodes 764 Insulating Film 768 Insulating film 770 Planarizing Insulator 772 Conductive film 774 Conductive film 775 liquid crystal elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic conductive film 790 Capacitive elements 800 Input / Output Devices 801 Display Module 802 pixels 802B subpixel 802G sub-pixels 802R sub-pixel 803c capacity 803g scan line drive circuit 803t transistor 810 Base material 811 Wiring 819 terminal 820U Detection Unit 821 Electrode 822 Electrode 823 Insulating layer 834 Window section 836 Base material 837 Protective base material 837p protective layer 839 Detection Circuit 850 Input device 867p anti-reflection layer 872 Reflecting electrode 880 liquid crystal elements 1400 Mobile Information Terminals 1401 cabinet 1402 Display section 1403 Operation Buttons 1410 Mobile phone 1411 cabinet 1412 Display section 1413 Operation Buttons 1414 Speaker 1415 Mike 1420 Music Player 1421 cabinet 1422 Display section 1423 Operation Buttons 1424 Antenna

Claims

[Claim 1] It has a first transistor, a second transistor, and a circuit. The gate of the first transistor is electrically connected to the first input terminal. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the output terminal, The gate of the second transistor is electrically connected to the second input terminal, Either the source or the drain of the second transistor is electrically connected to the second wiring. The source or drain of the second transistor, the other of which is electrically connected to the output terminal, The circuit has a function to switch between a first state in which the first input terminal and the back gate of the first transistor are electrically connected, and a second state in which the output terminal and the back gate of the first transistor are electrically connected, according to a control signal. The circuit includes a first switch and a second switch, A semiconductor device wherein the control signal is a signal that switches between the first state and the second state by alternately turning the first switch and the second switch on or off.

Images