Semiconductor device and manufacturing method

Abstract

In semiconductor devices, it is preferable to reduce variations in characteristics. [Solution] A semiconductor device is provided comprising: a trench contact portion having a cross-sectional area at a second depth position, which is further from the upper surface than the first depth position, smaller than the cross-sectional area at a first depth position; a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trench portion; a second emitter portion of a first conductivity type provided below the first emitter portion and having a lower doping concentration than the first emitter portion; and a side wall region of a second conductivity type provided between the side wall of the trench contact portion and the second emitter portion.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and methods for manufacturing them. [Background technology]

[0002] Paragraph 0119 of Patent Document 1 states that "In this example, the doping concentration of the P-type diffusion region 16 is higher than the doping concentration of the P-type base region 14. The P-type diffusion region 16 may have a concentration peak with a higher doping concentration than the P-type base region 14. It is preferable to perform oblique ion implantation to form the P-type diffusion region 16." Paragraph 0040 of Patent Document 2 discloses that "a first oblique ion implantation 32 is performed on the side wall 8b of the contact trench 8 at a shallow depth d1." Paragraph 0021 of Patent Document 3 discloses that "the side wall of the body contact trench (second trench) 8 has a slope connecting the vicinity of the upper end of the first trench 4 and the bottom of the body contact trench (second trench) 8, which is located deeper than the upper surface of the gate electrode." Paragraph 0075 of Patent Document 4 discloses that "the contact trench 52 is formed deeper than the p-well region 26. The contact trench 52 is formed such that the first inclination angle (θ1 in Figure 3) of the side surface of the contact trench 52 with respect to the first surface is 60 degrees or more and 85 degrees or less." Paragraph 0048 of Patent Document 5 discloses that "the source region 104 includes a first source portion region 1041 that is directly adjacent to the contact 112 in the source contact area 113 of the first surface 110. The source region 104 further includes a second source portion region 1042 and a third source portion region 1043." Patent Document 1: Japanese Unexamined Patent Publication No. 2023-128635 Patent Document 2: Japanese Unexamined Patent Publication No. 2018-110166 Patent Document 3: Japanese Unexamined Patent Publication No. 2011-134985 Patent Document 4: Japanese Unexamined Patent Publication No. 2018-14455 Patent Document 5: Japanese Unexamined Patent Publication No. 2020-145430 [Overview of the project] [Problems that the invention aims to solve]

[0003] In semiconductor devices, it is preferable to reduce variations in characteristics. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. The semiconductor device may include a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate. Any of the above semiconductor devices may include a mesa portion sandwiched between two of the trench portions in the semiconductor substrate. Any of the above semiconductor devices may include a trench contact portion in the mesa portion provided from the upper surface to the interior of the semiconductor substrate, wherein the cross-sectional area at a second depth position, which is further from the upper surface than the first depth position, is smaller than the cross-sectional area at a first depth position. Any of the above semiconductor devices may include a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trench portion in the mesa portion. Any of the above semiconductor devices may include a second emitter portion of a first conductivity type, provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, and having a lower doping concentration than the first emitter portion. Any of the above semiconductor devices may include a second conductivity type sidewall region provided between the sidewall of the trench contact portion and the second emitter portion. In any of the above semiconductor devices, the second emitter portion may have one of the following: a flat portion where the doping concentration distribution in the depth direction is flat, a valley portion where the doping concentration shows a minimum value in the depth direction, or a peak where the doping concentration shows a maximum value in the depth direction and is lower in concentration than the first emitter portion.

[0005] In any of the semiconductor devices described above, the side wall of the trench contact portion may have an oblique portion extending in a direction intersecting the depth direction between the first depth position and the second depth position. In any of the semiconductor devices described above, the side wall region may be in contact with the oblique portion.

[0006] In any of the above semiconductor devices, the angle between the oblique portion and the depth direction may be 5 degrees or more.

[0007] In any of the above semiconductor devices, the plurality of trenches may be arranged in a line in the first direction. In any of the above semiconductor devices, the angle between the region of the trench contact portion facing the first emitter portion in the first direction and the depth direction may be smaller than the angle between the oblique portion and the depth direction.

[0008] In any of the semiconductor devices described above, the region of the side wall of the trench contact portion that faces the first emitter portion in the first direction may include a portion parallel to the depth direction.

[0009] In any of the semiconductor devices described above, the side wall of the trench contact portion may include a stepped portion in which the inclination of the side wall changes discontinuously between the first depth position and the second depth position.

[0010] In any of the above semiconductor devices, the plurality of trenches may be arranged in a line in the first direction. In any of the above semiconductor devices, the stepped portion may be positioned facing the first emitter portion or the second emitter portion in the first direction.

[0011] In any of the semiconductor devices described above, the stepped portion may be positioned facing the second emitter portion in the first direction.

[0012] In any of the semiconductor devices described above, the step portion may be disposed facing the boundary between the first emitter portion and the second emitter portion in the first direction.

[0013] In any of the semiconductor devices described above, the plurality of trench portions may be provided side by side in the first direction. In any of the semiconductor devices described above, the first emitter portion may have a region that does not face the sidewall region in the first direction.

[0014] In any of the semiconductor devices described above, the first emitter portion may be in contact with the sidewall of the trench contact portion.

[0015] In any of the semiconductor devices described above, the sidewall region may be in contact with the sidewall of the trench contact portion.

[0016] In any of the semiconductor devices described above, the sidewall region may be separated from the sidewall of the trench contact portion.

[0017] In any of the semiconductor devices described above, the concentration of the p-type dopant in the sidewall region may be higher than the concentration of the n-type dopant in the second emitter portion.

[0018] In any of the semiconductor devices described above, the concentration of the p-type dopant in the sidewall region may be lower than the concentration of the n-type dopant in the first emitter portion.

[0019] Any of the semiconductor devices described above may be provided below the second emitter portion between the sidewall of the trench contact portion and the trench portion, and may include a third emitter portion of the first conductivity type having a doping concentration higher than that of the second emitter portion.

[0020] In any of the semiconductor devices described above, the sidewall region may also be provided between the sidewall of the trench contact portion and the third emitter portion.

[0021] In any of the semiconductor devices described above, the concentration of the p-type dopant in the sidewall region may be higher than the concentration of the n-type dopant in the third emitter portion.

[0022] In any of the semiconductor devices described above, the semiconductor substrate may be a wide bandgap substrate formed of a material having a larger bandgap than silicon.

[0023] In a second aspect of the present invention, there is provided a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type. The semiconductor device may include a plurality of trench portions provided from the upper surface of the semiconductor substrate to the inside. Any of the semiconductor devices may include a mesa portion sandwiched between two of the trench portions in the semiconductor substrate. Any of the semiconductor devices may include a trench contact portion provided from the upper surface of the semiconductor substrate to the inside in the mesa portion. Any of the semiconductor devices may include a first emitter portion of a first conductivity type provided between the sidewall of the trench contact portion and the trench portion in the mesa portion. Any of the semiconductor devices may include a second emitter portion of a first conductivity type provided below the first emitter portion between the sidewall of the trench contact portion and the trench portion, and having a lower doping concentration than the first emitter portion. Any of the semiconductor devices may include a sidewall region of a second conductivity type provided away from the sidewall between the sidewall of the trench contact portion and the trench portion. In any of the semiconductor devices, the second emitter portion may have any one of a flat portion having a flat doping concentration distribution in the depth direction, a valley portion having a minimum value of the doping concentration in the depth direction, or a peak having a maximum value of the doping concentration in the depth direction and a lower concentration than the first emitter portion.

[0024] In any of the semiconductor devices described above, the sidewall region may be provided between the trench contact portion and the second emitter portion.

[0025] Any of the above semiconductor devices may include a third emitter portion of a first conductivity type having a higher doping concentration than the second emitter portion, located below the second emitter portion between the side wall of the trench contact portion and the trench portion. In any of the above semiconductor devices, the side wall region may also be provided between the side wall of the trench contact portion and the third emitter portion.

[0026] In any of the semiconductor devices described above, the first emitter portion may be in contact with the side wall of the trench contact portion.

[0027] A third aspect of the present invention provides a method for manufacturing a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. The semiconductor device may include a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate, a mesa portion sandwiched between two of the trench portions in the semiconductor substrate, a trench contact portion provided in the mesa portion from the upper surface to the interior of the semiconductor substrate, a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trench portion in the mesa portion, a second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion and provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, and a side wall region of a second conductivity type provided between the side wall of the trench contact portion and the second emitter portion. In the above manufacturing method, contact trenches for forming the trench contact portion may be formed in the mesa portion. In any of the above manufacturing methods, the dopant may be injected through the contact trench to form the side wall region, such that the angle between the side wall of the contact trench and the injection direction of the second conductive dopant is not parallel.

[0028] In any of the above manufacturing methods, at least a portion of the side wall of the contact trench may be formed at an angle with respect to the depth direction.

[0029] In any of the above manufacturing methods, the angle between the portion of the side wall of the contact trench and the depth direction may be 5 degrees or more.

[0030] In any of the above manufacturing methods, the injection direction of the dopant may be oblique to the depth direction.

[0031] In any of the above manufacturing methods, the angle between the injection direction of the dopant and the depth direction may be 5 degrees or more.

[0032] In any of the above manufacturing methods, the side wall region may be formed in contact with the side wall of the contact trench.

[0033] In any of the above manufacturing methods, the side wall region may be formed separately from the side wall of the contact trench.

[0034] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0035] [Figure 1] This is a top view showing an example of a semiconductor device 100. [Figure 2] This is an example of an enlarged view of region D in Figure 1. [Figure 3] This figure shows an example of a cross-section along line aa in Figure 2. [Figure 4] This is an enlarged view of the cross-section near the mesa portion 60. [Figure 5] Figure 4 shows an example of the doping concentration distribution along the hh line. [Figure 6] This figure shows another example of doping concentration distribution along the HH line. [Figure 7] This figure shows another example of doping concentration distribution along the HH line. [Figure 8]This figure shows another example of the structure of the mesa section 60. [Figure 9] This diagram shows some of the steps in the manufacturing process of semiconductor device 100. [Figure 10] This figure shows an example of a method for forming a contact trench 220. [Figure 11] This figure shows another example of the structure of the mesa section 60. [Figure 12] This figure shows another example of the structure of the mesa section 60. [Figure 13] This figure shows another example of the structure of the mesa section 60. [Figure 14] This figure shows another example of steps S410 to S430 for forming the trench contact portion 210, the side wall region 86, and the bottom region 87. [Figure 15] This figure shows another example of the structure of the mesa section 60. [Figure 16] This figure shows an example of the collector voltage-collector current characteristics of semiconductor device 100. [Modes for carrying out the invention]

[0036] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0037] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0038] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0039] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0040] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0041] In this specification, when we refer to items as "identical" or "equal," we may include items that have errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0042] In this specification, the conductivity type of a doped region containing impurities is described as either p-type or n-type. In this specification, impurities may specifically refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an n-type conductivity or a p-type conductivity.

[0043] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0044] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron donors. In this specification, VOH defects may be referred to as hydrogen donors.

[0045] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type. In this specification, conductivity types represented by lowercase p or n, such as p type or n type, do not indicate the relative magnitude of the doping concentration. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0046] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the n-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the p-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the n-type region may be referred to as the donor concentration, and the doping concentration in the p-type region may be referred to as the acceptor concentration.

[0047] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0048] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0049] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. The concentrations used herein may be values ​​at room temperature. For example, values ​​at 300 K (Kelvin) (approximately 26.9°C) may be used.

[0050] Figure 1 is a top view showing an example of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0051] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. The semiconductor substrate 10 may be a wide-bandgap substrate formed of a material with a larger bandgap than silicon. For example, the semiconductor substrate 10 may be a SiC substrate or a compound semiconductor substrate such as a GaN substrate.

[0052] The semiconductor substrate 10 has a first edge 161 and a second edge 162 when viewed from above. In this specification, "top view" simply means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of first edges 161 facing each other when viewed from above. The semiconductor substrate 10 in this example also has two pairs of second edges 162 facing each other when viewed from above. In Figure 1, the first edge 161 is parallel to the X-axis direction. The second edge 162 is parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The first edge 161 is perpendicular to the extension direction or longitudinal direction of the gate trench portion, which will be described later. The second edge 162 is parallel to the extension direction or longitudinal direction of the gate trench portion, which will be described later.

[0053] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active section 160, but it is omitted in Figure 1.

[0054] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. In other examples, the transistor section 70 and the diode section including a diode element such as an FWD (Free Wheel Diode) may be arranged alternately along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. In this example, one transistor section 70 is provided, but multiple transistor sections 70 may be provided. P+ type well regions or gate runners may be provided between the transistor sections 70.

[0055] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a surface MOS structure periodically arranged on the upper surface side of the semiconductor substrate 10, which has an N+ type emitter region, a P- type base region, an N- type drift region, a gate conductor, and a gate insulating film.

[0056] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed in the vicinity of the first side 161. The vicinity of the first side 161 refers to the region between the first side 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0057] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is hatched with oblique lines.

[0058] The gate wiring 130 is disposed between the active portion 160 and the first side 161 or the second side 162 in a top view. The gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the gate wiring 130 in a top view may be regarded as the active portion 160. Also, the gate wiring 130 is connected to the gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like. The gate wiring 130 may be provided separately from the emitter electrode.

[0059] The p-type outer peripheral well region 11 is provided overlapping with the gate wiring 130. That is, like the gate wiring 130, the p-type outer peripheral well region 11 surrounds the active portion 160 in a top view. The p-type outer peripheral well region 11 extends with a predetermined width also in a range where it does not overlap with the gate wiring 130. The p-type outer peripheral well region 11 is a region of the second conductivity type. The p-type outer peripheral well region 11 in this example is P+ type. The doping concentration of the p-type outer peripheral well region 11 is 5.0×10 17 atoms / cm 3 or more and 5.0×10 19atoms / cm 3 The following is acceptable: The doping concentration in the p-type outer well region 11 is 2.0 × 10⁻⁶. 18 atoms / cm 3 The above and 2.0 × 10 19 atoms / cm 3 The following is acceptable:

[0060] The semiconductor device 100 may include a temperature sensing unit (not shown), which is a pn junction diode made of polysilicon or the like, and a current detection unit (not shown) that simulates the operation of the transistor unit 70 provided in the active unit 160. The temperature sensing unit may be connected to the anode pad and cathode pad via wiring. If a temperature sensing unit is provided, it is preferable that it be located in the center of the semiconductor substrate 10 in the X-axis and Y-axis directions.

[0061] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the first edge 161 or the second edge 162 when viewed from above. The edge termination structure 90 in this example is located between the outer peripheral gate wiring 130 and the first edge 161 or the second edge 162. The edge termination structure 90 mitigates electric field concentration on the upper side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0062] Figure 2 is an example of an enlarged view of region D in Figure 1. Region D is the region that includes the transistor portion 70 of the active portion 160 shown in Figure 1. Figure 2 shows the structure of the upper surface of the semiconductor substrate 10 in region D. In region D, the semiconductor device 100 comprises a plurality of gate trench portions 40 and a plurality of mesa portions 60.

[0063] Multiple gate trenches 40 are arranged in a line in a first direction on the upper surface of the semiconductor substrate 10. In this example, the first direction is the X-axis direction. Each gate trench 40 is arranged at a predetermined interval in the X-axis direction. Each gate trench 40 extends in a second direction intersecting the first direction on the upper surface of the semiconductor substrate 10. In other words, the gate trench 40 has an elongated length in the second direction on the upper surface of the semiconductor substrate 10. In this example, the second direction is the Y-axis direction. Each gate trench 40 extends from the upper surface to the interior of the semiconductor substrate 10.

[0064] The gate trench section 40 is a trench section to which the gate potential is applied. Inside the gate trench section 40, a gate conductive section made of a conductive material such as polysilicon is arranged. The gate conductive section is electrically connected to the gate wiring 130 (see Figure 1), and a predetermined gate voltage is applied. Some of the gate trench sections 40 shown in Figure 2 may be replaced with dummy trench sections. The dummy trench section is a trench section to which the emitter electrode potential is applied. The dummy trench section has the same structure as the gate trench section. A trench section adjacent to a gate trench section 40 in the X-axis direction may be a dummy trench section. One or more dummy trench sections may be arranged between two gate trench sections 40. However, the gate trench sections 40 may be arranged adjacent to each other in the X-axis direction.

[0065] In the X-axis direction, the region of the semiconductor substrate 10 sandwiched between the two trenches is defined as the mesa portion 60. Both ends of the mesa portion 60 in the X-axis direction are the boundaries with the respective trenches. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of at least one of the trenches on both sides.

[0066] At least one mesa portion 60 is provided with an emitter region 12 and a trench contact portion 210. The emitter region 12 and trench contact portion 210 may be provided in at least one mesa portion 60 that is in contact with the gate trench portion 40, the emitter region 12 and trench contact portion 210 may be provided in all mesa portions 60 that are in contact with the gate trench portion 40, or all mesa portions 60 may be provided with an emitter region 12 and trench contact portion 210.

[0067] The emitter region 12 is an N+ type region exposed on the upper surface of the semiconductor substrate 10. In this example, the emitter region 12 is in contact with the gate trench portion 40. Each emitter region 12 may have a strip shape extending in the Y-axis direction. The emitter regions 12 may be provided for each gate trench portion 40 that sandwiches the mesa portion 60. In the portion in contact with the gate trench portion 40, one emitter region 12 extending in the Y-axis direction may be provided for one mesa portion 60. In other examples, multiple emitter regions 12 discretely arranged in the Y-axis direction may be provided in the portion in contact with the gate trench portion 40. In this case, a P+ type contact region may be provided between two emitter regions 12 in the Y-axis direction. That is, the emitter regions 12 and contact regions may be arranged alternately in the Y-axis direction.

[0068] The trench contact portion 210 is provided in the mesa portion 60 from the upper surface to the interior of the semiconductor substrate 10. The trench contact portion 210 may be provided extending in the Y-axis direction on the upper surface of the semiconductor substrate 10. In other words, the trench contact portion 210 may have a longitudinal length in the Y-axis direction on the upper surface of the semiconductor substrate 10. The trench contact portion 210 has a structure in which a conductive material is filled into a trench provided in the mesa portion 60. An emitter potential is applied to the conductive material. The trench contact portion 210 is not in contact with the trench portion. In this example, an emitter region 12 is provided between the trench contact portion 210 and the trench portion. The above-described contact region may be provided in a part of the area between the trench contact portion 210 and the trench portion.

[0069] Figure 3 shows an example of a cross-section along line aa in Figure 2. Cross-section aa is the XZ cross-section passing through the emitter region 12 and the trench contact portion 210. In this example, the semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0070] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor substrate 10 with the largest surface area. An n-type drift region 18 is provided inside the semiconductor substrate 10.

[0071] The emitter electrode 52 is located above the upper surface 21 of the semiconductor substrate 10. A portion of the upper surface 21 of the semiconductor substrate 10 is covered by an interlayer insulating film 38. The emitter electrode 52 is in contact with at least a portion of the upper surface 21 of the semiconductor substrate 10 that is not covered by the interlayer insulating film 38. In this example, the emitter electrode 52 is in contact with the emitter region 12 and the trench contact portion 210.

[0072] The emitter electrode 52 is formed from a material containing metal. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium or titanium nitride below the region made of aluminum or the like. The barrier metal may be in contact with the semiconductor substrate 10.

[0073] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 may cover each trench portion. Alternatively, the interlayer insulating film 38 may be provided inside the trench portion.

[0074] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a metallic material such as aluminum, similar to the emitter electrode 52. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0075] Multiple mesa portions 60 are provided on the upper surface 21 of the semiconductor substrate 10. Each mesa portion 60 is provided with an emitter region 12, a trench contact region 210, a side wall region 86, a bottom region 87, and a base region 14. The configuration of each mesa portion 60 will be described later.

[0076] Multiple gate trenches 40 are provided on the upper surface 21 of the semiconductor substrate 10. Each gate trench 40 extends from the upper surface 21 of the semiconductor substrate 10 into the interior. In this example, the gate trenches 40 penetrate from the upper surface 21 through the base region 14 and reach the drift region 18. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region first and then the trenches. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0077] The gate trench portion 40 has a groove-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon, which is a conductive material. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, inside the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0078] The gate conductive portion 44 within the gate trench portion 40 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130 at a position other than the cross-section shown in Figure 3.

[0079] A lower end region 230 may or may not be provided in contact with the lower end of each gate trench section 40. The lower end region 230 is a p-shaped region. The lower end region 230 may be provided so as to cover the lowest surface of the gate trench section 40. The lower end region 230 is located away from the base region 14. By providing the lower end region 230, electric field concentration at the lower end of the gate trench section 40 can be mitigated. The lower end region 230 may be provided across multiple gate trench sections 40.

[0080] In this example, the semiconductor substrate 10 has an N-type drift region 18. The emitter region 12 has a higher doping concentration than the drift region 18. The drift region 18 is located below the base region 14. The drift region 18 may be in contact with the base region 14. In other examples, an N+-type storage region 232 with a higher doping concentration than the drift region 18 may or may not be provided between the drift region 18 and the base region 14. By providing the storage region 232, an injection enhancement effect can be generated, which can lower the on-voltage of the semiconductor device 100.

[0081] A P+ type collector region 22 is provided between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The doping concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or it may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The elements that act as acceptors are not limited to the examples described above. The collector region 22 is exposed to the lower surface 23 of the semiconductor substrate 10 and is connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. As described above, if a diode region is provided in the active region 160, an N+ type cathode region may be provided in the diode region instead of the collector region 22.

[0082] An N+ type buffer region 20 may be provided between the drift region 18 and the collector region 22. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may have one or more concentration peaks with higher doping concentrations than the drift region 18. The doping concentration of a concentration peak refers to the doping concentration at the peak of the concentration peak. In addition, the doping concentration in the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0083] The buffer region 20 may be formed by ion implantation of an n-type dopant such as hydrogen (proton) or phosphorus. In this example, the buffer region 20 is formed by ion implantation of hydrogen. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22.

[0084] Figure 4 is an enlarged view of a cross-section near the mesa portion 60. As described above, the mesa portion 60 is provided with an emitter region 12, a trench contact region 210, a side wall region 86, a bottom region 87, and a base region 14. Below the base region 14 in the mesa portion 60, an N-type drift region 18 may be provided, and an n-type accumulation region 232 with a higher concentration than the drift region 18 may also be provided.

[0085] The trench contact portion 210 is provided in the mesa portion 60 from the upper surface 21 of the semiconductor substrate 10 to the interior. In this example, the trench contact portion 210 is a plug formed of a conductive material such as tungsten. The trench contact portion 210 may be formed of a different material from the emitter electrode 52. The depth position of the boundary between the trench contact portion 210 and the emitter electrode 52 (i.e., the position in the Z-axis direction) may or may not coincide with the upper surface 21 of the semiconductor substrate 10.

[0086] The trench contact portion 210 has a bottom portion 212 and a side wall 214. The bottom portion 212 is the lowest part of the trench contact portion 210. The bottom portion 212 may be a plane parallel to the XY plane. The bottom portion 212 may be a portion of the trench contact portion 210 that is within a predetermined distance in the depth direction from the lowest part. This predetermined distance may be 0.1 μm, 0.2 μm, or 0.5 μm. The side wall 214 is the portion of the boundary of the trench contact portion 210 in the XZ cross section that extends from the bottom portion 212 to the upper surface 21 of the semiconductor substrate 10.

[0087] The emitter region 12 in this example has a first emitter portion 81 and a second emitter portion 82. The emitter region 12 may further have a third emitter portion 83. The first emitter portion 81 is an n-type region provided in the mesa portion 60 between the side wall 214 of the trench contact portion 210 and the trench portion. The first emitter portion 81 in this example is an N+-type region with a higher concentration than the drift region 18. The first emitter portion 81 is connected to at least one of the emitter electrode 52 and the trench contact portion 210. In the example of Figure 4, the first emitter portion 81 is connected to both the emitter electrode 52 and the trench contact portion 210. The first emitter portion 81 may be in contact with the side surface of the gate trench portion 40.

[0088] The second emitter portion 82 is located below the first emitter portion 81 between the side wall 214 of the trench contact portion 210 and the trench portion. In this example, the second emitter portion 82 is an N-type region with a lower doping concentration than the first emitter portion 81. The second emitter portion 82 is located in contact with the first emitter portion 81. The second emitter portion 82 may be in contact with the side surface of the gate trench portion 40. In this example, the second emitter portion 82 is not in contact with the emitter electrode 52.

[0089] The sidewall region 86 is a p-type region provided between the sidewall 214 of the trench contact portion 210 and the second emitter portion 82. In this example, the sidewall region 86 is in contact with the sidewall 214 of the trench contact portion 210. The sidewall region 86 may be a P+-type region with a higher concentration than the base region 14. The doping concentration of the sidewall region 86 may be 10 times or more, 50 times or more, or 100 times or more, than the doping concentration of the base region 14.

[0090] In this example, the side wall region 86 is provided to cover the entire side surface of the second emitter portion 82 that faces the side wall 214 in the X-axis direction. In other words, the second emitter portion 82 is not in contact with the trench contact portion 210.

[0091] The first emitter portion 81 has a region that does not face the sidewall region 86 in the X-axis direction. In other words, the sidewall region 86 is not provided on at least a portion of the side surface of the first emitter portion 81 that faces the sidewall 214 in the X-axis direction. The sidewall region 86 does not have to be provided in the entire region between the sidewall 214 and the first emitter portion 81. In this example, the first emitter portion 81 is in contact with the sidewall 214 of the trench contact portion 210. The entire side surface of the first emitter portion 81 may be in contact with the sidewall 214.

[0092] By providing the side wall region 86, the entire current flowing between the second emitter portion 82 and the emitter electrode 52 passes through the first emitter portion 81. Also, the entire current flowing between the first emitter portion 81 and the base region 14 passes through the second emitter portion 82.

[0093] In this example, the doping concentration of the second emitter portion 82 is lower than that of the first emitter portion 81. This results in a higher resistance value for the second emitter portion 82. Also, the current flowing between the first emitter portion 81 and the base region 14 passes through the second emitter portion 82. Therefore, by providing the second emitter portion 82, the resistance of the emitter region 12 can be increased.

[0094] By increasing the resistance of the emitter region 12, a relatively low saturation current and a relatively low on-voltage can be achieved simultaneously. The MOS structure provided on the upper surface 21 of the semiconductor substrate 10 has a saturation characteristic in which the collector current saturates even when the collector-emitter voltage is increased. As a result, the semiconductor device 100 has a short-circuit withstand characteristic in which the element will not be destroyed within a certain period of time in a short-circuit state where a large current and a large voltage are applied simultaneously. As the miniaturization of the device progresses, if a MOS structure is formed on all mesa portions 60, the saturation current becomes very large. Therefore, a decimation structure in which a MOS structure is not formed on some mesa portions 60, or a ladder structure in which emitter regions 12 having a longitudinal length in the X-axis direction are discretely arranged in the Y-axis direction may be used to suppress the saturation current. However, if the saturation current is suppressed with such a structure, the on-voltage becomes high.

[0095] The current saturation characteristic of the MOS structure is expressed by the following equation (1).

number

[0096] The channel resistance Rch of a MOS structure is given by equation (2) below.

number

[0097] In contrast, the semiconductor device 100 suppresses saturation current by providing a second emitter portion 82. When the semiconductor device 100 is turned on, current flows between the emitter electrode 52 and the emitter region 12 through the second emitter portion 82. Therefore, the potential of the emitter region 12 changes according to the magnitude of the current flowing through the second emitter portion 82. Since current flows from the emitter region 12 to the emitter electrode 52, if the current flowing through the second emitter portion 82 is large, the potential of the emitter region 12 becomes higher. If the current flowing through the second emitter portion 82 is small, the potential of the emitter region 12 rises only slightly.

[0098] Since the on-voltage applied to the gate conductive portion 44 is approximately constant, when the current flowing through the second emitter portion 82 increases, the potential difference between the gate conductive portion 44 and the emitter region 12 decreases, and the voltage applied to the gate insulating film 42 decreases. On the other hand, when the current flowing through the second emitter portion 82 is small, the voltage applied to the gate insulating film 42 becomes relatively large. Therefore, the saturation current flowing through the MOS structure can be suppressed.

[0099] In the semiconductor device 100, by providing an emitter region 12 having a longitudinal length in the Y-axis direction, the total emitter width Z can be increased, thereby reducing the on-voltage. This makes it possible to achieve both a low saturation current and a low on-voltage.

[0100] In this example, the trench contact portion 210 has a smaller cross-sectional area at the second depth position Z2, which is further from the top surface 21 than the first depth position Z1, than the cross-sectional area at the first depth position Z1. The width of the trench contact portion 210 in the X-axis direction may also be treated as the cross-sectional area. The side wall 214 of the trench contact portion 210 may include an oblique portion extending in a direction intersecting the depth direction between the first depth position Z1 and the second depth position Z2. This makes the cross-sectional area at the first depth position Z1 larger than the cross-sectional area at the second depth position Z2. Part of the side wall 214 between the first depth position Z1 and the second depth position Z2 may be an oblique portion, or the entire side wall 214 may be an oblique portion. In the example of Figure 4, the entire side wall 214 is an oblique portion. In other words, the trench contact portion 210 in Figure 4 has a tapered shape in which the cross-sectional area increases as it approaches the top surface 21.

[0101] The second depth position Z2 may be below the upper end of the second emitter portion 82. The second depth position may also be at the lower end of the second emitter portion 82. The first depth position Z1 may be located within the range from the upper end of the second emitter portion 82 to the upper end of the first emitter portion 81. The first depth position Z1 may also be at the upper end of the second emitter portion 82.

[0102] In the trench contact section 210, by making the cross-sectional area at the first depth position Z1 larger than the cross-sectional area at the second depth position Z2, variations in the doping concentration of the sidewall region 86 between the first depth position Z1 and the second depth position Z2 can be suppressed. For example, the sidewall region 86 can be formed by injecting p-type dopant ions into the trench from above after forming the trench for forming the trench contact section 210. If the sidewall 214 consists only of vertical portions, a small deviation in the dopant ion injection direction will cause fluctuations in the amount of dopant ions injected per unit area of ​​the sidewall 214, resulting in variations in the doping concentration of the sidewall region 86. In contrast, by having slanted or stepped portions in the sidewall 214, variations in the amount of dopant ions injected into those portions can be suppressed. Therefore, the doping concentration of the sidewall region 86 can be controlled with high precision. This makes it possible to suppress variations in characteristics such as collector voltage-collector current when the mesa section 60 is ON.

[0103] Let θ1 be the angle between the slanted portion of the side wall 214 and the depth direction. The angle θ1 may be 5 degrees or more. The angle θ1 may be 10 degrees or more, 15 degrees or more, or 20 degrees or more. Increasing the angle θ1 can suppress variations in the amount of dopant ions implanted into the side wall 214. On the other hand, increasing the angle θ1 increases the width of the trench contact portion 210 on the upper surface 21 of the semiconductor substrate 10, making it difficult to miniaturize the mesa portion 60. The angle θ1 may be 45 degrees or less, 40 degrees or less, 35 degrees or less, or 30 degrees or less. The angle of the slanted portion of the side wall 214 may be the angle of the straight line drawn connecting the side wall 214 at the upper end of the second emitter portion 82 and the side wall 214 at the lower end of the second emitter portion 82.

[0104] The lower end of the trench contact portion 210 may be in contact with the p-type bottom region 87. The bottom region 87, like the side wall region 86, can be formed by injecting p-type dopant ions into the trench from above after forming the trench for forming the trench contact portion 210. The bottom region 87 may be a P+-type region with a higher concentration than the base region 14. The doping concentration of the bottom region 87 may be twice or more the doping concentration of the base region 14, five times or more, ten times or more, fifty times or more, or even one hundred times or more.

[0105] The trench contact portion 210 is provided from the upper surface 21 of the semiconductor substrate 10 to a depth greater than the lower end of the second emitter portion 82. The bottom region 87 is in contact with the base region 14. By providing a high-density bottom region 87, the contact resistance between the trench contact portion 210 and the base region 14 can be reduced.

[0106] The sidewall region 86 may be a region with a higher concentration than the base region 14. The doping concentration in the sidewall region 86 may be at least twice, five times, ten times, fifty times, or even one hundred times the doping concentration in the base region 14. The bottom region 87 may be a region with a higher concentration than the sidewall region 86. The doping concentration in the bottom region 87 may be at least twice, five times, or even ten times the doping concentration in the sidewall region 86.

[0107] The third emitter portion 83 is located below the second emitter portion 82, between the side wall 214 of the trench contact portion 210 and the trench portion. The third emitter portion 83 is an N-type region with a higher doping concentration than the second emitter portion 82. The third emitter portion 83 is located in contact with the second emitter portion 82. The doping concentration of the third emitter portion 83 may be lower than that of the first emitter portion 81. The third emitter portion 83 may be in contact with the side surface of the trench portion. In this example, the third emitter portion 83 is not in contact with the emitter electrode 52.

[0108] By providing the third emitter portion 83, it is possible to prevent the second emitter portion 82 from directly contacting the base region 14. Therefore, diffusion of the dopant in the base region 14 into the low-concentration second emitter portion 82 can be suppressed, and the length of the second emitter portion 82 in the depth direction can be precisely controlled. As a result, variations in the resistance value in the second emitter portion 82 can be suppressed.

[0109] In this example, the side wall region 86 is also provided between the side wall 214 of the trench contact portion 210 and the third emitter portion 83. As a result, the third emitter portion 83 is not in contact with the trench contact portion 210.

[0110] The upper end 84 of the gate conductive portion 44 of the gate trench portion 40 is preferably positioned facing the third emitter portion 83 in the X-axis direction. The upper end 84 of the gate conductive portion 44 may refer to the upper end of the side wall of the gate conductive portion 44. Facing the upper end 84 means that the upper end 84 is positioned between the upper end position and the lower end position of the third emitter portion 83 in the Z-axis direction. The upper and lower ends of the third emitter portion 83 may refer to the upper and lower ends of the portion in contact with the side wall of the gate trench portion 40.

[0111] When an ON voltage is applied to the gate conductive portion 44, electrons are attracted to the region of the boundary between the mesa portion 60 and the trench portion that faces the gate conductive portion 44. When the second emitter portion 82 and the gate conductive portion 44 are arranged facing each other, electrons are also attracted to the boundary portion of the second emitter portion 82. Since the doping concentration of the second emitter portion 82 is low, the resistance value at the boundary portion may fluctuate due to the attracted electrons. In contrast, by arranging the third emitter portion 83 to face the upper end 84 of the gate conductive portion 44, fluctuations in the resistance value at the boundary portion of the second emitter portion 82 can be suppressed. Furthermore, since the doping concentration of the third emitter portion 83 is high, even if electrons are attracted to the boundary portion of the third emitter portion 83, the fluctuation in the resistance value at that boundary portion is very small.

[0112] Each mesa portion 60 is provided with a P-type base region 14. The base region 14 is in contact with the gate trench portion 40. The base region 14 may also be in contact with each of the trench portions on both sides of the mesa portion 60. At least a portion of the base region 14 is provided below the emitter region 12. The base region 14 may also be in contact with the emitter region 12. When a predetermined ON voltage is applied to the gate trench portion 40, the surface layer of the base region 14 in contact with the gate trench portion 40 inverts into an n-type region, forming a channel. This channel electrically connects the emitter region 12 to the drift region 18, which will be described later.

[0113] The base region 14 is also provided below the trench contact portion 210. The base region 14 may be in contact with the trench contact portion 210, or it may be in contact with the bottom region 87. The doping concentration of the base region 14 is 5.0 × 10⁻¹⁴. 16 atoms / cm 3 The above is 1.0 × 10 18 atoms / cm 3 The following is acceptable:

[0114] Figure 5 shows an example of the doping concentration distribution along the hh line in Figure 4. The hh line is a line parallel to the Z-axis that passes through the first emitter portion 81, the second emitter portion 82, and the third emitter portion 83.

[0115] In this example, the first emitter portion 81 has a peak 91 in the doping concentration distribution in the depth direction. A peak in the doping concentration distribution is a mountain-shaped portion that shows a maximum value at its apex. The doping concentration at the apex of the peak is defined as the doping concentration of that peak. The doping concentration of peak 91 is defined as P1. In addition, the doping concentration of the first emitter portion 81 may continue to increase from the boundary with the second emitter portion 82 to the upper surface 21 of the semiconductor substrate 10. In this case, the doping concentration of the first emitter portion 81 at the upper surface 21 is defined as P1.

[0116] In this example, the second emitter portion 82 has a peak 92 in the doping concentration distribution in the depth direction. Let P2 be the doping concentration at peak 92. Between the first emitter portion 81 and the second emitter portion 82, a valley 94 where the doping concentration shows a minimum value is defined as the boundary between the first emitter portion 81 and the second emitter portion 82.

[0117] In this example, the third emitter portion 83 has a peak 93 in the doping concentration distribution in the depth direction. The doping concentration at peak 93 is denoted as P3. Between the second emitter portion 82 and the third emitter portion 83, a valley 95 where the doping concentration shows a minimum value is defined as the boundary between the second emitter portion 82 and the third emitter portion 83.

[0118] As described above, the concentration P2 of the peak 92 of the second emitter portion 82 is lower than the concentration P1 of the peak 91 of the first emitter portion 81. The concentration P2 may be 1 / 100th or less of the concentration P1, or 1 / 1000th or less. The concentration P2 may be 10 times or less of the doping concentration of the valley portion 94, or 5 times or less. The concentration P2 is higher than the doping concentration of the drift region 18. The concentration P2 may be 100 times or less of the doping concentration of the drift region 18, or 10 times or less, or 5 times or less. By adjusting the concentration P2, the resistance value in the resistive portion can be adjusted.

[0119] The length of the second emitter portion 82 in the depth direction may be 2 μm or less. This length may be 1.5 μm or less, or 1 μm or less. This length may be 0.1 μm or more, or 0.5 μm or more. The overall length of the emitter region 12 in the depth direction may be 3 μm or less.

[0120] In this example, the emitter region 12 can be formed by implanting n-type dopant ions at the positions of peaks 91, 92, and 93, respectively. The length of the second emitter portion 82 can be adjusted by the depth at which peaks 91 and 93 are formed. By adjusting the length of the second emitter portion 82, the resistance value in the resistive section can be adjusted.

[0121] As described above, the concentration P3 of peak 93 in the third emitter portion 83 is higher than the concentration P2 of peak 92 in the second emitter portion 82. The concentration P3 may be 10 times or more, 50 times or more, or 100 times or more than the concentration P2. The concentration P3 of peak 93 in the third emitter portion 83 may be less than or equal to the concentration P1 of peak 91 in the first emitter portion 81. The concentration P3 may be 1 / 2 times or less, 1 / 5 times or less, or 1 / 10 times or less of the concentration P1.

[0122] As explained in Figure 4, the depth position of the upper end 84 of the gate conductive portion 44 is included in the depth range in which the third emitter portion 83 is provided. The upper end 84 may be provided within the range of the full width at half maximum of the peak 93. The range of the full width at half maximum of the peak 93 is the range in which the doping concentration at peak 93 is half or more of P3.

[0123] The length of the third emitter portion 83 in the depth direction may be 0.4 μm or more. This allows the upper end 84 of the gate conductive portion 44 to be positioned opposite the third emitter portion 83 even if the depth position of the upper end 84 of the gate conductive portion 44 fluctuates due to manufacturing variations, etc. The length of the third emitter portion 83 in the depth direction may be 1 μm or less. The third emitter portion 83 only needs to be able to absorb variations in the depth position of the upper end 84. By making the length of the third emitter portion 83 1 μm or less, the total length of the emitter region 12 can be reduced.

[0124] Figure 6 shows another example of the doping concentration distribution in the hh line. In this example, the doping concentration distribution in the second emitter portion 82 differs from that of the example in Figure 6. The distributions in the first emitter portion 81 and the third emitter portion 83 are the same as those in the example in Figure 5.

[0125] The second emitter portion 82 in this example has a flat portion 96 in which the doping concentration distribution in the depth direction is flat. For example, the flat portion 96 is the portion in which the maximum doping concentration is less than or equal to twice the minimum doping concentration. The length of the flat portion 96 in the depth direction may be 0.1 μm or more, or 0.5 μm or more.

[0126] The minimum doping concentration in the flat portion 96 may be 10 times or less, 5 times or less, or 2 times or less of the doping concentration Dd. The minimum doping concentration in the flat portion 96 may also be the same as the doping concentration Dd in the drift region 18. In this example, n-type dopant ions are not implanted in the second emitter portion 82.

[0127] Figure 7 shows another example of the doping concentration distribution in the hh line. In this example, the doping concentration distribution in the second emitter portion 82 differs from that in the example in Figure 5. The distributions in the first emitter portion 81 and the third emitter portion 83 are the same as in the example in Figure 5.

[0128] In this example, the second emitter portion 82 has a valley 97 in which the doping concentration shows a minimum value in the depth direction. The minimum value of the doping concentration in the valley 97 is denoted as V1. The concentration V1 may be 100 times or less, 50 times or less, 10 times or less, or 5 times or less, the doping concentration Dd in the drift region 18. The concentration V1 may also be the same as the concentration Dd. In this example, n-type dopant ions are not implanted into the second emitter portion 82. The valley 97 near the boundary between the first peak 91 and the third peak 93 functions as the second emitter portion 82.

[0129] Let Db be the doping concentration at both ends of the second emitter portion 82 in the depth direction. The concentration Db may be 10 times, 5 times, or any other value of the concentration V1. The length of the second emitter portion 82 in the depth direction is the same as in the example in Figure 5 or Figure 6.

[0130] The second emitter portion 82 has one of the peaks 92 shown in Figure 5, the flat portion 96 shown in Figure 6, and the trough portion 97 shown in Figure 7. The second emitter portion 82 may have more than one of the peaks 92, flat portion 96, and trough portion 97.

[0131] Figure 8 shows another example of the structure of the mesa section 60. Figure 8 shows an enlarged view of a cross-section near the mesa section 60. In this example, the structure of the side wall 214 of the trench contact section 210 of the mesa section 60 differs from the example shown in Figure 4. The other structures are the same as those in the example in Figure 4.

[0132] The side wall 214 in this example includes a first side wall portion 218 and an oblique portion 216. The oblique portion 216 is the portion where the extension direction in the XZ cross section intersects with the depth direction (Z-axis direction). The oblique portion 216 in this example intersects with the depth direction at an angle θ1. The side wall 214 in this example has the oblique portion 216 in at least a portion between the first depth position Z1 and the second depth position Z2. The oblique portion 216 may be provided on the entire side surface of the second emitter portion 82. The oblique portion 216 may also be provided on at least a portion of the side surface of the third emitter portion 83. The oblique portion 216 in this example is not provided on the side surface of the first emitter portion 81.

[0133] The side wall region 86 is in contact with the oblique portion 216. The side wall region 86 may be in contact with the entire oblique portion 216 in the XZ cross-section. The upper end of the side wall region 86 may be in contact with the lower surface of the first emitter portion 81.

[0134] The first sidewall portion 218 is the region of the sidewall 214 of the trench contact portion 210 that faces the first emitter portion 81 in the X-axis direction. The angle between the first sidewall portion 218 and the depth direction is smaller than the angle θ1 between the oblique portion 216 and the depth direction. The angle between the first sidewall portion 218 and the depth direction may be half or less of the angle θ1, or even one-quarter or less. The first sidewall portion 218 may include a portion parallel to the depth direction. More than half of the area of ​​the first sidewall portion 218 may be parallel to the depth direction, or the entire first sidewall portion 218 may be parallel to the depth direction.

[0135] By reducing the angle between the first sidewall portion 218 and the depth direction, the amount of p-type dopant ions injected per unit area of ​​the first sidewall portion 218 can be reduced compared to the angled portion 216. As a result, the amount of p-type dopant ions injected into the interface between the first emitter portion 81 and the trench contact portion 210 can be reduced, and the decrease in the net doping concentration of the first emitter portion 81 at that interface can be suppressed.

[0136] Figure 9 shows a part of the manufacturing process for the semiconductor device 100. Figure 9 shows the process of forming the trench contact portion 210, the side wall region 86, and the bottom region 87.

[0137] In step S410 of this example, a gate trench 40, a mesa 60, a lower end region 230, a storage region 232, an interlayer insulating film 38, an emitter region 12, and a base region 14 are formed on the semiconductor substrate 10. Also in S410, a contact trench 220 is formed in the mesa 60 for forming a trench contact portion 210. Before the formation of the contact trench 220, each part of the emitter region 12 may be provided across the entire mesa 60 in the X-axis direction. In other examples, each part of the emitter region 12 may be formed after the formation of the contact trench 220. Furthermore, the interlayer insulating film 38 may be formed after S410 or after S420.

[0138] The contact trench 220 has a first side wall portion 218, an angled portion, and a bottom surface 213. The bottom surface 213 is the surface that includes the lower end of the contact trench 220. The bottom surface 213 may be a surface parallel to the XY plane. In other examples, the bottom surface 213 may be a portion of the surface of the contact trench 220 whose distance in the Z-axis direction from the lower end of the contact trench 220 is within a predetermined value. This predetermined value may be, for example, 0.1 μm, 0.2 μm, or 0.5 μm.

[0139] The slanted portion 216 and the first sidewall portion 218 are parts of the contact trench 220 that extend from the bottom surface 213 to the top surface 21 of the semiconductor substrate 10. The slanted portion 216 is connected to the bottom surface 213, and the first sidewall portion 218 is connected to the top surface 21. The upper end of the slanted portion 216 is connected to the lower end of the first sidewall portion 218. In other words, the slanted portion 216 is the lower part of the sidewall of the contact trench 220, and the first sidewall portion 218 is the upper part.

[0140] In this example, of the slanted portion 216 and the first side wall portion 218, at least the slanted portion 216 has an angle with respect to the depth direction. This angle may be the angle θ1 described in Figure 4, etc. The first side wall portion 218 may also have an angle with respect to the depth direction. This angle of the first side wall portion 218 may be the same as, smaller than, or larger than the angle of the slanted portion 216. In the example in Figure 9, this angle of the first side wall portion 218 is smaller than the angle of the slanted portion 216. The first side wall portion 218 may also be parallel to the depth direction.

[0141] At least a portion of the second emitter portion 82 may be exposed in the slanted portion 216. The slanted portion 216 may expose the side surface of the second emitter portion 82 from the lower end to the upper end. In other words, the upper end of the slanted portion 216 is located at the same depth as, or higher than, the upper end of the second emitter portion 82. At least a portion of the side surface of the third emitter portion 83 may be exposed in the slanted portion 216.

[0142] At least a portion of the first emitter portion 81 is exposed in the first side wall portion 218. The lower end of the slanted portion 216 may be located at the same depth as the lower end of the first emitter portion 81, or higher.

[0143] In step S420, p-type dopant ions are injected into the semiconductor substrate 10 from the upper surface 21 side, using the interlayer insulating film 38 as a mask. This allows the p-type dopant ions to be injected through the sidewalls of the contact trench 220 that are not covered by the interlayer insulating film 38. In step S420, the p-type dopant ions are injected through the contact trench 220 in a state where the angle between at least a part of the sidewall of the contact trench 220 and the injection direction of the p-type dopant ions is not parallel. This angle may be 5 degrees or more, 10 degrees or more, 15 degrees or more, or 20 degrees or more. This angle may be 45 degrees or less, 40 degrees or less, 35 degrees or less, or 30 degrees or less.

[0144] For example, in S420, dopant ions are injected such that at least one of the injection direction of the dopant ions and the extension direction of the oblique portion 216 is at an angle with respect to the depth direction. At least a portion of the side wall of the contact trench 220 (e.g., oblique portion 216) may be formed obliquely with respect to the depth direction. As described above, the angle between a portion of the side wall of the contact trench 220 (e.g., oblique portion 216) and the depth direction may be 5 degrees or more.

[0145] The injection direction of the p-type dopant ion may be oblique to the depth direction. This angle may be 5 degrees or more, 10 degrees or more, 15 degrees or more, or 20 degrees or more. This angle may be 45 degrees or less, 40 degrees or less, 35 degrees or less, or 30 degrees or less.

[0146] In the example shown in Figure 9, both the dopant ion injection direction and the extension direction of the oblique portion 216 are at an angle with respect to the depth direction. In other examples, if the oblique portion 216 is formed obliquely, the dopant ion injection direction may be parallel to the depth direction. Also, if the dopant ion injection direction is oblique, the oblique portion 216 may be parallel to the depth direction.

[0147] A sidewall region 86 is formed by implanting p-type dopant ions. The semiconductor substrate 10 may be heat-treated after implanting the p-type dopant ions. The concentration of p-type dopant in the sidewall region 86 after manufacturing the semiconductor device 100 may be higher than the concentration of n-type dopant in the second emitter portion 82. In this example, the region is inverted from n-type to p-type by implanting p-type dopant ions into the side surface of the second emitter portion 82. Therefore, the concentration of p-type dopant in the sidewall region 86 is higher than the concentration of n-type dopant in the second emitter portion 82. The concentration of each dopant may be measured using, for example, the chemical concentration measured by the CEMS method. The concentration of p-type dopant in the sidewall region 86 may be twice or more, five times or more, or ten times or more, than the concentration of n-type dopant in the second emitter portion 82.

[0148] The concentration of the p-type dopant in the sidewall region 86 of the semiconductor device 100 after manufacturing may be lower than the concentration of the n-type dopant in the first emitter portion 81. This prevents the side surface of the first emitter portion 81 from being inverted to the p-type. The concentration of the p-type dopant in the sidewall region 86 may be 1 / 2 or less, 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the concentration of the n-type dopant in the first emitter portion 81.

[0149] The concentration of the p-type dopant in the sidewall region 86 of the semiconductor device 100 after manufacturing may be higher than the concentration of the n-type dopant in the third emitter portion 83. This allows the side surface of the third emitter portion 83 to be inverted from n-type to p-type. The concentration of the p-type dopant in the sidewall region 86 may be twice or more, five times or more, or even ten times or more, than the concentration of the n-type dopant in the third emitter portion 83.

[0150] In S420, a bottom region 87 may be formed. The bottom region 87 may be formed in the same process as the side wall region 86, and in parallel with the side wall region 86. In other words, p-type dopant ions may be implanted into the bottom region 87 and the side wall region 86 in the same process. In another example, in addition to the first implantation step of implanting p-type dopant ions into the side wall region 86, a second implantation step of implanting p-type dopant ions into the bottom region 87 may be provided. The implantation direction in the second implantation step may have a smaller angle with respect to the depth direction compared to the implantation direction in the first implantation step. In other words, the implantation direction in the second implantation step is closer to perpendicular to the top surface 21 compared to the implantation direction in the first implantation step. This allows for efficient implantation of p-type dopant ions into the bottom surface 213 of the contact trench 220 in the second implantation step. After the manufacture of the semiconductor device 100, the doping concentration in the bottom region 87 may be higher than the doping concentration in the side wall region 86.

[0151] Furthermore, in S420, the dose amount ( / cm²) of dopant ions injected into the sidewall of the first emitter portion 81 is... 2 The amount of dopant ions injected into the sidewall of the second emitter portion 82 may be less than the dose of dopant ions injected into the sidewall of the second emitter portion 82. For example, by making the angle between the first sidewall portion 218 and the injection direction smaller than the angle between the oblique portion 216 and the injection direction, the injection of dopant ions into the first sidewall portion 218 can be suppressed. Also, when the injection direction of the dopant ions is oblique, the injection of dopant ions into the first sidewall portion 218 can be suppressed by forming a mask that shields the dopant ions on the upper surface 21 near the opening of the contact trench.

[0152] In S420, the sidewall region 86 may be formed in contact with the oblique portion 216 of the contact trench 220. The position of the sidewall region 86 can be adjusted by the implantation depth (acceleration energy) of the p-type dopant ions. By implanting p-type dopant ions near the surface of the oblique portion 216, a sidewall region 86 in contact with the oblique portion 216 can be formed.

[0153] In step S430, a conductive material is filled into the contact trench 220 to form the trench contact portion 210. The conductive material may be the same material as the emitter electrode 52, or it may be a different material. The conductive material may include, for example, tungsten. In addition, a barrier layer containing at least one of titanium and titanium nitride may be formed between the metal plug such as tungsten and the semiconductor substrate 10.

[0154] Figure 10 shows an example of a method for forming contact trenches 220. In step S420, a plurality of openings 221, 222, and 223 with varying opening areas in a step-like manner are formed on the upper surface 21 of the semiconductor substrate 10. Each opening may be formed by anisotropic etching. The etching gas used in anisotropic etching is, for example, CHF3, Cl2, or BCl3, but is not limited to these.

[0155] As an example, the largest opening 221 is formed first. Next, the second largest opening 222 is formed on the bottom surface of opening 221. Then, the third largest opening 223 is formed on the bottom surface of opening 222. Step-shaped openings are formed through this process. The depth position of the lower end of opening 221 may coincide with or differ from the depth position of the lower end of the first emitter portion 81. The depth position of the lower end of opening 222 may coincide with or differ from the depth position of the lower end of the second emitter portion 82. The depth position of the lower end of opening 223 may be located inside the third emitter portion 83, may coincide with the depth position of the lower end of the third emitter portion 83, or may be located deeper than the lower end of the third emitter portion 83.

[0156] In step S404, the step-shaped openings are isotropically etched to form a contact trench 220 having continuous side walls. In S404, the contact trench 220 may be formed by wet etching. The side walls of the contact trench 220 may or may not retain a step shape in which the opening area changes discontinuously along the depth direction. Alternatively, step S404 may be omitted, and multiple openings 221, 222, and 223 with step-shaped opening areas may be used as the contact trench 220.

[0157] Figure 11 shows another example of the structure of the mesa section 60. Figure 11 shows an enlarged view of a cross-section near the mesa section 60. In this example, the structure of the side wall 214 of the trench contact section 210 of the mesa section 60 differs from the example shown in Figure 4 or Figure 8. The other structures are the same as those in Figure 4 or Figure 8.

[0158] In this example, the side wall 214 of the trench contact portion 210 includes a stepped portion 240 in which the inclination of the side wall 214 changes discontinuously between a first depth position Z1 and a second depth position Z2. As described above, the cross-sectional area of ​​the trench contact portion 210 at the first depth position Z1 is larger than the cross-sectional area of ​​the trench contact portion 210 at the second depth position Z2. In the stepped portion 240, the cross-sectional area of ​​the trench contact portion 210 in the XY plane changes discontinuously along the Z axis direction. The side wall 214 of the trench contact portion 210 may have a surface parallel to the XY plane in the stepped portion 240. In portions other than the stepped portion 240, the side wall 214 may or may not have an angle with respect to the depth direction.

[0159] By providing the stepped portion 240, p-type dopant ions can be efficiently injected into the upper surface of the stepped portion 240. This makes it easier to provide a side wall region 86 in the area below the stepped portion 240.

[0160] A side wall region 86 may be provided in the portion of the side wall 214 below the stepped portion 240. The side wall region 86 may be exposed on the upper surface of the stepped portion 240. The upper surface of the stepped portion 240 may have portions where the side wall region 86 is not provided, or the entire surface may be exposed to the side wall region 86. In the example of Figure 12, the side wall region 86 is not provided in the portion of the side wall 214 above the stepped portion 240, but a side wall region 86 may be provided in a portion of the portion above the stepped portion 240.

[0161] The stepped portion 240 may be positioned opposite the first emitter portion 81 or the second emitter portion 82 in the X-axis direction. In the example shown in Figure 11, the stepped portion 240 is positioned opposite the boundary between the first emitter portion 81 and the second emitter portion 82 in the X-axis direction. In this case, the cross-sectional area of ​​the first emitter portion 81 in the XY plane and the cross-sectional area of ​​the second emitter portion 82 in the XY plane may be different.

[0162] The side wall 214 of the trench contact portion 210 may have a step portion below the second depth position Z2. In the example of Figure 11, the step portion is provided at a position opposite the boundary between the second emitter portion 82 and the third emitter portion 83 in the X-axis direction. The depth position of the step portion is not limited to this position.

[0163] Figure 12 shows another example of the mesa section 60 structure. Figure 11 shows an enlarged view of a cross-section near the mesa section 60. In this example, the position of the stepped section 240 differs from the example shown in Figure 11. The other structures are the same as those in the example in Figure 11.

[0164] In the example shown in Figure 12, a stepped portion 240 is provided at a position opposite the first emitter portion 81 in the X-axis direction. In this case, the first emitter portion 81 may also have a stepped portion. That is, the cross-sectional area of ​​the first emitter portion 81 in the XY plane may change discontinuously at the stepped portion 240.

[0165] Figure 13 shows another example of the mesa section 60 structure. Figure 13 shows an enlarged view of a cross-section near the mesa section 60. In this example, the position of the stepped section 240 differs from the example shown in Figure 11. The other structures are the same as those in the example in Figure 11.

[0166] In the example shown in Figure 13, a stepped portion 240 is provided at a position opposite the second emitter portion 82 in the X-axis direction. In this case, the second emitter portion 82 may also have a stepped portion. That is, the cross-sectional area of ​​the second emitter portion 82 in the XY plane may change discontinuously at the stepped portion 240. Also, the side wall region 86 may be provided on the side surface of the second emitter portion 82 along the stepped portion 240. That is, the side wall region 86 may also have a stepped portion.

[0167] Figure 14 shows another example of steps S410 to S430 for forming the trench contact portion 210, the side wall region 86, and the bottom region 87. In this example, the shape of the contact trench 220 formed in S410 and the injection direction of the p-type dopant ions injected in S420 differ from the example in Figure 9. Otherwise, it is the same as the example in Figure 9.

[0168] In this example as well, p-type dopant ions are implanted through the contact trench 220 in a state where the angle between at least a portion of the side wall 219 of the contact trench 220 and the implantation direction of the p-type dopant ions is not parallel. However, in step S410 of this example, the contact trench 220 may be formed such that the side wall 219 extends in a direction parallel to the depth direction, at least in the range facing the second emitter portion 82. The entire side wall 219 may extend in a direction parallel to the depth direction.

[0169] In step S420 of this example, p-type dopant ions are injected in an injection direction that is at an angle to the depth direction. This angle may be 5 degrees or more, 10 degrees or more, 15 degrees or more, or 20 degrees or more. This angle may be 45 degrees or less, 40 degrees or less, 35 degrees or less, or 30 degrees or less. Step S430 of this example is the same as the example in Figure 9. The side wall region 86 can also be formed with high precision by such a process.

[0170] In this example, the side wall 219 is formed parallel to the depth direction. In other examples, the side wall 219 may be formed at an angle so that the cross-sectional area of ​​the contact trench 220 decreases as it approaches the top surface 21. Even in this case, by adjusting the injection direction of the p-type dopant ions, the injection direction can be made at an angle to the side wall 219, and the side wall region 86 can be formed with high precision.

[0171] Figure 15 shows another example of the structure of the mesa 60. Figure 15 shows an enlarged view of a cross-section near the mesa 60. In this example, the mesa 60 differs from the other examples described herein in the position of the side wall region 86. The other structures are the same as in any of the examples described herein. In the example of Figure 15, the shape of the trench contact portion 210 is the same as in the example of Figure 14, but the shape of the trench contact portion 210 may be any of the examples described herein.

[0172] In this example, the sidewall region 86 is positioned away from the sidewall 214 of the trench contact portion 210. For example, in S420 in Figure 9 or Figure 14, the sidewall region 86 can be formed away from the sidewall 214 of the trench contact portion 210 by increasing the acceleration energy of the p-type dopant ion.

[0173] The side wall region 86 is provided at least between the trench contact portion 210 and the second emitter portion 82. The side wall region 86 may also be provided between the trench contact portion 210 and the third emitter portion 83. In this example, the side wall region 86 may be provided over the entirety of the second emitter portion 82 and the third emitter portion 83 in the depth direction. By adjusting the position of the side wall region 86, the width of the emitter region 12 between the side wall region 86 and the gate trench portion 40 can be adjusted, thereby adjusting the resistance value in the emitter region 12.

[0174] A second emitter portion 82 and a third emitter portion 83 may be provided between the side wall region 86 and the side wall 214. A second emitter portion 82 and a third emitter portion 83 are provided between the side wall region 86 and the gate trench portion 40.

[0175] The side wall region 86 may be connected to the bottom region 87. In this case, the emitter region 12 between the side wall region 86 and the side wall 214 is not directly connected to the base region 14. This prevents current from flowing between the emitter electrode 52 and the base region 14 through the emitter region 12 between the side wall region 86 and the side wall 214.

[0176] The side wall region 86 may be positioned between the side wall 214 and the gate trench portion 40, on the side closer to the side wall 214. This prevents the side wall region 86 from coming into contact with the gate trench portion 40.

[0177] Figure 16 shows an example of the collector voltage-collector current characteristics of the semiconductor device 100. Figure 16 shows multiple characteristics for an embodiment in which the side wall region 86 is provided by the method described in Figure 9 or Figure 14, and multiple characteristics for a comparative example in which the side wall region 86 is provided by a different method. In the comparative example, the side wall of the contact trench 220 was formed parallel to the depth direction, and p-type dopant ions were injected parallel to the depth direction.

[0178] In Figure 16, the characteristics of the comparative example are shown with a dashed line, and the characteristics of the example are shown with a solid line. As shown in Figure 16, in the comparative example, the variation in the collector current saturation current Vr is large. In contrast, in the example, the variation in the collector current saturation current Ve is small. In the example, it is thought that the variation in doping concentration, etc., in the side wall region 86 is small, resulting in a smaller variation in the saturation current Ve.

[0179] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0180] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0181] 10...Semiconductor substrate, 11...p-type outer well region, 12...Emitter region, 14...Base region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 38...Interlayer insulating film, 40...Gate trench region, 42...Gate insulating film, 44...Gate conductive region, 52...Emitter electrode, 60...Mesa region, 70...Transistor region, 81...First emitter portion, 82...Second emitter portion, 83...Third emitter portion, 84...Upper end, 86...Side wall region, 87...Bottom region, 9 0...Edge termination structure, 91, 92, 93...Peak, 94, 95...Valley, 96...Flat section, 97...Valley, 100...Semiconductor device, 130...Gate wiring, 160...Active section, 161...First edge, 162...Second edge, 164...Gate pad, 210...Trench contact section, 212...Bottom section, 213...Bottom surface, 214...Side wall, 216...Slanted section, 218...First side wall section, 219...Side wall, 220...Contact trench, 221, 222, 223...Opening, 230...Lower end region, 240...Stepped section

Claims

1. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type, Multiple trenches are provided from the upper surface to the interior of the semiconductor substrate, In the semiconductor substrate, a mesa portion is sandwiched between two trench portions, In the mesa portion, a trench contact portion is provided extending from the upper surface to the interior of the semiconductor substrate, wherein the cross-sectional area at a second depth position, which is further from the upper surface than the first depth position, is smaller than the cross-sectional area at a first depth position. In the mesa portion, a first emitter portion of the first conductivity type is provided between the side wall of the trench contact portion and the trench portion, A second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion is provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, A second conductive side wall region is provided between the side wall of the trench contact portion and the second emitter portion. Equipped with, The second emitter portion has one of the following characteristics: a flat portion where the doping concentration distribution in the depth direction is flat, a trough where the doping concentration shows a minimum value in the depth direction, or a peak where the doping concentration shows a maximum value in the depth direction and is lower in concentration than the first emitter portion. Semiconductor equipment.

2. The side wall of the trench contact portion has an oblique portion extending in a direction intersecting the depth direction between the first depth position and the second depth position. The aforementioned side wall region is in contact with the aforementioned oblique portion. The semiconductor device according to claim 1.

3. The angle between the aforementioned oblique portion and the aforementioned depth direction is 5 degrees or more. The semiconductor device according to claim 2.

4. The aforementioned plurality of trench sections are arranged in a line in the first direction, Of the side walls of the trench contact portion, the angle formed between the region facing the first emitter portion in the first direction and the depth direction is smaller than the angle formed between the oblique portion and the depth direction. The semiconductor device according to claim 2.

5. Of the side walls of the trench contact portion, the region facing the first emitter portion in the first direction includes a portion parallel to the depth direction. The semiconductor device according to claim 4.

6. The side wall of the trench contact portion includes a stepped portion in which the inclination of the side wall changes discontinuously between the first depth position and the second depth position. The semiconductor device according to claim 1.

7. The aforementioned plurality of trench sections are arranged in a line in the first direction, The stepped portion is positioned facing the first emitter portion or the second emitter portion in the first direction. The semiconductor device according to claim 6.

8. The stepped portion is positioned opposite the second emitter portion in the first direction. The semiconductor device according to claim 7.

9. The stepped portion is located opposite the boundary between the first emitter portion and the second emitter portion in the first direction. The semiconductor device according to claim 7.

10. The aforementioned plurality of trench sections are arranged in a line in the first direction, The first emitter portion has a region that does not face the side wall region in the first direction. The semiconductor device according to claim 1.

11. The first emitter portion is in contact with the side wall of the trench contact portion. The semiconductor device according to claim 10.

12. The aforementioned side wall region is in contact with the aforementioned side wall of the trench contact portion. The semiconductor device according to any one of claims 1 to 11.

13. The aforementioned side wall region is separated from the aforementioned side wall of the trench contact portion. The semiconductor device according to any one of claims 1 to 11.

14. The concentration of the p-type dopant in the sidewall region is higher than the concentration of the n-type dopant in the second emitter region. The semiconductor device according to any one of claims 1 to 11.

15. The concentration of the p-type dopant in the sidewall region is lower than the concentration of the n-type dopant in the first emitter portion. The semiconductor device according to any one of claims 1 to 11.

16. The trench contact portion is further provided below the second emitter portion between the side wall and the trench portion, and comprises a third emitter portion of a first conductivity type having a higher doping concentration than the second emitter portion. The semiconductor device according to any one of claims 1 to 11.

17. The aforementioned side wall region is also provided between the side wall of the trench contact portion and the third emitter portion. The semiconductor device according to claim 16.

18. The concentration of the p-type dopant in the sidewall region is higher than the concentration of the n-type dopant in the third emitter portion. The semiconductor device according to claim 16.

19. The semiconductor substrate is a wide-bandgap substrate formed from a material with a larger bandgap than silicon. The semiconductor device according to any one of claims 1 to 11.

20. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type, Multiple trenches are provided from the upper surface to the interior of the semiconductor substrate, In the semiconductor substrate, a mesa portion is sandwiched between two trench portions, In the mesa portion, a trench contact portion is provided from the upper surface to the interior of the semiconductor substrate, In the mesa portion, a first emitter portion of the first conductivity type is provided between the side wall of the trench contact portion and the trench portion, A second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion is provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, Between the side wall of the trench contact portion and the trench portion, a second conductive type side wall region is provided away from the side wall. Equipped with, The second emitter portion has one of the following characteristics: a flat portion where the doping concentration distribution in the depth direction is flat, a trough where the doping concentration shows a minimum value in the depth direction, or a peak where the doping concentration shows a maximum value in the depth direction and is lower in concentration than the first emitter portion. Semiconductor equipment.

21. The aforementioned side wall region is provided between the trench contact portion and the second emitter portion. The semiconductor device according to claim 20.

22. The trench contact portion is provided below the second emitter portion between the side wall and the trench portion, and further comprises a third emitter portion of a first conductivity type having a higher doping concentration than the second emitter portion, The aforementioned side wall region is also provided between the side wall of the trench contact portion and the third emitter portion. The semiconductor device according to claim 21.

23. The first emitter portion is in contact with the side wall of the trench contact portion. The semiconductor device according to claim 22.

24. A method for manufacturing a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type, The semiconductor device comprises a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate, a mesa portion sandwiched between two of the trench portions in the semiconductor substrate, a trench contact portion provided in the mesa portion from the upper surface to the interior of the semiconductor substrate, a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trench portion in the mesa portion, a second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion, provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, and a side wall region of a second conductivity type provided between the side wall of the trench contact portion and the second emitter portion. The aforementioned manufacturing method is A contact trench is formed in the mesa portion for forming the trench contact portion. The side wall region is formed by injecting the dopant through the contact trench while the angle between the side wall of the contact trench and the injection direction of the second conductive dopant is not parallel. Manufacturing method.

25. At least a portion of the side wall of the contact trench is formed at an angle with respect to the depth direction. The manufacturing method according to claim 24.

26. The angle between the portion of the side wall of the contact trench and the depth direction is 5 degrees or more. The manufacturing method according to claim 25.

27. The injection direction of the dopant is made oblique to the depth direction. The manufacturing method according to claim 24.

28. The angle between the injection direction of the dopant and the depth direction is 5 degrees or more. The manufacturing method according to claim 27.

29. The side wall region is formed in contact with the side wall of the contact trench. The manufacturing method according to any one of claims 24 to 28.

30. The side wall region is formed separately from the side wall of the contact trench. The manufacturing method according to any one of claims 24 to 28.

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