Manufacturing method for semiconductor devices

Abstract

In semiconductor devices, it is preferable to reduce variations in characteristics. [Solution] A manufacturing method is provided in which a contact trench is formed in the mesa portion, a contact insulating film is formed on the side walls and bottom surface of the contact trench, a part of the contact insulating film is etched to expose the first emitter portion on the side wall of the contact trench, and the second conductivity type region is exposed on the bottom surface of the contact trench, and a conductive material is filled inside the contact trench to bring the conductive material into contact with the first emitter portion and the second conductivity type region.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Paragraph 0119 of Patent Document 1 states that "In this example, the doping concentration of the P-type diffusion region 16 is higher than the doping concentration of the P-type base region 14. The P-type diffusion region 16 may have a concentration peak with a higher doping concentration than the P-type base region 14. It is preferable to perform oblique ion implantation to form the P-type diffusion region 16." Paragraph 0040 of Patent Document 2 discloses that "a first oblique ion implantation 32 is performed on the side wall 8b of the contact trench 8 at a shallow depth d1." Paragraph 0021 of Patent Document 3 discloses that "the side wall of the body contact trench (second trench) 8 has a slope connecting the vicinity of the upper end of the first trench 4 and the bottom of the body contact trench (second trench) 8, which is located deeper than the upper surface of the gate electrode." Paragraph 0075 of Patent Document 4 discloses that "the contact trench 52 is formed deeper than the p-well region 26. The contact trench 52 is formed such that the first inclination angle (θ1 in Figure 3) of the side surface of the contact trench 52 with respect to the first surface is 60 degrees or more and 85 degrees or less." Paragraph 0048 of Patent Document 5 discloses that "the source region 104 includes a first source portion region 1041 that is directly adjacent to the contact 112 in the source contact area 113 of the first surface 110. The source region 104 further includes a second source portion region 1042 and a third source portion region 1043." Patent Document 1: Japanese Unexamined Patent Publication No. 2023-128635 Patent Document 2: Japanese Unexamined Patent Publication No. 2018-110166 Patent Document 3: Japanese Unexamined Patent Publication No. 2011-134985 Patent Document 4: Japanese Unexamined Patent Publication No. 2018-14455 Patent Document 5: Japanese Unexamined Patent Publication No. 2020-145430 [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In semiconductor devices, it is preferable to reduce variations in characteristics. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a method for manufacturing a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. The semiconductor device may include a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate, a mesa portion sandwiched between two of the trench portions in the semiconductor substrate, a trench contact portion provided in the mesa portion from the upper surface to the interior of the semiconductor substrate, a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trench portion in the mesa portion, a second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion and provided below the first emitter portion between the side wall of the trench contact portion and the trench portion, a region of a second conductivity type provided below the trench contact portion, and a contact insulating film provided between the side wall of the trench contact portion and the second emitter portion. In the above manufacturing method, contact trenches for forming the trench contact portion may be formed in the mesa portion. In any of the above manufacturing methods, the contact insulating film may be formed on the side walls and bottom surface of the contact trench. In any of the above manufacturing methods, a portion of the contact insulating film may be etched to expose the first emitter portion on the side wall of the contact trench and the second conductivity region on the bottom surface of the contact trench. In any of the above manufacturing methods, a conductive material may be filled inside the contact trench to bring the conductive material into contact with the first emitter portion and the second conductivity region.

[0005] In any of the above manufacturing methods, the contact insulating film may also be formed on the upper surface of the semiconductor substrate. In any of the above manufacturing methods, the contact insulating film on the upper surface of the semiconductor substrate may be etched by anisotropic etching. In any of the above manufacturing methods, a mask may be formed that covers the upper surface of the semiconductor substrate and the contact insulating film provided on the side wall of the contact trench. In any of the above manufacturing methods, the contact insulating film provided on the bottom surface of the contact trench may be etched.

[0006] In any of the above manufacturing methods, after etching the contact insulating film, the contact insulating film may cover the entire side surface of the second emitter portion.

[0007] The semiconductor device may include a third emitter portion of a first conductivity type having a higher doping concentration than the second emitter portion, located below the second emitter portion between the side wall of the trench contact portion and the trench portion. In any of the above manufacturing methods, after etching the contact insulating film, the contact insulating film may cover the entire side surface of the third emitter portion.

[0008] In any of the above manufacturing methods, the thickness of the contact insulating film may be less than the depth of the trench contact portion.

[0009] In any of the above manufacturing methods, after filling with the conductive material, the thickness of the conductive material and the contact insulating film remaining inside the contact trench in a first direction parallel to the upper surface of the semiconductor substrate may be greater for the conductive material.

[0010] In any of the above manufacturing methods, the thickness of the conductive material may be twice or more the thickness of the contact insulating film.

[0011] In any of the above manufacturing methods, the trench portion may have an in-trench insulating film covering the inner wall of the trench portion. In any of the above manufacturing methods, the contact insulating film may be thinner than the in-trench insulating film.

[0012] The semiconductor device may further include a base region of a second conductivity type provided in contact with the trench. In any of the above manufacturing methods, the region of the second conductivity type may be in contact with the base region and the conductive material, and may have a higher concentration than the base region. In any of the above manufacturing methods, the region of the second conductivity type may be formed by injecting a dopant of the second conductivity type into the bottom surface of the contact trench after forming the contact trench and before forming the contact insulating film.

[0013] The semiconductor device may further include a base region of a second conductivity type provided in contact with the trench portion. In any of the above manufacturing methods, the region of the second conductivity type may be in contact with the base region and the conductive material, and may have a higher concentration than the base region. In the manufacturing method, after etching the contact insulating film and before filling with the conductive material, the region of the second conductivity type may be formed by injecting a dopant of the second conductivity type into the bottom surface of the contact trench.

[0014] In any of the above manufacturing methods, the opening width of the contact trench on the upper surface of the semiconductor substrate may be 0.8 μm or more and 2 μm or less. In any of the above manufacturing methods, the thickness of the contact insulating film after etching may be 0.3 μm or more and 0.7 μm or less.

[0015] In any of the above manufacturing methods, the semiconductor substrate may be a wide-bandgap substrate formed of a material with a larger bandgap than silicon.

[0016] In any of the above manufacturing methods, the angle between the side wall of the contact trench and the depth direction may be less than 5 degrees.

[0017] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0018] [Figure 1] It is a top view showing an example of the semiconductor device 100. [Figure 2] It is an example of an enlarged view of the region D in FIG. 1. [Figure 3] It is a diagram showing an example of a cross-section along the line a-a in FIG. 2. [Figure 4] It is an enlarged view of a cross-section in the vicinity of the mesa portion 60. [Figure 5] It is a diagram showing an example of a doping concentration distribution along the line h-h in FIG. 4. [Figure 6] It is a diagram showing another example of the doping concentration distribution along the line h-h. [Figure 7] It is a diagram showing another example of the doping concentration distribution along the line h-h. [Figure 8] It is a diagram showing a part of the manufacturing process of the semiconductor device 100. [Figure 9] It is a diagram showing a part of the manufacturing process of the semiconductor device 100. [Figure 10] It is a diagram showing an example of the collector voltage - collector current characteristics of the semiconductor device 100.

Embodiments for Carrying Out the Invention

[0019] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0020] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0021] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0022] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0023] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0024] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0025] In this specification, the conductivity type of a doped region containing impurities is described as either p-type or n-type. In this specification, impurities may specifically refer to either n-type donors or p-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an n-type conductivity or a p-type conductivity.

[0026] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0027] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron donors. In this specification, VOH defects may be referred to as hydrogen donors.

[0028] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type. In this specification, conductivity types represented by lowercase p or n, such as p type or n type, do not indicate the relative magnitude of the doping concentration. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0029] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the n-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the p-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the n-type region may be referred to as the donor concentration, and the doping concentration in the p-type region may be referred to as the acceptor concentration.

[0030] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0031] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0032] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. The concentrations used herein may be values ​​at room temperature. For example, values ​​at 300 K (Kelvin) (approximately 26.9°C) may be used.

[0033] Figure 1 is a top view showing an example of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0034] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. The semiconductor substrate 10 may be a wide-bandgap substrate formed of a material with a larger bandgap than silicon. For example, the semiconductor substrate 10 may be a SiC substrate or a compound semiconductor substrate such as a GaN substrate.

[0035] The semiconductor substrate 10 has a first edge 161 and a second edge 162 when viewed from above. In this specification, "top view" simply means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of first edges 161 facing each other when viewed from above. The semiconductor substrate 10 in this example also has two pairs of second edges 162 facing each other when viewed from above. In Figure 1, the first edge 161 is parallel to the X-axis direction. The second edge 162 is parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The first edge 161 is perpendicular to the extension direction or longitudinal direction of the gate trench portion, which will be described later. The second edge 162 is parallel to the extension direction or longitudinal direction of the gate trench portion, which will be described later.

[0036] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active section 160, but it is omitted in Figure 1.

[0037] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. In other examples, the transistor section 70 and the diode section including a diode element such as an FWD (Free Wheel Diode) may be arranged alternately along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. In this example, one transistor section 70 is provided, but multiple transistor sections 70 may be provided. P+ type well regions or gate runners may be provided between the transistor sections 70.

[0038] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a surface MOS structure periodically arranged on the upper surface side of the semiconductor substrate 10, which has an N+ type emitter region, a P- type base region, an N- type drift region, a gate conductor, and a gate insulating film.

[0039] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed in the vicinity of the first end side 161. The vicinity of the first end side 161 refers to the region between the first end side 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0040] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is shaded.

[0041] The gate wiring 130 is disposed between the active portion 160 and the first end side 161 or the second end side 162 in a top view. The gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the gate wiring 130 in a top view may be regarded as the active portion 160. Also, the gate wiring 130 is connected to the gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like. The gate wiring 130 may be provided separately from the emitter electrode.

[0042] The p-type outer peripheral well region 11 is provided overlapping the gate wiring 130. That is, similar to the gate wiring 130, the p-type outer peripheral well region 11 surrounds the active portion 160 in a top view. The p-type outer peripheral well region 11 extends with a predetermined width also in a range where it does not overlap the gate wiring 130. The p-type outer peripheral well region 11 is a region of the second conductivity type. The p-type outer peripheral well region 11 in this example is P+. The doping concentration of the p-type outer peripheral well region 11 is 5.0×10 17 atoms / cm 3 or more and 5.0×10 19atoms / cm 3 The following is acceptable: The doping concentration in the p-type outer well region 11 is 2.0 × 10⁻⁶. 18 atoms / cm 3 The above and 2.0 × 10 19 atoms / cm 3 The following is acceptable:

[0043] The semiconductor device 100 may include a temperature sensing unit (not shown), which is a pn junction diode made of polysilicon or the like, and a current detection unit (not shown) that simulates the operation of the transistor unit 70 provided in the active unit 160. The temperature sensing unit may be connected to the anode pad and cathode pad via wiring. If a temperature sensing unit is provided, it is preferable that it be located in the center of the semiconductor substrate 10 in the X-axis and Y-axis directions.

[0044] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the first edge 161 or the second edge 162 when viewed from above. The edge termination structure 90 in this example is located between the outer peripheral gate wiring 130 and the first edge 161 or the second edge 162. The edge termination structure 90 mitigates electric field concentration on the upper side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0045] Figure 2 is an example of an enlarged view of region D in Figure 1. Region D is the region that includes the transistor portion 70 of the active portion 160 shown in Figure 1. Figure 2 shows the structure of the upper surface of the semiconductor substrate 10 in region D. In region D, the semiconductor device 100 comprises a plurality of gate trench portions 40 and a plurality of mesa portions 60.

[0046] Multiple gate trenches 40 are arranged in a line in a first direction on the upper surface of the semiconductor substrate 10. In this example, the first direction is the X-axis direction. Each gate trench 40 is arranged at a predetermined interval in the X-axis direction. Each gate trench 40 extends in a second direction intersecting the first direction on the upper surface of the semiconductor substrate 10. In other words, the gate trench 40 has an elongated length in the second direction on the upper surface of the semiconductor substrate 10. In this example, the second direction is the Y-axis direction. Each gate trench 40 extends from the upper surface to the interior of the semiconductor substrate 10.

[0047] The gate trench section 40 is a trench section to which the gate potential is applied. Inside the gate trench section 40, a gate conductive section made of a conductive material such as polysilicon is arranged. The gate conductive section is electrically connected to the gate wiring 130 (see Figure 1), and a predetermined gate voltage is applied. Some of the gate trench sections 40 shown in Figure 2 may be replaced with dummy trench sections. The dummy trench section is a trench section to which the emitter electrode potential is applied. The dummy trench section has the same structure as the gate trench section. A trench section adjacent to a gate trench section 40 in the X-axis direction may be a dummy trench section. One or more dummy trench sections may be arranged between two gate trench sections 40. However, the gate trench sections 40 may be arranged adjacent to each other in the X-axis direction.

[0048] In the X-axis direction, the region of the semiconductor substrate 10 sandwiched between the two trenches is defined as the mesa portion 60. Both ends of the mesa portion 60 in the X-axis direction are the boundaries with the respective trenches. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of at least one of the trenches on both sides.

[0049] At least one mesa portion 60 is provided with an emitter region 12 and a trench contact portion 210. The emitter region 12 and trench contact portion 210 may be provided in at least one mesa portion 60 that is in contact with the gate trench portion 40, the emitter region 12 and trench contact portion 210 may be provided in all mesa portions 60 that are in contact with the gate trench portion 40, or all mesa portions 60 may be provided with an emitter region 12 and trench contact portion 210.

[0050] The emitter region 12 is an N+ type region exposed on the upper surface of the semiconductor substrate 10. In this example, the emitter region 12 is in contact with the gate trench portion 40. Each emitter region 12 may have a strip shape extending in the Y-axis direction. The emitter regions 12 may be provided for each gate trench portion 40 that sandwiches the mesa portion 60. In the portion in contact with the gate trench portion 40, one emitter region 12 extending in the Y-axis direction may be provided for one mesa portion 60. In other examples, multiple emitter regions 12 discretely arranged in the Y-axis direction may be provided in the portion in contact with the gate trench portion 40. In this case, a P+ type contact region may be provided between two emitter regions 12 in the Y-axis direction. That is, the emitter regions 12 and contact regions may be arranged alternately in the Y-axis direction.

[0051] The trench contact portion 210 is provided in the mesa portion 60 from the upper surface to the interior of the semiconductor substrate 10. The trench contact portion 210 may be provided extending in the Y-axis direction on the upper surface of the semiconductor substrate 10. In other words, the trench contact portion 210 may have a longitudinal length in the Y-axis direction on the upper surface of the semiconductor substrate 10. The trench contact portion 210 has a structure in which a conductive material is filled into a trench provided in the mesa portion 60. An emitter potential is applied to the conductive material. The trench contact portion 210 is not in contact with the trench portion. In this example, an emitter region 12 is provided between the trench contact portion 210 and the trench portion. The above-described contact region may be provided in a part of the area between the trench contact portion 210 and the trench portion.

[0052] Figure 3 shows an example of a cross-section along line aa in Figure 2. Cross-section aa is the XZ cross-section passing through the emitter region 12 and the trench contact portion 210. In this example, the semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0053] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor substrate 10 with the largest surface area. An n-type drift region 18 is provided inside the semiconductor substrate 10.

[0054] The emitter electrode 52 is located above the upper surface 21 of the semiconductor substrate 10. A portion of the upper surface 21 of the semiconductor substrate 10 is covered by an interlayer insulating film 38. The emitter electrode 52 is in contact with at least a portion of the upper surface 21 of the semiconductor substrate 10 that is not covered by the interlayer insulating film 38. In this example, the emitter electrode 52 is in contact with the emitter region 12 and the trench contact portion 210.

[0055] The emitter electrode 52 is formed from a material containing metal. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium or titanium nitride below the region made of aluminum or the like. The barrier metal may be in contact with the semiconductor substrate 10.

[0056] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 may cover each trench portion. Alternatively, the interlayer insulating film 38 may be provided inside the trench portion.

[0057] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a metallic material such as aluminum, similar to the emitter electrode 52. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0058] Multiple mesa portions 60 are provided on the upper surface 21 of the semiconductor substrate 10. Each mesa portion 60 is provided with an emitter region 12, a trench contact portion 210, a contact insulating film 86, a bottom region 87, and a base region 14. The configuration of each mesa portion 60 will be described later.

[0059] Multiple gate trenches 40 are provided on the upper surface 21 of the semiconductor substrate 10. Each gate trench 40 extends from the upper surface 21 of the semiconductor substrate 10 into the interior. In this example, the gate trenches 40 penetrate from the upper surface 21 through the base region 14 and reach the drift region 18. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region first and then the trenches. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0060] The gate trench portion 40 has a groove-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon, which is a conductive material. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, inside the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0061] The gate conductive portion 44 within the gate trench portion 40 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130 at a position other than the cross-section shown in Figure 3.

[0062] A lower end region 230 may or may not be provided in contact with the lower end of each gate trench section 40. The lower end region 230 is a p-shaped region. The lower end region 230 may be provided so as to cover the lowest surface of the gate trench section 40. The lower end region 230 is located away from the base region 14. By providing the lower end region 230, electric field concentration at the lower end of the gate trench section 40 can be mitigated. The lower end region 230 may be provided across multiple gate trench sections 40.

[0063] In this example, the semiconductor substrate 10 has an N-type drift region 18. The emitter region 12 has a higher doping concentration than the drift region 18. The drift region 18 is located below the base region 14. The base region 14 is located in contact with the gate trench 40. The drift region 18 may be in contact with the base region 14. In other examples, an N+-type storage region 232 with a higher doping concentration than the drift region 18 may or may not be provided between the drift region 18 and the base region 14. By providing the storage region 232, an injection enhancement effect can be generated, which can lower the on-voltage of the semiconductor device 100.

[0064] A P+ type collector region 22 is provided between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The doping concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or it may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The elements that act as acceptors are not limited to the examples described above. The collector region 22 is exposed to the lower surface 23 of the semiconductor substrate 10 and is connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. As described above, if a diode region is provided in the active region 160, an N+ type cathode region may be provided in the diode region instead of the collector region 22.

[0065] An N+ type buffer region 20 may be provided between the drift region 18 and the collector region 22. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may have one or more concentration peaks with higher doping concentrations than the drift region 18. The doping concentration of a concentration peak refers to the doping concentration at the peak of the concentration peak. In addition, the doping concentration in the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat.

[0066] The buffer region 20 may be formed by ion implantation of an n-type dopant such as hydrogen (proton) or phosphorus. In this example, the buffer region 20 is formed by ion implantation of hydrogen. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22.

[0067] Figure 4 is an enlarged view of a cross-section near the mesa portion 60. As described above, the mesa portion 60 is provided with an emitter region 12, a trench contact portion 210, a contact insulating film 86, a bottom region 87, and a base region 14. Below the base region 14 in the mesa portion 60, an N-type drift region 18 may be provided, and an n-type accumulation region 232 with a higher concentration than the drift region 18 may be provided.

[0068] The trench contact portion 210 is provided in the mesa portion 60 from the upper surface 21 of the semiconductor substrate 10 to the interior. In this example, the trench contact portion 210 is a plug formed of a conductive material such as tungsten. The trench contact portion 210 may be formed of a different material from the emitter electrode 52. The depth position of the boundary between the trench contact portion 210 and the emitter electrode 52 (i.e., the position in the Z-axis direction) may or may not coincide with the upper surface 21 of the semiconductor substrate 10.

[0069] The trench contact portion 210 has a bottom portion 212 and a side wall 214. The bottom portion 212 is the lowest part of the trench contact portion 210. The bottom portion 212 may be a plane parallel to the XY plane. The bottom portion 212 may be a portion of the trench contact portion 210 that is within a predetermined distance in the depth direction from the lowest part. This predetermined distance may be 0.1 μm, 0.2 μm, or 0.5 μm. The side wall 214 is the portion of the boundary of the trench contact portion 210 in the XZ cross section that extends from the bottom portion 212 to the upper surface 21 of the semiconductor substrate 10. The side wall 214 may extend in a direction parallel to the depth direction in the XZ cross section, or it may extend in a direction intersecting the depth direction. The side wall 214 may have a step shape in which the inclination changes discontinuously in the XZ cross section. In other examples, the inclination of the side wall 214 may change continuously in the XZ cross section.

[0070] A p-type region is provided below the trench contact portion 210. The trench contact portion 210 is in contact with this p-type region. In this example, a bottom region 87 is provided below the trench contact portion 210. The bottom region 87 is a p-type region with a higher concentration than the base region 14. The bottom region 87 is in contact with the conductive material of the base region 14 and the trench contact portion 210. The base region 14 may be provided instead of the bottom region 87.

[0071] The emitter region 12 in this example has a first emitter portion 81 and a second emitter portion 82. The emitter region 12 may further have a third emitter portion 83. The first emitter portion 81 is an n-type region provided in the mesa portion 60 between the side wall 214 of the trench contact portion 210 and the trench portion. The first emitter portion 81 in this example is an N+-type region with a higher concentration than the drift region 18. The first emitter portion 81 is connected to at least one of the emitter electrode 52 and the trench contact portion 210. In the example of Figure 4, the first emitter portion 81 is connected to both the emitter electrode 52 and the trench contact portion 210. The first emitter portion 81 may be in contact with the side surface of the gate trench portion 40.

[0072] The second emitter portion 82 is located below the first emitter portion 81 between the side wall 214 of the trench contact portion 210 and the trench portion. In this example, the second emitter portion 82 is an N-type region with a lower doping concentration than the first emitter portion 81. The second emitter portion 82 is located in contact with the first emitter portion 81. The second emitter portion 82 may be in contact with the side surface of the gate trench portion 40. In this example, the second emitter portion 82 is not in contact with the emitter electrode 52.

[0073] The contact insulating film 86 is provided between the side wall 214 of the trench contact portion 210 and the second emitter portion 82. The contact insulating film 86 may also be provided between the side wall 214 of the trench contact portion 210 and the third emitter portion 83, which will be described later. In this example, the contact insulating film 86 is in contact with the side wall 214 of the trench contact portion 210. The contact insulating film 86 may be an insulating film formed by oxidizing or nitriding the semiconductor substrate 10 at the position in contact with the side wall 214, or it may be a deposited film deposited at the position in contact with the side wall 214. In this example, the contact insulating film 86 is a high-temperature oxide film (HTO) such as silicon, but is not limited thereto.

[0074] In this example, the contact insulating film 86 is provided so as to cover the entire side surface of the second emitter portion 82 facing the side wall 214 in the X-axis direction. In other words, the second emitter portion 82 is not in contact with the trench contact portion 210. Similarly, the contact insulating film 86 is provided so as to cover the entire side surface of the third emitter portion 83 facing the side wall 214 in the X-axis direction. In other words, the third emitter portion 83 is not in contact with the trench contact portion 210.

[0075] The contact insulating film 86 is not provided on at least a portion of the bottom surface 212 of the trench contact portion 210. As a result, the trench contact portion 210 contacts a p-shaped region such as the bottom region 87 or the base region 14.

[0076] The first emitter portion 81 has a region that does not face the contact insulating film 86 in the X-axis direction. In other words, the contact insulating film 86 is not provided on at least a portion of the side surface of the first emitter portion 81 that faces the side wall 214 in the X-axis direction. The contact insulating film 86 does not need to be provided in the entire region between the side wall 214 and the first emitter portion 81. In this example, the first emitter portion 81 is in contact with the side wall 214 of the trench contact portion 210. The entire side surface of the first emitter portion 81 may be in contact with the side wall 214.

[0077] By providing the contact insulating film 86, the entire current flowing between the second emitter portion 82 and the emitter electrode 52 passes through the first emitter portion 81. Also, the entire current flowing between the first emitter portion 81 and the base region 14 passes through the second emitter portion 82.

[0078] In this example, the doping concentration of the second emitter portion 82 is lower than that of the first emitter portion 81. This results in a higher resistance value for the second emitter portion 82. Also, the current flowing between the first emitter portion 81 and the base region 14 passes through the second emitter portion 82. Therefore, by providing the second emitter portion 82, the resistance of the emitter region 12 can be increased.

[0079] By increasing the resistance of the emitter region 12, a relatively low saturation current and a relatively low on-voltage can be achieved simultaneously. The MOS structure provided on the upper surface 21 of the semiconductor substrate 10 has a saturation characteristic in which the collector current saturates even when the collector-emitter voltage is increased. As a result, the semiconductor device 100 has a short-circuit withstand characteristic in which the element will not be destroyed within a certain period of time in a short-circuit state where a large current and a large voltage are applied simultaneously. As the miniaturization of the device progresses, if a MOS structure is formed on all mesa portions 60, the saturation current becomes very large. Therefore, a decimation structure in which a MOS structure is not formed on some mesa portions 60, or a ladder structure in which emitter regions 12 having a longitudinal length in the X-axis direction are discretely arranged in the Y-axis direction may be used to suppress the saturation current. However, if the saturation current is suppressed with such a structure, the on-voltage becomes high.

[0080] The current saturation characteristic of the MOS structure is expressed by the following equation (1).

number

[0081] The channel resistance Rch of a MOS structure is given by equation (2) below.

number

[0082] In contrast, the semiconductor device 100 suppresses saturation current by providing a second emitter portion 82. When the semiconductor device 100 is turned on, current flows between the emitter electrode 52 and the emitter region 12 through the second emitter portion 82. Therefore, the potential of the emitter region 12 changes according to the magnitude of the current flowing through the second emitter portion 82. Since current flows from the emitter region 12 to the emitter electrode 52, if the current flowing through the second emitter portion 82 is large, the potential of the emitter region 12 becomes higher. If the current flowing through the second emitter portion 82 is small, the potential of the emitter region 12 rises only slightly.

[0083] Since the on-voltage applied to the gate conductive portion 44 is approximately constant, when the current flowing through the second emitter portion 82 increases, the potential difference between the gate conductive portion 44 and the emitter region 12 decreases, and the voltage applied to the gate insulating film 42 decreases. On the other hand, when the current flowing through the second emitter portion 82 is small, the voltage applied to the gate insulating film 42 becomes relatively large. Therefore, the saturation current flowing through the MOS structure can be suppressed.

[0084] In the semiconductor device 100, by providing an emitter region 12 having a longitudinal length in the Y-axis direction, the total emitter width Z can be increased, thereby reducing the on-voltage. This makes it possible to achieve both a low saturation current and a low on-voltage.

[0085] The lower end of the trench contact portion 210 is in contact with a p-type bottom region 87. The bottom region 87 can be formed by injecting p-type dopant ions into the trench from above after forming the trench for the trench contact portion 210. The bottom region 87 may be a P+-type region with a higher concentration than the base region 14. The doping concentration of the bottom region 87 may be twice or more, five times or more, ten times or more, fifty times or more, or even one hundred times or more, the doping concentration of the base region 14.

[0086] The trench contact portion 210 is provided from the upper surface 21 of the semiconductor substrate 10 to a depth greater than the lower end of the second emitter portion 82. The bottom region 87 is in contact with the base region 14. By providing a high-density bottom region 87, the contact resistance between the trench contact portion 210 and the base region 14 can be reduced.

[0087] The third emitter portion 83 is located below the second emitter portion 82, between the side wall 214 of the trench contact portion 210 and the trench portion. The third emitter portion 83 is an N-type region with a higher doping concentration than the second emitter portion 82. The third emitter portion 83 is located in contact with the second emitter portion 82. The doping concentration of the third emitter portion 83 may be lower than that of the first emitter portion 81. The third emitter portion 83 may be in contact with the side surface of the trench portion. In this example, the third emitter portion 83 is not in contact with the emitter electrode 52.

[0088] By providing the third emitter portion 83, it is possible to prevent the second emitter portion 82 from directly contacting the base region 14. Therefore, diffusion of the dopant in the base region 14 into the low-concentration second emitter portion 82 can be suppressed, and the length of the second emitter portion 82 in the depth direction can be precisely controlled. As a result, variations in the resistance value in the second emitter portion 82 can be suppressed.

[0089] In this example, the contact insulating film 86 is also provided between the side wall 214 of the trench contact portion 210 and the third emitter portion 83. As a result, the third emitter portion 83 is not in contact with the trench contact portion 210.

[0090] The upper end 84 of the gate conductive portion 44 of the gate trench portion 40 is preferably positioned facing the third emitter portion 83 in the X-axis direction. The upper end 84 of the gate conductive portion 44 may refer to the upper end of the side wall of the gate conductive portion 44. Facing the upper end 84 means that the upper end 84 is positioned between the upper end position and the lower end position of the third emitter portion 83 in the Z-axis direction. The upper and lower ends of the third emitter portion 83 may refer to the upper and lower ends of the portion in contact with the side wall of the gate trench portion 40.

[0091] When an ON voltage is applied to the gate conductive portion 44, electrons are attracted to the region of the boundary between the mesa portion 60 and the trench portion that faces the gate conductive portion 44. When the second emitter portion 82 and the gate conductive portion 44 are arranged facing each other, electrons are also attracted to the boundary portion of the second emitter portion 82. Since the doping concentration of the second emitter portion 82 is low, the resistance value at the boundary portion may fluctuate due to the attracted electrons. In contrast, by arranging the third emitter portion 83 to face the upper end 84 of the gate conductive portion 44, fluctuations in the resistance value at the boundary portion of the second emitter portion 82 can be suppressed. Furthermore, since the doping concentration of the third emitter portion 83 is high, even if electrons are attracted to the boundary portion of the third emitter portion 83, the fluctuation in the resistance value at that boundary portion is very small.

[0092] Each mesa portion 60 is provided with a P-type base region 14. The base region 14 is in contact with the gate trench portion 40. The base region 14 may also be in contact with each of the trench portions on both sides of the mesa portion 60. At least a portion of the base region 14 is provided below the emitter region 12. The base region 14 may also be in contact with the emitter region 12. When a predetermined ON voltage is applied to the gate trench portion 40, the surface layer of the base region 14 in contact with the gate trench portion 40 inverts into an n-type region, forming a channel. This channel electrically connects the emitter region 12 to the drift region 18, which will be described later.

[0093] The base region 14 is also provided below the trench contact portion 210. The base region 14 may be in contact with the trench contact portion 210, or it may be in contact with the bottom region 87. The doping concentration of the base region 14 is 5.0 × 10⁻¹⁴. 16 atoms / cm 3 The above is 1.0 × 10 18 atoms / cm 3 The following is acceptable:

[0094] In this example, by providing a contact insulating film 86 on the side wall 214 of the trench contact portion 210, the resistance value in the emitter region 12 can be controlled with high precision. For example, by providing a p-type region instead of the contact insulating film 86, the current path in the emitter region 12 can be restricted and the resistance value in the emitter region 12 can be controlled. However, the resistance value in the emitter region 12 will vary depending on variations in the doping concentration of the p-type region. In this example, by providing the contact insulating film 86, the current path in the emitter region 12 can be restricted with high precision.

[0095] Figure 5 shows an example of the doping concentration distribution along the hh line in Figure 4. The hh line is a line parallel to the Z-axis that passes through the first emitter portion 81, the second emitter portion 82, and the third emitter portion 83.

[0096] In this example, the first emitter portion 81 has a peak 91 in the doping concentration distribution in the depth direction. A peak in the doping concentration distribution is a mountain-shaped portion that shows a maximum value at its apex. The doping concentration at the apex of the peak is defined as the doping concentration of that peak. The doping concentration of peak 91 is defined as P1. In addition, the doping concentration of the first emitter portion 81 may continue to increase from the boundary with the second emitter portion 82 to the upper surface 21 of the semiconductor substrate 10. In this case, the doping concentration of the first emitter portion 81 at the upper surface 21 is defined as P1.

[0097] In this example, the second emitter portion 82 has a peak 92 in the doping concentration distribution in the depth direction. Let P2 be the doping concentration at peak 92. Between the first emitter portion 81 and the second emitter portion 82, a valley 94 where the doping concentration shows a minimum value is defined as the boundary between the first emitter portion 81 and the second emitter portion 82.

[0098] In this example, the third emitter portion 83 has a peak 93 in the doping concentration distribution in the depth direction. The doping concentration at peak 93 is denoted as P3. Between the second emitter portion 82 and the third emitter portion 83, a valley 95 where the doping concentration shows a minimum value is defined as the boundary between the second emitter portion 82 and the third emitter portion 83.

[0099] As described above, the concentration P2 of peak 92 in the second emitter portion 82 is lower than the concentration P1 of peak 91 in the first emitter portion 81. The concentration P2 may be 1 / 100th or less of the concentration P1, or 1 / 1000th or less. The concentration P2 may be 10 times or less of the doping concentration in the valley 94, or 5 times or less. The concentration P2 is higher than the doping concentration in the drift region 18. The concentration P2 may be 100 times or less of the doping concentration in the drift region 18, or 10 times or less, or 5 times or less. By adjusting the concentration P2, the resistance value in the emitter region 12 can be adjusted.

[0100] The length of the second emitter portion 82 in the depth direction may be 2 μm or less. This length may be 1.5 μm or less, or 1 μm or less. This length may be 0.1 μm or more, or 0.5 μm or more. The overall length of the emitter region 12 in the depth direction may be 3 μm or less.

[0101] In this example, the emitter region 12 can be formed by implanting n-type dopant ions at the positions of peaks 91, 92, and 93, respectively. The length of the second emitter portion 82 can be adjusted by the depth at which peaks 91 and 93 are formed. By adjusting the length of the second emitter portion 82, the resistance value in the emitter region 12 can be adjusted.

[0102] As described above, the concentration P3 of peak 93 in the third emitter portion 83 is higher than the concentration P2 of peak 92 in the second emitter portion 82. The concentration P3 may be 10 times or more, 50 times or more, or 100 times or more than the concentration P2. The concentration P3 of peak 93 in the third emitter portion 83 may be less than or equal to the concentration P1 of peak 91 in the first emitter portion 81. The concentration P3 may be 1 / 2 times or less, 1 / 5 times or less, or 1 / 10 times or less of the concentration P1.

[0103] As explained in Figure 4, the depth position of the upper end 84 of the gate conductive portion 44 is included in the depth range in which the third emitter portion 83 is provided. The upper end 84 may be provided within the range of the full width at half maximum of the peak 93. The range of the full width at half maximum of the peak 93 is the range in which the doping concentration at peak 93 is half or more of P3.

[0104] The length of the third emitter portion 83 in the depth direction may be 0.4 μm or more. This allows the upper end 84 of the gate conductive portion 44 to be positioned opposite the third emitter portion 83 even if the depth position of the upper end 84 of the gate conductive portion 44 fluctuates due to manufacturing variations, etc. The length of the third emitter portion 83 in the depth direction may be 1 μm or less. The third emitter portion 83 only needs to be able to absorb variations in the depth position of the upper end 84. By making the length of the third emitter portion 83 1 μm or less, the total length of the emitter region 12 can be reduced.

[0105] Figure 6 shows another example of the doping concentration distribution in the hh line. In this example, the doping concentration distribution in the second emitter portion 82 differs from that of the example in Figure 6. The distributions in the first emitter portion 81 and the third emitter portion 83 are the same as those in the example in Figure 5.

[0106] The second emitter portion 82 in this example has a flat portion 96 in which the doping concentration distribution in the depth direction is flat. For example, the flat portion 96 is the portion in which the maximum doping concentration is less than or equal to twice the minimum doping concentration. The length of the flat portion 96 in the depth direction may be 0.1 μm or more, or 0.5 μm or more.

[0107] The minimum doping concentration in the flat portion 96 may be 10 times or less, 5 times or less, or 2 times or less of the doping concentration Dd. The minimum doping concentration in the flat portion 96 may also be the same as the doping concentration Dd in the drift region 18. In this example, n-type dopant ions are not implanted in the second emitter portion 82.

[0108] Figure 7 shows another example of the doping concentration distribution in the hh line. In this example, the doping concentration distribution in the second emitter portion 82 differs from that in the example in Figure 5. The distributions in the first emitter portion 81 and the third emitter portion 83 are the same as in the example in Figure 5.

[0109] In this example, the second emitter portion 82 has a valley 97 in which the doping concentration shows a minimum value in the depth direction. The minimum value of the doping concentration in the valley 97 is denoted as V1. The concentration V1 may be 100 times or less, 50 times or less, 10 times or less, or 5 times or less, the doping concentration Dd in the drift region 18. The concentration V1 may also be the same as the concentration Dd. In this example, n-type dopant ions are not implanted into the second emitter portion 82. The valley 97 near the boundary between the first peak 91 and the third peak 93 functions as the second emitter portion 82.

[0110] Let Db be the doping concentration at both ends of the second emitter portion 82 in the depth direction. The concentration Db may be 10 times, 5 times, or any other value of the concentration V1. The length of the second emitter portion 82 in the depth direction is the same as in the example in Figure 5 or Figure 6.

[0111] The second emitter portion 82 has one of the peaks 92 shown in Figure 5, the flat portion 96 shown in Figure 6, and the trough portion 97 shown in Figure 7. The second emitter portion 82 may have more than one of the peaks 92, flat portion 96, and trough portion 97.

[0112] Figures 8 and 9 show some of the steps in the manufacturing process of the semiconductor device 100. Figures 8 and 9 show the steps for forming the trench contact portion 210, the contact insulating film 86, and the bottom region 87.

[0113] In step S410 of this example, a gate trench 40, a mesa 60, a bottom region 87, a storage region 232, a lower end region 230, an emitter region 12, and a base region 14 are formed on the semiconductor substrate 10. Also in S410, a contact trench 220 for forming a trench contact portion 210 is formed in the mesa 60. In S410, the contact trench 220 may be formed by anisotropic etching or by isotropic etching. Before forming the contact trench 220, each part of the emitter region 12 may be provided across the entire mesa 60 in the X-axis direction. In other examples, each part of the emitter region 12 may be formed after the contact trench 220 has been formed.

[0114] The contact trench 220 has side walls 216 and a bottom surface 213. The bottom surface 213 is the surface that includes the lower end of the contact trench 220. The bottom surface 213 may be a surface parallel to the XY plane. In other examples, the bottom surface 213 may be the portion of the surface of the contact trench 220 whose distance in the Z-axis direction from the lower end of the contact trench 220 is within a predetermined value. This predetermined value may be, for example, 0.1 μm, 0.2 μm, or 0.5 μm.

[0115] The side wall 216 is the portion of the contact trench 220 that extends from the bottom surface 213 to the top surface 21 of the semiconductor substrate 10. At least a portion of the side wall 216 may be provided parallel to the Z-axis direction, or it may be provided at an angle.

[0116] The side wall 216 exposes each part of the emitter region 12. In Figure 8, the side wall 216 exposes the first emitter portion 81, the second emitter portion 82, and the third emitter portion 83.

[0117] In this example, the bottom region 87 is exposed on the bottom surface 213. The bottom region 87 may be exposed over the entire bottom surface 213. After forming the contact trench 220 and before forming the contact insulating film 86, a p-type dopant may be injected into the bottom surface 213 of the contact trench 220 to form the bottom region 87. If the bottom region 87 is not provided, the base region 14 may be exposed on the bottom surface 213.

[0118] In step S420, a contact insulating film 86 is formed on the side walls 216 and bottom surface 213 of the contact trench 220. The contact insulating film 86 may cover the entire side walls 216 and the entire bottom surface 213. In S420, a contact insulating film 86 may also be formed on the top surface 21 of the semiconductor substrate 10. The contact insulating film 86 may be formed by CVD, or by other methods.

[0119] In step S420, the contact insulating film 86 may be formed such that a portion of the contact trench 220 is not filled with the contact insulating film 86. As shown in Figure 8, a recess may be provided on the upper surface of the contact insulating film 86 formed in S420 that extends into the interior of the contact trench 220. This recess can be formed by adjusting the thickness of the contact insulating film 86.

[0120] In step S430, a portion of the contact insulating film 86 is etched to expose the first emitter portion 81 on the side wall 216 of the contact trench 220. After etching, a portion of the side surface of the first emitter portion 81 may be covered by the contact insulating film 86, or the entire side surface of the first emitter portion 81 may be exposed on the side wall 216. After etching the contact insulating film 86 in S430, the contact insulating film 86 covers the entire side surface of the second emitter portion 82. In this example, after etching the contact insulating film 86, the contact insulating film 86 also covers the entire side surface of the third emitter portion 83. In S430, the contact insulating film 86 may be etched in such a way that the bottom surface 213 of the contact trench 220 is not exposed. In other examples, after etching in S430, at least a portion of the bottom surface 213 may be exposed without being covered by the contact insulating film 86. In this example, steps S440 and S450, described later, do not need to be performed.

[0121] In S430, the contact insulating film 86 on the upper surface 21 of the semiconductor substrate 10 is etched by anisotropic etching. In other words, in S430, the entire contact insulating film 86 is etched from the upper surface 21 side of the semiconductor substrate 10. Because the thickness of the contact insulating film 86 covering the side wall 216 is large in the Z-axis direction, even if the entire contact insulating film 86 is etched by anisotropic etching, some of the contact insulating film 86 remains on the side wall 216. In S430, etching conditions such as etching time are adjusted so that the second emitter portion 82 is not exposed.

[0122] In step S440 of Figure 9, a mask 240 is formed that covers the upper surface 21 of the semiconductor substrate 10 and the contact insulating film 86 provided on the side wall of the contact trench 220. The mask 240 is, for example, a photosensitive resist. The mask 240 may cover at least the upper end of the contact insulating film 86 provided on the side wall 216. The mask 240 does not cover at least a portion of the contact insulating film 86 provided on the bottom surface 213.

[0123] In step S450, after forming the mask 240, the contact insulating film 86 provided on the bottom surface 213 of the contact trench 220 is etched. The contact insulating film 86 on the bottom surface 213 may be etched by anisotropic etching. The etching process from S430 to S450 allows the contact insulating film 86 covering the second emitter portion 82 and the third emitter portion 83 on the side wall 216 to remain while exposing a p-type region (bottom region 87 or base region 14) on the bottom surface 213. In S450, after etching the contact insulating film 86 on the bottom surface 213, the mask 240 is removed.

[0124] In step S460, a conductive material is filled into the contact trench 220, bringing the conductive material into contact with the first emitter portion 81 and the p-type region (bottom region 87 or base region 14). This forms a trench contact portion 210 that is in contact with the first emitter portion 81 and the p-type region, and is insulated from the second emitter portion 82 and the third emitter portion 83 by the contact insulating film 86. As mentioned above, the conductive material is, for example, tungsten. The conductive material may be formed by sputtering or the like.

[0125] As shown in Figure 4, after filling the contact trench 220 with conductive material in S460, the thickness of the contact insulating film 86 remaining inside the contact trench 220 in the X-axis direction is denoted as W1, and the thickness of the conductive material in the X-axis direction is denoted as W2. Thickness W1 may be the maximum thickness of the contact insulating film 86, or the thickness at the center of the contact insulating film 86 in the Z-axis direction. Thickness W2 may be the maximum thickness of the conductive material sandwiched between the contact insulating film 86, or the thickness at the center of the conductive material sandwiched between the contact insulating film 86 in the Z-axis direction. In addition, in the trench portion, the thickness of the in-trench insulating film covering the inner wall of the trench portion in the X-axis direction is denoted as W3. In this example, the gate insulating film 42 of the gate trench portion 40 corresponds to the in-trench insulating film. Thickness W3 may be the maximum thickness of the gate insulating film 42 sandwiched between the gate conductive portion 44 and the semiconductor substrate 10, or the thickness at the center of the gate insulating film 42 sandwiched between the gate conductive portion 44 and the semiconductor substrate 10 in the Z-axis direction. Let W4 be the opening width in the X-axis direction of the trench contact portion 210 on the upper surface 21 of the semiconductor substrate 10 (i.e., the opening width of the contact trench 220 formed with S410). The opening width W4 may be the maximum value of the opening width in the X-axis direction of the trench contact portion 210 (or contact trench 220). Let Z1 be the depth of the trench contact portion 210. The depth Z1 is the distance in the Z-axis direction from the upper surface 21 of the semiconductor substrate 10 to the lowest end of the trench contact portion 210.

[0126] The thickness W1 of the contact insulating film 86 may be less than the depth Z1 of the trench contact portion 210. If the thickness W1 is too large, it becomes difficult to form a depression on the upper surface of the contact insulating film 86, as shown in S420 in Figure 8. Therefore, in etching in S430, it becomes difficult to leave the contact insulating film 86 on the side wall 216 of the contact trench 220. The thickness W1 may be half or less of the depth Z1, or even one-quarter or less.

[0127] The thickness W2 of the conductive material may be greater than the thickness W1 of the contact insulating film 86. The thickness W2 of the conductive material may be twice or more the thickness W1 of the contact insulating film 86, and may also be four times or more.

[0128] The thickness W1 of the contact insulating film 86 may be thinner than the thickness W3 of the trench insulating film (e.g., gate insulating film 42). The thickness W1 may be 0.8 times or less of the thickness W3, or 0.5 times or less. The contact insulating film 86 and the trench insulating film may be insulating films formed from different materials or by different methods. For example, the contact insulating film 86 may be a high-temperature oxide film (HTO) formed by the CVD method, and the trench insulating film may be a thermal oxide film obtained by thermal oxidation of the semiconductor substrate 10. The contact insulating film 86 and the interlayer insulating film 38 may be insulating films formed from different materials or by different methods. For example, the interlayer insulating film 38 may be a BPSG film or a BSG film. The thickness W1 of the contact insulating film 86 may be less than the maximum thickness of the interlayer insulating film 38 in the Z-axis direction.

[0129] The opening width W4 of the contact trench 220 may be 0.8 μm or more and 2 μm or less. The opening width W4 may be 1 μm or more and 1.2 μm or more. The opening width W4 may be 1.8 μm or less and 1.6 μm or less.

[0130] The thickness W1 of the contact insulating film 86 after etching in S450 may be 0.3 μm or more and 0.7 μm or less. The thickness W1 may be 0.35 μm or more and 0.4 μm or more. The thickness W1 may be 0.65 μm or less and 0.6 μm or less.

[0131] The depth Z1 of the trench contact portion 210 may be 0.8 μm or more and 2 μm or less. The depth Z1 may be 1 μm or more and 1.2 μm or more. The depth Z1 may be 1.8 μm or less and 1.6 μm or less.

[0132] The thickness of the first emitter portion 81 in the Z-axis direction at the position in contact with the gate trench portion 40 may be 0.05 μm or more and 1 μm or less. This thickness may be 0.1 μm or more. This thickness may be 0.5 μm or less.

[0133] The thickness of the second emitter portion 82 in the Z-axis direction at the position in contact with the gate trench portion 40 may be 0.05 μm or more and 1 μm or less. The thickness may be 0.1 μm or more. The thickness may be 0.5 μm or less.

[0134] The thickness of the third emitter portion 83 in the Z-axis direction at the position in contact with the gate trench portion 40 may be 0.2 μm or more and 2 μm or less. The thickness may be 0.5 μm or more. The thickness may be 1.5 μm or less.

[0135] In the examples shown in Figures 8 and 9, the bottom region 87 is formed in S420. In other examples, after etching the contact insulating film 86 on the bottom surface 213 in S450, and before filling with conductive material in S460, a p-type dopant may be injected into the bottom surface 213 of the contact trench 220 to form the bottom region 87. In this case, etching of the bottom region 87 during the etching process of the contact insulating film 86 on the bottom surface 213 can be prevented. Therefore, the bottom region 87 can be formed with high precision.

[0136] The angle between the side wall 216 of the contact trench 200 formed in S410 and the Z-axis direction may be less than 5 degrees. This angle may also be less than 3 degrees. The angle of the side wall 216 may be the value of the center of the side wall 216 in the Z-axis direction. By reducing the angle between the side wall 216 and the Z-axis direction, when etching the contact insulating film 86 in S430, it becomes easier to remove the contact insulating film 86 on the upper side of the side wall 216 while leaving the contact insulating film 86 on the lower side.

[0137] Figure 10 shows an example of the collector voltage-collector current characteristics of the semiconductor device 100. Figure 10 shows multiple examples of characteristics for an embodiment in which the contact insulating film 86 described in Figures 1 to 9 is provided, and multiple examples of characteristics for a comparative example in which a p-type region is provided instead of the contact insulating film 86. In the comparative example, the side walls of the contact trench 220 were formed parallel to the depth direction, and the p-type region was formed by injecting p-type dopant ions parallel to the depth direction.

[0138] In Figure 10, the characteristics of the comparative example are shown with a dashed line, and the characteristics of the embodiment are shown with a solid line. As shown in Figure 10, in the comparative example, the variation in the collector current saturation current Vr is large. In contrast, in the embodiment, the variation in the collector current saturation current Ve is small. In the embodiment, the current path in the emitter region 12 is precisely restricted, which is considered to be the reason why the variation in saturation current Ve is small.

[0139] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0140] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0141] 10...Semiconductor substrate, 11...p-type outer well region, 12...Emitter region, 14...Base region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 38...Interlayer insulating film, 40...Gate trench region, 42...Gate insulating film, 44...Gate conductive region, 52...Emitter electrode, 60...Mesa region, 70...Transistor region, 81...First emitter portion, 82...Second emitter portion, 83...Third emitter portion, 84...Upper end, 86 ...Contact insulating film, 87...Bottom region, 90...Edge termination structure, 91, 92, 93...Peak, 94, 95...Valley, 96...Flat portion, 97...Valley, 100...Semiconductor device, 130...Gate wiring, 160...Active portion, 161...First edge, 162...Second edge, 164...Gate pad, 210...Trench contact portion, 212...Bottom, 213...Bottom surface, 214...Side wall, 216...Side wall, 220...Contact trench, 230...Lower end region, 240...Mask

Claims

1. A method for manufacturing a semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a first conductivity type drift region, The semiconductor device comprises a plurality of trenches provided from the upper surface to the interior of the semiconductor substrate, a mesa portion sandwiched between two of the trenches in the semiconductor substrate, a trench contact portion provided in the mesa portion from the upper surface to the interior of the semiconductor substrate, a first emitter portion of a first conductivity type provided between the side wall of the trench contact portion and the trenches in the mesa portion, a second emitter portion of a first conductivity type having a lower doping concentration than the first emitter portion and provided below the first emitter portion between the side wall of the trench contact portion and the trenches, a region of a second conductivity type provided below the trench contact portion, and a contact insulating film provided between the side wall of the trench contact portion and the second emitter portion. The aforementioned manufacturing method is A contact trench is formed in the mesa portion for forming the trench contact portion. The contact insulating film is formed on the side walls and bottom surface of the contact trench. A portion of the contact insulating film is etched to expose the first emitter portion on the side wall of the contact trench, and the region of the second conductivity type is exposed on the bottom surface of the contact trench. A conductive material is filled into the contact trench, and the conductive material is brought into contact with the first emitter portion and the second conductivity region. Manufacturing method.

2. The contact insulating film is also formed on the upper surface of the semiconductor substrate. The contact insulating film on the upper surface of the semiconductor substrate is etched by anisotropic etching. A mask is formed that covers the upper surface of the semiconductor substrate and the contact insulating film provided on the side wall of the contact trench. Etching the contact insulating film provided on the bottom surface of the contact trench. The manufacturing method according to claim 1.

3. After etching the contact insulating film, the contact insulating film covers the entire side surface of the second emitter portion. The manufacturing method according to claim 1.

4. The semiconductor device further comprises a third emitter portion of a first conductivity type having a higher doping concentration than the second emitter portion, located below the second emitter portion between the side wall of the trench contact portion and the trench portion. After etching the contact insulating film, the contact insulating film covers the entire side surface of the third emitter portion. The manufacturing method according to claim 3.

5. The thickness of the contact insulating film is smaller than the depth of the trench contact portion. The manufacturing method according to any one of claims 1 to 4.

6. After filling with the conductive material, the thickness of the conductive material and the contact insulating film remaining inside the contact trench in the first direction parallel to the upper surface of the semiconductor substrate is greater for the conductive material. The manufacturing method according to any one of claims 1 to 4.

7. The thickness of the conductive material is at least twice the thickness of the contact insulating film. The manufacturing method according to claim 6.

8. The trench portion has an in-trench insulating film covering the inner wall of the trench portion. The contact insulating film is thinner than the trench insulating film. The manufacturing method according to any one of claims 1 to 4.

9. The semiconductor device further comprises a second conductivity type base region provided in contact with the trench portion, The second conductivity type region is in contact with the base region and the conductive material, and has a higher concentration than the base region. In the above manufacturing method, After forming the contact trench and before forming the contact insulating film, a second conductivity type dopant is injected into the bottom surface of the contact trench to form the second conductivity type region. The manufacturing method according to any one of claims 1 to 4.

10. The semiconductor device further comprises a second conductivity type base region provided in contact with the trench portion, The second conductivity type region is in contact with the base region and the conductive material, and has a higher concentration than the base region. In the above manufacturing method, After etching the contact insulating film and before filling with the conductive material, a second conductivity type dopant is injected into the bottom surface of the contact trench to form a region of the second conductivity type. The manufacturing method according to any one of claims 1 to 4.

11. The opening width of the contact trench on the upper surface of the semiconductor substrate is 0.8 μm or more and 2 μm or less. The thickness of the contact insulating film after etching is 0.3 μm or more and 0.7 μm or less. The manufacturing method according to any one of claims 1 to 4.

12. The semiconductor substrate is a wide-bandgap substrate formed from a material with a larger bandgap than silicon. The manufacturing method according to any one of claims 1 to 4.

13. The angle between the side wall of the contact trench and the depth direction is less than 5 degrees. The manufacturing method according to any one of claims 1 to 4.

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