Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor 1 that can suppress the failure rate. [Solution] In the multilayer ceramic capacitor 1, in the cross section in the length direction L and the stacking direction T of the center 113 in the width direction, the length dimension of the inner layer 10 is larger than the length dimension of the outer layer 11, and in the cross section in the length direction L and the stacking direction T of the center 113 in the width direction, the length dimension of the inner layer 10 at the center 111 in the stacking direction is larger than the length dimension of the inner layer 10 at the end of the stacking direction, and at the first end face 7 or the second end face 8, there is a recess 270 near the boundary between the outer layer 11 and the inner layer 10 that is recessed more than the inner layer 10 and the outer layer 11.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] A multilayer ceramic capacitor is one of the important components constituting an electronic device, and there is a demand for a highly reliable multilayer ceramic capacitor in the market. Patent Document 1 discloses a multilayer ceramic capacitor capable of reducing the failure rate of a multilayer ceramic capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, usually, the thickness of the external electrode becomes thinner as it approaches the corner portion of the inner layer portion, that is, the end portion in the stacking direction. Therefore, in a multilayer ceramic capacitor with a protruding inner layer portion as in Patent Document 1, in the internal electrode layer near the main surface, the distance from the external electrode surface to the end face exposed portion of the internal electrode layer tends to be short. For this reason, in a conventional multilayer ceramic capacitor, the moisture resistance reliability at the corner portion of the inner layer portion deteriorates, and the failure rate may increase.

[0005] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the failure rate.

Means for Solving the Problems

[0006] The multilayer ceramic capacitor of the present invention comprises a laminate having an inner layer having a dielectric layer and an internal electrode layer stacked in the stacking direction, and an outer layer provided so as to sandwich the inner layer in the stacking direction, and including a first main surface and a second main surface facing the stacking direction, a first side surface and a second side surface facing the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing the length direction perpendicular to the stacking direction and the width direction, and an external electrode provided on the first end surface and the second end surface and connected to the internal electrode layer The inner layer comprises, in a cross-section in the length direction and stacking direction at the center of the width direction, the length dimension of the inner layer is greater than the length dimension of the outer layer, and in a cross-section in the length direction and stacking direction at the center of the width direction, the length dimension of the inner layer at the center of the stacking direction is greater than the length dimension of the inner layer at the end of the stacking direction, and the first end face or the second end face has a recess near the boundary between the outer layer and the inner layer that is more recessed than the inner layer and the outer layer. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the failure rate. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is an external perspective view of a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. [Figure 4] Figure 4 is a cross-sectional view taken along line 103-103 in Figure 1. [Figure 5] Figure 5 corresponds to the cross-sectional view along line 101-101 in Figure 1. [Figure 6] Figure 6 is an enlarged view of the framed area 220 in Figure 5. [Figure 7] Figure 7 corresponds to the cross-sectional view along line 101-101 in Figure 1. [Modes for carrying out the invention]

[0009] (Multilayer ceramic capacitor) Referring to the drawings, a multilayer ceramic capacitor 1, which is one embodiment of the present disclosure, will be described. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of the embodiment of the present disclosure.

[0010] As shown in Figure 1, the shape of the multilayer ceramic capacitor 1 is approximately a rectangular parallelepiped. The multilayer ceramic capacitor 1 consists of a laminate 2 and external electrodes 40. The shape of the laminate 2 is approximately a rectangular parallelepiped.

[0011] The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrodes 40 are positioned at opposite ends of the laminate 2, separated from each other. The external electrode 40 positioned at one end is the first external electrode 41. The external electrode 40 positioned at the other end is the second external electrode 42.

[0012] (Laminated structure) The laminate 2 will be described with reference to Figure 1, as well as Figures 2, 3, and 4. Figure 2 is a cross-sectional view taken from 101-101 in Figure 1. Figure 3 is a cross-sectional view taken from 102-102 in Figure 1. Figure 3 shows the first internal electrode layer 31. Figure 4 is a cross-sectional view taken from 103-103 in Figure 1.

[0013] As shown in Figure 2, the laminate 2 is composed of dielectric layers 20 and internal electrode layers 30. Multiple dielectric layers 20 and multiple internal electrode layers 30 are stacked on top of each other. The internal electrode layer 30 is composed of a first internal electrode layer 31 and a second internal electrode layer 32.

[0014] The directions in the multilayer ceramic capacitor 1 and the laminate 2 will be described. As shown in FIG. 2, the direction in which the dielectric layer 20 and the internal electrode layer 30 are laminated is defined as the lamination direction T. In the multilayer ceramic capacitor 1, the direction in which the first external electrode 41 and the second external electrode 42 face each other, intersecting the lamination direction T, is defined as the length direction L. The direction intersecting both the lamination direction T and the length direction L is defined as the width direction W.

[0015] In the present embodiment, the lamination direction T, the length direction L, and the width direction W are orthogonal to each other. The lamination direction T, the length direction L, and the width direction W indicate the same directions as described above even in figures other than FIG. 2.

[0016] Two surfaces of the laminate 2 facing the lamination direction T are defined as the first main surface 3 and the second main surface 4. Two surfaces of the laminate 2 facing the width direction W are defined as the first side surface 5 and the second side surface 6. Two surfaces of the laminate 2 facing the length direction L are defined as the first end surface 7 and the second end surface 8.

[0017] The portion where two surfaces of the laminate 2 intersect is defined as the ridge line portion. The portion where three surfaces of the laminate 2 intersect is defined as the corner portion. The corner portion and the ridge line portion preferably have rounded edges.Cuboid shape which is the shape of the laminate 2 includes the shape of a cuboid with rounded ridge line portions and corner portions. Also, the laminate 2 having a cuboid shape includes all members having the first main surface 3, the second main surface 4, the first side surface 5, the second side surface 6, the first end surface 7, and the second end surface 8. Also, irregularities or the like may be formed on part or all of the main surface, side surface, and end surface.

[0018] As shown in FIG. 2, the central position in the lamination direction T of the laminate 2 is defined as the lamination direction center 111. The central position in the length direction L of the laminate 2 is defined as the length direction center 112. The central position in the width direction W of the laminate 2 is defined as the width direction center 113.

[0019] (Dielectric layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 or more and 1800 or less.

[0020] Examples of the ceramic material included in the dielectric layer 20 are dielectric ceramics mainly composed of BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. The ceramic material may be those obtained by adding sub-components such as Mg, Mn, Si, Ni, Fe, Cr, Co, etc. or compounds containing said elements to these main components.

[0021] The thickness of the dielectric layer 20 is preferably, for example, 0.5 μm or more and 30 μm or less.

[0022] The dimensions of the laminate 2 are not particularly limited. The dimension in the length direction L of the laminate 2 can be, for example, 0.2 mm or more and 4.0 mm or less. The dimension in the width direction W of the laminate 2 can be, for example, 0.1 mm or more and 3.0 mm or less. The dimension in the stacking direction T of the laminate 2 can be, for example, 0.1 mm or more and 3.0 mm or less.

[0023] (Internal electrode layer) The internal electrode layer 30 will be described. As described above, the internal electrode layer 30 is composed of a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The internal electrode layer 30 exposed on the first end face 7 is defined as the first internal electrode layer 31. The internal electrode layer 30 exposed on the second end face 8 is defined as the second internal electrode layer 32. The portion where the ends of the first internal electrode layer 31 and the second internal electrode layer 32 are drawn out to the surface of the laminate 2, that is, the end face, is defined as the exposed portion.

[0024] Specifically, the first internal electrode layer 31 is exposed on the first end face 7 and is not exposed on the first main face 3, the second main face 4, the first side face 5, the second side face 6, and the second end face 8. The second internal electrode layer 32 is exposed on the second end face 8 and is not exposed on the first main face 3, the second main face 4, the first side face 5, the second side face 6, and the first end face 7.

[0048]

[0025] Also, specifically, the ends of the first internal electrode layer 31 and the second internal electrode layer 32 may be arranged at positions slightly recessed from the first end face 7 or the second end face 8.

[0026] Inside the laminate 2, a plurality of roughly rectangular first internal electrode layers 31 and second internal electrode layers 32 are arranged alternately at equal intervals along the stacking direction T. Each of the first internal electrode layers 31 and the second internal electrode layers 32 is substantially parallel to the first main surface 3 and the second main surface 4. In the stacking direction T, the first internal electrode layers 31 and the second internal electrode layers 32 face each other via the dielectric layer 20.

[0027] The first internal electrode layer 31 is composed of a first opposing portion 33 and a first leading portion 35. The portion of the first internal electrode layer 31 that faces the second internal electrode layer 32 is defined as the first opposing portion 33. The portion of the first internal electrode layer 31 that is led out from the first opposing portion 33 to the first end face 7 is defined as the first leading portion 35. Similarly, the second internal electrode layer 32 is composed of a second opposing portion 34 and a second leading portion 36. The portion of the second internal electrode layer 32 that faces the first internal electrode layer 31 is defined as the second opposing portion 34. The portion of the second internal electrode layer 32 that is led out from the second opposing portion 34 to the second end face 8 is defined as the second leading portion 36.

[0028] The shape of the first opposing portion 33 is not particularly limited. Preferably, the first opposing portion 33 is rectangular. The corners of the first opposing portion 33 can be rounded, or tapered. Similarly, the shape of the second opposing portion 34 is not particularly limited. Preferably, the second opposing portion 34 is rectangular. The corners of the second opposing portion 34 can be rounded, or tapered. The taper may have a gradient in thickness towards the end.

[0029] The shape of the first drawer section 35 is not particularly limited. Preferably, the first drawer section 35 is rectangular. The corners of the first drawer section 35 can be rounded, or tapered at an angle. Similarly, the shape of the second drawer section 36 is not particularly limited. Preferably, the second drawer section 36 is rectangular. The corners of the second drawer section 36 can be rounded, or tapered at an angle. The taper may have a gradient in thickness towards the end.

[0030] The corner portion refers to the part located at the corner of the outer shape of the internal electrode layer 30 when the internal electrode layer 30 is viewed in cross-section in the length direction L and the width direction W.

[0031] The width in the width direction W of the first opposing section 33 and the width in the width direction W of the first drawer section 35 may be the same width, or one of them may be narrower. The width in the width direction W of the second opposing section 34 and the width in the width direction W of the second drawer section 36 may be the same width, or one of them may be narrower.

[0032] The internal electrode layer 30 contains at least Cu, among Ni, Cu, Ag, Pd, Ag-Pd alloy, and Au. The main component of the internal electrode layer 30 can be Cu.

[0033] The metal constituting the internal electrode layer 30 forms a compound with the metal contained in the external electrode 40, or with the metal constituting the conductive filler contained in the external electrode 40.

[0034] The total number of layers, including the first internal electrode layer 31 and the second internal electrode layer 32, can be between 2 and 100.

[0035] The thickness of the first internal electrode layer 31 and the thickness of the second internal electrode layer 32 are preferably, for example, 0.5 μm or more and 3 μm or less.

[0036] (Classification in the stacking direction) The division of the laminate 2 in the stacking direction T will now be explained. As shown in Figures 2 and 4, the laminate 2 can be divided into an inner layer 10 and an outer layer 11 along the stacking direction T. The outer layer 11 consists of a first outer layer 12 and a second outer layer 13.

[0037] (Inner layer) In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the first main surface 3 and the position of the internal electrode layer closest to the second main surface 4 is defined as the inner layer portion 10.

[0038] More specifically, the inner layer 10 is a portion in which the first internal electrode layer 31 and the second internal electrode layer 32 and the dielectric layer 20 are alternately stacked, and refers to the portion from the first internal electrode layer 31 or the second internal electrode layer 32 closest to the first main surface 3 to the first internal electrode layer 31 or the second internal electrode layer 32 closest to the second main surface 4.

[0039] (outer layer) In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the first main surface 3 and the first main surface 3 is defined as the first outer layer portion 12. The first outer layer portion 12 is the portion of the laminate 2 located between the inner layer portion 10 and the first main surface 3.

[0040] In the stacking direction T, the portion of the laminate 2 located between the position of the internal electrode layer closest to the second main surface 4 and the second main surface 4 is defined as the second outer layer portion 13. The second outer layer portion 13 is the portion of the laminate 2 located between the inner layer portion 10 and the second main surface 4.

[0041] In other words, the outer layer 11 is the portion that sandwiches the inner layer 10 in the stacking direction T. The dielectric layer 20 constituting the outer layer 11 preferably contains BaTiO3 or CaZrO3 as the main material, and preferably contains Si, V, Mn, Mg or Ni as an additive.

[0042] (Division in the width direction) The division of the laminate 2 in the width direction W will now be explained. As shown in Figures 3 and 4, the laminate 2 can be divided along the width direction W into a core portion 25 and a side gap 14. The side gap 14 consists of a first side gap 15 and a second side gap 16.

[0043] (Core part) In the width direction W, the portion of the laminate 2 in which the internal electrode layer 30 is provided is defined as the core portion 25.

[0044] (Side gap) In the width direction W, the portion of the laminate 2 located between the core portion 25 and the first side surface 5 is defined as the first side gap 15. In the width direction W, the portion of the laminate 2 located between the core portion 25 and the second side surface 6 is defined as the second side gap 16. No internal electrode layer is provided in the side gap 14. Only the dielectric layer 20 is provided in the side gap 14. The side gap is also called a W gap or side gap.

[0045] (Classification of the core section) The division of the core portion 25 in the stacking direction T will now be explained. As shown in Figure 4, the core portion 25 can be divided into an effective layer portion 26 and an ineffective portion 27 along the stacking direction T. The ineffective portion 27 consists of a first ineffective portion 28 and a second ineffective portion 29.

[0046] (Effective layer) In the stacking direction T, the portion of the core 25 where the first internal electrode layer 31 or the second internal electrode layer 32 is located is defined as the effective layer portion 26.

[0047] (Invalid section) In the stacking direction T, the portion of the core 25 located between the effective layer 26 and the first main surface 3 is defined as the first inactive portion 28. In the stacking direction T, the portion of the core 25 located between the effective layer 26 and the second main surface 4 is defined as the second inactive portion 29. The inactive portion 27 does not have an internal electrode layer 30. The inactive portion 27 is provided only with a dielectric layer 20.

[0048] (Counter electrode part) The portion where the first internal electrode layer 31 and the second internal electrode layer 32 overlap is defined as the opposing electrode portion 38. In the opposing electrode portion 38, the first opposing portion 33 and the second opposing portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when opposing portions of the internal electrode layers 30 face each other via the dielectric layer 20. That is, capacitance is formed in the opposing electrode portion 38. Capacitance is expressed in the multilayer ceramic capacitor 1 due to this capacitance.

[0049] (End face gap) The end face gap 17 will be described with reference to Figures 2 and 3. In the laminate 2, the portion located between the opposing electrode portion 38 and the end face, and including the lead portion of either the first internal electrode layer 31 or the second internal electrode layer 32, is defined as the end face gap 17. The end face gap 17 is also referred to as the L gap.

[0050] The end face gap 17 is composed of a first end face gap 18 and a second end face gap 19. The portion located between the opposing electrode portion 38 and the first end face 7, including the first lead portion 35, is defined as the first end face gap 18. Similarly, the portion located between the opposing electrode portion 38 and the second end face 8, including the second lead portion 36, is defined as the second end face gap 19.

[0051] (external electrode) The external electrode 40 consists of a first external electrode 41 and a second external electrode 42. The external electrode 40 that is positioned on the first end face 7 and connected to the first internal electrode layer 31 is defined as the first external electrode 41. In addition to the first end face 7, the first external electrode 41 may be positioned on a portion of the first main surface 3, a portion of the second main surface 4, a portion of the first side surface 5, and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is positioned to extend from the first end face 7 to a portion of the first main surface 3, a portion of the second main surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0052] An external electrode 40 positioned on the second end face 8 and connected to the second internal electrode layer 32 is defined as the second external electrode 42. The second external electrode 42 may be positioned not only on the second end face 8, but also on a portion of the first main surface 3, a portion of the second main surface 4, a portion of the first side surface 5, and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is positioned to extend from the second end face 8 to a portion of the first main surface 3, a portion of the second main surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0053] The external electrode 40 is composed of a base electrode layer 50 and a plating layer 60. The base electrode layer 50 constituting the first external electrode 41 is defined as the first base electrode layer 51. The base electrode layer 50 constituting the second external electrode 42 is defined as the second base electrode layer 52.

[0054] The plating layer 60 constituting the first external electrode 41 is defined as the first plating layer 61. The plating layer 60 constituting the second external electrode 42 is defined as the second plating layer 62.

[0055] (base electrode layer) The base electrode layer 50 can be composed of a baked layer or a conductive resin layer. The case where the base electrode layer 50 is a baked layer will be described below. The baked layer contains glass components and metals. The glass components include at least one element such as B, Si, Ba, Mg, Al, and Li. The metal components include at least one such element such as Cu, Ni, Ag, Pd, Ag-Pd alloy, and Au.

[0056] The baked layer may consist of multiple layers. This baked layer is formed by applying a conductive paste containing glass components and metal to the laminate 2 and baking it. Baking can be performed simultaneously with the firing of the internal electrode layer 30 and the dielectric layer 20, or after their firing. Furthermore, when the baked layer is baked simultaneously with the firing of the internal electrode layer and the dielectric layer, it is preferable to add a dielectric material instead of glass components to form the baked layer.

[0057] The thickness L in the longitudinal direction at the center 111 of the stacking direction of the baked layer located at the first end face 7 and the second end face 8 is preferably, for example, 3 μm or more and 160 μm or less.

[0058] Furthermore, when forming a baked layer as a base electrode layer 50 on a part of the first main surface 3, a part of the second main surface 4, a part of the first side surface 5, and a part of the second side surface 6, it is preferable that the thickness of the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6 at the central position in the longitudinal direction L is, for example, 3 μm or more and 40 μm or less.

[0059] (Plating layer) The first plating layer 61 is positioned to cover the first base electrode layer 51. The second plating layer 62 is positioned to cover the second base electrode layer 52.

[0060] The material of the plating layer 60 includes at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, and Au.

[0061] The plating layer 60 may be composed of multiple layers. In this embodiment, the first plating layer 61 and the second plating layer 62 are each composed of two plating layers. When the plating layer 60 is composed of two layers, preferably one layer is a nickel plating layer and the other layer is a tin plating layer.

[0062] The nickel plating layer included in the first plating layer 61 is defined as the first nickel plating layer 63. The tin plating layer included in the first plating layer 61 is defined as the first tin plating layer 65. Similarly, the nickel plating layer included in the second plating layer 62 is defined as the second nickel plating layer 64. The tin plating layer included in the second plating layer 62 is defined as the second tin plating layer 66.

[0063] The nickel plating layer prevents the underlying electrode layer 50 from being eroded by the solder used when mounting the multilayer ceramic capacitor 1.

[0064] The tin-plated layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This makes mounting easier.

[0065] Based on the above, it is preferable that the plating layers 60 in contact with the base electrode layer 50 be, in order, a nickel plating layer and a tin plating layer. The plating layer 60 may consist of three or more layers. The main component of the plating layer 60 may be a metal species other than Ni and Sn.

[0066] The preferred thickness of each layer of the plating layer 60 is 1 μm or more and 15 μm or less.

[0067] (Conductive resin layer) The base electrode layer 50 may consist of a baked layer and a conductive resin layer. In this case, the base electrode layer 50 has a two-layer structure in which the baked layer and the conductive resin layer are laminated in order. The conductive resin layer is arranged, for example, to cover the base electrode layer 50.

[0068] Specifically, the conductive resin layer is placed on the base electrode layer 50 located on the first end face 7 and the second end face 8. Preferably, the conductive resin layer is placed so as to extend to the base electrode layer 50 located on the first main surface 3, the second main surface 4, the first side surface 5, and the second side surface 6. However, the conductive resin layer may be placed only on the base electrode layer 50 located on the first end face 7 and the second end face 8.

[0069] The conductive resin layer is more flexible than the baked-on layer because it contains resin and metal. The conductive resin layer functions as a buffer layer. Therefore, even if flexural stress is applied to the mounting substrate and a physical force is applied to the multilayer ceramic capacitor 1 due to this stress, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0070] Furthermore, even when forces caused by thermal cycling act on the multilayer ceramic capacitor 1, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0071] The resin contained in the conductive resin layer can be a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, or polyimide resin. Among these, epoxy resin is one of the suitable resins because it has excellent heat resistance, moisture resistance, and adhesion. In addition, multiple types of resins, such as epoxy resin and phenolic resin, can be used in the conductive resin layer.

[0072] The conductive resin layer preferably contains a curing agent in addition to the resin. When epoxy resin is used as the resin, the curing agent is preferably a compound such as a phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, or amide-imide-based compound.

[0073] The conductive resin layer contains metal. The presence of metal in the conductive resin layer makes it electrically conductive. The metal contained in the conductive resin layer is included in the conductive resin layer as metal powder, i.e., conductive filler. The shape of the conductive filler is, for example, flattened. Contact between conductive fillers creates an electrical pathway within the conductive resin layer. This formed electrical pathway makes the conductive resin layer electrically conductive.

[0074] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The metal is particularly preferably Ag. Ag may be pure Ag, or Ag may be an alloy containing Ag. For example, the metal can be at least one of Ag, Ag-coated Cu, Ag-coated Ni, and Ag-coated alloy powder.

[0075] When using a material in which the surface of the metal powder is coated with Ag, it is preferable to use copper powder or nickel powder as the metal powder. Antioxidant treated Cu can also be used. The reason for using an Ag-coated metal is that it allows for the use of an inexpensive metal as the base material while maintaining the properties of Ag.

[0076] The metal content in the conductive resin layer is preferably 35 vol% to 75 vol% relative to the total volume of the conductive resin layer. The shape of the conductive filler is not limited to the flattened shape described above, and may be spherical, etc. Furthermore, a mixture of spherical and flattened metal powders can be used. The average particle size of the conductive filler is also not particularly limited and can be, for example, 0.3 μm to 10 μm. The thickness of the conductive resin layer is suitable to be 10 μm to 200 μm.

[0077] Furthermore, the base electrode layer 50 may consist only of a conductive resin layer and not include a baking layer. In other words, it is also possible to form a conductive resin layer directly on the laminate 2 without forming a baking layer.

[0078] (Dimensions of multilayer ceramic capacitors) The dimensions of the multilayer ceramic capacitor 1, including the laminated body 2 and external electrodes, will now be described. The length L dimension of the multilayer ceramic capacitor 1 can be, for example, 1.0 mm or more and 4.0 mm or less. The width W dimension of the multilayer ceramic capacitor 1 can be, for example, 1.0 mm or more and 3.0 mm or less. The stacking direction T dimension of the multilayer ceramic capacitor 1 can be, for example, 1.0 mm or more and 3.0 mm or less. Note that the dimensions of the multilayer ceramic capacitor 1 are not limited to these examples.

[0079] Furthermore, the lengthwise dimension L of the multilayer ceramic capacitor 1 can be made larger than the widthwise dimension W of the multilayer ceramic capacitor 1 and the stacking dimension T of the multilayer ceramic capacitor 1.

[0080] (Dimensions of the inner and outer layers) Referring to Figure 5, the dimensions of the inner layer 10 and outer layer 11 in the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 5 is a diagram corresponding to the cross-sectional view taken along line 101-101 in Figure 1. In Figure 5, characteristic parts are exaggerated to illustrate the features of this embodiment.

[0081] (Average dimensions of the inner layer and average dimensions of the outer layer) In the multilayer ceramic capacitor 1 of this embodiment, in the cross-section in the length direction L and the stacking direction T at the center 113 in the width direction, the dimension in the length direction L of the inner layer 10 is larger than the dimension in the length direction L of the outer layer 11.

[0082] (Average dimensions of the inner layer) Here, the lengthwise dimension L of the inner layer 10 is the average value over the entire inner layer 10. The cross section in the lengthwise direction L and the stacking direction T at the center 113 in the width direction is defined as the LT cross section. The lengthwise dimension L of the inner layer 10 in the LT cross section is defined as the inner layer dimension 201. The average value of the inner layer dimension 201 over the entire stacking direction T of the inner layer 10 is defined as the average inner layer dimension.

[0083] (Average dimensions of the outer layer) Similarly, the lengthwise dimension L of the outer layer 11 here is the average value over the entire outer layer 11. The lengthwise dimension L of the outer layer 11 in the LT section is defined as the outer layer dimension 202. The average value of the outer layer dimension 202 over the entire stacking direction T of the outer layer 11 is defined as the average outer layer dimension.

[0084] In the multilayer ceramic capacitor 1 of this embodiment, the average dimensions of the inner layer are larger than the average dimensions of the outer layer. In other words, the average dimensions of the inner layer are greater than the average dimensions of the outer layer.

[0085] In the multilayer ceramic capacitor 1 of this embodiment, the average dimensions of the inner layer are larger than the average dimensions of the outer layer, resulting in good contact between the internal electrode layer 30 and the external electrode 40. As a result, the failure rate of the multilayer ceramic capacitor 1 when it discharges after being mounted on a wiring board or the like can be suppressed.

[0086] Since the average dimensions of the inner layer are larger than the average dimensions of the outer layer, the distance between the internal electrode layer 30 and the external electrode 40 can be shortened. As a result, the contact between the internal electrode layer 30 and the external electrode 40 is improved, and the failure rate of the multilayer ceramic capacitor 1 during mounted discharge can be suppressed.

[0087] (Step) Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the average dimensions of the inner layer are larger than the average dimensions of the outer layer. As a result, in the LT cross-section, a step is formed in the dielectric layer 20 near the boundary between the outer layer 11 and the inner layer 10 at the end face. In other words, there is a step near the boundary between the outer layer 11 and the inner layer 10 at the end face.

[0088] (Dimensions of the center of the inner layer and the average dimensions of the outer layer) In the multilayer ceramic capacitor 1 of this embodiment, in the LT cross-section, the length L dimension at the center 111 of the inner layer 10 in the stacking direction is larger than the length L dimension at the end of the inner layer 10 in the stacking direction T.

[0089] (Dimensions of the center of the inner layer) As shown in Figure 5, the dimension of the inner layer portion 10 at the center 111 in the stacking direction in the LT cross section is defined as the inner layer portion center dimension 205.

[0090] (Dimensions of the inner layer end) As shown in Figure 5, the end of the inner layer 10 in the stacking direction T is defined as the stacking direction inner layer end 115. The length L dimension at the stacking direction inner layer end 115 of the inner layer 10 in the LT cross section is defined as the inner layer end dimension 207.

[0091] In the multilayer ceramic capacitor 1 of this embodiment, the central dimension 205 of the inner layer is larger than the edge dimension 207 of the inner layer. In other words, the central dimension of the inner layer is greater than the edge dimension of the inner layer.

[0092] As shown in Figure 5, the outer surface of the external electrode 40 is defined as the external electrode surface 43. In the multilayer ceramic capacitor 1 of this embodiment, since the central dimension 205 of the inner layer is larger than the end dimension 207 of the inner layer, the distance from the inner layer 10 to the external electrode surface 43 at the inner layer end 115 in the stacking direction can be made relatively larger.

[0093] This makes it possible to lengthen the moisture intrusion path at the corner portion 250 of the inner layer 10, where moisture intrusion was prone to deterioration of moisture resistance. As a result, the multilayer ceramic capacitor 1 of this embodiment can ensure moisture resistance while suppressing the failure rate.

[0094] (recess) Referring to Figure 6, the recess 270 formed by the outer layer 11 and the inner layer 10 will be described. Figure 6 is an enlarged view of the framed area 220 in Figure 5. In this embodiment, the multilayer ceramic capacitor 1 has a recess 270 in the LT cross section near the boundary between the outer layer 11 and the inner layer 10 at the first end face 7 or the second end face 8, which is recessed more than either the inner layer 10 or the outer layer 11.

[0095] At the first end face 7, the end of the inner layer portion 10 on the first end face 7 side is defined as the inner layer end 271. Similarly, at the first end face 7, the end of the outer layer portion 11 on the first end face 7 side is defined as the outer layer end 272. The bottom of the recess 270 is defined as the recess bottom 273.

[0096] As shown in Figure 6, the bottom of the recess 273 is located further from the first end face 7 in the longitudinal direction than either the inner layer end 271 or the outer layer end 272. That is, the recess 270 has a shape that is more recessed than the inner layer 10 and the outer layer 11.

[0097] The boundary between the outer layer 11 and the inner layer 10 is defined as the inner-outer layer boundary 300. In addition to the fact that the central dimension 205 of the inner layer is larger than the end dimension 207 of the inner layer, as described earlier, the multilayer ceramic capacitor 1 of this embodiment has a recess 270 in the portion of the inner-outer layer boundary 300 that is exposed on the end face, which is recessed more deeply than the inner layer 10 and outer layer 11 other than the inner-outer layer boundary 300.

[0098] Thus, the multilayer ceramic capacitor 1 of this embodiment has a central inner layer dimension 205 > inner layer edge dimension 207, and also has a recess 270. Therefore, the distance from the inner layer 10 to the outer electrode surface 43 at the inner layer edge 115 in the stacking direction can be made relatively larger. This makes the moisture intrusion path at the corner portion 250 of the inner layer 10 longer. As a result, the multilayer ceramic capacitor 1 of this embodiment can ensure moisture resistance while further suppressing the failure rate.

[0099] (Boundary area) Referring to Figure 6, the boundary peripheral region 310 will be described. The area surrounding the inner-outer layer boundary 300, which is the boundary between the inner layer 10 and the outer layer 11, is defined as the boundary peripheral region 310. The boundary peripheral region 310 consists of the outer layer boundary peripheral region 312 and the inner layer boundary peripheral region 311.

[0100] (Region around the inner layer boundary) In the LT cross-section, the region within 15 μm in the stacking direction T from the inner / outer layer boundary 300 toward the stacking direction center 111 is defined as the inner layer boundary peripheral region 311. The dimension 221 shown in Figure 6 is 15 μm. The boundary of the inner layer boundary peripheral region 311 opposite the inner / outer layer boundary 300 is defined as the inner layer peripheral boundary 301. Note that the stacking direction center 111 is not shown in Figure 6, but is shown in Figure 5, etc.

[0101] As shown in Figure 6, the inner layer boundary peripheral region 311 is a region that extends in the stacking direction T from the inner / outer layer boundary 300 toward the center 111 in the stacking direction. Furthermore, the inner layer boundary peripheral region 311 is not limited to the distance from one end in the length direction L to the other end in the length direction L, but is a region that extends in the width direction W within the inner layer portion 10.

[0102] (Region around the outer boundary) In the LT cross-section, the region within 5 μm in the stacking direction T toward the main surface from the inner / outer layer boundary 300 is defined as the outer layer boundary peripheral region 312. The dimension 222 shown in Figure 6 is 5 μm. The boundary of the outer layer boundary peripheral region 312 opposite the inner / outer layer boundary 300 is defined as the outer layer peripheral boundary 302.

[0103] As shown in Figure 6, the outer layer boundary peripheral region 312 is a region that extends in the stacking direction T toward the main surface from the inner-outer layer boundary 300. Furthermore, the outer layer boundary peripheral region 312 is not limited to the distance from one end in the longitudinal direction L to the other end in the longitudinal direction L, but is a region that extends in the width direction W in the outer layer portion 11.

[0104] (Thickness of the underlying electrode) Referring to Figure 7, the thickness of the base electrode layer 50 in the multilayer ceramic capacitor 1 of this embodiment will be described. Figure 7 is a diagram corresponding to the cross-sectional view along line 101-101 in Figure 1.

[0105] In the multilayer ceramic capacitor 1 of this embodiment, the relationship between the thickness L1 of the base electrode layer 50 in the recess 270, the thickness L2 of the base electrode layer 50 at the end of the inner layer portion 10 of the boundary peripheral region 310 on the stacking direction center 111 side, i.e., the inner layer peripheral boundary 301, and the thickness L3 of the base electrode layer 50 at the stacking direction center 111 is as follows: L2 <L1<L3、となる。

[0106] As described above, the multilayer ceramic capacitor 1 of this embodiment has a recess 270. As shown in Figures 6 and 7, the base electrode layer 50 is also placed in the recess 270 up to the bottom 273 of the recess. The thickness of the base electrode layer 50 is L2 at the inner layer peripheral boundary 301 < L1 at the recess 270 < L3 at the center 111 in the stacking direction.

[0107] Thus, in the multilayer ceramic capacitor 1 of this embodiment, the thickness of the base electrode layer 50 is greater at the corner portion 250 of the inner layer 10 than at the peripheral boundary 301 of the inner layer. As a result, moisture penetration is less likely to occur at the corner portion 250 of the inner layer 10, which was previously prone to moisture intrusion, improving moisture resistance reliability.

[0108] Furthermore, preferably, the ratio of the thickness L1 of the base electrode layer 50 in the recess 270 to the thickness L3 of the base electrode layer 50 in the center 111 in the lamination direction is 75% or more and 95% or less.

[0109] By keeping the thickness ratio of the base electrode layer 50, i.e., (L1 in the recess 270 / L3 in the center 111 in the lamination direction) within the range of 75% to 95%, it is possible to maintain the best moisture resistance reliability while making it less likely for the inner layer 10 and the outer layer 11 to peel off.

[0110] If the thickness ratio of the base electrode layer 50 is less than 75%, the length of the moisture penetration path may not be sufficient, and the moisture resistance reliability may be insufficient.

[0111] When the thickness ratio of the base electrode layer 50 exceeds 95%, the stress difference between the inner layer 10 and the outer layer 11 during firing in the multilayer ceramic capacitor 1 becomes large, making delamination between the inner layer 10 and the outer layer 11 more likely.

[0112] (Residual stress) The stress difference between the inner layer 10 and the outer layer 11 during firing, as described above, remains as residual stress near the interface between the inner layer 10 and the outer layer 11 after firing. The type of residual stress is tensile stress or compressive stress, etc., depending on the difference in the manner of shrinkage between the inner layer 10 and the outer layer 11. The presence and magnitude of residual stress can be measured by Raman spectroscopy and X-ray diffraction.

[0113] In the multilayer ceramic capacitor 1 of this embodiment, residual stress is low. Therefore, it is possible to realize a multilayer ceramic capacitor 1 that has improved moisture resistance reliability and a reduced failure rate while suppressing the occurrence of delamination and cracking due to temperature changes, etc.

[0114] (Curvature in the peripheral region of the boundary) Referring to Figure 6, the curvature in the peripheral region of the multilayer ceramic capacitor 1 of this embodiment will be described.

[0115] In the multilayer ceramic capacitor 1 of this embodiment, in the LT cross-section, the radius of curvature of the boundary region 310 of the outer layer 11 exposed to the first end face 7 or the second end face 8 is smaller than the radius of curvature of the boundary region 310 of the inner layer 10 exposed to the first end face 7 or the second end face 8.

[0116] The radius of curvature of the boundary region 310 of the outer layer 11 is the radius of curvature of the portion indicated by arrow 322 in Figure 6. This radius of curvature is defined as the outer layer radius of curvature 322. The radius of curvature of the boundary region 310 of the inner layer 10 is the radius of curvature of the portion indicated by arrow 321 in Figure 6. This radius of curvature is defined as the inner layer radius of curvature 321.

[0117] In the multilayer ceramic capacitor 1 of this embodiment, the radius of curvature is such that the boundary region of the outer layer is less than the boundary region of the inner layer. That is, the radius of curvature of the outer layer 322 is less than the radius of curvature of the inner layer 321.

[0118] Because the radius of curvature 322 of the outer layer is smaller than the radius of curvature 321 of the inner layer, the portion of the inner electrode layer 30 exposed at the end face near the corner portion 250 of the inner layer 10 is further away from the outer electrode surface 43. As a result, the moisture intrusion path is lengthened, further improving moisture resistance.

[0119] Furthermore, in the multilayer ceramic capacitor 1 of this embodiment, the radius of curvature of the boundary region 310 of the inner layer portion 10 exposed on the first end face 7 or the second end face 8 in the LG cross-section is 10 μm or more and 20 μm or less.

[0120] By setting the inner layer curvature radius 321 to between 10 μm and 20 μm, it is possible to maintain good moisture resistance while minimizing the impact on electrical characteristics. If the inner layer curvature radius 321 is less than 10 μm, the distance between the internal electrode layer 30 and the external electrode surface 43 at the corner portion 250 of the inner layer 10 becomes shorter. As a result, it may be difficult to ensure moisture resistance reliability. Also, if the inner layer curvature radius 321 exceeds 20 μm, the lead portion of the internal electrode layer 30 may be excessively curved. As a result, it may be difficult to maintain the electrical characteristics of the multilayer ceramic capacitor.

[0121] The radius of curvature of the outer layer, 322, is preferably 3 μm or more and 6 μm or less.

[0122] Furthermore, the effect of improving moisture resistance in the multilayer ceramic capacitor 1 of this embodiment, as described above, is more pronounced when the dimensions of the multilayer ceramic capacitor 1 are within the following ranges. Specifically, the effect of improving moisture resistance is more pronounced when the dimensions of the multilayer ceramic capacitor 1, including the external electrodes 40, are such that the length L is 1.0 mm or more and 4.0 mm or less, the stacking direction T is 1.0 mm or more and 3.0 mm or less, and the width W is 1.0 mm or more and 3.0 mm or less.

[0123] The effect of improved moisture resistance becomes even more pronounced when the length L dimension is 3.5 mm or more.

[0124] (Measurement method) The measurement methods for the dimensions and radius of curvature described above are explained below. At the center 113 in the width direction of the multilayer ceramic capacitor 1, the surfaces in the length direction L and the stacking direction T are polished. This exposes the LG cross-section. By observing the exposed LG cross-section, the dimensions and radius of curvature can be measured.

[0125] (Manufacturing method for multilayer ceramic capacitors) A method for manufacturing a multilayer ceramic capacitor 1 will be described below. However, the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0126] Prepare a conductive paste for the dielectric sheet and internal electrode layer. The conductive paste for the dielectric sheet and internal electrode layer contains a binder and a solvent. Known binders and solvents can be used. The dielectric sheet is also called a ceramic green sheet.

[0127] A dielectric sheet with an internal electrode layer pattern is prepared. Specifically, a conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern to prepare a dielectric sheet with a first internal electrode layer pattern and a dielectric sheet with a second internal electrode layer pattern. Printing is performed, for example, by screen printing or gravure printing.

[0128] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer. On top of this, dielectric sheets with printed first internal electrode layer patterns and dielectric sheets with printed second internal electrode layer patterns are sequentially stacked to form the inner layer. Furthermore, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the inner layer to form the second outer layer. This creates a laminated sheet.

[0129] The dielectric paste for the dielectric sheet constituting the outer layer is defined as the outer layer paste. The dielectric paste for the dielectric sheet constituting the inner layer is defined as the inner layer paste. When formulating the outer layer paste, the amount of organic components is increased so that it shrinks easily during firing. Preferably, the outer layer paste is formulated so that it shrinks more easily during firing than the inner layer paste.

[0130] Specifically, the ratio of the volume of organic matter to the total volume of dielectric material and organic matter in the outer layer paste is made greater than that of the inner layer paste. Alternatively, the degree of shrinkage of the outer layer paste may also be controlled by the type and amount of additives.

[0131] The created laminated sheets are pressed in the lamination direction using a hydrostatic press or similar method to produce laminated blocks.

[0132] Laminated blocks are cut into individual pieces to produce laminated chips. Specifically, laminated blocks are cut with a cutting blade to create individual pieces, and a pre-firing laminate is created.

[0133] The laminated chips are fired to create the laminated structure. Before firing, the corners and edges of the laminated chips may be rounded using barrel polishing or other methods. The firing temperature depends on the dielectric and internal electrode layer materials, but a temperature of 900°C to 1400°C is desirable. Barrel polishing and other methods can also be performed on the laminated structure after firing.

[0134] Next, the external electrodes are formed. First, a conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 2 to form the base electrode layer. In forming the baked layer as the base electrode layer, a conductive paste containing glass components and metal is applied by dipping or other means, and then baked. The baking temperature at this time is preferably between 700°C and 900°C.

[0135] Subsequently, a plating layer is formed on the surface of the base electrode layer. A nickel plating layer and a tin plating layer are sequentially formed on the base electrode layer. These plating layers are formed, for example, by barrel plating. In this way, a multilayer ceramic capacitor is obtained.

[0136] Embodiments of the present invention have been described above. However, the present invention is not limited to the embodiments described above, and various modifications, alterations, and combinations are possible. Furthermore, multilayer ceramic capacitors are just one example of multilayer ceramic electronic components. The techniques described above can also be applied to other multilayer ceramic electronic components besides multilayer ceramic capacitors. [Explanation of symbols]

[0137] 1. Multilayer ceramic capacitor 2 Laminate 3. First main surface 4. Second main surface 5. First Aspect 6. Second Aspect 7. First end face 8. Second end face 10 Inner layer 11 Outer layer 12 First outer layer 13. Second outer layer 111 Center of stacking direction 112 Center in the length direction 113 Width center 250 Corner section 270 recess L (Length direction) T Stacking direction W (width direction)

Claims

1. It has an inner layer portion in which a dielectric layer and an internal electrode layer are stacked in the stacking direction, and an outer layer portion provided so as to sandwich the inner layer portion in the stacking direction, A laminate comprising: a first main surface and a second main surface facing the stacking direction; a first side surface and a second side surface facing the width direction perpendicular to the stacking direction; and a first end surface and a second end surface facing the length direction perpendicular to the stacking direction and the width direction. The device comprises an external electrode provided on the first end face and the second end face, and connected to the internal electrode layer, In the cross-section in the length direction and the stacking direction at the center in the width direction, the length dimension of the inner layer is larger than the length dimension of the outer layer. In the cross-section in the length direction and the stacking direction at the center in the width direction, the length dimension of the inner layer at the center in the stacking direction is greater than the length dimension of the inner layer at the end in the stacking direction. In the first or second end face, near the boundary between the outer layer and the inner layer, there is a recess that is more recessed than the inner layer and the outer layer. Multilayer ceramic capacitor.

2. The external electrode comprises a base electrode disposed on the first end face or the second end face, and a plating layer disposed on the base electrode. If the region surrounding the boundary between the inner layer and the outer layer is defined as the boundary peripheral region, The thickness L1 of the base electrode in the recess, The thickness L2 of the base electrode at the end of the inner layer portion of the boundary peripheral region on the central side in the stacking direction, The relationship between the thickness L3 of the base electrode at the center of the stacking direction and the above is: L2 < L1 < L3 This means, The multilayer ceramic capacitor according to claim 1.

3. The ratio of the thickness L1 of the base electrode in the recess to the thickness L3 of the base electrode in the center of the stacking direction is 75% or more and 95% or less. The multilayer ceramic capacitor according to claim 2.

4. If the region surrounding the boundary between the inner layer and the outer layer is defined as the boundary peripheral region, In the cross-section in the length direction and the stacking direction at the center in the width direction, The radius of curvature of the boundary region of the outer layer exposed to the first or second end face is smaller than the radius of curvature of the boundary region of the inner layer exposed to the first or second end face. A multilayer ceramic capacitor according to any one of claims 1 to 3.

5. In the cross-section in the length direction and the stacking direction at the center in the width direction, The radius of curvature of the boundary region of the inner layer exposed to the first or second end face is 10 μm or more and 20 μm or less. The multilayer ceramic capacitor according to claim 4.

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